CN112332849A - Digital-to-analog converter and analog-to-digital converter for realizing low power consumption and low noise - Google Patents

Digital-to-analog converter and analog-to-digital converter for realizing low power consumption and low noise Download PDF

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CN112332849A
CN112332849A CN202011249988.7A CN202011249988A CN112332849A CN 112332849 A CN112332849 A CN 112332849A CN 202011249988 A CN202011249988 A CN 202011249988A CN 112332849 A CN112332849 A CN 112332849A
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capacitors
low
order
capacitor
switches
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CN112332849B (en
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李靖
肖航
张启辉
田明
宁宁
于奇
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University of Electronic Science and Technology of China
Shanghai Huali Microelectronics Corp
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University of Electronic Science and Technology of China
Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/54—Input signal sampled and held with linear return to datum
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing

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Abstract

A digital-to-analog converter and analog-to-digital converter realizing low power consumption and low noise adopt a C2C + binary capacitor array, a low-order terminal capacitor is connected with a low-order weight capacitor at the lowest level in parallel, a high-order terminal capacitor is connected with M high-order weight capacitors in parallel, second connecting ends of the L low-order weight capacitors and the L high-order terminal capacitors are respectively used as a node, and a bridging capacitor is inserted into each two adjacent nodes; the L +1 nodes are respectively connected with the common-mode voltage through second switches for resetting, the low-order terminal capacitors and the L low-order weight capacitors do not participate in sampling, and first connection ends of the low-order terminal capacitors and the L low-order weight capacitors are respectively connected with reference voltage or ground voltage through first switches; the high-order terminal capacitor and the M high-order weight capacitors participate in sampling, and the first connection ends of the high-order terminal capacitor and the M high-order weight capacitors are respectively connected with an input voltage, a reference voltage or a ground voltage through a third switch. The invention has the characteristics of small area and low power consumption of the C2C + binary structure, and solves the problems of large noise and reliability.

Description

Digital-to-analog converter and analog-to-digital converter for realizing low power consumption and low noise
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a digital-to-analog converter for realizing low power consumption and low noise and an analog-to-digital converter formed by the digital-to-analog converter.
Background
An analog-to-digital converter (ADC) is a bridge connecting the analog world and the digital world, and includes a successive approximation analog-to-digital converter (SAR ADC), a digital-to-analog converter (DAC) is an important component of the SAR ADC, and the DAC is roughly of three types: a voltage scaling type, a current scaling type, and a charge scaling type.
The voltage scaling DAC is the simplest DAC, and divides a reference voltage into 2N segmented reference voltages by a resistor string consisting of 2N unit resistors, and the segmented reference voltages are sequentially compared with an analog input voltage according to a binary search algorithm to complete the DAC function.
The current scaling DAC can be divided into two types: binary weighted current array, R-2R ladder. The circuit structure of the binary weighted current array is provided with a binary weighted current source array, the combined current of the current sources is converted into voltage, and the voltage is compared with the analog input voltage to complete the DAC function. Based on the characteristic that the resistance value of any node of the R-2R ladder is equal to R, a group of binary weighted currents are generated through reference voltage, combination is selected through a switch, and finally the currents are converted into voltages to be compared with analog input, so that the DAC function is completed.
The charge scaling DAC (CDAC) uses the charges on the capacitor array to store the input information, and then performs successive redistribution on the charges to complete the binary search algorithm. Because of the good matching of the capacitor and the resistance in the MOS process and the small static power consumption of the CDAC, the DAC is the most applied DAC in the SAR ADC at present. In addition, CDAC need notAn additional sample-and-hold S/H circuit is required because it can sample and hold the input signal as a sample-and-hold circuit by itself and has a smaller area with the same matching accuracy. Thus, charge redistribution DACs have been widely used in the design of SAR ADCs, however, the required capacitance for a DAC array to achieve N-bit precision is 2NThe capacitance area increases exponentially with the accuracy. Because the total capacitance of a common binary charge redistribution type DAC is overlarge in a high-precision SAR ADC, a split capacitor array is gradually developed, the required capacitance is reduced by dividing the whole DAC into a main bit and a secondary bit, if each capacitance still meets the binary relation, a bridging capacitance needs to be set to be a fraction value, but the fraction value capacitance cannot be matched with a unit capacitance, the error is large, and meanwhile, the linearity is reduced. The C2C capacitor cell can make the respective weighted capacitances satisfy the binary relation without using fractional capacitance, and the capacitance required by the C2C capacitor array is much smaller than that of the conventional DAC array while achieving the same accuracy, however, the C2C capacitor structure has a big problem regardless of the upper plate sampling and the lower plate sampling: when the upper polar plate is used for sampling, the equivalent sampling capacitance is very small, the kT/C noise is very large, and the requirements of the ADC cannot be met. When the bottom plate samples, because the C2C capacitor array introduces too many nodes on the top plate, these nodes all need to reset after the quantization cycle of each time is finished, guarantee that the voltage is accurate after next sampling keeps, but these reset switches can't guarantee to turn off simultaneously because of the inconsistency of MOS pipe parameter and the reason of delay in the signal path in the actual preparation, when the bottom plate inserts the input signal, what leads to each weight electric capacity to gather is not the voltage information at the same moment, thereby the sampling process appears the mistake, ADC conversion result loses the reliability.
Disclosure of Invention
Based on the requirement for the area of the digital-to-analog converter, the low-order capacitor array is formed by adopting the C2C capacitor structure without fractional capacitors, and the high-order capacitor array is formed by combining the traditional binary DAC structure, so that the whole DAC capacitor array does not need fractional capacitors and realizes the binary proportional relation of all digits, the area of the needed capacitors under the same precision is greatly reduced, and the power consumption of the whole digital-to-analog converter is reduced. Based on the noise and reliability problems of the C2C capacitor structure during sampling, the invention improves the connection, reset and sampling modes of the traditional C2C capacitor structure, so that a low-order capacitor array formed by the C2C capacitor structure does not participate in sampling, only a high-order capacitor array performs sampling, the sampling capacitor is large enough, and the kT/C noise is reduced; in addition, only one reset switch on the upper polar plate of the high-order capacitor participating in sampling influences the voltage information of sampling in the sampling process, the possibility of error of the sampling information is eliminated, and the reliability is improved.
The technical scheme of the digital-to-analog converter provided by the invention is as follows:
a digital-to-analog converter for realizing low power consumption and low noise comprises 1 low-order terminal capacitor, 1 high-order terminal capacitor, L low-order weight capacitors, L bridging capacitors, M high-order weight capacitors, L +1 first switches, L +1 second switches and M +1 third switches, wherein L, M are positive integers which are larger than 1, L + M is equal to N, and N is the digit of the digital-to-analog converter; the L low-order weight capacitors, the low-order terminal capacitors and the high-order terminal capacitors are all Cu in capacitance value, the Cu is a unit capacitor, the L bridging capacitors are all 2Cu in capacitance value, and the L low-order weight capacitors are arranged as C from low to high according to weightL1、CL2、……、CLLThe M high-bit weight capacitors are arranged as C according to weight from low to highM1、CM2、……、CMM(ii) a The M high-order weight capacitors CM1、CM2、……、CMMRespectively 20Cu and 21Cu、……、2M-1Cu；
The first connection ends of the L low-order weight capacitors and the first connection ends of the low-order terminal capacitors are respectively connected with a reference voltage or a ground voltage through the L +1 first switches; the second connection ends of the L low-order weight capacitors and the second connection end of the high-order terminal capacitor are respectively connected with a common-mode voltage through the L +1 second switches; the second connecting end of the low-level terminal capacitor is connected with the lowest low-level weight capacitor CL1To (1) aA second connecting end; one bridging capacitor and the highest low-order weight capacitor C are connected between the second connecting ends of the low-order weight capacitors of every two adjacent bitsLLThe second connection terminal of the high-order terminal capacitor and the second connection terminal of the high-order terminal capacitor are connected with one bridging capacitor; the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are respectively connected with input voltage, reference voltage or ground voltage through the M +1 third switches, and the second connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are connected with the output end of the digital-to-analog converter;
when the digital-to-analog converter is reset, the L +1 second switches are all closed, the L +1 first switches are all connected to the ground voltage, and the M +1 third switches are all connected to the input voltage; after the digital-to-analog converter is reset, all the L +1 second switches are switched off, all the L +1 first switches and all the M +1 third switches are connected to the ground voltage, and the digital-to-analog converter performs sampling.
Specifically, the lower electrode plates of the low-order terminal capacitor, the high-order terminal capacitor, the L low-order weight capacitors, the L bridging capacitors, and the M high-order weight capacitors serve as first connection ends, and the upper electrode plate serves as a second connection end.
The analog-to-digital converter formed based on the digital-to-analog converter provided by the invention comprises a single-ended input analog-to-digital converter and a fully differential input analog-to-digital converter, wherein the technical scheme of the single-ended input analog-to-digital converter is as follows:
a single-ended input analog-to-digital converter comprises a digital-to-analog converter, a comparator and a logic module, wherein the digital-to-analog converter comprises 1 low-order terminal capacitor, 1 high-order terminal capacitor, L low-order weight capacitors, L bridging capacitors, M high-order weight capacitors, L +1 first switches, L +1 second switches and M +1 third switches, L, M are positive integers larger than 1, L + M is equal to N, and N is the digit of the analog-to-digital converter; the L low-order weight capacitors, the low-order terminal capacitors and the high-order terminal capacitors are all Cu in capacitance value, the Cu is a unit capacitor, the L bridging capacitors are all 2Cu in capacitance value, and the L low-order weight capacitors are arranged as C from low to high according to weightL1、CL2、……、CLLThe M high-bit weight capacitors are arranged as C according to weight from low to highM1、CM2、……、CMM(ii) a The M high-order weight capacitors are CM1、CM2、……、CMMRespectively 20Cu and 21Cu、……、2M-1Cu；
The first connection ends of the L low-order weight capacitors and the first connection ends of the low-order terminal capacitors are respectively connected with a reference voltage or a ground voltage through the L +1 first switches; the second connection ends of the L low-order weight capacitors and the second connection end of the high-order terminal capacitor are respectively connected with a common-mode voltage through the L +1 second switches; the second connecting end of the low-level terminal capacitor is connected with the lowest low-level weight capacitor CL1A second connection end of (a); one bridging capacitor and the highest low-order weight capacitor C are connected between the second connecting ends of the low-order weight capacitors of every two adjacent bitsLLThe second connection terminal of the high-order terminal capacitor and the second connection terminal of the high-order terminal capacitor are connected with one bridging capacitor; the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are respectively connected with input voltage, reference voltage or ground voltage through the M +1 third switches, and the second connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are connected with the output end of the digital-to-analog converter;
the comparator is used for comparing the voltage of the output end of the digital-to-analog converter with the common-mode voltage, and the generated comparison result is used for guiding the logic module to control each switch in the digital-to-analog converter in the quantization process; at the beginning of quantization, the logic module controls to close all the L +1 second switches, all the L +1 first switches are connected to a ground voltage, and all the M +1 third switches are connected to an input voltage; after the reset is finished, the logic module controls to disconnect all the L +1 second switches, all the L +1 first switches and all the M +1 third switches are connected to the ground voltage, and the digital-to-analog converter samples input signals.
The technical scheme of the fully differential input analog-to-digital converter is as follows:
fully differential transmissionThe analog-to-digital converter comprises a digital-to-analog converter, a comparator and a logic module, wherein the digital-to-analog converter comprises two switched capacitor arrays, and each switched capacitor array comprises 1 low-order terminal capacitor, 1 high-order terminal capacitor, L low-order weight capacitors, L bridging capacitors, M high-order weight capacitors, L +1 first switches, L +1 second switches and M +1 third switches, wherein L, M are positive integers larger than 1, L + M is equal to N, and N is the digit of the analog-to-digital converter; the L low-order weight capacitors, the low-order terminal capacitors and the high-order terminal capacitors are all Cu in capacitance value, the Cu is a unit capacitor, the L bridging capacitors are all 2Cu in capacitance value, and the L low-order weight capacitors are arranged as C from low to high according to weightL1、CL2、……、CLLThe M high-bit weight capacitors are arranged as C according to weight from low to highM1、CM2、……、CMM(ii) a The M high-order weight capacitors are CM1、CM2、……、CMMRespectively 20Cu and 21Cu、……、2M-1Cu；
The first connection ends of the L low-order weight capacitors and the first connection ends of the low-order terminal capacitors are respectively connected with a reference voltage or a ground voltage through the L +1 first switches; the second connection ends of the L low-order weight capacitors and the second connection end of the high-order terminal capacitor are respectively connected with a common-mode voltage through the L +1 second switches; the second connecting end of the low-level terminal capacitor is connected with the lowest low-level weight capacitor CL1A second connection end of (a); one bridging capacitor and the highest low-order weight capacitor C are connected between the second connecting ends of the low-order weight capacitors of every two adjacent bitsLLThe second connection terminal of the high-order terminal capacitor and the second connection terminal of the high-order terminal capacitor are connected with one bridging capacitor;
the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors in the first switched capacitor array are respectively connected with a forward input voltage, a reference voltage or a ground voltage through the M +1 third switches, and the second connection ends of the high-order terminal capacitors are connected with a forward input end of the comparator;
the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order termination capacitors in the second switched capacitor array are respectively connected with a negative input voltage, a reference voltage or a ground voltage through the M +1 third switches, and the second connection ends of the M high-order weight capacitors and the first connection ends of the high-order termination capacitors are connected with a negative input end of the comparator;
the comparator is used for comparing the voltage of the positive input end with the voltage of the negative input end, and the generated comparison result is used for guiding the logic module to control each switch in the digital-to-analog converter in the quantization process; at the beginning of quantization, the logic module is configured to control the L +1 second switches of both of the switched-capacitor arrays to be closed, the L +1 first switches to be connected to a ground voltage, and control the M +1 third switches of a first one of the switched-capacitor arrays to be connected to a positive input voltage and control the M +1 third switches of a second one of the switched-capacitor arrays to be connected to a negative input voltage; after the reset is finished, the logic module controls the L +1 second switches in the two switched capacitor arrays to be disconnected, the L +1 first switches and the M +1 third switches are connected to the ground voltage, and the digital-to-analog converter samples input signals.
The invention has the beneficial effects that: the digital-to-analog converter is formed by the low-order C2C capacitor array and the high-order binary capacitor array, and has the characteristics of small area and low power consumption. And the invention combines the reset and sampling method, proposes the mode of sampling without sampling at the low position, adding a one-bit terminal capacitor at the high position, and only one reset switch of the upper polar plate at the high position affects the voltage information of sampling in the sampling process, which not only reduces kT/C noise, but also eliminates the possibility of error of sampling information, solves the problems of high noise of the traditional C2C + binary capacitor array and the reliability problem of disordered input voltage sampling caused by the fact that the reset switches cannot be turned off at the same time because a plurality of nodes are introduced into the C2C structure, has the advantages of low power consumption, low noise and high reliability, and can be applied to the image sensor. In the embodiment, the upper polar plate with smaller parasitic capacitance is connected with the input of the comparator by adopting a lower polar plate sampling mode, so that the influence of the parasitic capacitance on the linearity in the quantization process is reduced. When the digital-to-analog converter provided by the invention is applied to form the analog-to-digital converter, the capacitor area is reduced by using the C2C capacitor structure, and the quantization is performed by using the monotonic switch switching mode, so that the switching times of the capacitor switches in two groups of switched capacitor arrays of the fully differential input structure can be reduced, and the power consumption of the DAC is further reduced.
Drawings
Fig. 1 is a schematic circuit diagram of a digital-to-analog converter with low power consumption and low noise according to a first embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of an analog-to-digital converter with low power consumption and low noise according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The invention provides a digital-to-analog converter for realizing low power consumption and low noise, which comprises an L-bit C2C capacitor array as a low bit and an M-bit traditional binary capacitor array as a high bit, wherein the total bit number N is L + M, L, M is a positive integer larger than 1, the division of the low bit and the high bit in the digital-to-analog converter is determined by the values of L and M, and for the N-bit digital-to-analog converter, the larger the value of L is, the smaller the number of capacitors is, and the smaller the area is.
The low-order C2C capacitor array comprises 1 low-order terminalCapacitor CT_LSBL low-weight capacitors CL1、CL2、……、CLLAnd L bridge capacitors CS1、CS2、……、CSLThe high-order binary capacitor array comprises 1 high-order terminal capacitor CT_MSBAnd M high-weight capacitors CM1、CM2、……、CMM. The capacitance value of each capacitor in the digital-to-analog converter is measured by a unit capacitor Cu, and L low-weight capacitors CL1、CL2、……、CLLLow terminal capacitor CT_LSBAnd a high-order terminal capacitor CT_MSBThe capacitance values of (1) are unit capacitance Cu and L bridging capacitances CS1、CS2、……、CSLAll the capacitance values of (1) are 2 XCu, M high-order weight capacitors CM1、CM2、CM3、……、CMMThe capacitance values of the two capacitors are 20Cu and 2 in turn from low to high according to the weight1Cu、22Cu、……、2M-1Cu, i.e. Cu, 2 XCu, 4 XCu, 8 XCu … … 2(M-1)×Cu。
Arranging L low-bit weight capacitors into C according to weight from low to highL1、CL2、……、CLLLow terminal capacitance CT_LSBLow-order weight capacitor C arranged at lowest orderL1Then the lowest weighted capacitor CL1Parallel low-order terminal capacitor CT_LSBThe second connecting end is connected with the lowest low-level weight capacitor CL1A second connection end of (a); high-order terminal capacitor CT_MSBA weight capacitor C arranged at the highest position and lower positionLLThen, L second connection terminals of low-order weight capacitors and high-order terminal capacitor CT_MSBThe second connecting ends of the first and second connecting ends are respectively used as a node and have L +1 nodes. In this embodiment, the lower plate of the capacitor is used as the first connection end, and the upper plate is used as the second connection end, so that L low-weight capacitors C in the low-weight C2C capacitor arrayL1、CL2、……、CLLAnd a high-order terminal capacitor CT_MSBThe upper electrode plate of the capacitor has L +1 nodes, and a bridging capacitor with the capacitance value of 2 multiplied by Cu, namely the lowest-order low-order weight capacitor C is inserted into every two adjacent nodesL1Upper pole plate and secondary pole plateLow-order low-weight capacitor CL2A bridging capacitor C is inserted between the upper platesS1A sub-low-order weight capacitor CL2Upper plate and third low-order low-weight capacitor CL3A bridging capacitor C is inserted between the upper platesS2… …, highest low-weight capacitor CLLUpper plate and high-order terminal capacitor CT_MSBA bridging capacitor C is inserted between the upper platesSLAnd L bridging capacitors. High-order terminal capacitor CT_MSBM high-order weight capacitors C of high-order binary capacitor arrayM1、CM2、……、CMMM high-order weight capacitors C of high-order binary capacitor array all connected in parallelM1、CM2、……、CMMAnd the lower weight capacitor C of the highest bit in the lower C2C capacitor arrayLLVia the highest bridging capacitance CSLAnd (4) connecting.
The digital-to-analog converter further comprises L +1 first switches, L +1 second switches and M +1 third switches, wherein the second switches are used as reset switches, the first switches control the capacitance switching of the low-order C2C capacitor array, and the third switches control the capacitance switching of the high-order binary capacitor array. The L +1 nodes are respectively connected with a common-mode voltage V through L +1 second switchesCMReset, L low-weight capacitors CL1、CL2、……、CLLFirst connection terminal and low-order terminal capacitor CT_LSBThe first connection end is respectively connected with a reference voltage Vref or a ground voltage GND through L +1 first switches, and M high-level weight capacitors CM1、CM2、……、CMMFirst connection terminal and high-order terminal capacitor CT_MSBThe first connection end of the voltage regulator is connected with an input voltage, a reference voltage Verf or a ground voltage GND through M +1 third switches respectively, and the second connection end of the voltage regulator is connected with the output end of the digital-to-analog converter.
The digital-to-analog converter comprises a single-ended input structure and a fully differential input structure, wherein the single-ended input structure comprises a group of low-order C2C capacitor arrays, a group of high-order binary capacitor arrays and M high-order weight capacitors CM1、CM2、……、CMMAnd is highBit terminal capacitance CT_MSBThe output voltage V of the digital-to-analog converter is connected with the input voltage through the control of the third switchdacAnd common mode voltage VCMA comparison is made. The fully differential input structure comprises two groups of low-order C2C capacitor arrays and two groups of high-order binary capacitor arrays, wherein the first group of low-order C2C capacitor arrays and the first group of high-order binary capacitor arrays form a P-end switched capacitor array, the second group of low-order C2C capacitor arrays and the second group of high-order binary capacitor arrays form an N-end switched capacitor array, and M high-order weight capacitors C in the P-end switched capacitor arrayM1、CM2、……、CMMAnd a high-order terminal capacitor CT_MSBControl and forward input voltage V through third switchipConnected to produce a forward output voltage V at an output terminaldacpN-terminal M high-order weight capacitors C in switched capacitor arrayM1、CM2、……、CMMAnd a high-order terminal capacitor CT_MSBControl by a third switch and a negative input voltage VinConnected to produce a negative output voltage V at the outputdacn. Digital-to-analog converter with fully differential input structure, two paths of forward output voltage V generated after sampling and holdingdacpAnd a negative output voltage VdacnThe digital code values are respectively input from two ends of the comparator, are generated after the comparator is compared for the first time, and control corresponding switches in the digital-to-analog converter to switch so as to correspondingly change the weight value VdacnAnd VdacpAnd continuously comparing, and finally achieving the purpose of successive approximation of the input analog voltage value through multiple comparison and switching. The fully differential input structure is used for ensuring that the change of the output common-mode voltage is maintained in a small range under the condition of using a monotone switch switching mode, and the influence on the input offset of the comparator is reduced.
The upper electrode plates of all capacitors in a group of switched capacitor arrays of a digital-to-analog converter DAC have L +1 nodes, the L +1 nodes need to be reset after each quantization period is finished so as to wait for charge redistribution under sampling of the next period, and the L +1 nodes are connected to a common-mode voltage V through reset switches (namely L +1 second switches)CMTo avoid the node voltage from being unstable and ensure each timeThe voltage is accurate after one-time sampling and holding. In the embodiment, the lower plate of the capacitor is used as the first connecting end for sampling, the upper plate is used as the second connecting end for resetting, the parasitic capacitance of the upper plate is small, the sampling of the lower plate can reduce the influence on the input swing of the comparator, and the influence of the parasitic capacitance on the linearity of the ADC is also reduced. The lower plate of the DAC capacitor array is selectively connected to an input voltage and a reference voltage V through a switchrefOr ground potential GND, and the output code value generated after comparison of the comparator controls the switching of the corresponding weight capacitor, so that VdacSuccessive approximation inputs analog voltage values.
The invention provides a new reset and sampling mode, which ensures that all high-order capacitors in a switched capacitor array of a digital-to-analog converter DAC participate in sampling, and low-order capacitors do not participate in sampling, so that the high-order capacitors have to be introduced into a one-order terminal capacitor in the sampling mode, and the number of the sampling capacitors is ensured to be 2NThereby slightly changing the output voltage VdacA certain gain error is introduced, but this sampling is necessary for the hybrid structure of C2C + conventional binary proposed by the present invention for the following reasons.
First, if sampling is performed from the lowest upper plate, the capacitance value of the sampling capacitor is equivalent to the lower terminal capacitor C of one unit capacitor CuT_LSBA low-weight capacitor C connected with a unit capacitor CuL1The equivalent resistor is connected in parallel and then connected in series with other equivalent capacitors, the series-parallel relation of the capacitors is easy to obtain, the equivalent resistor does not exceed the capacitance value of 2 multiplied by Cu of the bridging capacitor, so the capacitance value of the sampling capacitor does not exceed 2 multiplied by Cu, and the kT/C noise of the upper plate sampling mode is very large and is difficult to meet the requirements of the ADC.
Secondly, if all the weighted capacitances are sampled, there is also a problem that is difficult to solve, and this problem is caused by the upper plate reset switch. The C2C capacitor structure inevitably introduces a plurality of nodes on the upper plate, and after one quantization period is finished, the nodes are all reset to the common mode voltage VCMIdeally, the potentials of the nodes are all set to a common mode voltage VCMRear, capacitor arrayThe input voltage Vt1 at the time t1 starts to be sampled, and then the nodes of the upper plate are simultaneously turned off, and the lower plate is grounded, thereby completing the sampling operation. However, because a plurality of nodes are introduced into the C2C structure, the required reset switches are increased, and because of the inconsistency of MOS transistor parameters in actual manufacturing and the influence of delay in a signal path, it is difficult to simultaneously open the lower plate after the voltage Vt1 is connected, if one of the switches is not opened at the time t1 but is opened at the time t2, the voltage Vt2 at the time t2 is obtained as the sampling of the weight capacitance corresponding to the reset switch, which causes the problem that the voltage sampled by the switch capacitance array of the whole DAC is disordered, that is, if all the weight capacitances are sampled (i.e. the weight capacitances of the low-bit C2C capacitance array are also involved in sampling), the plurality of reset switches connected to the plurality of nodes introduced into the C2C structure cannot be guaranteed to be simultaneously opened, so that the collected voltage is not the voltage input at the same time, but may be the input voltage at the time t + Δ t, although Δ t is small, erroneous acquisition of the input voltage can cause the comparator's comparison and the overall quantization result to lose reliability.
Based on the analysis, the invention provides a new sampling and resetting mode, namely, the low position does not carry out sampling, and the high position is added with a one-position terminal capacitor to carry out sampling, so that the sampling mode not only ensures that the sampling capacitor is large enough, but also reduces the kT/C noise because the capacitance value is parallel connection of the high position capacitor; and only one reset switch (namely, a high-order terminal capacitor C) of the high-order upper polar plate is connected in the sampling processT_MSBA second switch of the second connection) affects the sampled voltage information, eliminating the possibility of errors in the sampled information. Thereby increasing a high-terminal capacitance CT_MSBIn order to ensure that the voltages participating in sampling meet the power term of 2, the weighted voltages from the high order to the low order are 1/2, 1/4, 1/8 and 1/16 … 1/(2) of the initial Vdac at the output end after sample and holdM) Double, even if doing so would introduce an item 2M/(2M+1) gain error. In addition, the upper polar plate with smaller parasitic capacitance can be connected with the input of the comparator by the lower polar plate sampling, and the influence of the parasitic capacitance on the linearity in the quantization process is reduced.
The following describes a sampling method and a quantization method of applying the digital-to-analog converter of the present invention to an analog-to-digital converter with single-ended input and an analog-to-digital converter with fully differential input, with reference to two embodiments.
Example one
Fig. 1 is a schematic structural diagram of an analog-to-digital converter with single-ended input, in which a 6+6 segmented structure is adopted in the present embodiment, and includes a 6-bit C2C capacitor array as a low bit and a 6-bit conventional binary capacitor array as a high bit, and the total number of bits is 12 bits. Specifically comprises 1 low-order terminal capacitor CT_LSB6 low-weight capacitors C of C2C partL1-CL66 bridge capacitors C of C2C partS1-CS6A high-order terminal capacitor CT_MSBAnd 6 high-order weight capacitors C of conventional binary partM1-CM66 low-weight capacitors CL1-CL6The upper electrode plate is respectively node (I) -sixth, low terminal capacitance CT_LSBThe upper electrode plate of (C) is also connected with a node (I), and a high-level terminal capacitor (C)T_MSBUpper plate of and 6 high-order weight capacitors CM1-CM6The upper electrode plates are connected together to serve as a node (c), so that the upper electrode plates of all capacitors have 7 nodes (c-c), and the nodes (c-c) are connected to a common-mode voltage (V) through 7 reset switches (i.e. second switches) respectivelyCMLow terminal capacitance CT_LSBAnd 6 low-weight capacitors CL1-CL6The lower polar plate is respectively connected with a reference voltage V through 7 first switchesrefOr ground voltage GND connection, high-order terminal capacitor CT_MSBAnd 6 high-weight capacitors CM1-CM6The lower polar plate is respectively connected with an input capacitor V through 7 third switchesinReference voltage VrefOr ground voltage GND.
The capacitance value of the capacitor in the digital-to-analog conversion structure is measured by a unit capacitor Cu, wherein 6 low-order weight capacitors C of a low-order C2C partL1-CL6Low terminal capacitor CT_LSBAnd a high-order terminal capacitor CT_MSBThe capacitance values are unit capacitance Cu, and the bridging capacitance C of the lower C2C partS1-CS6Capacity of2 × Cu, thus a low-order terminal capacitance CT_LSBAnd the lowest bit low weight capacitor CL1Parallel connection equivalent to 2 × Cu, and then with a bridging capacitor CS1Serially connected to be equivalent to Cu, and then connected to a low-weight capacitor CL2Parallel connection, equivalent to 2 × Cu, … …, so that all capacitances (including the low terminal capacitance C) of the entire low C2C capacitor arrayT_LSB6 low-weight capacitors CL1-CL6And 6 bridge capacitors CS1-CS6) Can be equivalent to a unit capacitor Cu and can serve as a terminal capacitor of a conventional binary DAC array. 6 high-order weight capacitors C of high-order traditional binary capacitor arrayM1-CM6Cu, 2 xCu, 4 xCu, 8 xCu, 16 xCu, and 32 xCu in the order of weight from low to high. A bridging capacitor C with the capacitance value of 2 multiplied by Cu is inserted between every two adjacent nodes of 7 nodes of the upper polar plateS1-CS6Low terminal capacitance CT_LSBAnd the lowest bit low weight capacitor CL1Parallel high-order terminal capacitor CT_MSBAnd 6 high-weight capacitors CM1-CM6All in parallel, all high-order capacitors (C)T_MSBAnd CM1-CM6) And the lower weight capacitor C of the highest bit in the lower C2C capacitor arrayL6Via the highest bridging capacitance CS6Connected and all high-order capacitors (C)T_MSBAnd CM1-CM6) The upper plate of the comparator is connected to the input end of the comparator and the common-mode voltage VCMA comparison is made. In the embodiment, the upper plate of the DAC array has 7 nodes, the 7 nodes need to be reset after each quantization period is finished so as to be subjected to charge redistribution under the sampling of the next period, and all the nodes are connected to a common-mode voltage VCMThe reset switch of the electric potential to avoid the indefinite state of the node voltage, guarantee the accuracy of the quantized result. The capacitor uses the lower polar plate for sampling, the low-level capacitor does not participate in the sampling, and the high-level weight capacitor CM1-CM6And a high-order terminal capacitor CT_MSBInvolving sampling, the lower plate of which is selectively connected to the input voltage V by means of a changeover switchinReference voltage VrefOr ground potential GND, and the output code value generated after comparison of the comparator controls the switching of the corresponding weight capacitor, so thatVdacSuccessive approximation inputs analog voltage values.
When the previous quantization period is finished and a new quantization period is started, all reset switches of all nodes (i-c) of the upper electrode plate of the capacitor array are closed, and the potential of each node is reset to the common-mode voltage VCMLow terminal capacitance CT_LSBAnd a low-weight capacitor CL1-CL6A ground potential GND of the lower plate and a high-level terminal capacitor CT_MSBAnd a high-weight capacitor CM1-CM6The lower polar plate is connected with an input signal VinAnd when the reset switches of the nodes (r) -c at the time t0 are all turned off, the upper electrode plate retains the information of the V (t0) at the time t0, and then the lower electrode plate has all ground potential GND, and the initial V (V) of the nodes (r) -c can be calculateddac: (denoted Vo1-Vo 7)
Figure BDA0002771299810000101
The above equations can be obtained by simultaneous
Figure BDA0002771299810000102
From the above formula, the invention provides a sampling mode of low-order non-sampling and high-order sampling to increase the high-order terminal capacitance CT_MSBIntroducing gain error 64/65, but for common mode voltage VCMNo influence is produced. The weight of each capacitor from the highest bit to the lowest bit is calculated from the voltage of each node and is respectively
Figure BDA0002771299810000103
The binary proportional relation is still satisfied, and only the coefficient 64/65 is introduced, so that the linearity and the accuracy of the quantization result are ensured.
After the accuracy of the weight is verified, the quantization stage is entered, the quantization mode can adopt various existing suitable quantization methods, the quantization mode of the analog-to-digital converter in this embodiment adopts a monotonic switch switching capacitance type, and first, the highest high-order weight capacitor C is usedM6Switching of the lower plate switchReference voltage VrefAt this time, the voltage V at the input end of the comparatordacBecome into
Figure BDA0002771299810000104
Figure BDA0002771299810000105
Irrespective of common mode level VCMI.e. by
Figure BDA0002771299810000106
Compare to 0. If it is not
Figure BDA0002771299810000107
The next highest order high-weight capacitor CM5Switching of the lower plate switch to a reference voltage VrefAt this time, the voltage at the input terminal of the comparator becomes
Figure BDA0002771299810000108
If it is not
Figure BDA0002771299810000109
The highest bit weight capacitor CM6The lower plate switch is switched back to GND, the next higher high-order weight capacitor CM5The lower plate switch is switched to a reference voltage VrefAt this time, the voltage at the input terminal of the comparator becomes
Figure BDA0002771299810000111
Comparing with 0, and so on, that is, the result of the whole successive approximation is monotonously increased and gradually approaches from 0 to
Figure BDA0002771299810000112
Thereby completing one quantization cycle of the SAR ADC.
Example two
Fig. 2 is a schematic structural diagram of an analog-to-digital converter using the digital-to-analog converter of the present invention to form a fully differential input, in this embodiment, a 6+6 segmented structure is also adopted, the digital-to-analog conversion structure of this embodiment adopts a fully differential input form to sample a fully differential input signal, so as to ensure that common mode level variation at two ends of a comparator is maintained within a small range, the digital-to-analog converter includes two sets of switched capacitor arrays, each set of switched capacitor array includes a 6-bit C2C capacitor array as a low bit, and a 6-bit conventional binary capacitor array as a high bit, the total number of bits is 12 bits.
The upper pole plate of the P-end switch capacitor array has 7 nodes, the upper pole plate of the N-end switch capacitor array also has 7 nodes, 14 nodes are reset after each quantization period is finished so as to redistribute the charge sampled in the next period, and all the nodes are connected to a common mode level VCMThe reset switch of (2) to avoid the unstable state of the node voltage and keep the accuracy of the quantization result. The capacitors are sampled by using a lower polar plate, low-order capacitors do not participate in sampling, high-order weight capacitors and high-order terminal capacitors of two groups of switched capacitor arrays participate in sampling, and high-order weight capacitors C in the P-end switched capacitor arrayM1-CM6And a high-order terminal capacitor CT_MSBThe lower plate is selectively connected to a forward input voltage V by a switchipReference voltage VrefOr ground GND having an output connected to the comparator at a voltage VdacpHigh-order weight capacitor C in N-terminal switch capacitor arrayM1-CM6And a high-order terminal capacitor CT_MSBThe lower plate is selectively connected to a negative input voltage V by a switchinReference voltage VrefOr ground GND having an output connected to the comparator at a voltage VdacnComparator comparison VdacpAnd VdacnThe output code value generated later controls the switching of the corresponding weight capacitor, so that Vdacp-VdacnApproaching zero, the generated digital code successively approximates the input analog voltage value.
Let the input analog voltage value be ViWith two inputs each being Vip＝Vi/2，Vin＝-ViAnd/2, all reset switches are closed during sampling, so that the voltage of each node is set to the common-mode voltage VCMLow-order weight capacitorCL1-CL6The lower polar plate is connected to the ground potential GND, and the high-level weight capacitors C of the two groups of switched capacitor arraysM1-CM6The lower pole plates are respectively connected to VinAnd VipThen the reset switch is turned off, the information of the input signal is retained on the upper plate of the capacitor, then all the weighted capacitors and the lower plate of the terminal capacitor are at the ground potential GND, the initial state of the DAC is established, and the DAC can be obtained by an equation set obtained by inputting the column at one end in the figure 1, and at the moment
Figure BDA0002771299810000113
Figure BDA0002771299810000114
The comparator makes a first comparison if Vdacp>Vdacn, then VdacnThe highest-order high-order weight capacitor C of the N-terminal switch capacitor array needs to be increasedM6Switching the lower plate to a reference voltage VrefAt this time
Figure BDA0002771299810000115
Figure BDA0002771299810000116
Making a second comparison if Vdacp<Vdacn, then VdacpThe next highest-order high-order weight capacitor C of the P-terminal switch capacitor array needs to be increasedM5Switching the lower plate to a reference voltage VrefAt this time
Figure BDA0002771299810000117
Figure BDA0002771299810000121
By analogy, gradually Vdacp-VdacnApproaching zero, the generated digital code corresponds to the analog input voltage value Vi. It can be seen that the DAC with the monotonic switch switching only has one bit of capacitor on one side for switching at each time, the switching times are much less than those of the traditional bottom plate sampling DAC, and the average power consumption is also obviously reduced.
In summary, the invention provides a group of DAC structures of C2C + binary mixed DAC, and adds a reset switch to each node, so as to eliminate the unstable state of the node voltage and ensure the accuracy of the voltage of the mixed DAC structure after sampling and holding; the weight capacitor of the low-order C2C capacitor array does not participate in sampling, the weight capacitor of the high-order binary capacitor array participates in sampling, the problem of disordered sampling of input voltage caused by the fact that reset switches at a plurality of nodes introduced by a C2C capacitor unit cannot be turned off at the same time is solved, and the sampling capacitor is the sum of all traditional binary capacitor arrays, so that the DAC has low sampling noise and the kT/C noise is reduced; the digital-to-analog converter has the advantages of greatly reducing the capacitance area and low power consumption of a C2C + binary mixed DAC structure, solves the problem of disordered input voltage sampling implied by the mixed DAC structure, simultaneously realizes low kT/C noise, and reduces the switching times of fully-differential input double-row capacitance switches and further reduces the power consumption by using a monotonic switch switching mode on the digital-to-analog conversion structure.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (4)

1. A digital-to-analog converter for realizing low power consumption and low noise is characterized by comprising 1 low-order terminal capacitor, 1 high-order terminal capacitor, L low-order weight capacitors, L bridge capacitors, M high-order weight capacitors, L +1 first switches, L +1 second switches and M +1 third switches, wherein L, M are positive integers larger than 1, L + M is N, and N is the digit of the digital-to-analog converter; the L low-order weight capacitors, the low-order terminal capacitors and the high-order terminal capacitors are all Cu in capacitance value, the Cu is a unit capacitor, the L bridging capacitors are all 2Cu in capacitance value, and the L low-order weight capacitors are arranged as C from low to high according to weightL1、CL2、……、CLLThe M high-bit weight capacitors are arranged as C according to weight from low to highM1、CM2、……、CMM(ii) a The M high-order weight capacitors CM1、CM2、……、CMMRespectively is 20Cu、21Cu、……、2M-1Cu；
The first connection ends of the L low-order weight capacitors and the first connection ends of the low-order terminal capacitors are respectively connected with a reference voltage or a ground voltage through the L +1 first switches; the second connection ends of the L low-order weight capacitors and the second connection end of the high-order terminal capacitor are respectively connected with a common-mode voltage through the L +1 second switches; the second connecting end of the low-level terminal capacitor is connected with the lowest low-level weight capacitor CL1A second connection end of (a); one bridging capacitor and the highest low-order weight capacitor C are connected between the second connecting ends of the low-order weight capacitors of every two adjacent bitsLLThe second connection terminal of the high-order terminal capacitor and the second connection terminal of the high-order terminal capacitor are connected with one bridging capacitor; the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are respectively connected with input voltage, reference voltage or ground voltage through the M +1 third switches, and the second connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are connected with the output end of the digital-to-analog converter;
when the digital-to-analog converter is reset, the L +1 second switches are all closed, the L +1 first switches are all connected to the ground voltage, and the M +1 third switches are all connected to the input voltage; after the digital-to-analog converter is reset, all the L +1 second switches are switched off, all the L +1 first switches and all the M +1 third switches are connected to the ground voltage, and the digital-to-analog converter performs sampling.
2. The DAC with low power consumption and low noise as claimed in claim 1, wherein the lower plate of the low-side termination capacitor, the high-side termination capacitor, the L low-side weighting capacitors, the L bridge capacitors and the M high-side weighting capacitors is used as the first connection terminal, and the upper plate is used as the second connection terminal.
3. A single-ended input analog-to-digital converter comprises a digital-to-analog converter, a comparator and a logic module, and is characterized in thatThe digital-to-analog converter comprises 1 low-order terminal capacitor, 1 high-order terminal capacitor, L low-order weight capacitors, L bridging capacitors, M high-order weight capacitors, L +1 first switches, L +1 second switches and M +1 third switches, wherein L, M are positive integers larger than 1, L + M is N, and N is the digit of the analog-to-digital converter; the L low-order weight capacitors, the low-order terminal capacitors and the high-order terminal capacitors are all Cu in capacitance value, the Cu is a unit capacitor, the L bridging capacitors are all 2Cu in capacitance value, and the L low-order weight capacitors are arranged as C from low to high according to weightL1、CL2、……、CLLThe M high-bit weight capacitors are arranged as C according to weight from low to highM1、CM2、……、CMM(ii) a The M high-order weight capacitors are CM1、CM2、……、CMMRespectively is 20Cu、21Cu、……、2M-1Cu；
The first connection ends of the L low-order weight capacitors and the first connection ends of the low-order terminal capacitors are respectively connected with a reference voltage or a ground voltage through the L +1 first switches; the second connection ends of the L low-order weight capacitors and the second connection end of the high-order terminal capacitor are respectively connected with a common-mode voltage through the L +1 second switches; the second connecting end of the low-level terminal capacitor is connected with the lowest low-level weight capacitor CL1A second connection end of (a); one bridging capacitor and the highest low-order weight capacitor C are connected between the second connecting ends of the low-order weight capacitors of every two adjacent bitsLLThe second connection terminal of the high-order terminal capacitor and the second connection terminal of the high-order terminal capacitor are connected with one bridging capacitor; the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are respectively connected with input voltage, reference voltage or ground voltage through the M +1 third switches, and the second connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors are connected with the output end of the digital-to-analog converter;
the comparator is used for comparing the voltage of the output end of the digital-to-analog converter with the common-mode voltage, and the generated comparison result is used for guiding the logic module to control each switch in the digital-to-analog converter in the quantization process; at the beginning of quantization, the logic module controls to close all the L +1 second switches, all the L +1 first switches are connected to a ground voltage, and all the M +1 third switches are connected to an input voltage; after the reset is finished, the logic module controls to disconnect all the L +1 second switches, all the L +1 first switches and all the M +1 third switches are connected to the ground voltage, and the digital-to-analog converter samples input signals.
4. A fully differential input analog-to-digital converter comprises a digital-to-analog converter, a comparator and a logic module, and is characterized in that the digital-to-analog converter comprises two switched capacitor arrays, and the switched capacitor arrays comprise 1 low-order terminal capacitor, 1 high-order terminal capacitor, L low-order weight capacitors, L bridging capacitors, M high-order weight capacitors, L +1 first switches, L +1 second switches and M +1 third switches, wherein L, M are positive integers greater than 1, L + M is N, and N is the digit of the analog-to-digital converter; the L low-order weight capacitors, the low-order terminal capacitors and the high-order terminal capacitors are all Cu in capacitance value, the Cu is a unit capacitor, the L bridging capacitors are all 2Cu in capacitance value, and the L low-order weight capacitors are arranged as C from low to high according to weightL1、CL2、……、CLLThe M high-bit weight capacitors are arranged as C according to weight from low to highM1、CM2、……、CMM(ii) a The M high-order weight capacitors are CM1、CM2、……、CMMRespectively is 20Cu、21Cu、……、2M-1Cu；
The first connection ends of the L low-order weight capacitors and the first connection ends of the low-order terminal capacitors are respectively connected with a reference voltage or a ground voltage through the L +1 first switches; the second connection ends of the L low-order weight capacitors and the second connection end of the high-order terminal capacitor are respectively connected with a common-mode voltage through the L +1 second switches; the second connecting end of the low-level terminal capacitor is connected with the lowest low-level weight capacitor CL1A second connection end of (a); every two adjacent bits of the lowOne bridging capacitor and the highest low-order weight capacitor C are connected between the second connecting ends of the bit weight capacitorsLLThe second connection terminal of the high-order terminal capacitor and the second connection terminal of the high-order terminal capacitor are connected with one bridging capacitor;
the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order terminal capacitors in the first switched capacitor array are respectively connected with a forward input voltage, a reference voltage or a ground voltage through the M +1 third switches, and the second connection ends of the high-order terminal capacitors are connected with a forward input end of the comparator;
the first connection ends of the M high-order weight capacitors and the first connection ends of the high-order termination capacitors in the second switched capacitor array are respectively connected with a negative input voltage, a reference voltage or a ground voltage through the M +1 third switches, and the second connection ends of the M high-order weight capacitors and the first connection ends of the high-order termination capacitors are connected with a negative input end of the comparator;
the comparator is used for comparing the voltage of the positive input end with the voltage of the negative input end, and the generated comparison result is used for guiding the logic module to control each switch in the digital-to-analog converter in the quantization process; at the beginning of quantization, the logic module is configured to control the L +1 second switches of both of the switched-capacitor arrays to be closed, the L +1 first switches to be connected to a ground voltage, and control the M +1 third switches of a first one of the switched-capacitor arrays to be connected to a positive input voltage and control the M +1 third switches of a second one of the switched-capacitor arrays to be connected to a negative input voltage; after the reset is finished, the logic module controls the L +1 second switches in the two switched capacitor arrays to be disconnected, the L +1 first switches and the M +1 third switches are connected to the ground voltage, and the digital-to-analog converter samples input signals.
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