CN101534115A - Stepped capacitor array for a full binary weight capacitor - Google Patents

Abstract

The invention relates to a stepped capacitor array for a full binary weight capacitor in the technical field of an integrated circuit. The stepped capacitor array comprises a most significant bit capacitor array, a least significant bit capacitor array, a plurality of groups of stepped capacitor arrays, connecting capacitors, wherein a plurality of groups of the stepped capacitor arrays are connected between the most significant bit capacitor array and the least significant bit capacitor array; the connecting capacitors are arranged among the stepped capacitor arrays; the connecting capacitor completely consists of full binary weight multiples of a unit capacitor C0; all the binary weight capacitors connected with the next capacitor array in two capacitor arrays are connected in series, and two groups of the serially connected capacitor arrays are connected in parallel, thereby forming the connecting capacitor. The stepped capacitor array for the full binary weight capacitor avoids adopting non binary weight capacitance value, avoids the volume of the capacitor and area of a chip required in realization of a high accuracy analog-to-digital converter or digital-to-analog conversion, and relieves limit bottleneck matched among capacitors to a certain extent.

Description

The sectional capacitance array of full binary weight electric capacity

Technical field

What the present invention relates to is a kind of capacitor array of technical field of integrated circuits, and specifically, what relate to is a kind of sectional capacitance array of full binary weight electric capacity.

Background technology

The capacitor array of binary weight is the core of approaching comparison analog to digital converter (SAR-ADC) one by one, yet along with reducing of integrated circuit characteristic size, the increase of integrated level, realize high accuracy, at a high speed, low-power consumption, small size become the trend of chip design, and particular importance especially seems in realizing portable system and SOC system.In traditional analog to digital converter design, exist the balance between speed and precision, power consumption and the area, it is a kind of realization low-power consumption that binary system is weighed one by one comparator, the analog to digital converter of medium speed, precision always.But be subjected to the restriction of electric capacity matching precision always, can not realize high-precision design.

Find through retrieval prior art, James L.McCreary etc. are at " IEEE Journal OfSolid-State Circuits " (electric engineering solid-state electronic circuit periodical, deliver in December, 1975,371 pages of the 6th phases) " All-MOS Charge Redistribution Analog-to-DigitalConversion Techniques---Part I " (" the heavy modulus of distribution converter technology of full MOS electric charge---first ").Mention in the document and can adopt binary-weighted capacitor array to realize approaching one by one the modulus comparator, binary system balance capacitor array is made up of N binary weight electric capacity, is used for realizing the power voltage reference value.Yet this circuit structure is subjected to the coupling influence between the electric capacity, under limit match condition near modern integrated circuits technology electric capacity, probably can only realize the analog-to-digital conversion of 10 precision, simultaneously, this capacitor array needs very large capacitance to realize when realizing the high accuracy comparison, thereby consumes bigger chip area; Afterwards, people propose the thought of sectional capacitance array, Eugenio Culurciello etc. are at " IEEE Circuits andSystems, ISCAS ' 03.Proceeding of the 2003 International Symposium on " (electronic apparatus engineering circuit and system, international conference in 2003 progress publication, in May, 2003,301 to 304 pages of the 1st phases) " the An8-bit 1m W successive approximation ADC in SOICMOS " that delivers on is (a kind of based on realizing 8 on the silicon-on-insulator CMOS technology, the 1mW gradually-appoximant analog-digital converter), adopted the sectional capacitance array technique in this article, capacitor array is made up of M position MSB and L position LSB capacitor array, realizes the binary weight voltage of N=M+L position by connecting electric capacity.Though this circuit structure has been extenuated the bottleneck of chip area to a certain extent, but introduced the connection electric capacity of a nonbinary balance, this gives in the designs such as the coupling of electric capacity and domain and brings certain difficulty, because the electric capacity that the design nonbinary is weighed in the middle of actual process is the main bottleneck of this capacitor array.

In the requirement of gradually-appoximant analog-digital converter, need to realize the design of high accuracy and small size, need resolve the difficult design of the coupling of chip area and electric capacity, yet there is the trade-off problem of mating between chip area and the electric capacity in above-mentioned two technology.

Summary of the invention

The objective of the invention is to be directed to the deficiency of present technology, a kind of sectional capacitance array of full binary weight electric capacity is provided, avoid employing nonbinary power capacitance and avoided needed capacitance size and chip area when realizing high-precision adc or digital-to-analogue conversion, extenuated the limit bottleneck that mates between the electric capacity simultaneously to a certain extent.

The present invention is achieved by the following technical solutions, the present invention includes: highest significant position (MSB) capacitor array, least significant bit (LSB) capacitor array, be connected the multicomponent section capacitor array between highest significant position capacitor array and the least significant bit capacitor array, and the connection electric capacity between each sectional capacitance array (wherein for connecting the electric capacity of any two sections capacitor arrays), wherein the present invention's innovation is to connect electric capacity fully by specific capacitance C ₀The full binary weight multiple form, to connect electric capacity be by all the binary weight capacitances in series in next section capacitor array that connects in two sections capacitor arrays, its series capacitance carried out two groups again and in parallelly constitute.

The present invention represents the highest significant position capacitor array with symbol M, M-1 represents time significance bit capacitor array, M-2 represents time high significance bit capacitor array, L represents the least significant bit capacitor array, next stage capacitor array available symbols M-2 at M-1 significance bit capacitor array represents, being connected the middle any capacitor array of M capacitor array and L capacitor array represents with symbol i, the next capacitor array that promptly is connected the M capacitor array is the i=M-1 capacitor array, the next stage capacitor array that is connected M-1 significance bit capacitor array is the i=M-2 lattice array, at the next stage capacitor array that connects the M-2 capacitor array is the i=M-3 capacitor array, the next stage capacitor array that connects the M-3 capacitor array is the i=M-4 capacitor array, the next stage capacitor array that connects the M-4 capacitor array is the i=M-5 capacitor array, so analogize, being connected to time low order capacitor array (the upper level capacitor array that promptly connects least significant bit capacitor array L) is L+1, and the least significant bit capacitor array can be expressed as L.Wherein i represents any one section capacitor array in the multicomponent section capacitor array, connects the connection electric capacity Cs between i section capacitor array and the i+1 section capacitor array _iExpression, the wherein connection capacitor C s that narrates according to epimere _iFully by specific capacitance C ₀The full binary weight multiple form Cs _iRealization be at first by all the binary weight capacitances in series in the i-1 section capacitor array, again its series capacitance is carried out two groups of parallel connections.When realizing N (N represents natural number) position analog-to-digital conversion, the number of sectional capacitance array can be chosen arbitrarily, therefore 1≤M-L≤2 ^NL≤i≤M.Simultaneously the number that can comprise binary system balance electric capacity in the structure in each section capacitor array can be chosen arbitrarily, but the binary weight electric capacity total number that need satisfy in the total to be comprised is all 2 ^NWithin the scope.

Circuit of the present invention is realized N position binary weight array of voltages, promptly realizes N position gradually-appoximant analog-digital converter or digital to analog converter, and the expression formula of the binary weight voltage of N position is:

$V_x=K*(\frac{1}{2}{b}_1+\frac{1}{2^2}{b}_2+\frac{1}{2^3}{b}_3+...+\frac{1}{2^N}{b}_N)$

Therefore, in order to obtain the suitable capacitance array size, the power voltage segment of N position is segmented into highest significant position MSB capacitor array M, inferior high significance bit capacitor array M-1 ... i+1 section electric capacity battle array, i section capacitor array, i-1 section capacitor array,, inferior low order capacitor array L+1, and least significant bit LSB capacitor array L.Therefore design need obtain:

The connection capacitor C s between each section capacitor array wherein _i(Cs wherein _iBe the capacitance that i section capacitor array links to each other with i-1 section capacitor array, i=M, M-1 ... L+2 L+i), wherein connects capacitor C s _iFully by specific capacitance C ₀The full binary weight multiple form.Under general situation, the whole capacitor array is made up of sectional capacitance in this way, needed connection capacitor C s _iSize can be expressed as:

${\mathrm{Cs}}_i=\frac{2^{i-1}}{2^{i-1}-1}{C}_0$ (C wherein ₀Be specific capacitance)

This electric capacity is the specific capacitance multiple value of a nonbinary power, yet the present invention has adopted structure cleverly, by utilizing the connection in series-parallel between the electric capacity, obtain obtaining connecting electric capacity by the specific capacitance of full binary weight, the specific implementation process is as follows: at first, the parallel connection of electric capacity equals the stack of two electric capacity, with Cs _iBe divided into two parts, promptly ${\mathrm{Cs}}_i=\frac{2^{i-1}}{2^{i-1}-1}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0=\frac{2^{i-2}}{2^{i-1}-1}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+\frac{2^{i-2}}{2^{i-1}-1}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0,$ On circuit, can just can utilize two groups of capacitance sizes to be like this

The electric capacity parallel connection obtain, yet Capacitance also has certain characteristics, and it can be connected by a series of binary weight electric capacity and obtain:

$\frac{2^{i-2}}{2^i-1}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0=\frac{1}{\frac{2^i-1}{2^{i-2}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}}=\frac{1}{\frac{1}{{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+\frac{1}{2{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+\frac{1}{2^2{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+...+\frac{1}{2^{i-3}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+\frac{1}{2^{i-2}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}}$

Thereby connect capacitor C s _iCan be at first by all the binary system balance capacitances in series in the i-1 section capacitor array, again its series capacitance is carried out two groups of parallel connections, forming on circuit structure has a plurality of sectional capacitance arrays, and the connecting circuit structure of being made up of i-1 section capacitor array constitutes the whole capacitor array.This structure has been avoided employing nonbinary power capacitance and has been avoided needed capacitance size and chip area when realizing high-precision adc or digital-to-analogue conversion, and this circuit has also been extenuated the limit bottleneck that mates between the electric capacity to a certain extent simultaneously.

Connection capacitor C s of the present invention _iFully by specific capacitance C ₀The full binary weight multiple form, be different from and traditional realize connecting electric capacity with fractional value electric capacity, fractional value connects electric capacity, and to have very big capacitance mismatch on technology realizes fault-tolerant.Connect capacitor C s _iRealization be at first by all the binary weight capacitances in series in the i-1 section capacitor array, again its series capacitance is carried out two groups of parallel connections, thereby obtains the Cs that needs _i

The number that contains binary weight weighing apparatus electric capacity in any capacitor array of the present invention can freely be chosen, the hop count of electric capacity also can freely be chosen, for example: if select two sections capacitor array MSB arrays and LSB array, wherein the MSB capacitor array is realized M position binary weighting, LSB capacitor array realization L position binary weighting, is connected capacitor C s by specific capacitance C ₀Full binary balance multiple form, then the whole capacitor array can be realized N=M+L position binary weighting.Therefore, during the realization of capacitor array, can be with reference to the demand of reality, carry out chip area and electric capacity technology matching condition is carried out optimal selection, this brings maximum flexibility ratio for design of circuit.

The present invention has adopted and has used specific capacitance C ₀Realize connecting capacitor C s dexterously _iThereby structure can carry out the capacitor array that many son section capacitor arrays are formed, this capacitor array has good flexibility, can in the binary system balance electric capacity number of electric capacity segments and electric capacity segmented array electric capacity, carry out freely selecting, it be carried out optimal selection according to different process conditions and different area requirements.The present invention is simple in structure, and flexibility ratio is big, and can realize high accuracy, low-power consumption and small size, and is all realizing easily on the circuit and in the technology manufacturing.

Description of drawings

Fig. 1 is a structural representation of the present invention;

Wherein: (a) be the system configuration of full binary weight capacitor array analog to digital converter; (b) be the circuit structure of binary-weighted capacitor array analog to digital converter and the capacitor array structure that a plurality of segmentation power electric capacity is formed.

Fig. 2 is for realizing the full binary weight capacitor array structure chart of N position analog to digital converter or digital to analog converter.

Fig. 3 is for connecting capacitor C s _iImplementation structure figure.

Fig. 4 is one and realizes heavily the distribute capacitor array figure of gradually-appoximant analog-digital converter of 16 electric charges.

Embodiment

Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.

As shown in the figure, present embodiment comprises: highest significant position (MSB) capacitor array, least significant bit (LSB) capacitor array, be connected the multicomponent section capacitor array between highest significant position capacitor array and the least significant bit capacitor array, and the connection electric capacity between each sectional capacitance array, wherein connect electric capacity fully by specific capacitance C ₀The full binary weight multiple form, the realization that connects electric capacity is at first by all the binary weight capacitances in series in next section capacitor array that connects in two sections capacitor arrays, its series capacitance is carried out two groups of parallel connections again.

(a) shows as accompanying drawing 1, the S0 switch is zero setting (Reset) switch, Comp is a comparator, Area1, Area2, Area3, Area4 and Area5 represent five different sectional capacitance arrays and the part that is connected electric capacity, Pad represents to be connected to the input interface of input input voltage vin or input reference voltage Vref, C _Array(M) capacitor array of expression highest significant position MSB section array capacitor M, C _Array(M-1) capacitor array of expression time high significance bit section array capacitor M-1, C _Array(i) capacitor array of any section array capacitor i in the middle of the expression, C _Array(L+1) capacitor array of expression time low order L+1 section array capacitor L, C _Array(L) capacitor array of expression least significant bit MSB section array capacitor L.Circuit structure diagram as the complete segmented full binary plenary capacitance array analog to digital converter of accompanying drawing 1 (b) expression: adopt b _NThe control switch of representing the N position, b _N-1The control switch of representing the N-1 position ... b _Nm+2The control switch of representing the Nm+2 position, b _Nm+1The control switch of representing the Nm+1 position, b _NmThe control switch of representing the Nm position, b _Nm-1The control switch of representing the Nm-1 position, b _Nm-2The control switch of representing the Nm-2 position ... b _{Nm-Nm "+1}Represent Nm-Nm "+1 control switch, b _{Nm-Nm "}Represent Nm-Nm " position control switch, b _{Nm-Nm " 1}Represent Nm-Nm " 1 control switch ... b _NiThe control switch of representing the Ni position, b _Ni-1The control switch of representing the Ni-1 position ... b _{Ni-Ni "+2}Represent Ni-Ni "+2 control switch, b _{Ni-Ni "+1}Represent Ni-Ni "+1 control switch, b _{Ni-Ni "}Represent Ni-Ni " control switch of position ... b _{NL+NL "}Represent NL+NL " position control switch, b _{NL+NL " 1}Represent NL+NL " 1 control switch ... b _NL+2The control switch of representing the NL+2 position, b _NL+1The control switch of representing the NL+1 position, b _NLThe control switch of representing the NL position, b _NL-1The control switch of representing the NL-1 position ... b ₃Represent the 3rd control switch, b ₂Represent the 2nd control switch, b ₁Represent the 1st control switch, switch is S _zBe employing zero setting (reset) switch above the Dummy specific capacitance, Pad represents to be connected to the input interface of input input voltage vin or input reference voltage Vref, and wherein Area1, Area2, Area3, Area4 and the Area5 of expression form with concrete binary-weighted capacitor array structure among Fig. 1 (a).

In accompanying drawing 2 and 3, the meaning of each sign flag at first is described below: circuit structure comprises a comparator C omp and threshold voltage elimination switch S 0; Switch S ₁, S ₂... S _i, S _I+1... S _L+1, S _LIt all is zero setting (reset) switch; Switch is S _zBe employing zero setting (reset) switch above the Dummy specific capacitance; Vref represents input reference voltage; Vin represents applied signal voltage;

Highest significant position power electric capacity in the expression M capacitor array,

The power electric capacity of time high significance bit in the expression M capacitor array,

Time low order power electric capacity in the expression M capacitor array, The power electric capacity of least significant bit in the expression M capacitor array, C ₀Be specific capacitance;

Highest significant position power electric capacity in the expression M-1 capacitor array,

The power electric capacity of time high significance bit in the expression M-1 capacitor array,

Time low order power electric capacity in the expression M-1 capacitor array,

The power electric capacity of least significant bit in the expression M-1 capacitor array;

Highest significant position power electric capacity in the expression i capacitor array,

The power electric capacity of time high significance bit in the expression i capacitor array,

Time low order power electric capacity in the expression i capacitor array,

The power electric capacity of least significant bit in the expression i capacitor array;

Highest significant position power electric capacity in the expression L+1 capacitor array,

The power electric capacity of time high significance bit in the expression L+1 capacitor array,

Time low order power electric capacity in the expression L+1 capacitor array,

The power electric capacity of least significant bit in the expression L+1 capacitor array; This gradually-appoximant analog-digital converter is used to realize the conversion of N position, and digital code can be expressed as: b _Nb _N-1b _N-2... b ₃b ₂b ₁, promptly also can be written as:

Therefore, present embodiment adopts b _NThe control switch of representing the N position, b _N-1The control switch of representing the N-1 position ... b _Nm+2The control switch of representing the Nm+2 position, b _Nm+1The control switch of representing the Nm+1 position, b _NmThe control switch of representing the Nm position, b _Nm-1The control switch of representing the Nm-1 position, b _Nm-2The control switch of representing the Nm-2 position ... b _{Nm-Nm "}Represent Nm-Nm " control switch of position ... b _NiThe control switch of representing the Ni position, b _Ni-1The control switch of representing the Ni-1 position ... b _{Ni-Ni "}Represent Ni-Ni " position control switch, b _{Ni-Ni " 1}Represent Ni-Ni " 1 control switch ... b _{Ni-Ni " "}The control switch of representing Ni-Ni " " position ... b _NL+NLThe control switch of representing the NL+NL position ... b _NL+1The control switch of representing the NL+1 position, b _NLThe control switch of representing the NL position, b _NL-1The control switch of representing the NL-1 position ... b ₃Represent the 3rd control switch, b ₂Represent the 2nd control switch, b ₁Represent the 1st control switch.

As shown in Figure 4, b16, b15, b14, b13, b12, b11, b10, b9, b8, b7, b6, b5, b4, b3, b2, b1 are respectively the control switch of b16 to the b1 position, Sr1, Sr2, Sr3 and Sr4 are respectively reset switch, S0 is the set sampling switch, S-signal1, S-signal2, S-signal3 and S-signal4 are respectively signaling switch and are connected reference voltage Vref or input voltage vin, S-ground1, S-ground2 and S-ground3 are for putting the ground switch, and Cs represents the connection electric capacity between the different sectional capacitance arrays.

As shown in Figure 2, the full binary weight capacitor array of the analog to digital converter of N position or digital to analog converter is by the MSB capacitor array ... i+1 section capacitor array, i section capacitor array, i-1 section capacitor array ... and the LSB capacitor array constitutes connection capacitor C s _iForm by the connection in series-parallel of all binary weight electric capacity of i-1 section electric capacity respectively, suppose that the value of any electric capacity is: C _i=2 ^I-1C ₀, in the MSB capacitor array by N _M-1 binary weight electric capacity is formed ... i+1 section capacitor array is by N _I+1-1 binary weight electric capacity is formed, and i section capacitor array is by N _i-1 binary weight electric capacity is formed, and i-1 section capacitor array is by N _I-1-1 binary weight electric capacity is formed ... and the LSB capacitor array is by N _LIndividual binary weight electric capacity is formed formation and (is wherein comprised N _L-1 power electric capacity and a dummy capacitor C ₀), therefore, N=N _M+ ... + N _I+1+ N _i+ N _I-1+ ... + N _LThen the whole capacitor value is:

$C_{\mathrm{total}}=2^{{\mathrm{<figure-callout\; id="0"\; label="N\; M\; C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">N</figure-callout>}}_M}{C}_{}{}_0+...+2^{N_{i+1}}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+2^{N_i}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+2^{N_{i-1}}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+...++2^{{\mathrm{<figure-callout\; id="0"\; label="N\; L\; C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">N</figure-callout>}}_L}{C}_{}{}_0+\left(\mathrm{\&Sigma;}{\mathrm{Cs}}_i\right)$

First electric capacity of MSB capacitor array is $C_{\mathrm{Nm}}^M=2^{\mathrm{<figure-callout\; id="0"\; label="Nm\; C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">Nm</figure-callout>}}{C}_{}{}_0,$ J capacitance in the MSB capacitor array can be expressed as $C_j^M=2^j{C}_0$ (j=Nm wherein, Nm-1 ... 2,1,0); First capacitance of the capacitor array of MSB-1 is $C_{\mathrm{NM}\&prime;\&prime;}^{M-1}=2^{N_{m-1}}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0,$ K capacitance in the MSB-1 capacitor array can be expressed as equally $C_k^{M-1}=2^{N_k}{C}_0$ (k=N wherein _{M "}, N _{M " 1}2,1,0, M wherein "=MSB-1); First capacitance of i section capacitor array is $C_{\mathrm{Ni}}^i=2^{\mathrm{<figure-callout\; id="0"\; label="Ni\; C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">Ni</figure-callout>}}{C}_{}{}_0,$ G capacitance can be expressed as in the i section capacitor array $C_g^i=2^{N_g}{C}_0$ (g=N wherein _i, N _I-12,1,0); First capacitance of i-1 section capacitor array is $C_{\mathrm{Ni}\&prime;\&prime;}^{i-1}=2^{N_{i-1}}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0,$ The size of h capacitance is in the i-1 section capacitor array $C_h^i=2^{N_h}{C}_0$ (h=N wherein _{I "}, N _{I " 1}2,1,0, i wherein "=i-1); First capacitance of L+1 section capacitor array is $C_{\mathrm{NL}\&prime;\&prime;}^{L+1}=2^{N_{L+1}}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0,$ F capacitance size is in the L+1 section capacitor array $C_f^i=2^{N_f}{C}_0$ (f=N wherein _{L "}, N _{L " 1}2,1,0, L wherein "=L+1); First capacitance of L section capacitor array is $C_{\mathrm{NL}}^L=2^{{\mathrm{<figure-callout\; id="0"\; label="N\; L\; C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">N</figure-callout>}}_L}{C}_{}{}_0,$ The 1st capacitance size is in the L section capacitor array $C_I^L=2^{N_I}{C}_0$ (1=N wherein _L, N _L-12,1,0).

Needed total capacitance value has reduced to a great extent when realizing same precision analog-to-digital conversion or digital-to-analogue conversion like this, thereby has saved area of chip.

As shown in Figure 3, connect capacitor C s _iRealization form by the connection in series-parallel of a series of specific capacitances, it comprises two groups of identical capacitor array parallel connections, the electric capacity on the road of each parallel connection all is to be connected by all electric capacity of i-1 sectional capacitance array to obtain then, promptly i-1 section electric capacity is by N _I-1-1 binary weight electric capacity is formed, and then connects the connection capacitor C s of i section and i-1 section electric capacity _iCan be earlier by N _I-1The N that contains in-1 section capacitor array _I-1-1 binary weight electric capacity is connected, and the capacitance that obtains is:

$\frac{2^{i-2}}{2^i-1}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0=\frac{1}{\frac{2^i-1}{2^{i-2}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}}=\frac{1}{\frac{1}{{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+\frac{1}{2{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+\frac{1}{2^2{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+...+\frac{1}{2^{i-3}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}+\frac{1}{2^{i-2}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0}}$

Again this electric capacity is carried out parallel connection and is equivalent to two capacitance, thereby obtain the connection capacitance that needs:

${\mathrm{Cs}}_i=\frac{2^{i-1}}{2^{i-1}-1}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0$

This circuit structure is simple, but resulting function and use are very obvious, and it has avoided adopting a series of binary system balance electric capacity, therefore can realize small size realization high accuracy; Capacitor array has adopted the sectional capacitance array structure simultaneously, and has avoided using non-binary connection electric capacity, thereby has overcome the difficulty in electric capacity coupling and technology manufacturing; This structure can be selected between the contained electric capacity number of the segmentation of capacitor array and each sectional capacitance simultaneously freely, in the circuit design process, can consider the balance between technological requirement and the area, select one and the actual electric capacity number that comprises in optimum segments and every section of requiring, so the design of capacitor array has good flexibility ratio.

The course of work of entire circuit probably can be divided into four parts: the Reset part; Keep sampling date; Distribution and distribution phase in advance again.At first, be called the Reset part with the switch of bottom crown on the electric capacity of entire circuit ground connection all; Keep sampling date: under control logic circuit control, all electric capacity top board ground connection, base plate connects analog input, and input voltage is stored on the electric capacity; The pre-distribution: all capacitor bottom plate ground connection, top board disconnects with ground, and electric charge keeps on the electric capacity; Distribution phase again: under control circuit control, the switch of capacitor array is switch successively, and input signal is retrieved from MSB to LSB successively.

For sectional capacitance array operation principle also is so, supposes that the N bit switch is respectively:

As shown in Figure 2, at first by comparing the highest significant position in the MSB section array capacitor, the N position is by b _NSwitch control is compared b one by one according to comparator output valve size then _N-1B _Nm, and then carry out the switch control of M-1 section capacitor array, by controlling b successively _Nm-1b _Nm-2... b _Nm-Nm-1Finish comparing one by one of M-1 section capacitor array ... similarly, compare i+1 section capacitor array successively, i section capacitor array, the i-1 capacitor array ... until least significant bit L section capacitor array b _NLb _NL-1... b ₂b ₁As the structure chart of instance graph 4 resulting 16 gradually-appoximant analog-digital converters, be divided into 4 sections capacitor arrays, the electric capacity number that every section capacitor array comprises all has 4, and promptly needed capacitance is respectively C ₀, 2C ₀, 4C ₀, 8C ₀(C wherein ₀Be specific capacitance), needed total capacitance value is:

C _tot＝(1+2+1+2+1+2+1)*15C ₀+C ₀＝151C ₀

Obviously with respect to the needed electric capacity total value of the binary-weighted capacitor array of not segmentation C _Tor=2 ¹⁸C ₀Area has significantly reduced, and the requirement of the coupling of electric capacity simultaneously also becomes relatively easy.In addition, this sectional capacitance array structure has avoided using the connection electric capacity of fractional value, if connect the sectional capacitance array according to traditional fractional value electric capacity, connect capacitance should for $C_s=\frac{16}{15}{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="A200910049404E00141.png"\; state="\{\{state\}\}">C</figure-callout>}}_0,$ This mark capacitance is in the middle of the design of domain, obviously can bring and not match between the very big electric capacity and design top difficulty, thereby mating the demanding electric charge gradually-appoximant analog-digital converter that heavily distributes for electric capacity is a very big bottleneck, the structure that proposes has in this invention been avoided use fractional value electric capacity then, and connecting electric capacity all is to be realized combining by binary weight electric capacity.Therefore, this capacitor array and traditional capacitor array and traditional sectional capacitance array needed clock cycle when the analog-to-digital conversion of finishing suitable figure place precision or digital-to-analogue conversion are the same, but this circuit has reduced the area of electric capacity largely and extenuated coupling between the electric capacity and difficulty that technology is made.

Claims (3)

1, a kind of sectional capacitance array of full binary weight electric capacity, comprise: highest significant position capacitor array, least significant bit capacitor array, be connected the multicomponent section capacitor array between highest significant position capacitor array and the least significant bit capacitor array, and the connection electric capacity between each sectional capacitance array, it is characterized in that: described connection electric capacity is fully by specific capacitance C ₀The full binary weight multiple form, connecting electric capacity is by all the binary weight capacitances in series in next section capacitor array that connects in two sections capacitor arrays, its series capacitance is carried out two groups again and in parallelly constitutes.

2, the sectional capacitance array of full binary weight electric capacity according to claim 1 is characterized in that, described sectional capacitance array is when realizing N position analog-to-digital conversion, and its number is chosen arbitrarily, i.e. 1≤M-L≤2 ^N, L≤i≤M, N represents natural number, and M represents the highest significant position capacitor array, and L represents the least significant bit capacitor array, is connected the middle any capacitor array of M capacitor array and L capacitor array and represents with symbol i.

3, the sectional capacitance array of full binary weight electric capacity according to claim 1, it is characterized in that, the number that comprises binary system balance electric capacity in described each sectional capacitance array is chosen arbitrarily, but the binary weight electric capacity total number that need satisfy in the total to be comprised is all 2 ^NWithin the scope, N represents natural number.

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