CN102148618A - Analogue-digital converter with low-recoil noise and secondary analogue-digital converter - Google Patents
Analogue-digital converter with low-recoil noise and secondary analogue-digital converter Download PDFInfo
- Publication number
- CN102148618A CN102148618A CN2010101162043A CN201010116204A CN102148618A CN 102148618 A CN102148618 A CN 102148618A CN 2010101162043 A CN2010101162043 A CN 2010101162043A CN 201010116204 A CN201010116204 A CN 201010116204A CN 102148618 A CN102148618 A CN 102148618A
- Authority
- CN
- China
- Prior art keywords
- signal
- input transistors
- order
- coupled
- type input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides an analogue-digital (A/D) converter with low-recoil noise and a secondary A/D converter. A first comparator produces a first output signal at a first output end according to an input signal and a first reference voltage, and comprises a first N-type input transistor for receiving a first signal and a second N-type input transistor for receiving a second signal, wherein the first signal and the second signal are a differential signal pair for forming the input signal. A second comparator produces a second output signal at a second output end according to the input signal and the second reference voltage, and comprises a first P-type input transistor for receiving the first signal and a second P-type input transistor for receiving the second signal. The A/D converter described by the embodiment of the invention can be applied to the analogue-digital conversion of any electronic product, and can reduce the recoil noise without adding extra circuit so as to avoid signal distortion.
Description
Technical field
The invention relates to a kind of analog-digital converter, particularly relevant for a kind of analog-digital converter with low recoil noise (kickback noise).
Background technology
Analog digital conversion (Analog to Digital Conversion) technology has been widely used in the different electronic products, pipelined analog-to-digital converter (Pipelined Analog to Digital Converter wherein, pipelined ADC) has the characteristic of high speed and high-res, so often be used in the communication system.
Fig. 1 is the schematic diagram of display pipeline formula analog-digital converter 100.Pipelined analog-to-digital converter 100 comprises sample-and-hold circuit 110, modular converter 140 and digital correction circuit 130.Modular converter 140 comprises n level change-over circuit 120a-120n and rear end flash type analog-digital converter (FlashADC) 125, and wherein flash type analog-digital converter 125 is coupled to the change-over circuit 120n of afterbody to n level change-over circuit 120a-120n with the series system connection.After taking a sample, 110 couples of input signal Si n of sample-and-hold circuit produce sampled signal S1.Each change-over circuit 120a-120n comprise time simulation digital quantizer (Sub-ADC) and multiple digital analog converter (Multiplier Digital to AnalogConverter, MDAC).In a change-over circuit, inferior simulation digital quantizer can convert the analog output signal of previous stage change-over circuit to digital signal, and this digital signal is sent to digital correction circuit 130 and multiple digital analog converter.Then, the multiple digital analog converter can convert this digital signal to analog signal and export the next stage change-over circuit to.For instance, first order change-over circuit 120a can produce digital signal D1 to digital correction circuit 130 and produce analog signal A1 to second level change-over circuit 120b according to sampled signal S1.Then, change-over circuit 120b in the second level can produce digital signal D2 to digital correction circuit 130 and produce analog signal A2 to third level change-over circuit 120c according to analog signal A1.By that analogy, when flash type analog-digital converter 125 produces digital signal Df to digital correction circuit 130 according to analog signal An, digital correction circuit 130 can be proofreaied and correct received digital signal D1-Dn and digital signal Df and encode, so that produce the digital output signal OUT corresponding to analog input signal Sin.
Fig. 2 is the schematic diagram that shows change-over circuit 200.Change-over circuit 200 comprises time simulation digital quantizer 220 and multiple digital analog converter 240.Inferior simulation digital quantizer 220 comprises comparator 222 and comparator 224, and multiple digital analog converter 240 comprises digital analog converter 242, adder 244 and amplifier 246.See through comparator 222 and comparator 224, the inferior simulation digital quantizer 220 in the change-over circuit 200 can produce digital signal Dn according to the analog signal An-1 from the previous stage change-over circuit, and provides digital signal Dn to multiple digital analog converter 240.Then, digital analog converter 242 can produce signal S2 according to digital signal Dn.Then, adder 244 obtains signal S3 with analog signal An-1 subtraction signal S2, and signal S3 is sent to amplifier 246 amplifies, so that produce the analog signal An of change-over circuit 200.In inferior simulation digital quantizer 220, when comparator 222 and comparator 224 switch inside when switching, the coupling effect of parasitic capacitance will make the input of comparator 222 and comparator 224 have the generation of recoil noise (kickback noise).In other words, the switching noise of comparator 222 and comparator 224 will recoil to the change-over circuit of previous stage, thereby reduces the quality of signal and cause distortion.
In order to reduce the recoil noise, can add amplifier (Pre-amplifier in advance at the front end of latch circuit traditionally, Pre-AMP), understand recoil (kickback) change-over circuit with the switching noise (noise) that stops comparator to previous stage, as shown in Fig. 3, comparator 300 comprises amplifier 310 and latch circuit 320 in advance.Yet using in advance, amplifier 310 will make the power consumption of comparator 300 to increase.So, get over for a long time when the quantity of pipelined analog-to-digital converter internal conversion circuit, the quantity of amplifier also can be many more in advance, therefore reduce whole power usefulness easily.
Fig. 4 shows the another kind of comparator 400 that can reduce the recoil noise traditionally.Comparator 400 comprises input stage circuit 410 and latch circuit 420, and wherein input stage circuit 410 more comprises neutrality (neutralization) circuit 430.In comparator 400, come oxide-semiconductor control transistors 432,434,436 and 438 by latch-up signal latch, can stop switching noise from latch circuit 420, therefore avoid this switching noise can see through input stage circuit 410 and disturb input signal V
IPAnd V
IN
In addition, also can use redundancy (dummy) circuit (for example comparator or amplifier) to come of the interference of balance switching noise traditionally, to reduce the recoil noise to input signal.Fig. 5 A shows a kind of comparator circuit 500 that uses redundant comparator to reduce the recoil noise.Comparator circuit 500 comprises first comparator 510 and second comparator 520.In Fig. 5 A, second comparator 520 is for carrying out the redundant comparator that switch switches according to signal latchB, and wherein signal latchB is the inversion signal of latch-up signal latch.Therefore, the ON time of the breech lock transistor 531,532,533,534 in first comparator 510 and the breech lock transistor 541,542,543,544 in 535 and second comparator 520 and 545 is complementary.So breech lock transistor 531,532,533,534 and 535 is at input signal V in first comparator 510
IPAnd V
INThe first recoil noise that end is produced can be by breech lock transistor 541,542,543,544 and 545 in second comparator 520 at input signal V
IPAnd V
INThe second recoil noise that end is produced offsets.In addition, because second comparator 520 is redundant comparator, therefore in inferior simulation digital quantizer, second comparator 520 of each comparator circuit can not provide and output signal to follow-up circuit, for example multiple digital analog converter and digital correction circuit.Yet in the inferior simulation digital quantizer of each grade change-over circuit, each original comparator all needs additionally to use redundant comparator and reduces the recoil noise.
With reference to figure 5B, Fig. 5 B shows the inferior simulation digital quantizer 550 that uses redundant comparator.Inferior simulation digital quantizer 550 comprises comparator circuit 500A and comparator circuit 500B, and wherein comparator 520A and comparator 520B are redundant comparator, and the output signal Dn of inferior simulation digital quantizer 550 is provided by comparator 510A and 510B.Therefore, get over for a long time when the quantity of pipelined analog-to-digital converter internal conversion circuit, the quantity of redundant circuit also can be many more, thereby the area that reduces whole power usefulness and increase integrated circuit easily.
Therefore, need a kind of analog-digital converter that reduces the recoil noise, it can be saved area and avoid power consumption.
Summary of the invention
The invention provides a kind of analog-digital converter with low recoil noise.Above-mentioned analog-digital converter comprises one first comparator and one second comparator.Above-mentioned first comparator produces one first output signal according to an input signal and one first reference voltage in one first output, and comprises: one the one N type input transistors, in order to receive one first signal; And, one the 2nd N type input transistors, in order to receive a secondary signal, wherein above-mentioned first signal and above-mentioned secondary signal are right for a differential wave of forming above-mentioned input signal.Above-mentioned second comparator produces one second output signal according to above-mentioned input signal and one second reference voltage in one second output, and comprises: one the one P type input transistors, in order to receive above-mentioned first signal; And one the 2nd P type input transistors is in order to receive above-mentioned secondary signal.
Moreover, the invention provides a kind of pipelined analog-to-digital converter, in order to convert an input signal to a digital signal with low recoil noise.Above-mentioned pipelined analog-to-digital converter comprises: a sample-and-hold circuit, in order to produce a sampled signal according to above-mentioned input signal; Multistage change-over circuit is connected in above-mentioned sample-and-hold circuit with series system; And, a digital correction circuit.Each above-mentioned multistage change-over circuit comprises: an analog-digital converter, and one first analog signal in order to export according to the above-mentioned change-over circuit of previous stage produces a digital signal; And a multiple digital analog converter is in order to produce the above-mentioned change-over circuit of one second analog signal to the back one-level according to above-mentioned digital signal.Above-mentioned digital correction circuit produces the above-mentioned digital signal corresponding to above-mentioned input signal according to the above-mentioned digital signal that each above-mentioned multistage change-over circuit provided.Above-mentioned time the simulation digital quantizer comprises: one first comparator, in order to produce one first output signal in one first output according to above-mentioned first analog signal and one first reference voltage; And one second comparator is in order to produce one second output signal according to above-mentioned first analog signal and one second reference voltage in one second output.Above-mentioned first comparator comprises: one the one N type input transistors, in order to receive one first signal; And, one the 2nd N type input transistors, in order to receive a secondary signal, wherein above-mentioned first signal and above-mentioned secondary signal are right for a differential wave of forming above-mentioned first analog signal.Above-mentioned second comparator comprises: one the one P type input transistors, in order to receive above-mentioned first signal; And, one the 2nd P type input transistors, in order to receive above-mentioned secondary signal, wherein above-mentioned first output signal and above-mentioned second output signal are formed above-mentioned digital signal.
The simulation that can be applicable to any electronic product according to the described analog-digital converter of the embodiment of the invention can reduce the recoil noise, and then avoid distorted signals in the digital transformation applications under the situation that does not increase additional circuit.
Description of drawings
Fig. 1 is the schematic diagram of display pipeline formula analog-digital converter;
Fig. 2 is the schematic diagram that shows change-over circuit;
Fig. 3 shows a kind of comparator that can reduce the recoil noise traditionally;
Fig. 4 shows the another kind of comparator that can reduce the recoil noise traditionally;
Fig. 5 A shows a kind of comparator circuit that uses redundant circuit to reduce the recoil noise;
Fig. 5 B shows a kind of the simulation digital quantizer that uses redundant circuit;
Fig. 6 is the schematic diagram that shows according to each grade change-over circuit in the described pipelined analog-to-digital converter of one embodiment of the invention;
Fig. 7 A and Fig. 7 B are the schematic diagrames that shows according to described simulation digital quantizer of one embodiment of the invention;
Fig. 8 is the analog signal An-1 (630) in comparator 630 and the comparator 640 and the oscillogram of analog signal An-1 (640) in the displayed map 7; And
Fig. 9 is the oscillogram of the recoil noise of display simulation signal An-1.
Drawing reference numeral:
100～pipelined analog-to-digital converter;
110～sample-and-hold circuit;
120a-120n～change-over circuit;
125～flash type analog-digital converter;
130～digital correction circuit;
140,200～modular converter;
220,610～inferior simulation digital quantizer;
222,224,400,630,640～comparator;
240,620～multiple digital analog converter;
242～digital analog converter;
244～adder;
246,650～amplifier;
410～input stage circuit;
420～latch circuit;
432,434,436,438,531-535,541-545, M6-M9, M26-M29～transistor;
500～comparator circuit;
510,630～the first comparators;
520,640～the second comparators;
660～multiplexer;
720,740～output unit;
A1, A2, An-1, An～analog signal;
An-1P, An-1N～differential output signal
C1-C4～parasitic capacitance;
C5-C6～electric capacity;
D1-Dn, Df～digital signal;
GND～earth terminal;
Latch, latchB～latch-up signal;
M1, M10-M13, M21, M30-M33～switching transistor;
M2-M5, M22-M25～input transistors;
OUT～digital output signal;
S1, S2, S3～signal;
Sin, V
IP, V
IN～input signal
SW1, SW2, SW3～switch;
VDD～power end;
V
Out1, V
Out2～output signal; And
V
REF1, V
REF2, V
REFN, V
REFP～reference voltage.
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Embodiment:
Fig. 6 is the schematic diagram that shows according to each grade change-over circuit 600 in the described pipelined analog-to-digital converter of one embodiment of the invention.Change-over circuit 600 comprises time simulation digital quantizer 610 and multiple digital analog converter 620.Inferior simulation digital quantizer 610 comprises comparator 630 and comparator 640, and multiple digital analog converter 620 comprises three switch SW 1, SW2 and SW3, two capacitor C 5 and C6, amplifier 650 and multiplexer (multiplexer, MUX) 660.In inferior simulation digital quantizer 610, comparator 630 and 640 meetings will be from the analog signal An-1 and the reference voltage V of previous stage change-over circuit
REF1And V
REF2Compare, to obtain digital signal Dn.Then, in multiple digital analog converter 620, multiplexer 660 can be selected reference voltage V according to digital signal Dn
REFN, ground signalling " 0 " and reference voltage V
REFPOne export i.e. signal S2.In this embodiment, the digital analog converter 242 of the functional similarity of multiplexer 660 in Fig. 2.Then, by the switching of control switch SW1, SW2 and SW3, can produce signal S3 according to the analog signal An-1 and the signal S2 of previous stage change-over circuit.Then, 650 couples of signal S3 of amplifier amplify to produce analog signal An.In this embodiment, reference voltage V
REF1And reference voltage V
REF2Be respectively V
Ref/ 4 and-V
Ref/ 4, and digital signal Dn is 1.5 bit data.In addition, reference voltage V
REFPWith reference voltage V
REFNBetween voltage difference be V
Ref, V wherein
RefPractical operation situation according to pipelined analog-to-digital converter determines.Therefore, reference voltage V
REFPWith reference voltage V
REFNBetween voltage difference V
RefRespectively with reference voltage V
REF1And reference voltage V
REF2Has the multiple relation.
Fig. 7 A and Fig. 7 B show the schematic diagram according to described simulation digital quantizer 610 of one embodiment of the invention.In this embodiment, first comparator 630 and second comparator 640 are dynamic comparer (dynamic comparator).First comparator 630 comprises input transistors M2-M5, switching transistor M1, M10-M13 and output unit 720.Input transistors M2-M5 is respectively coupled between switching transistor M1 and the output unit 720, and wherein switching transistor M1 is coupled to earth terminal GND and output unit 720 is coupled to power end VDD.The grid of input transistors M3 and M5 receives differential output signal An-1P and the An-1N from the previous stage change-over circuit respectively, wherein the difference of signal An-1P and signal An-1N is analog signal An-1, and the grid of input transistors M2 and M5 receives reference voltage V respectively
REFNWith V
REFP, reference voltage V wherein
REFPDeduct reference voltage V
REFNValue be reference voltage V
REF1Output unit 720 comprises transistor M6-M9, and wherein output unit 720 can be in output N
Out1Output signal V is provided
Out1Transistor M6 is coupled to input transistors M3 and node N
1Between, transistor M8 is coupled to power end VDD and node N
1Between, transistor M7 is coupled to input transistors M5 and output N
Out1Between and transistor M9 be coupled to power end VDD and output N
Out1Between.
Moreover switching transistor M11 is coupled to node N
1And between the power end VDD, switching transistor M10 is coupled between input transistors M3 and the power end VDD, switching transistor M12 is coupled to output N
Out1And between the power end VDD and switching transistor M13 be coupled between input transistors M5 and the power end VDD.In comparator 630, switching transistor M1 and M10-M13 are controlled by latch-up signal latch.Therefore, when latch-up signal latch control switching transistor M1 and M10-M13 switched, the parasitic capacitance (for example C1, C2 etc.) that switching noise will see through on the input transistors M2-M5 be coupled to differential output signal An-1P and An-1N and reference voltage V
REFNWith V
REFP, make analog signal An-1 and reference voltage V
REFNWith V
REFPBe interfered, and then cause distorted signals.
In Fig. 7 A and Fig. 7 B, second comparator 640 and first comparator 630 are complementary framework.For instance, power end VDD in first comparator 630 and earth terminal GND are exchanged, and simultaneously each transistorized type is made suitable change, then can obtain second comparator 640.Therefore, in second comparator 640, switching transistor M21 and input transistors M22-M25 are the P transistor npn npn, and switching transistor M30-M33 is the N transistor npn npn.In output unit 740, transistor M26 is coupled to input transistors M23 and node N
2Between, transistor M28 is coupled to earth terminal GND and node N
2Between, transistor M27 is coupled to input transistors M25 and output N
Out2Between and transistor M29 be coupled to earth terminal GND and output N
Out2Between.
In addition, transistor M26-M27 is a P transistor npn npn and transistor M28-M29 is the N transistor npn npn, and output unit 740 can be in output N
Out2Output signal V is provided
Out2Moreover in comparator 640, switching transistor M21 and M30-M33 are controlled by signal latchB, and wherein signal latchB is the inversion signal of latch-up signal latch.In addition, the grid of input transistors M23 and M25 receives differential output signal An-1P and the An-1N from the previous stage change-over circuit respectively, wherein the difference of signal An-1P and signal An-1N is analog signal An-1, and the grid of input transistors M22 and M25 receives reference voltage V respectively
REFPWith V
REFN, reference voltage V wherein
REFNDeduct reference voltage V
REFPValue be reference voltage V
REF2Produce output signal V respectively at comparator 630 and comparator 640
Out1And output signal V
Out2Afterwards, inferior simulation digital quantizer 610 can be with output signal V
Out1And output signal V
Out2Be integrated into digital signal Dn, and provide digital signal Dn to digital correction circuit (for example 130 of Fig. 1) to proofread and correct and to encode.In comparator 640, switching transistor M21 and M30-M33 are also controlled by latch-up signal latchB.Therefore, when latch-up signal latchB control switching transistor M21 and M30-M33 switched, the parasitic capacitance (for example C3, C4 etc.) that switching noise also can see through on the input transistors M22-M25 be coupled to differential output signal An-1P and An-1N and reference voltage V
REFNWith V
REFP
Can be coupled respectively to differential output signal An-1P and An-1N and reference voltage V though it should be noted that the switching noise of comparator 630 and comparator 640
REFNWith V
REFPBut the complementary framework of comparator 630 and comparator 640 can make 630 couples of differential output signal An-1P of comparator and An-1N and reference voltage V
REFNWith V
REFPThe recoil noise can be compared the recoil noise institute's balance and the payment of device 640.With reference to figure 8, Fig. 8 is the analog signal An-1 (630) in comparator 630 and the comparator 640 and the oscillogram of analog signal An-1 (640) among displayed map 7A and Fig. 7 B, wherein in analog signal An-1 (630) the expression comparator 630 differential wave An-1P analog signal An-1 (640) represents that differential wave An-1P's and An-1N in the comparator 640 is poor with the difference of An-1N.When time point t1, the recoil noise of comparator 630 can make analog signal An-1 (630) produce surging P1 up and the recoil noise of comparator 640 can make analog signal An-1 (640) produce surging P2 down.Because surging P1 and surging P2 can mutually offset, the interference of noise that therefore in fact recoils on analog signal An-1 can reduce.Fig. 9 is the oscillogram of the recoil noise of display simulation signal An-1, and wherein waveform S910 describes classical inverse towards The noise and waveform S920 describes according to the described recoil The noise of the embodiment of the invention.For recoil caused by noise surging, the peak swing H2 of waveform S920 is significantly less than the peak swing H1 of waveform S910.
Characteristics of the present invention are to utilize the kenel difference of the input transistors of two comparators in time simulation digital quantizer, promptly the input transistors of a comparator is the N transistor npn npn, the input transistors of another comparator is the P transistor npn npn, and because the electrical characteristic of P type and N transistor npn npn can mutually offset its recoil noise that produces in the signal.And above-mentioned for embodiment be not in order to limit the present invention, as prior art Fig. 3, comparator in the inferior simulation digital quantizer among Fig. 4 and Fig. 5 A and Fig. 5 B, after removing in advance amplifying circuit, neutral circuit and redundant comparator respectively, select the input transistors that receives differential wave the transistor of two kinds of kenels for use respectively, spirit promptly according to the invention and can reach the effect that reduces the recoil noise.
As described previously, the simulation that can be applicable to any electronic product according to the described analog-digital converter of the embodiment of the invention is in the digital transformation applications, and it can reduce the recoil noise under the situation that does not increase additional circuit, and then avoids distorted signals.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (10)
1. the analog-digital converter with low recoil noise also can reduce the recoil noise in order to an input signal is converted to a digital signal, it is characterized in that described analog-digital converter comprises:
One sample-and-hold circuit is in order to produce a sampled signal according to described input signal;
Multistage change-over circuit is connected in described sample-and-hold circuit with series system, and wherein each described multistage change-over circuit comprises:
An analog-digital converter, the analog signal in order to export according to the change-over circuit of previous stage produces a digital signal, and wherein said time the simulation digital quantizer comprises:
One first comparator has a plurality of first type input transistors, in order to produce one first output signal according to described first analog signal and one first reference voltage in one first output; And
One second comparator, have a plurality of second type input transistors, in order to produce one second output signal in one second output according to described first analog signal and one second reference voltage, wherein said first output signal and described second output signal are formed described digital signal, can reduce the recoil noise of described digital signal by described first type of use and the second type input transistors;
One multiple digital analog converter is in order to produce the described change-over circuit of one second analog signal to the back one-level according to described digital signal; And
One digital correction circuit in order to according to the described digital signal that each described multistage change-over circuit provided, produces the described digital signal corresponding to described input signal.
2. analog-digital converter as claimed in claim 1, it is characterized in that, when the described first type input transistors be the N transistor npn npn then the second type input transistors be the P transistor npn npn, otherwise when the described first type input transistors be the P transistor npn npn then the second type input transistors be the N transistor npn npn, right in order to a differential wave that receives described previous stage output analog signal respectively.
3. analog-digital converter as claimed in claim 1 is characterized in that, described first comparator more comprises: one the one N type input transistors, in order to receive one first signal; And one the 2nd N type input transistors, in order to receive a secondary signal, wherein said first signal and described secondary signal are right for a differential wave of forming described analog signal; And
Described second comparator comprises: one the one P type input transistors, in order to receive described first signal; And one the 2nd P type input transistors, in order to receive described secondary signal.
4. analog-digital converter as claimed in claim 3 is characterized in that, described first comparator more comprises:
One the one N type switching transistor is coupled to an earth terminal, has a grid in order to receive one first latch-up signal;
One first output unit is in order to provide described first output signal;
One the 3rd N type input transistors is coupled between a described N type switching transistor and described first output unit and is parallel to a described N type input transistors, in order to receive one the 3rd reference voltage; And
One the 4th N type input transistors is coupled between a described N type switching transistor and described first output unit and is parallel to described the 2nd N type input transistors, in order to receive one the 4th reference voltage; And
Described second comparator more comprises:
One the one P type switching transistor is coupled to a power end, has a grid in order to receive one second latch-up signal, and wherein said second latch-up signal is the inversion signal of described first latch-up signal;
One second output unit is in order to provide described second output signal;
One the 3rd P type input transistors is coupled between described the 5th P type switching transistor and described second output unit and is parallel to a described P type input transistors, in order to receive described the 4th reference voltage; And
One the 4th P type input transistors, be coupled between described the 5th P type switching transistor and described second output unit and be parallel to described the 2nd P type input transistors, in order to receive described the 3rd reference voltage, the difference that wherein said the 3rd reference voltage deducts described the 4th reference voltage is described first reference voltage, is described second reference voltage and described the 4th reference voltage deducts the difference of described the 3rd reference voltage.
5. one kind simulation digital quantizer according to an analog signal that is received, produces a digital signal, it is characterized in that described time the simulation digital quantizer comprises:
One first comparator has a plurality of first type input transistors, in order to produce one first output signal according to described analog signal and one first reference voltage; And
One second comparator has a plurality of second type input transistors, in order to producing one second output signal according to described analog signal and one second reference voltage,
Wherein said first output signal and described second output signal are formed described digital signal, can reduce the recoil noise of described digital signal by described first type of use and the second type input transistors.
6. as claimed in claim 5 simulation digital quantizer, it is characterized in that, when the described first type input transistors be the N transistor npn npn then the second type input transistors be the P transistor npn npn, otherwise when the described first type input transistors be the P transistor npn npn then the second type input transistors be the N transistor npn npn, right in order to a differential wave that receives described analog signal respectively.
7. as claimed in claim 5 simulation digital quantizer is characterized in that,
Described first comparator more comprises: one the one N type input transistors, in order to receive one first signal; And one the 2nd N type input transistors, in order to receive a secondary signal, wherein said first signal and described secondary signal are right for a differential wave of forming described analog signal; And
Described second comparator comprises: one the one P type input transistors, in order to receive described first signal; And one the 2nd P type input transistors, in order to receive described secondary signal.
8. as claimed in claim 7 simulation digital quantizer is characterized in that, described first comparator more comprises:
One the one N type switching transistor is coupled to an earth terminal, has a grid in order to receive one first latch-up signal;
One first output unit is in order to provide described first output signal;
One the 3rd N type input transistors is coupled between a described N type switching transistor and described first output unit and is parallel to a described N type input transistors, in order to receive one the 3rd reference voltage; And
One the 4th N type input transistors is coupled between a described N type switching transistor and described first output unit and is parallel to described the 2nd N type input transistors, in order to receive one the 4th reference voltage; And
Described second comparator more comprises:
One the 5th P type switching transistor is coupled to a power end, has a grid in order to receive one second latch-up signal, and wherein said second latch-up signal is the inversion signal of described first latch-up signal;
One second output unit is in order to provide described second output signal;
One the 3rd P type input transistors is coupled between described the 5th P type switching transistor and described second output unit and is parallel to a described P type input transistors, in order to receive described the 4th reference voltage; And
One the 4th P type input transistors, be coupled between described the 5th P type switching transistor and described second output unit and be parallel to described the 2nd P type input transistors, in order to receive described the 3rd reference voltage, the difference that wherein said the 3rd reference voltage deducts described the 4th reference voltage is described first reference voltage, is described second reference voltage and described the 4th reference voltage deducts the difference of described the 3rd reference voltage.
9. as claimed in claim 8 simulation digital quantizer is characterized in that, described first comparator more comprises:
One the one P type switching transistor is coupled between a described power end and the described N type input transistors, has a grid in order to receive described first latch-up signal;
One the 2nd P type switching transistor is coupled between described power end and the described first node, has a grid in order to receive described first latch-up signal;
One the 3rd P type switching transistor is coupled between described power end and described the 2nd N type input transistors, has a grid in order to receive described first latch-up signal; And
One the 4th P type switching transistor is coupled between described power end and described first output, has a grid in order to receive described first latch-up signal; And
Described first output unit comprises:
One the one P transistor npn npn is coupled between a power end and the first node, has a grid and is coupled to described first output;
One the 2nd P transistor npn npn is coupled between described power end and described first output, has a grid and is coupled to described first node;
One the one N transistor npn npn is coupled between a described P transistor npn npn and the described N type input transistors, has a grid and is coupled to described first output; And
One the 2nd N transistor npn npn is coupled between described the 2nd P transistor npn npn and described the 2nd N type input transistors, has a grid and is coupled to described first node.
10. as claimed in claim 8 simulation digital quantizer is characterized in that, described second comparator more comprises:
One the 2nd N type switching transistor is coupled between a described earth terminal and the described P type input transistors, has a grid in order to receive described second latch-up signal;
One the 3rd N type switching transistor is coupled between described earth terminal and the described Section Point, has a grid in order to receive described second latch-up signal;
One the 4th N type switching transistor is coupled between described earth terminal and described the 2nd P type input transistors, has a grid in order to receive described second latch-up signal;
One the 5th N type switching transistor is coupled between described earth terminal and described second output, has a grid in order to receive described second latch-up signal; And
Described second output unit comprises:
One the 3rd N transistor npn npn is coupled between a described earth terminal and the Section Point, has a grid and is coupled to described second output;
One the 4th N transistor npn npn is coupled between described earth terminal and described second output, has a grid and is coupled to described Section Point;
One the 3rd P transistor npn npn is coupled between a described N transistor npn npn and the described P type input transistors, has a grid and is coupled to described second output; And
One the 4th P transistor npn npn is coupled between described the 2nd N transistor npn npn and described the 2nd P type input transistors, has a grid and is coupled to described Section Point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010116204.3A CN102148618B (en) | 2010-02-09 | 2010-02-09 | Analogue-digital converter with low-recoil noise and analogue-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010116204.3A CN102148618B (en) | 2010-02-09 | 2010-02-09 | Analogue-digital converter with low-recoil noise and analogue-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102148618A true CN102148618A (en) | 2011-08-10 |
| CN102148618B CN102148618B (en) | 2014-03-26 |
Family
ID=44422654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010116204.3A Expired - Fee Related CN102148618B (en) | 2010-02-09 | 2010-02-09 | Analogue-digital converter with low-recoil noise and analogue-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102148618B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138762A (en) * | 2011-11-30 | 2013-06-05 | 禾瑞亚科技股份有限公司 | Multi-stage sample and hold circuit |
| CN110139049A (en) * | 2018-02-09 | 2019-08-16 | 佳能株式会社 | Imaging device, imaging system and moving body |
| CN110504969A (en) * | 2018-05-18 | 2019-11-26 | 创意电子股份有限公司 | Analog-digital converter device and measured signal production method |
| CN110957999A (en) * | 2018-09-27 | 2020-04-03 | 台湾积体电路制造股份有限公司 | Circuit for comparator and method for reducing kickback noise in comparator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7768432B2 (en) * | 2008-06-05 | 2010-08-03 | Mediatek Inc. | Analog-to-digital conversion devices and analog-to-digital conversion stages thereof |
| CN101640538A (en) * | 2008-08-01 | 2010-02-03 | 扬智科技股份有限公司 | Analog-to-digital converter |
-
2010
- 2010-02-09 CN CN201010116204.3A patent/CN102148618B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138762A (en) * | 2011-11-30 | 2013-06-05 | 禾瑞亚科技股份有限公司 | Multi-stage sample and hold circuit |
| CN103138762B (en) * | 2011-11-30 | 2016-04-27 | 禾瑞亚科技股份有限公司 | Multistage sample-and-hold circuit |
| CN110139049A (en) * | 2018-02-09 | 2019-08-16 | 佳能株式会社 | Imaging device, imaging system and moving body |
| US11509849B2 (en) | 2018-02-09 | 2022-11-22 | Canon Kabushiki Kaisha | Imaging device, imaging system, and moving body |
| CN110504969A (en) * | 2018-05-18 | 2019-11-26 | 创意电子股份有限公司 | Analog-digital converter device and measured signal production method |
| CN110957999A (en) * | 2018-09-27 | 2020-04-03 | 台湾积体电路制造股份有限公司 | Circuit for comparator and method for reducing kickback noise in comparator |
| CN110957999B (en) * | 2018-09-27 | 2023-10-13 | 台湾积体电路制造股份有限公司 | Circuit for a comparator and method for reducing kickback noise in a comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102148618B (en) | 2014-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101133556B (en) | Multiplication digital to analog converter and pipeline analog to digital converter | |
| US7515086B2 (en) | Pipelined analog-to-digital converter and method of analog-to-digital conversion | |
| CN102075189B (en) | Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration | |
| US6337651B1 (en) | Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage | |
| US8643529B2 (en) | SAR assisted pipelined ADC and method for operating the same | |
| CN1199356C (en) | Deigital logic correction circuit for a pipeline analog to digital (A/D) converter | |
| CN201957001U (en) | Pipeline analog-to-digital converter capable of carrying out background digital calibration | |
| JPH098604A (en) | Switched capacitor gain stage | |
| EP3567720B1 (en) | Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage | |
| CN106953637B (en) | Charge domain amplitude error calibration circuit and DDS circuit adopting same | |
| Malki et al. | A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC | |
| US20130127646A1 (en) | Multiplying digital-to-analog converter (dac) | |
| CN102148618B (en) | Analogue-digital converter with low-recoil noise and analogue-digital converter | |
| CN106788429B (en) | DAC offset error calibration circuit based on charge domain signal processing | |
| CN104184478B (en) | Complementary cascade phase inverter and increment Sigma Delta analog to digital conversion circuits | |
| WO2011104761A1 (en) | Pipeline a/d converter and a/d conversion method | |
| US6295016B1 (en) | Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage | |
| CN110224701B (en) | Pipelined ADC | |
| CN102474264A (en) | Pipeline ad converter and method of correcting output from the converter | |
| KR20160090951A (en) | Low-Power Analog Digital Converter By Using Time-Domain Multi-Stage Interpolation | |
| US8581171B2 (en) | Cyclic A/D converter, image sensor device, and method for generating digital signal from analog signal | |
| CN101789789A (en) | Generating circuit from reference voltage | |
| EP3570436A1 (en) | Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage with reduced capacitor mismatch sensitivity | |
| KR101122734B1 (en) | Multiplying digital-to-analog converter using series capacitors and pipelined analog-to-digital converter including the same | |
| JP6270202B2 (en) | Pipeline type A / D converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140326 Termination date: 20190209 |