CN102148618B - Analogue-digital converter with low-recoil noise and analogue-digital converter - Google Patents
Analogue-digital converter with low-recoil noise and analogue-digital converter Download PDFInfo
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- CN102148618B CN102148618B CN201010116204.3A CN201010116204A CN102148618B CN 102148618 B CN102148618 B CN 102148618B CN 201010116204 A CN201010116204 A CN 201010116204A CN 102148618 B CN102148618 B CN 102148618B
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Abstract
The invention provides an analogue-digital (A/D) converter with low-recoil noise and a secondary A/D converter. A first comparator produces a first output signal at a first output end according to an input signal and a first reference voltage, and comprises a first N-type input transistor for receiving a first signal and a second N-type input transistor for receiving a second signal, wherein the first signal and the second signal are a differential signal pair for forming the input signal. A second comparator produces a second output signal at a second output end according to the input signal and the second reference voltage, and comprises a first P-type input transistor for receiving the first signal and a second P-type input transistor for receiving the second signal. The A/D converter described by the embodiment of the invention can be applied to the analogue-digital conversion of any electronic product, and can reduce the recoil noise without adding extra circuit so as to avoid signal distortion.
Description
Technical field
The invention relates to a kind of analog-digital converter, particularly relevant for a kind of analog-digital converter with low recoil noise (kickback noise).
Background technology
Analog digital conversion (Analog to Digital Conversion) technology has been widely used in different electronic products, pipelined analog-to-digital converter (Pipelined Analog to Digital Converter wherein, pipelined ADC) there is the characteristic of high speed and high-res, be therefore often used in communication system.
Fig. 1 is the schematic diagram of display pipeline formula analog-digital converter 100.Pipelined analog-to-digital converter 100 comprises sample-and-hold circuit 110, modular converter 140 and digital correction circuit 130.Modular converter 140 comprises n level change-over circuit 120a-120n and rear end flash type analog-digital converter (FlashADC) 125, and wherein with series system connection, flash type analog-digital converter 125 is coupled to the change-over circuit 120n of afterbody to n level change-over circuit 120a-120n.110 couples of input signal Si n of sample-and-hold circuit sample rear generation sampled signal S1.Each change-over circuit 120a-120n comprises time analog-digital converter (Sub-ADC) and multiple digital analog converter (Multiplier Digital to AnalogConverter, MDAC).In a change-over circuit, inferior analog-digital converter can convert the analog output signal of previous stage change-over circuit to digital signal, and this digital signal is sent to digital correction circuit 130 and multiple digital analog converter.Then, multiple digital analog converter can convert this digital signal to analog signal and export next stage change-over circuit to.For instance, first order change-over circuit 120a can produce digital signal D1 to digital correction circuit 130 and produce analog signal A1 to second level change-over circuit 120b according to sampled signal S1.Then, change-over circuit 120b in the second level can produce digital signal D2 to digital correction circuit 130 and produce analog signal A2 to third level change-over circuit 120c according to analog signal A1.By that analogy, when flash type analog-digital converter 125 produces digital signal Df to digital correction circuit 130 according to analog signal An, digital correction circuit 130 can be proofreaied and correct received digital signal D1-Dn and digital signal Df and encode, to produce the digital output signal OUT corresponding to analog input signal Sin.
Fig. 2 is the schematic diagram that shows change-over circuit 200.Change-over circuit 200 comprises time analog-digital converter 220 and multiple digital analog converter 240.Inferior analog-digital converter 220 comprises comparator 222 and comparator 224, and multiple digital analog converter 240 comprises digital analog converter 242, adder 244 and amplifier 246.See through comparator 222 and comparator 224, the inferior analog-digital converter 220 in change-over circuit 200 can produce digital signal Dn according to the analog signal An-1 from previous stage change-over circuit, and provides digital signal Dn to multiple digital analog converter 240.Then, digital analog converter 242 can produce signal S2 according to digital signal Dn.Then, adder 244 obtains signal S3 by analog signal An-1 subtraction signal S2, and signal S3 is sent to amplifier 246 amplifies, to produce the analog signal An of change-over circuit 200.In inferior analog-digital converter 220, when the switch of comparator 222 and comparator 224 inside is when switching, the coupling effect of parasitic capacitance has the input that makes comparator 222 and comparator 224 generation of recoil noise (kickback noise).In other words, the switching noise of comparator 222 and comparator 224 will recoil to the change-over circuit of previous stage, thereby reduces the quality of signal and cause distortion.
In order to reduce recoil noise, can add at the front end of latch circuit amplifier (Pre-amplifier in advance traditionally, Pre-AMP), to stop that switching noise (noise) the meeting recoil (kickback) of comparator is to change-over circuit of previous stage, as shown in Fig. 3, comparator 300 comprises amplifier 310 and latch circuit 320 in advance.Yet, use amplifier 310 in advance will make the power consumption of comparator 300 to increase.So when the quantity of pipelined analog-to-digital converter internal conversion circuit is more, the quantity of amplifier also can be more in advance, therefore easily reduce whole power usefulness.
Fig. 4 shows the another kind of comparator 400 that can reduce traditionally recoil noise.Comparator 400 comprises input stage circuit 410 and latch circuit 420, and wherein input stage circuit 410 more comprises neutrality (neutralization) circuit 430.In comparator 400, by latch-up signal latch, control transistor 432,434,436 and 438, can stop the switching noise from latch circuit 420, therefore avoid this switching noise can see through input stage circuit 410 and disturb input signal V
iPand V
iN.
In addition, also can use traditionally redundancy (dummy) circuit (for example comparator or amplifier) to carry out the interference of balance switching noise to input signal, to reduce recoil noise.Fig. 5 A shows a kind of comparator circuit 500 that reduces recoil noise with redundancy comparator.Comparator circuit 500 comprises the first comparator 510 and the second comparator 520.In Fig. 5 A, the second comparator 520 is for carrying out the redundancy comparator of switching over according to signal latchB, and wherein signal latchB is the inversion signal of latch-up signal latch.Therefore, the ON time of the breech lock transistor 531,532,533,534 in the first comparator 510 and the breech lock transistor 541,542,543,544 in the 535 and second comparator 520 and 545 is complementary.So the interior breech lock transistor 531,532,533,534 of the first comparator 510 and 535 is at input signal V
iPand V
iNthe first recoil noise that end produces, can be by the interior breech lock transistor 541,542,543,544 of the second comparator 520 and 545 at input signal V
iPand V
iNthe second recoil noise that end produces offsets.In addition,, because the second comparator 520 is redundancy comparator, therefore, in inferior analog-digital converter, the second comparator 520 of each comparator circuit can not provide and output signal to follow-up circuit, for example multiple digital analog converter and digital correction circuit.Yet in the inferior analog-digital converter of every one-level change-over circuit, each original comparator needs additionally to use redundancy comparator and reduces recoil noise.
With reference to figure 5B, Fig. 5 B shows the inferior analog-digital converter 550 that uses redundancy comparator.Inferior analog-digital converter 550 comprises comparator circuit 500A and comparator circuit 500B, and wherein comparator 520A and comparator 520B are redundancy comparator, and the output signal Dn of inferior analog-digital converter 550 is provided by comparator 510A and 510B.Therefore, when the quantity of pipelined analog-to-digital converter internal conversion circuit is more, the quantity of redundant circuit also can be more, thereby the area that easily reduces whole power usefulness and increase integrated circuit.
Therefore, need a kind of analog-digital converter that reduces recoil noise, it can be saved area and avoid power consumption.
Summary of the invention
The invention provides a kind of analog-digital converter with low recoil noise.Above-mentioned analog-digital converter comprises one first comparator and one second comparator.Above-mentioned the first comparator produces one first output signal according to an input signal and one first reference voltage in one first output, and comprises: one first N-type input transistors, in order to receive a first signal; And, one second N-type input transistors, in order to receive a secondary signal, wherein above-mentioned first signal and above-mentioned secondary signal are for forming a differential wave pair of above-mentioned input signal.Above-mentioned the second comparator produces one second output signal according to above-mentioned input signal and one second reference voltage in one second output, and comprises: one the one P type input transistors, in order to receive above-mentioned first signal; And one the 2nd P type input transistors, in order to receive above-mentioned secondary signal.
Moreover, the invention provides a kind of pipelined analog-to-digital converter with low recoil noise, in order to convert an input signal to a digital signal.Above-mentioned pipelined analog-to-digital converter comprises: a sample-and-hold circuit, in order to produce a sampled signal according to above-mentioned input signal; Multistage change-over circuit, is connected in above-mentioned sample-and-hold circuit with series system; And, a digital correction circuit.Each above-mentioned multistage change-over circuit comprises: an analog-digital converter, in order to one first analog signal of exporting according to the above-mentioned change-over circuit of previous stage, produces a digital signal; And a multiple digital analog converter, in order to produce one second analog signal to the above-mentioned change-over circuit of rear one-level according to above-mentioned digital signal.The above-mentioned digital signal that above-mentioned digital correction circuit provides according to each above-mentioned multistage change-over circuit, produces the above-mentioned digital signal corresponding to above-mentioned input signal.Above-mentioned time analog-digital converter comprises: one first comparator, in order to produce one first output signal according to above-mentioned the first analog signal and one first reference voltage in one first output; And one second comparator, in order to produce one second output signal according to above-mentioned the first analog signal and one second reference voltage in one second output.Above-mentioned the first comparator comprises: one first N-type input transistors, in order to receive a first signal; And, one second N-type input transistors, in order to receive a secondary signal, wherein above-mentioned first signal and above-mentioned secondary signal are for forming a differential wave pair of above-mentioned the first analog signal.Above-mentioned the second comparator comprises: one the one P type input transistors, in order to receive above-mentioned first signal; And, one the 2nd P type input transistors, in order to receive above-mentioned secondary signal, wherein above-mentioned the first output signal and above-mentioned the second output signal form above-mentioned digital signal.
According to the described analog-digital converter of the embodiment of the present invention, can be applicable to the simulation of any electronic product in digital transformation applications, can in the situation that not increasing additional circuit, reduce recoil noise, and then avoid distorted signals.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of display pipeline formula analog-digital converter;
Fig. 2 is the schematic diagram that shows change-over circuit;
Fig. 3 shows a kind of comparator that can reduce traditionally recoil noise;
Fig. 4 shows the another kind of comparator that can reduce traditionally recoil noise;
Fig. 5 A shows a kind of comparator circuit that reduces recoil noise with redundant circuit;
Fig. 5 B shows a kind of the analog-digital converter that uses redundant circuit;
Fig. 6 shows according to the schematic diagram of every one-level change-over circuit in the pipelined analog-to-digital converter described in one embodiment of the invention;
Fig. 7 A and Fig. 7 B show according to the schematic diagram of the inferior analog-digital converter described in one embodiment of the invention;
Fig. 8 shows analog signal An-1 (630) in comparator 630 in Fig. 7 and comparator 640 and the oscillogram of analog signal An-1 (640); And
Fig. 9 is the oscillogram of the recoil noise of display simulation signal An-1.
Drawing reference numeral:
100～pipelined analog-to-digital converter;
110～sample-and-hold circuit;
120a-120n～change-over circuit;
125～flash type analog-digital converter;
130～digital correction circuit;
140,200～modular converter;
220,610～inferior analog-digital converter;
222,224,400,630,640～comparator;
240,620～multiple digital analog converter;
242～digital analog converter;
244～adder;
246,650～amplifier;
410～input stage circuit;
420～latch circuit;
432,434,436,438,531-535,541-545, M6-M9, M26-M29～transistor;
500～comparator circuit;
510,630～the first comparators;
520,640～the second comparators;
660～multiplexer;
720,740～output unit;
A1, A2, An-1, An～analog signal;
An-1P, An-1N～differential output signal
C1-C4～parasitic capacitance;
C5-C6～electric capacity;
D1-Dn, Df～digital signal;
GND～earth terminal;
Latch, latchB～latch-up signal;
M1, M10-M13, M21, M30-M33～switching transistor;
M2-M5, M22-M25～input transistors;
OUT～digital output signal;
S1, S2, S3～signal;
Sin, V
iP, V
iN～input signal
SW1, SW2, SW3～switch;
VDD～power end;
V
out1, V
out2～output signal; And
V
rEF1, V
rEF2, V
rEFN, V
rEFP～reference voltage.
Embodiment
For above and other object of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and coordinate appended graphicly, be described in detail below:
Embodiment:
Fig. 6 shows according to the schematic diagram of every one-level change-over circuit 600 in the pipelined analog-to-digital converter described in one embodiment of the invention.Change-over circuit 600 comprises time analog-digital converter 610 and multiple digital analog converter 620.Inferior analog-digital converter 610 comprises comparator 630 and comparator 640, and multiple digital analog converter 620 comprises three interrupteur SW 1, SW2 and SW3, two capacitor C 5 and C6, amplifier 650 and multiplexer (multiplexer, MUX) 660.In inferior analog-digital converter 610, comparator 630 and 640 can be by the analog signal An-1 from previous stage change-over circuit and reference voltage V
rEF1and V
rEF2compare, to obtain digital signal Dn.Then,, in multiple digital analog converter 620, multiplexer 660 can be selected reference voltage V according to digital signal Dn
rEFN, ground signalling " 0 " and reference voltage V
rEFPone export, i.e. signal S2.In this embodiment, the digital analog converter 242 of the functional similarity of multiplexer 660 in Fig. 2.Then,, by the switching of control switch SW1, SW2 and SW3, can produce signal S3 according to the analog signal An-1 of previous stage change-over circuit and signal S2.Then, 650 couples of signal S3 of amplifier amplify to produce analog signal An.In this embodiment, reference voltage V
rEF1and reference voltage V
rEF2be respectively V
ref/ 4 and-V
ref/ 4, and digital signal Dn is 1.5 bit data.In addition reference voltage V,
rEFPwith reference voltage V
rEFNbetween voltage difference be V
ref, V wherein
refaccording to the practical operation situation of pipelined analog-to-digital converter, determine.Therefore, reference voltage V
rEFPwith reference voltage V
rEFNbetween voltage difference V
refrespectively with reference voltage V
rEF1and reference voltage V
rEF2there is multiple relation.
Fig. 7 A and Fig. 7 B show according to the schematic diagram of the inferior analog-digital converter 610 described in one embodiment of the invention.In this embodiment, the first comparator 630 and the second comparator 640 are dynamic comparer (dynamic comparator).The first comparator 630 comprises input transistors M2-M5, switching transistor M1, M10-M13 and output unit 720.Input transistors M2-M5 is respectively coupled between switching transistor M1 and output unit 720, and wherein switching transistor M1 is coupled to earth terminal GND and output unit 720 is coupled to power end VDD.The grid of input transistors M3 and M5 receives respectively differential output signal An-1P and the An-1N from previous stage change-over circuit, wherein the difference of signal An-1P and signal An-1N is analog signal An-1, and the grid of input transistors M2 and M5 receives respectively reference voltage V
rEFNwith V
rEFP, reference voltage V wherein
rEFPdeduct reference voltage V
rEFNvalue be reference voltage V
rEF1.Output unit 720 comprises transistor M6-M9, and wherein output unit 720 can be in output N
out1output signal V is provided
out1.Transistor M6 is coupled to input transistors M3 and node N
1between, transistor M8 is coupled to power end VDD and node N
1between, transistor M7 is coupled to input transistors M5 and output N
out1between and transistor M9 be coupled to power end VDD and output N
out1between.
Moreover switching transistor M11 is coupled to node N
1and between power end VDD, switching transistor M10 is coupled between input transistors M3 and power end VDD, switching transistor M12 is coupled to output N
out1and between power end VDD and switching transistor M13 be coupled between input transistors M5 and power end VDD.In comparator 630, switching transistor M1 and M10-M13 are controlled by latch-up signal latch.Therefore, when latch-up signal latch controls switching transistor M1 and M10-M13 and switches, the parasitic capacitance (such as C1, C2 etc.) that switching noise will see through on input transistors M2-M5 be coupled to differential output signal An-1P and An-1N and reference voltage V
rEFNwith V
rEFP, make analog signal An-1 and reference voltage V
rEFNwith V
rEFPbe interfered, and then cause distorted signals.
In Fig. 7 A and Fig. 7 B, the second comparator 640 and the first comparator 630 are complementary framework.For instance, the power end VDD in the first comparator 630 and earth terminal GND are exchanged, and each transistorized type is made to suitable change simultaneously, can obtain the second comparator 640.Therefore, in the second comparator 640, switching transistor M21 and input transistors M22-M25 are P transistor npn npn, and switching transistor M30-M33 is N-type transistor.In output unit 740, transistor M26 is coupled to input transistors M23 and node N
2between, transistor M28 is coupled to earth terminal GND and node N
2between, transistor M27 is coupled to input transistors M25 and output N
out2between and transistor M29 be coupled to earth terminal GND and output N
out2between.
In addition, transistor M26-M27 is P transistor npn npn and transistor M28-M29 is N-type transistor, and output unit 740 can be in output N
out2output signal V is provided
out2.Moreover in comparator 640, switching transistor M21 and M30-M33 are controlled by signal latchB, wherein signal latchB is the inversion signal of latch-up signal latch.In addition, the grid of input transistors M23 and M25 receives respectively differential output signal An-1P and the An-1N from previous stage change-over circuit, wherein the difference of signal An-1P and signal An-1N is analog signal An-1, and the grid of input transistors M22 and M25 receives respectively reference voltage V
rEFPwith V
rEFN, reference voltage V wherein
rEFNdeduct reference voltage V
rEFPvalue be reference voltage V
rEF2.At comparator 630 and comparator 640, produce respectively output signal V
out1and output signal V
out2afterwards, inferior analog-digital converter 610 can be by output signal V
out1and output signal V
out2be integrated into digital signal Dn, and provide digital signal Dn for example, to digital correction circuit (130 of Fig. 1) to proofread and correct and to encode.In comparator 640, switching transistor M21 and M30-M33 are also controlled by latch-up signal latchB.Therefore, when latch-up signal latchB controls switching transistor M21 and M30-M33 and switches, the parasitic capacitance (such as C3, C4 etc.) that switching noise also can see through on input transistors M22-M25 be coupled to differential output signal An-1P and An-1N and reference voltage V
rEFNwith V
rEFP.
Although it should be noted that the switching noise of comparator 630 and comparator 640 can be coupled respectively to differential output signal An-1P and An-1N and reference voltage V
rEFNwith V
rEFPbut the complementary framework of comparator 630 and comparator 640 can make 630 couples of differential output signal An-1P of comparator and An-1N and reference voltage V
rEFNwith V
rEFPrecoil noise can be compared recoil noise institute's balance and the payment of device 640.With reference to figure 8, Fig. 8 shows analog signal An-1 (630) in comparator 630 in Fig. 7 A and Fig. 7 B and comparator 640 and the oscillogram of analog signal An-1 (640), wherein analog signal An-1 (630) represent differential wave An-1P in comparator 630 with the difference of An-1N differential wave An-1P and An-1N poor in analog signal An-1 (640) expression comparator 640.When time point t1, the recoil noise of comparator 630 can make analog signal An-1 (630) produce surging P1 up and the recoil noise of comparator 640 can make analog signal An-1 (640) produce surging P2 down.Because surging P1 and surging P2 can mutually offset, the interference of the noise that therefore in fact recoils on analog signal An-1 can reduce.Fig. 9 is the oscillogram of the recoil noise of display simulation signal An-1, and wherein waveform S910 describes the impact of tradition recoil noise and waveform S920 describes according to the impact of the recoil noise described in the embodiment of the present invention.For the caused surging of recoil noise, the peak swing H2 of waveform S920 is significantly less than the peak swing H1 of waveform S910.
Feature of the present invention is to utilize the kenel of the input transistors of two comparators in time analog-digital converter different, the input transistors of a comparator is N-type transistor, the input transistors of another comparator is P transistor npn npn, and because P type and the transistorized electrical characteristic of N-type can mutually offset its recoil noise producing in signal.And above-mentioned lifted embodiment is not in order to limit the present invention, as prior art Fig. 3, comparator in inferior analog-digital converter in Fig. 4 and Fig. 5 A and Fig. 5 B, remove respectively in advance after amplifying circuit, neutral circuit and redundancy comparator, the input transistors that receives differential wave is selected respectively to the transistor of two kinds of kenels, i.e. spirit according to the invention and can reach the effect that reduces recoil noise.
As described previously, can be applicable to the simulation of any electronic product in digital transformation applications according to the described analog-digital converter of the embodiment of the present invention, it can reduce recoil noise in the situation that not increasing additional circuit, and then avoids distorted signals.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (4)
1. an analog-digital converter with low recoil noise, in order to an input signal converted to a digital signal and can reduce recoil noise, is characterized in that, described analog-digital converter comprises:
One sample-and-hold circuit, in order to produce a sampled signal according to described input signal;
Multistage change-over circuit, is connected in described sample-and-hold circuit with series system, and wherein described in each, multistage change-over circuit comprises:
An analog-digital converter, in order to the first analog signal of exporting according to the change-over circuit of previous stage, produces a digital signal, and wherein said time analog-digital converter comprises:
One first comparator, has a plurality of the first type input transistors, in order to produce one first output signal according to described the first analog signal and one first reference voltage in one first output; And
One second comparator, there are a plurality of Second-Type input transistors, in order to produce one second output signal according to described the first analog signal and one second reference voltage in one second output, wherein said the first output signal and described the second output signal form described digital signal, pass through the recoil noise that used described the first type and Second-Type input transistors can reduce described digital signal;
One multiple digital analog converter, in order to produce one second analog signal to the described change-over circuit of rear one-level according to described digital signal; And
One digital correction circuit, in order to the described digital signal providing according to multistage change-over circuit described in each, produces the described digital signal corresponding to described input signal;
Wherein, described the first comparator more comprises:
One first N-type input transistors, in order to receive a first signal;
One second N-type input transistors, in order to receive a secondary signal, wherein said first signal and described secondary signal are for forming a differential wave pair of described the first analog signal;
One first N-type switching transistor, is coupled to an earth terminal, has a grid in order to receive one first latch-up signal;
One first output unit, in order to provide described the first output signal;
One the 3rd N-type input transistors, is coupled between described the first N-type switching transistor and described the first output unit and is parallel to described the first N-type input transistors, in order to receive one the 3rd reference voltage; And
One the 4th N-type input transistors, is coupled between described the first N-type switching transistor and described the first output unit and is parallel to described the second N-type input transistors, in order to receive one the 4th reference voltage;
Described the second comparator comprises:
One the one P type input transistors, in order to receive described first signal;
One the 2nd P type input transistors, in order to receive described secondary signal;
One the one P type switching transistor, is coupled to a power end, has a grid in order to receive one second latch-up signal, and wherein said the second latch-up signal is the inversion signal of described the first latch-up signal;
One second output unit, in order to provide described the second output signal;
One the 3rd P type input transistors, is coupled between a described P type switching transistor and described the second output unit and is parallel to a described P type input transistors, in order to receive described the 4th reference voltage; And
One the 4th P type input transistors, is coupled between a described P type switching transistor and described the second output unit and is parallel to described the 2nd P type input transistors, in order to receive described the 3rd reference voltage;
The difference that wherein said the 3rd reference voltage deducts described the 4th reference voltage is described the first reference voltage, and the difference that described the 4th reference voltage deducts described the 3rd reference voltage is described the second reference voltage.
2. a time analog-digital converter, according to a received analog signal, produces a digital signal, it is characterized in that, described time analog-digital converter comprises:
One first comparator, has a plurality of the first type input transistors, in order to produce one first output signal according to described analog signal and one first reference voltage; And
One second comparator, has a plurality of Second-Type input transistors, in order to produce one second output signal according to described analog signal and one second reference voltage,
Wherein said the first output signal and described the second output signal form described digital signal, pass through the recoil noise that used described the first type and Second-Type input transistors can reduce described digital signal;
The first N-type input transistors, in order to receive a first signal;
One second N-type input transistors, in order to receive a secondary signal, wherein said first signal and described secondary signal are for forming a differential wave pair of described analog signal;
One first N-type switching transistor, is coupled to an earth terminal, has a grid in order to receive one first latch-up signal;
One first output unit, in order to provide described the first output signal;
One the 3rd N-type input transistors, is coupled between described the first N-type switching transistor and described the first output unit and is parallel to described the first N-type input transistors, in order to receive one the 3rd reference voltage; And
One the 4th N-type input transistors, is coupled between described the first N-type switching transistor and described the first output unit and is parallel to described the second N-type input transistors, in order to receive one the 4th reference voltage;
Wherein, described the second comparator more comprises:
One the one P type input transistors, in order to receive described first signal;
One the 2nd P type input transistors, in order to receive described secondary signal;
One the 5th P type switching transistor, is coupled to a power end, has a grid in order to receive one second latch-up signal, and wherein said the second latch-up signal is the inversion signal of described the first latch-up signal;
One second output unit, in order to provide described the second output signal;
One the 3rd P type input transistors, is coupled between described the 5th P type switching transistor and described the second output unit and is parallel to a described P type input transistors, in order to receive described the 4th reference voltage; And
One the 4th P type input transistors, is coupled between described the 5th P type switching transistor and described the second output unit and is parallel to described the 2nd P type input transistors, in order to receive described the 3rd reference voltage;
The difference that wherein said the 3rd reference voltage deducts described the 4th reference voltage is described the first reference voltage, and the difference that described the 4th reference voltage deducts described the 3rd reference voltage is described the second reference voltage.
3. as claimed in claim 2 analog-digital converter, is characterized in that, described the first comparator more comprises:
One the one P type switching transistor, is coupled between described power end and described the first N-type input transistors, has a grid in order to receive described the first latch-up signal;
One the 2nd P type switching transistor, is coupled between described power end and a first node, has a grid in order to receive described the first latch-up signal;
One the 3rd P type switching transistor, is coupled between described power end and described the second N-type input transistors, has a grid in order to receive described the first latch-up signal; And
One the 4th P type switching transistor, is coupled between described power end and described the first output, has a grid in order to receive described the first latch-up signal; And
Described the first output unit comprises:
One the one P transistor npn npn, is coupled between a power end and described first node, has a grid and is coupled to described the first output;
One the 2nd P transistor npn npn, is coupled between described power end and described the first output, has a grid and is coupled to described first node;
One first N-type transistor, is coupled between a described P transistor npn npn and described the first N-type input transistors, has a grid and is coupled to described the first output; And
One second N-type transistor, is coupled between described the 2nd P transistor npn npn and described the second N-type input transistors, has a grid and is coupled to described first node.
4. as claimed in claim 2 analog-digital converter, is characterized in that, described the second comparator more comprises:
One second N-type switching transistor, is coupled between described earth terminal and a described P type input transistors, has a grid in order to receive described the second latch-up signal;
One the 3rd N-type switching transistor, is coupled between described earth terminal and a Section Point, has a grid in order to receive described the second latch-up signal;
One the 4th N-type switching transistor, is coupled between described earth terminal and described the 2nd P type input transistors, has a grid in order to receive described the second latch-up signal;
One the 5th N-type switching transistor, is coupled between described earth terminal and described the second output, has a grid in order to receive described the second latch-up signal; And
Described the second output unit comprises:
One the 3rd N-type transistor, is coupled between described earth terminal and described Section Point, has a grid and is coupled to described the second output;
One the 4th N-type transistor, is coupled between described earth terminal and described the second output, has a grid and is coupled to described Section Point;
One the 3rd P transistor npn npn, is coupled between described the first N-type transistor and a described P type input transistors, has a grid and is coupled to described the second output; And
One the 4th P transistor npn npn, is coupled between described the second N-type transistor and described the 2nd P type input transistors, has a grid and is coupled to described Section Point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010116204.3A CN102148618B (en) | 2010-02-09 | 2010-02-09 | Analogue-digital converter with low-recoil noise and analogue-digital converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010116204.3A CN102148618B (en) | 2010-02-09 | 2010-02-09 | Analogue-digital converter with low-recoil noise and analogue-digital converter |
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| JP7059031B2 (en) | 2018-02-09 | 2022-04-25 | キヤノン株式会社 | Imaging device, imaging system, mobile body |
| CN110504969B (en) * | 2018-05-18 | 2023-03-24 | 创意电子股份有限公司 | Analog-digital converter device and method for generating signal to be tested |
| US10819316B2 (en) * | 2018-09-27 | 2020-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuits and methods for reducing kickback noise in a comparator |
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| CN101599765A (en) * | 2008-06-05 | 2009-12-09 | 联发科技股份有限公司 | Analog-digital commutator and analog-to-digital conversion level |
| CN101640538A (en) * | 2008-08-01 | 2010-02-03 | 扬智科技股份有限公司 | Analog-to-digital converter |
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| CN101640538A (en) * | 2008-08-01 | 2010-02-03 | 扬智科技股份有限公司 | Analog-to-digital converter |
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