CN117254811A - Successive approximation type analog-to-digital converter, and calibration method and medium for capacitor array of successive approximation type analog-to-digital converter - Google Patents
Successive approximation type analog-to-digital converter, and calibration method and medium for capacitor array of successive approximation type analog-to-digital converter Download PDFInfo
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Abstract
The present disclosure relates to a successive approximation type analog-to-digital converter and a method and medium for calibrating a capacitor array thereof, which belong to the technical field of signal processing and solve the technical problem that a large amount of chip area is required to be occupied during the calibration of the capacitor array in the current successive approximation type analog-to-digital converter, and meanwhile, additional power consumption is consumed by a switch and a logic circuit. The method comprises the following steps: performing analog-to-digital conversion on the first analog signal based on an analog-to-digital conversion formula, and acquiring a first digital signal after analog-to-digital conversion; inputting the first analog signal into a successive approximation type analog-to-digital converter to obtain a second digital signal output by the successive approximation type analog-to-digital converter; acquiring a difference signal between the first digital signal and the second digital signal; and calibrating the capacitor array based on the difference signal to obtain the calibrated weight of the capacitor in the capacitor array. By adopting the method, the parasitic capacitance in the successive approximation type analog-to-digital converter capacitor array can be corrected without using an additional correction circuit and a conversion period.
Description
Technical Field
The disclosure relates to the technical field of signal processing, and in particular relates to a successive approximation type analog-to-digital converter and a calibration method and medium of a capacitor array of the successive approximation type analog-to-digital converter.
Background
Analog-to-Digital Converter (ADC) is an essential component of almost every complex integrated circuit. Particularly in recent years, the rapid development of wireless communications has also provided exceptional opportunities for ADC applications therein. Among them, the fifth generation mobile communication (5G) requires that the ADC accuracy applied in the 5G base station is not lower than 12 bits. Faster data transmission rates in 5G applications, and higher data transmission quality place higher demands on the conversion speed and accuracy of the ADC. Meanwhile, wireless communication is mainly applied to a portable handheld terminal, and in order to increase the standby time of the terminal equipment, battery life is generally required to be as long as possible, which also puts higher demands on the low-power consumption technology of the ADC.
In order to meet the wider application scenario and increasing performance requirements, ADCs of different structures have been developed, wherein typical structures include Flash (Flash) ADC, pipelined (Pipeline) ADC, successive approximation (Successive Approximation Register, SAR) ADC, sigma-delta ADC. For the mainstream ADC structures at present, three characteristics of speed, precision and power consumption are mutually influenced and mutually restricted. Compared with the ADC with other structures, the structure of the SAR ADC has the characteristics of low power consumption, simple structure and passivity, and is always the first choice in the low power consumption application scene. SAR ADCs have the advantage of natural low power consumption because they use a combination of digital and analog circuitry, and the analog part does not require an accurate active amplifier, thus reducing dc power consumption. The main power consumption comes from dynamic power consumption caused by charging and discharging of the switch capacitor, and the overall power consumption can be further reduced by matching with a carefully designed switch switching mode. Meanwhile, the SAR ADC has the advantages of speed improvement and precision improvement, so that the SAR ADC stands out in a plurality of ADC structures.
In a high-precision SAR ADC, a high-precision DAC (Digital-to-Analog converter) is an important component, and is often composed of a binary capacitor array, and different output voltages are realized through the inversion of different capacitors. However, the actual capacitance value of the single capacitor deviates from the ideal value due to the process, the linearity of the output is deteriorated due to the mismatch between different capacitors, and the accuracy performance of the integral high-accuracy SAR ADC is directly limited. Proper amplification of the capacitor size can improve the matching degree of the capacitor, but can reduce the overall conversion speed of the ADC and improve the power consumption. Therefore, calibration techniques for capacitive mismatch in SAR ADCs appear successively.
Most of the existing self-calibration techniques belong to the foreground calibration method, and the auxiliary circuit is connected to the output end of the DAC through the calibration capacitance circuit. And mismatch error detection is carried out before the ADC works normally, and the calibration logic controls the auxiliary DAC and the comparator to quantify error voltage caused by capacitor mismatch and send the error voltage into the calibration memory. In the calibration stage, the stored error information is recovered into analog voltage quantity through the auxiliary DAC and is overlapped on the output of the main DAC, so that the calibrated accurate output is obtained. However, calibrating the DAC requires a lot of chip area, while the switches and logic consume additional power, and the accuracy of its mismatch detection is limited by the accuracy of the ADC itself. Quantization errors may be more severe if the resolution of the ADC itself is insufficient.
Disclosure of Invention
To overcome the problems in the related art, the present disclosure provides a successive approximation analog-to-digital converter and a method and medium for calibrating a capacitor array thereof.
According to a first aspect of the present disclosure, there is provided a method of calibrating a capacitor array in a successive approximation analog-to-digital converter, the method comprising:
performing analog-to-digital conversion on the first analog signal based on an analog-to-digital conversion formula, and acquiring a first digital signal after analog-to-digital conversion;
inputting the first analog signal into the successive approximation type analog-to-digital converter to obtain a second digital signal output by the successive approximation type analog-to-digital converter;
acquiring a difference signal between the first digital signal and the second digital signal;
and calibrating the capacitor array based on the difference signal to obtain the calibrated weight of the capacitor in the capacitor array.
The calibrating the capacitor array based on the difference signal to obtain a calibrated weight of a capacitor in the capacitor array includes:
acquiring ideal weight and weight to be calibrated of the capacitors in the capacitor array;
and calibrating the capacitor array based on the ideal weight, the weight to be calibrated and the difference signal to obtain the calibrated weight of the capacitors in the capacitor array.
The calibrating the capacitor array based on the ideal weight, the weight to be calibrated and the difference signal to obtain a calibrated weight of a capacitor in the capacitor array includes:
acquiring weight error parameters based on the ideal weight, the weight to be calibrated and the difference signal;
performing iterative calculation on the weight to be calibrated based on an iterative algorithm until the weight error parameter is smaller than a set threshold;
and taking the weight to be calibrated output by the last iterative calculation as the weight after calibration.
Wherein, the obtaining the weight error parameter includes:
the weight error is obtained based on the following manner:
weight error =Wherein N represents the number of the capacitors in the capacitor array, i represents the corresponding number of bits, +.>Representing the weight to be calibrated of the capacitance corresponding to bit i,/for the capacitor>Representing the ideal weight of the capacitance corresponding to bit i,/and>representing the value at said i-th bit of the first digital signal, delta representing said difference signal;
and obtaining the weight error parameter by calculating the root mean square of the weight error.
The obtaining the weight error parameter by calculating the root mean square of the weight error includes:
the weight error parameter is obtained based on the following modes:
weight error parameter =Wherein MINrms () represents root mean square, M represents the number of sampling points included in one periodic waveform of the successive approximation analog-to-digital converter output waveform, < + >>Representing the difference signal corresponding to the j-th sampling point in M sampling points,>and->Respectively representing the weight to be calibrated and the ideal weight corresponding to the ith bit of the jth sampling point,>representing a value on the ith bit of the first digital signal corresponding to the jth sampling point;
wherein the same sampling point is adopted for all sampling points in the M sampling pointsAnd->And (5) performing iterative calculation.
The iterative algorithm-based iterative calculation of the weight to be calibrated comprises the following steps:
in the first iterative calculation, setting the initial value of the weight to be calibrated as the ideal weight.
The iterative algorithm-based iterative calculation of the weight to be calibrated comprises the following steps:
and taking the weight to be calibrated output by each iterative calculation as an initial value of the weight to be calibrated adopted by the next iterative calculation.
Wherein the iterative algorithm is a simplex method.
According to a second aspect of the present disclosure, there is provided a successive approximation analog-to-digital converter comprising:
the first digital signal acquisition module is configured to perform analog-to-digital conversion on the first analog signal based on an analog-to-digital conversion formula and acquire the analog-to-digital converted first digital signal;
the analog-to-digital conversion module is arranged for carrying out analog-to-digital conversion on the input first analog signal to obtain a second digital signal;
a difference acquisition module configured to acquire a difference signal between the first digital signal and the second digital signal;
and the calibration module is used for calibrating the capacitor array based on the difference signal so as to acquire the calibrated weight of the capacitor in the capacitor array.
According to a third aspect of the present disclosure, there is provided a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of a successive approximation analog to digital converter, capable of performing the above method.
The method has the following beneficial effects: parasitic capacitance in the SAR ADC capacitor array can be corrected without using an additional correction circuit and a conversion period, so that the influence of the correction circuit on the self performance of the SAR ADC is avoided. In addition, the calibrating method has low dependency on the SAR ADC circuit structure, and is suitable for SAR ADCs with different precision and different circuit structures.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a flow chart illustrating a method of calibrating a capacitive array in a SAR ADC according to an exemplary embodiment;
FIG. 2 is a signal waveform of a single cycle obtained by averaging signals over multiple cycles of SAR ADC output, according to an exemplary embodiment;
FIG. 3 is an exemplary waveform of a difference signal between an ideal signal and an actual signal, shown according to an exemplary embodiment;
FIG. 4 is a flow chart illustrating a method of calibrating a capacitive array in a SAR ADC according to an exemplary embodiment;
FIG. 5 is a convergence process of an iterative algorithm in a method of calibrating a capacitive array in a SAR ADC, according to an exemplary embodiment;
FIG. 6 is a graph showing normalized post-calibration weights output when analog signals of different frequencies and different waveforms are input using a method of calibrating a capacitive array in a SAR ADC according to an exemplary embodiment;
FIG. 7 is a schematic diagram showing waveform comparison of calculated errors and actual errors using a method of calibrating a capacitive array in a SAR ADC according to an exemplary embodiment;
FIG. 8 is a spectral plot of a single tone sine wave output by a SAR ADC chip without capacitive weight calibration of the present disclosure;
FIG. 9 is a graph of a spectrum of a single tone sine wave output by a SAR ADC chip employing capacitive weight calibration of the present disclosure, shown in accordance with an exemplary embodiment;
fig. 10 is a block diagram of a SAR ADC, according to an example embodiment.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention as detailed in the accompanying claims.
Although the calibration technology of capacitor mismatch in the SAR ADC appears successively, in the foreground calibration method adopted at present, the calibration DAC needs to occupy a large amount of chip area, and meanwhile, the switch and the logic circuit consume additional power consumption, and the accuracy of mismatch detection is limited by the accuracy of the ADC. And, if the resolution of the ADC itself is insufficient, quantization errors may be more serious.
In an exemplary embodiment of the present disclosure, a method for calibrating a capacitor array in a successive approximation analog-to-digital converter (hereinafter SAR ADC) is provided. FIG. 1 is a flow chart illustrating a method of calibrating a capacitive array in a SAR ADC according to an exemplary embodiment, as shown in FIG. 1, including the steps of:
step 101, performing analog-to-digital conversion on a first analog signal based on an analog-to-digital conversion formula, and acquiring a first digital signal after analog-to-digital conversion;
102, inputting a first analog signal into an SAR ADC to obtain a second digital signal output by the SAR ADC;
step 103, obtaining a difference signal between the first digital signal and the second digital signal;
step 104, calibrating the capacitor array based on the difference signal to obtain the calibrated weight of the capacitor in the capacitor array.
In step 101, the first digital signal is a signal obtained by performing ideal analog-to-digital conversion on the first analog signal, that is, the signal is calculated based on an ideal analog-to-digital conversion model formula. That is, the first digital signal is an ideal digital signal after analog-to-digital conversion. For example, for a 12bit ADC, the input is 0-1V analog voltage signal, the output digital signal is 0-4095, when the input is 1V analog voltage signal, the output digital signal is 4095, and when the input is 0.5V analog voltage signal, the output digital signal is 0.5/1 multiplied by 2≡12 to 2048. Illustratively, the first analog signal input is a triangular wave, which is discussed here as an example because triangular waves are easy to implement on the one hand and traversal of the output from lowest to highest on the other hand can be implemented.
The second digital signal obtained in step 102 is a digital signal obtained after the first analog signal is subjected to analog-to-digital conversion by the SAR ADC. That is, the second digital signal is an actual digital signal after SAR ADC conversion. When the second digital signal is acquired, the second digital signal can be acquired by averaging signals over a plurality of periods, so that the influence of noise on the accuracy of the calibration algorithm is reduced. Illustratively, a single-cycle signal waveform obtained by averaging signals over a plurality of cycles is shown in fig. 2, where the abscissa represents time and the ordinate represents signal amplitude. The output waveform shown in fig. 2 is approximately triangular in shape because the number of points included in one cycle is large (4096 for a 12bit ADC), and the oscilloscope display interface is reduced to include one cycle or several cycles, and is a triangular wave, and if the oscilloscope display interface is enlarged to include only several points, it is a step-shaped wave.
In step 103, the first digital signal is an ideal signal obtained by performing analog-to-digital conversion on the first analog signal, and the second digital signal is an actual signal obtained by performing analog-to-digital conversion on the first analog signal through the SAR ADC, so that a difference signal between the first digital signal and the second digital signal is a difference signal between the ideal signal and the actual signal. Fig. 3 shows an exemplary waveform of a difference signal between an ideal signal and an actual signal, wherein the abscissa represents time and the ordinate represents signal amplitude.
In step 104, an objective function of an iterative algorithm is constructed by using the difference signals obtained in the above step to calibrate the capacitor array, so as to obtain the calibrated weights of the capacitors in the capacitor array.
By adopting the calibration method, parasitic capacitance in the SAR ADC capacitive array can be corrected without using an additional correction circuit and a conversion period, thereby avoiding the influence of the calibration circuit on the self performance of the SAR ADC. In addition, the calibrating method has low dependency on the SAR ADC circuit structure, and is suitable for SAR ADCs with different precision and different circuit structures.
In an exemplary embodiment, calibrating the capacitive array based on the difference signal to obtain a calibrated weight of a capacitance in the capacitive array includes:
acquiring ideal weight and weight to be calibrated of the capacitors in the capacitor array;
and calibrating the capacitor array based on the ideal weight, the weight to be calibrated and the difference signal to obtain the calibrated weight of the capacitor in the capacitor array.
The capacitor array includes N capacitors, where N is a positive integer, and generally N is greater than or equal to 12. Ideally, the capacitors in the capacitor array are binary weighted, e.g., for a capacitor array comprising 12 capacitors, where each capacitor is weighted by w 12 =2 11 ，w 11 =2 10 ，w 10 =2 9 ，…，w 1 =2 0 The weight is taken as an ideal weight. That is, the ideal weight is a binary weight. Because of parasitic capacitance and various noises, the weight to be calibrated is the real weight of each capacitor in the capacitor array, and the deviation between the weight to be calibrated and the real weight is expressed as w' 12 ，w' 11 ，w' 10 ，…，w' 1 . Similarly, for a 12bit ADC, i.e. a capacitor array in a SAR ADC comprising 12 capacitors, after inputting an analog signal, the output digital signal is B 12 B 11 B 10 …B 1 . For example, a SAR ADC with an input of 0.5V outputs 1000 0000 0000, where B 12 =1，B 11 =0，B 10 =0，…B 1 =0。
The error of the ith bit of the output of a certain SAR ADC under the real weight and the ideal weight is (w' i - w i ) And B is connected with i And calibrating each capacitance weight in the capacitance array based on the error of each bit output by the SAR ADC and the difference signal, and when the error of each bit is very close to the difference signal, considering that the error between the ideal weight and the real weight is close to the error between the ideal waveform and the real waveform, wherein the real weight at the moment represents the real weight after noise interference is eliminated. Wherein, for a 12bit ADC, the value range of i is 1-12.
The calibration method of the embodiment processes in the digital domain, so that the normal work of the SAR ADC is not disturbed in the calibration process, and the SAR ADC can keep the maximum sampling rate.
In an exemplary embodiment, calibrating the capacitor array based on the ideal weight, the weight to be calibrated, and the difference signal to obtain a calibrated weight of the capacitors in the capacitor array includes:
acquiring weight error parameters based on the ideal weight, the weight to be calibrated and the difference signal;
performing iterative calculation on the weight to be calibrated based on an iterative algorithm until the weight error parameter is smaller than a set threshold;
and taking the weight to be calibrated output by the last iterative calculation as the weight after calibration.
The weight error parameter is a parameter obtained based on the weight error, and is used for constructing a functional formula in an iterative algorithm. In the iterative algorithm, when the weight error parameter tends to 0, the weight to be calibrated adopted in the calculation is considered to be converged to a value closest to the real weight. The weight error parameter tending to 0 may be regarded as the weight error parameter being smaller than a set threshold value, which may be set according to actual needs. Therefore, the capacitance weight is calibrated by adopting the iterative algorithm, and a value close to the actual capacitance weight can be obtained. And the method does not require the aid of additional calibration circuitry.
In an exemplary embodiment, obtaining the weight error parameter includes:
the weight error is obtained based on the following manner:
weight error =Wherein N represents the number of capacitors in the capacitor array, i represents the corresponding number of bits, +.>Weight to be calibrated representing the capacitance corresponding to the ith bit,/->Ideal weight representing the capacitance corresponding to the ith bit, +.>Representing the first digital signal, i.e. the value at the i-th bit of the digital signal after ideal analog-to-digital conversion (based on an analog-to-digital conversion model formula) of the first analog signal, delta representing the difference signal;
and obtaining the weight error parameter by calculating the root mean square of the weight error.
In this embodiment, the weight error is calculated by calculating the error (w' i -w i ) And B is connected with i The product of the difference with the actual error delta. When calculating the error (w' i -w i ) And B is connected with i When the product is very close to the actual error delta, then it is considered thatThe actual weight of the capacitor is approached, so that the purpose of weight calibration is realized.
In an exemplary embodiment, obtaining the weight error parameter by calculating a root mean square of the weight error includes:
the weight error parameter is obtained based on the following modes:
weight error parameter =Wherein, MINrms () represents root mean square, M represents the sampling point number included in one period waveform of the SAR ADC output waveform, and the sampling point number can be set according to actual needs. />Representing the difference signal corresponding to the j-th sampling point in the M sampling points,/for>And->Respectively representing the weight to be calibrated and the ideal weight corresponding to the ith bit of the jth sampling point,/>Representing a value on an ith bit of the first digital signal corresponding to the jth sampling point;
wherein the same is used for all sampling points in the M sampling pointsAnd->And (5) performing iterative calculation.
In this embodiment, the weight error parameter is calculated by using all the number of points in one period obtained from the output waveform, and in this way, the weight after calibration can be obtained as accurately as possible. Wherein the weight error parameter may be obtained by calculating the root mean square of the weight error. That is, the root mean square of the weight error is used as the optimization function in the iterative algorithm.
The weight error parameter may be obtained by calculating a standard deviation of the weight error, an average value of absolute values, or the like.
In an exemplary embodiment, performing iterative calculation on weights to be calibrated based on an iterative algorithm includes:
in the first iterative calculation, the initial value of the weight to be calibrated is set as the ideal weight.
In this embodiment, the ideal weight of the capacitor is taken as the initial value of the weight to be calibrated when the first iterative calculation is performed, i.e. w 'at this time' i -w i =0。
In an exemplary embodiment, performing iterative calculation on weights to be calibrated based on an iterative algorithm includes:
and taking the weight to be calibrated output by each iterative calculation as an initial value of the weight to be calibrated adopted by the next iterative calculation.
The output result w 'of each iterative calculation' i As the initial value of the weight to be calibrated in the next iterative calculation, the convergence process of the iteration can be quickened. Therefore, the iteration error is close to 0 through multiple iteration calculations, and the output result of the iteration calculation is converged to the value closest to the real weight.
In an exemplary embodiment, the iterative algorithm is a simplex method.
The iterative algorithm may employ the Simplex Method. The algorithm uses a derivative-free method, and can find the minimum value of an unconstrained multi-variable function. The algorithm starts from an initial estimate and finds the minimum of a scalar function comprising a plurality of functions, which is a widely accepted unconstrained nonlinear optimization algorithm. Because of the above-described advantages of this algorithm, this embodiment employs a simplex method as the iterative algorithm.
It should be noted that the various implementation methods in the above-described exemplary embodiments may be variously combined in a desired manner.
Fig. 4 shows a specific embodiment of a calibration method according to the present disclosure, in which the SAR ADC is a 12bit ADC and the input is an analog triangle wave, the calibration method comprising:
step 401, performing analog-to-digital conversion on an analog signal input into the SAR ADC based on an analog-to-digital conversion formula, and acquiring an ideal digital signal after analog-to-digital conversion;
step 402, inputting the analog signal into a SAR ADC to obtain an actual digital signal output by the SAR ADC;
step 403, obtaining a difference signal delta between the ideal digital signal and the actual digital signal;
step 404, determining an ideal weight of the capacitor in the SAR ADC capacitor array as w 12 =2 11 ，w 11 =2 10 ，w 10 =2 9 ，…，w 1 =2 0 The initial value of the weight to be calibrated is w 12 =2 11 ，w 11 =2 10 ，w 10 =2 9 ，…，w 1 =2 0 ；
Step 405, determining a weight error;
step 406, obtaining weight error parameters by calculating the root mean square of the weight error;
step 407, performing iterative computation on the weight to be calibrated based on a Simplex iterative algorithm of the Simplex Method until the weight error parameter is smaller than a set threshold, wherein the weight to be calibrated output by each iterative computation is used as an initial value of the weight to be calibrated adopted by the next iterative computation;
in step 408, the weight to be calibrated output by the last iteration calculation is used as the weight after calibration of the capacitors in the capacitor array.
In the above step, the weight error =，
Weight error parameter =。
By adopting the calibration method, the calibrated weight w 'of each capacitor in the capacitor array can be obtained' 12 ，w' 11 ，w' 10 ，…，w' 1 . For the same SAR ADC chip to be calibrated, FIG. 5 shows the convergence process of the iterative algorithm in the calibration method, different lines correspond to different input signals, wherein the abscissa represents the number of loops, and the ordinate represents the minimum mean square error, and FIG. 5 is a display interface of the device simulating the convergence process. Fig. 6 shows that when analog signals of different frequencies and different waveforms are input, a very similar normalized weight after calibration is output, wherein the abscissa represents the number of bits corresponding to the weight, the number of bits decreases in order from left to right, and the ordinate represents the normalized weight. Wherein the lowest order w' 1 The difference is larger than the other bits because of the larger influence of noise factors. FIG. 7 shows the calculated error (w' i - w i ) And B is connected with i Comparing the product with the waveform of the actual error delta, it can be seen that the two are very similar, except that there is a constant deviation, where the abscissa indicates time and the ordinate indicates the error signal amplitude. Wherein fig. 5, fig. 6, and fig. 7 are all display interfaces of related devices.
The output performance of the SAR ADC chip after the capacitance weight calibration is greatly improved. For example, fig. 8 shows a spectrum of a single-tone sine wave output by a SAR ADC chip that has not been subjected to capacitive weight calibration, which shows that the spectrum contains harmonic components of different orders due to capacitive mismatch, with a Spurious free dynamic range (spirious-Free Dynamic Range, SFDR) of 50.0 dB and an effective number of bits (Effective Numbers of Bits, ENOB) of 7.87 bits. Fig. 9 shows a spectrum diagram of a single-tone sine wave output by a capacitor weight calibrated SAR ADC chip with a Spurious Free Dynamic Range (SFDR) boost of 63.5 dB and an effective bit number (ENOB) boost of 9.08 bits. Fig. 8 and 9 are both display interfaces of the apparatus for measuring a spectrum.
In an exemplary embodiment of the present disclosure, a SAR ADC is provided. Fig. 10 is a block diagram of a SAR ADC, shown in fig. 10, according to an exemplary embodiment, comprising:
a first digital signal acquisition module 1001 configured to perform analog-to-digital conversion on a first analog signal based on an analog-to-digital conversion formula, and acquire an analog-to-digital converted first digital signal;
the analog-to-digital conversion module 1002 is configured to perform analog-to-digital conversion on the input first analog signal, and obtain a second digital signal;
a difference acquisition module 1003 configured to acquire a difference signal between the first digital signal and the second digital signal;
the calibration module 1004 is configured to calibrate the capacitor array based on the difference signal to obtain a calibrated weight of the capacitors in the capacitor array.
In an exemplary embodiment, the calibration module 1004 is further configured to:
acquiring ideal weight and weight to be calibrated of the capacitors in the capacitor array;
and calibrating the capacitor array based on the ideal weight, the weight to be calibrated and the difference signal to obtain the calibrated weight of the capacitor in the capacitor array.
In an exemplary embodiment, the calibration module 1004 is further configured to:
acquiring weight error parameters based on the ideal weight, the weight to be calibrated and the difference signal;
performing iterative calculation on the weight to be calibrated based on an iterative algorithm until the weight error parameter is smaller than a set threshold;
and taking the weight to be calibrated output by the last iterative calculation as the weight after calibration.
In an exemplary embodiment, the calibration module 1004 is further configured to:
the weight error is obtained based on the following manner:
weight error =Wherein N represents the number of capacitors in the capacitor array, i represents the corresponding number of bits, +.>Weight to be calibrated representing the capacitance corresponding to the ith bit,/->Ideal weight representing the capacitance corresponding to the ith bit, +.>Representing the value at bit i of the first digital signal, delta representing the difference signal;
and obtaining the weight error parameter by calculating the root mean square of the weight error.
In an exemplary embodiment, the calibration module 1004 is further configured to:
the weight error parameter is obtained based on the following modes:
weight error parameter =Wherein MINrms () represents root mean square, M represents the number of sampling points included in one periodic waveform of the SAR ADC output waveform, +.>Representing the difference signal corresponding to the j-th sampling point in the M sampling points,/for>And->Respectively representing the weight to be calibrated and the ideal weight corresponding to the ith bit of the jth sampling point,/>Representing a value on an ith bit of the first digital signal corresponding to the jth sampling point;
wherein the method comprises the steps ofThe same is used for all of the M sampling pointsAnd->And (5) performing iterative calculation.
In an exemplary embodiment, the calibration module 1004 is further configured to:
in the first iterative calculation, the initial value of the weight to be calibrated is set as the ideal weight.
In an exemplary embodiment, the calibration module 1004 is further configured to:
and taking the weight to be calibrated output by each iterative calculation as an initial value of the weight to be calibrated adopted by the next iterative calculation.
In an exemplary embodiment, the iterative algorithm is a simplex method.
The specific manner in which the various modules perform the operations in relation to the SAR ADC of the above-described embodiments has been described in detail in relation to the embodiments of the method and will not be described in detail herein.
A non-transitory computer readable storage medium, which when executed by a processor of a SAR ADC, causes the SAR ADC to perform a method of calibrating a capacitive array in the SAR ADC.
In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as a memory including instructions, is also provided. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A method of calibrating a capacitor array in a successive approximation analog-to-digital converter, the method comprising:
performing analog-to-digital conversion on the first analog signal based on an analog-to-digital conversion formula, and acquiring a first digital signal after analog-to-digital conversion;
inputting the first analog signal into the successive approximation type analog-to-digital converter to obtain a second digital signal output by the successive approximation type analog-to-digital converter;
acquiring a difference signal between the first digital signal and the second digital signal;
and calibrating the capacitor array based on the difference signal to obtain the calibrated weight of the capacitor in the capacitor array.
2. The method of claim 1, wherein calibrating the capacitive array based on the difference signal to obtain a post-calibration weight for a capacitance in the capacitive array comprises:
acquiring ideal weight and weight to be calibrated of the capacitors in the capacitor array;
and calibrating the capacitor array based on the ideal weight, the weight to be calibrated and the difference signal to obtain the calibrated weight of the capacitor in the capacitor array.
3. The method of claim 2, wherein calibrating the capacitive array based on the ideal weight, the weight to be calibrated, and the difference signal to obtain the post-calibration weight for the capacitance in the capacitive array comprises:
acquiring weight error parameters based on the ideal weight, the weight to be calibrated and the difference signal;
performing iterative calculation on the weight to be calibrated based on an iterative algorithm until the weight error parameter is smaller than a set threshold;
and taking the weight to be calibrated output by the last iterative calculation as the weight after calibration.
4. A method according to claim 3, wherein said obtaining a weight error parameter comprises:
the weight error is obtained based on the following manner:
weight error =Wherein N represents the number of the capacitors in the capacitor array, i represents the corresponding number of bits, +.>Representing the weight to be calibrated of the capacitance corresponding to bit i,/for the capacitor>Representing the ideal weight of the capacitance corresponding to bit i,/and>representing a value at said i-th bit of said first digital signal, delta representing said difference signal;
and obtaining the weight error parameter by calculating the root mean square of the weight error.
5. The method of claim 4, wherein the obtaining the weight error parameter by calculating a root mean square of the weight error comprises:
the weight error parameter is obtained based on the following mode:
weight errorParameter =Wherein MINrms () represents root mean square, M represents the number of sampling points included in one periodic waveform of the successive approximation analog-to-digital converter output waveform, < + >>Representing the difference signal corresponding to the j-th sampling point in M sampling points,>and->Respectively representing the weight to be calibrated and the ideal weight corresponding to the ith bit of the jth sampling point,>representing a value on the ith bit of the first digital signal corresponding to the jth sample point;
wherein the same sampling point is adopted for all sampling points in the M sampling pointsAnd->And (5) performing iterative calculation.
6. The method according to any one of claims 3-5, wherein the iteratively calculating the weights to be calibrated based on an iterative algorithm comprises:
in the first iterative calculation, setting the initial value of the weight to be calibrated as the ideal weight.
7. The method according to any one of claims 3-5, wherein the iteratively calculating the weights to be calibrated based on an iterative algorithm comprises:
and taking the weight to be calibrated output by each iterative calculation as an initial value of the weight to be calibrated adopted by the next iterative calculation.
8. The method of any one of claims 3-5, wherein the iterative algorithm is a simplex method.
9. A successive approximation analog-to-digital converter, the successive approximation analog-to-digital converter comprising:
the first digital signal acquisition module is configured to perform analog-to-digital conversion on the first analog signal based on an analog-to-digital conversion formula and acquire the analog-to-digital converted first digital signal;
the analog-to-digital conversion module is arranged for carrying out analog-to-digital conversion on the input first analog signal to obtain a second digital signal;
a difference acquisition module configured to acquire a difference signal between the first digital signal and the second digital signal;
and the calibration module is used for calibrating the capacitor array based on the difference signal so as to acquire the calibrated weight of the capacitor in the capacitor array.
10. A non-transitory computer readable storage medium, characterized in that the instructions in the storage medium, when executed by a processor of a successive approximation analog to digital converter, are capable of performing the method of any of claims 1-8.
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