CN104113337B - A kind of production line analog-digital converter - Google Patents

Abstract

The present invention provides a kind of production line analog-digital converter, wherein, including：One-level first pipeline stages that connect step by step, seven grade of second pipeline stages, one-level the 3rd pipeline stages；The digital correction circuit being connected respectively with described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages；It is connected respectively with described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages and described digital correction circuit, for being respectively the clock circuit that described first pipeline stages, described second pipeline stages, described 3rd pipeline stages and described digital correction circuit provide the clock control signal of biphase non-overlapping.The solution of the present invention, in the systematic function ensureing high speed high linearity, reduces the power consumption of system.

Description

A kind of production line analog-digital converter

Technical field

The present invention relates to IC design field, more particularly to a kind of production line analog-digital converter.

Background technology

Developing rapidly with semiconductor technology, analog-digital converter is widely used in data communication, military radar etc. In field, the performance requirement also more and more higher to analog-digital converter for these systems.It is desirable to mould while pursuing high-speed, high precision Number converter has relatively low power consumption.The performance of analog-digital converter plays particularly important effect in the entire system, therefore sets Count high performance analog-digital converter to have great significance.

In the analog-digital converter of numerous structures, flow-line modulus converter has the advantage of high-speed, high precision simultaneously, Become first-selected in high-speed, high precision application.In practical application, in the speed ensureing pipeline organization analog-digital converter and precision On the premise of performance, the power consumption how reducing system becomes the focus of present research.

There is sampling hold circuit traditional streamline modulus a/d transducer front end, and sampling hold circuit is not as quantifying The front-end circuit of signal, can reduce system linearity degree and signal to noise ratio.Secondly, as precision and linearity highest one Level, sampling hold circuit accounts for the sizable power consumption of whole system and area.Kept using no sampling to reduce power consumption and area Circuit structure, but this also increases the design difficulty of first order multiplying digital-to-analog converter.

Content of the invention

It is an object of the invention to provide a kind of production line analog-digital converter, can solve current analog-digital converter front end all has Sampling hold circuit, sampling hold circuit, as the front-end circuit of not quantized signal, reduces system linear degree, and traditional mould The design of number converter sampling hold circuit increased the problem of the power consumption of system.

In order to solve above-mentioned technical problem, embodiments of the invention provide a kind of production line analog-digital converter, wherein, bag Include：Connect step by step for carrying out to signal quantifying and one-level first pipeline stages of output quantization signal, seven grade of second flowing water Line level, one-level the 3rd pipeline stages；

With described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages respectively Connect, for the quantization letter to described one-level the first pipeline stages output quantization signal, described seven grade of second pipeline stages output Number, described one-level the 3rd pipeline stages output quantized signal enter line delay be aligned with dislocation be added processs, and export through locating The digital correction circuit of the quantized signal of reason；

With described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages and Described digital correction circuit connects respectively, for be respectively described one-level first pipeline stages, described seven grade of second pipeline stages, Described one-level the 3rd pipeline stages and described digital correction circuit provide the clock of the clock control signal of biphase non-overlapping electric Road.

Wherein, described first pipeline stages include the first multiplying digital-to-analog converter, for the first multiplying digital-to-analog converter In sampling capacitance array carry out dynamic element matching circuit and first sub-adc converter of dynamic random selection；Wherein, It is poor that described first sub-adc converter includes the first differential input end, the second differential input end, the first difference output end and second Divide outfan；Described dynamic element matching circuit includes the 3rd differential input end, the 4th differential input end, the 3rd difference output end With the 4th difference output end；Described first multiplying digital-to-analog converter include the 5th differential input end, the 6th differential input end, the 5th Difference output end and the 6th difference output end；Wherein, described first differential input end connects the first differential electrical of analog-digital converter Pressure, described second differential input end connects the second differential voltage of analog-digital converter；Described first difference output end and described the Three differential input ends connect, and described second difference output end is connected with described 4th differential input end；Described first difference output End is connected with described digital correction circuit；Described 3rd difference output end is connected with described 5th differential input end, and the described 4th Difference output end is connected with described 6th differential input end.

Wherein, described seven grade of second pipeline stages are respectively：The first order second pipeline stages, the second level second streamline Level, the third level second pipeline stages, the fourth stage second pipeline stages, level V second pipeline stages, the 6th grade of the second streamline Level, the 7th grade of the second pipeline stages；Wherein, the second pipeline stages at different levels all include the second sub-adc converter and the second multiplication number Weighted-voltage D/A converter；

Wherein, to include the 7th differential input end, the 8th differential input end, the 7th difference defeated for described second subnumber weighted-voltage D/A converter Go out end and the 8th difference output end；Described second multiplying digital-to-analog converter includes：9th differential input end, the tenth Differential Input End, the 9th difference output end and the tenth difference output end；Described 7th difference output end is connected with described numeral emphasizer circuit；Institute State the 7th difference output end to be connected with described 9th differential input end；Described 8th difference output end and described tenth Differential Input End connects；

Wherein, described 7th differential input end of described second sub-adc converter of the described first order second pipeline stages It is connected with described 5th difference output end, described the of described second sub-adc converter of the described first order second pipeline stages Eight differential input ends are connected with described 6th difference output end；The described second submodule number of every one-level second pipeline stage turns backward Described 7th differential input end of parallel operation is all described with described second multiplying digital-to-analog converter of previous stage second pipeline stages 9th difference output end connects, backward described 8th difference of described second sub-adc converter of every one-level second pipeline stage Input is all connected with described tenth difference output end of described second multiplying digital-to-analog converter of previous stage second pipeline stages.

Wherein, described 3rd pipeline stages include：

3rd subnumber weighted-voltage D/A converter；Wherein, described 3rd subnumber weighted-voltage D/A converter include the 11st differential input end, the 12nd Differential input end, the 11st difference output end and the 12nd difference output end；Described 11st measurement shoutage is divided into end and the described 7th Described 9th difference output end of the second multiplying digital-to-analog converter described in level the second pipeline stages connects, described 12nd difference Input is connected with described tenth difference output end of the second multiplying digital-to-analog converter described in described 7th grade of the second pipeline stages Connect；Described 11st difference output end is connected with described digital correction circuit.

Wherein, described first sub-adc converter is made up of 14 first comparators；Wherein, each first comparator bag Include：First order prime amplifier, second level prime amplifier and the first latch；It is defeated that described first order prime amplifier includes the first homophase Enter end, the first inverting input, the first in-phase output end and the first reversed-phase output；Described second level prime amplifier includes second In-phase input end, the second inverting input, the second in-phase output end and the second reversed-phase output；Described first latch includes 13 differential input ends, the 14th differential input end, the 13rd difference output end, the 14th difference output end；Described first is anti- Phase output terminal is connected with described second in-phase input end, and described first in-phase output end is connected with the described second anti-phase access port； Described second reversed-phase output is connected with described 13rd differential input end, and described second in-phase output end is poor with the described 14th Input is divided to connect；Described 13rd difference output end of the first latch described in each first comparator is poor with described first Outfan is divided to connect, described 14th difference output end of described first latch of each first comparator is poor with described second Outfan is divided to connect；Described first in-phase input end is connected by the first clock switch with described first reversed-phase output；Described First inverting input is connected by described first clock switch with described first in-phase output end；The institute of each first comparator State the first in-phase input end to be connected by second clock switch with described first differential input end by the first electric capacity and pass through Described first electric capacity is connected by described first clock switch with the first reference voltage；Described the first of each first comparator is anti- Phase input is passed through the second electric capacity and is connected and by described by described second clock switch with described second differential input end Second electric capacity is connected by described first clock switch with the second reference voltage.

Wherein, described first multiplying digital-to-analog converter by：

Described first multiplying digital-to-analog converter by：

3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electricity Appearance, the 11st electric capacity, the 12nd electric capacity, the 13rd electric capacity, the 14th electric capacity, the 15th electric capacity, the 16th electric capacity, the 17th electricity Appearance, the 18th electric capacity, the 19th electric capacity, the 20th electric capacity, the 21st electric capacity, the 22nd electric capacity, the 23rd electric capacity, 24 electric capacity, the 25th electric capacity, the 26th electric capacity, the 27th electric capacity, the 28th electric capacity, the 29th electric capacity, 30th electric capacity, the 31st electric capacity, the 32nd electric capacity, the 33rd electric capacity, the 34th electric capacity, the 35th electric capacity, 36th electric capacity, the 37th electric capacity, the 38th electric capacity and the first operational amplifier composition；Wherein, described first fortune Calculate amplifier and include an in-phase input end, an inverting input, an in-phase output end and a reversed-phase output；Described homophase output End is connected by the first clock switch with described inverse output terminal；Described in-phase input end and described reverse input end are all by the Three clock switch connect common-mode voltage；Described in-phase output end is connected with described 5th difference output end；Described reversed-phase output It is connected with described 6th difference output end；

The first end of described 3rd electric capacity, the first end of described 4th electric capacity, the first end of described 5th electric capacity, described The first end of six electric capacity, the first end of described 7th electric capacity, the first end of described 8th electric capacity, the first of described 9th electric capacity End, the first end of described tenth electric capacity, the first end of described 11st electric capacity, the first end of described 12nd electric capacity, described The first end of 13 electric capacity, the first end of described 14th electric capacity, the first end of described 15th electric capacity, described 16th electric capacity First end, the first end of described 17th electric capacity, the first end of described 18th electric capacity, the first end of described 19th electric capacity It is connected with described in-phase input end by buss with the first end of described 20th electric capacity；The of described 3rd electric capacity Two ends, the second end of described 4th electric capacity, the second end of described 5th electric capacity, the second end of described 6th electric capacity, the described 7th Second end of electric capacity, the second end of described 8th electric capacity, the second end of described 9th electric capacity, the second end of described tenth electric capacity, Second end of described 11st electric capacity, the second end of described 12nd electric capacity, the second end of described 13rd electric capacity, the described tenth Second end of four electric capacity, the second end of described 15th electric capacity, the second end of described 16th electric capacity, described 17th electric capacity Second end, second end at second end, the second end of described 19th electric capacity and described 20th electric capacity of described 18th electric capacity When being connected by the first clock switch with described 5th differential input end respectively, passing through described first with the first reference voltage respectively Clock switch is connected, is connected by described first clock switch with the second reference voltage respectively, being led to described reversed-phase output respectively Cross second clock switch to connect；

The first end of described 21st electric capacity, the first end of described 22nd electric capacity, described 23rd electric capacity First end, the first end of described 24th electric capacity, the first end of described 25th electric capacity, the of described 26th electric capacity One end, the first end of described 27th electric capacity, the first end of described 28th electric capacity, the first of described 29th electric capacity End, the first end of described 30th electric capacity, the first end of described 31st electric capacity, the first end of described 32nd electric capacity, The first end of described 33rd electric capacity, the first end of described 34th electric capacity, the first end of described 35th electric capacity, institute First end, the first end of described 37th electric capacity and the first end of described 38th electric capacity of stating the 36th electric capacity are passed through One buss are connected with described inverting input；Second end of described 21st electric capacity, described 22nd electric capacity Second end, the second end of described 23rd electric capacity, the second end of described 24th electric capacity, the of described 25th electric capacity Two ends, the second end of described 26th electric capacity, the second end of described 27th electric capacity, the second of described 28th electric capacity End, the second end of described 29th electric capacity, the second end of described 30th electric capacity, the second end of described 31st electric capacity, Second end of described 32nd electric capacity, the second end of described 33rd electric capacity, the second end of described 34th electric capacity, institute State the second end, the second end of described 36th electric capacity, the second end of described 37th electric capacity and the institute of the 35th electric capacity The second end stating the 38th electric capacity is connected by described first clock switch with described 6th differential input end respectively, respectively with When described first reference voltage passes through described first clock switch connection, passes through described first with described second reference voltage respectively Clock switch is connected, is connected by described second clock switch with described in-phase output end respectively.

Wherein, the second sub-adc converter described in the second pipeline stages at different levels is by two the second comparator compositions；Its In, each second comparator includes：3rd prime amplifier, the 4th prime amplifier and the second latch；Described 3rd prime amplifier Including the second in-phase input end, the second inverting input, the second in-phase output end and the second reversed-phase output；Described 4th puts in advance Big device includes the 3rd in-phase input end, the 3rd inverting input, the 3rd in-phase output end and the 3rd reversed-phase output；Described second Latch includes the 15th differential input end, the 16th differential input end, the 15th difference output end, the 16th difference output End；Described second reversed-phase output is connected with described 3rd in-phase input end, and described second in-phase output end is anti-with the described 3rd Phase input connects；Described 3rd reversed-phase output is connected with described 15th differential input end, described 3rd in-phase output end It is connected with described 16th differential input end；

Wherein, described second in-phase input end of the 3rd prime amplifier described in each second comparator passes through the 39th Electric capacity is connected by second clock switch with described 7th differential input end, and by described 39th electric capacity and the first ginseng Examine voltage and pass through the first clock switch connection；Described second anti-phase input of the 3rd prime amplifier described in each second comparator End is passed through described second clock switch by the 40th electric capacity and described 8th differential input end and is connected, and passes through the described 4th Ten electric capacity are connected by described first clock switch with the second reference voltage；Second latch described in each second comparator Described 15th difference output end is connected with described 7th difference output end；Second latch described in each second comparator Described 16th difference output end is connected with described 8th difference output end.

Wherein, described in described second pipeline stages at different levels, the second multiplying digital-to-analog converter is selected by the first one-out-three Device, the second one-out-three selector, the second operational amplifier, the 3rd operational amplifier, the 41st electric capacity, the 42nd electric capacity, 43rd electric capacity, the 44th electric capacity composition；

Wherein, described first one-out-three selector includes：17th differential input end, the 18th differential input end, the tenth Nine differential input ends, the first control end, the 17th difference output end；Described second one-out-three selector includes：20th difference Input, the 21st differential input end, the 22nd differential input end, the second control end, the 18th difference output end；Described Second operational amplifier includes the 4th in-phase input end, the 4th inverting input and the 19th difference output end；Described 3rd fortune Calculate amplifier and include the 5th in-phase input end, the 5th inverting input and the 20th difference output end；

Described 17th differential input end, the 20th differential input end are connected with the 3rd reference voltage respectively；Described tenth Eight differential input ends, described 21st differential input end are connected with the 4th reference voltage respectively；Described 19th Differential Input End, described 22nd differential input end connect low level respectively；

Described 4th in-phase input end connects common-mode voltage；Described 19th difference output end pass through the first clock switch with Described common-mode voltage connects；Described 4th inverting input be connected with the first end of described 41st electric capacity respectively with described The first end of the 42nd electric capacity connects；The first end of described 42nd electric capacity is also by the 3rd clock switch and described common mode Voltage connects；Second end of described 41st electric capacity is connected with described 19th difference output end by second clock switch； Second end of described 42nd electric capacity is connected with the second end of described 41st electric capacity by described first clock switch；Institute The second end stating the 42nd electric capacity is connected with described 17th difference output end also by described second clock switch；Wherein, Second end of described 42nd electric capacity is connected with described 9th differential input end also by described first clock switch；Described Described 19th difference output end of two operational amplifiers is connected with described 9th difference output end；

Described 5th in-phase input end connects common-mode voltage；Described 20th difference output end is opened by described first clock Close and be connected with described common-mode voltage；Described 5th inverting input be connected with the first end of described 43rd electric capacity respectively and The first end of described 44th electric capacity connects；The first end of described 44th electric capacity also by described 3rd clock switch with Described common-mode voltage connects；Second end of described 43rd electric capacity is switched defeated with described 20 difference by described second clock Go out end to connect；The second of described first clock switch and described 43rd electric capacity is passed through at second end of described 44th electric capacity End connects；Second end of described 44th electric capacity is also by described second clock switch with described 18th difference output end even Connect；Wherein, the second end of described 44th electric capacity is connected with described tenth differential input end also by described first clock switch Connect；20th difference output end of described 3rd operational amplifier is connected with described tenth difference output end；

Described 15th difference output end of the second latch described in described second subnumber weighted-voltage D/A converters at different levels all with right Described in described second multiplying digital-to-analog converter answered, the first control end connects；Described in described second subnumber weighted-voltage D/A converters at different levels Described 16th difference output end of the second latch is all controlled with described in corresponding described second multiplying digital-to-analog converter second End processed connects.

Wherein, described 3rd subnumber weighted-voltage D/A converter is made up of seven the 3rd comparators；Wherein, each the 3rd comparator bag Include：5th prime amplifier, the 6th prime amplifier and the 3rd latch；Described 5th prime amplifier include the 6th in-phase input end, 6th inverting input, the 6th in-phase output end and the 6th reversed-phase output；It is defeated that described 6th prime amplifier includes the 7th homophase Enter end, the 7th inverting input, the 7th in-phase output end and the 7th reversed-phase output；Described 3rd latch includes the 21st Differential input end, the 22nd differential input end, the 21st difference output end, the 22nd difference output end；

Described 6th reversed-phase output is connected with described 7th in-phase input end, described 6th in-phase output end and described the Seven inverting inputs connect；Described 7th reversed-phase output is connected with described 21st differential input end, described 7th homophase Outfan is connected with described 22nd differential input end；

Wherein, described 6th in-phase input end of the 5th prime amplifier described in each the 3rd comparator passes through the 45th Electric capacity is connected by second clock switch with described 11st differential input end, and passes through described 45th electric capacity and the 5th Reference voltage passes through the first clock switch and connects；Described in each the 3rd comparator, the described 6th of the 5th prime amplifier the is anti-phase defeated Enter end to be connected by described second clock switch by the 46th electric capacity and described 12nd differential input end, and pass through institute State the 46th electric capacity to be connected by described first clock switch with the 6th reference voltage；The 3rd described in each the 3rd comparator Described 21st difference output end of latch is connected with described 11st difference output end；Described in each the 3rd comparator Described 22nd difference output end of the 3rd latch is connected with described 12nd difference output end.

Beneficial effects of the present invention are as follows：

The production line analog-digital converter of the present invention, using the structure of the pipeline-type of front end no sample circuit, by the present invention The first pipeline stages as front end, because the first pipeline stages adopt dynamic element matching technology, consecutive mean first flowing water The matching error of sampling capacitance in first multiplying digital-to-analog converter of line level, thus improve the Pipeline ADC of the present invention The linearity of device, due to reducing the requirement of electric capacity, thus further reduce the power consumption of system.

Brief description

Fig. 1 represents the overall structure diagram of the production line analog-digital converter of the present invention；

Fig. 2 represents the structural representation of the first pipeline stages in the production line analog-digital converter of the present invention；

Fig. 3 represents the structural representation of the second pipeline stages at different levels in the production line analog-digital converter of the present invention；

Fig. 4 represents the structural representation of the 3rd pipeline stages in the production line analog-digital converter of the present invention；

Fig. 5 represents first in the first sub-adc converter of the first pipeline stages in the production line analog-digital converter of the present invention The structural representation of comparator；

Fig. 6 represents the knot of the first multiplying digital-to-analog converter of the first pipeline stages in the production line analog-digital converter of the present invention Structure schematic diagram one；

Fig. 7 represents the knot of the first multiplying digital-to-analog converter of the first pipeline stages in the production line analog-digital converter of the present invention Structure schematic diagram two；

Fig. 8 represents in the second sub-adc converter of the second pipeline stages at different levels in the production line analog-digital converter of the present invention The structural representation of the second comparator；

Fig. 9 represents the second multiplying digital-to-analog converter of the second pipeline stages at different levels in the production line analog-digital converter of invention Structural representation；

Figure 10 represents the second multiplication digital-to-analogue conversion of the second pipeline stages at different levels in the production line analog-digital converter of the present invention The structural representation of device；

Figure 11 represents the first clock control signal and the second clock control signal schematic diagram of the clock circuit of the present invention；

Figure 12 represents the operation principle schematic diagram of first pipeline stages of the present invention；

Figure 13 represents the transmission curve schematic diagram of the first multiplying digital-to-analog converter in first pipeline stages of the present invention；

Figure 14 represents the fundamental diagram of second pipeline stages at different levels of the present invention；

Figure 15 represents the transmission curve schematic diagram of the second multiplying digital-to-analog converter in second pipeline stages at different levels of the present invention.

Specific embodiment

For making the object, technical solutions and advantages of the present invention clearer, right below in conjunction with the accompanying drawings and the specific embodiments The present invention is described in detail.

As shown in figure 1, in a particular embodiment of the present invention, embodiments of the invention provide a kind of Pipeline ADC Device, particularly a kind of 13 bit stream pipeline analog-to-digital converters, this 13 production line analog-digital converter mainly includes：

Connect step by step for signal is carried out quantify and output quantization signal one-level first pipeline stages, seven grade second Pipeline stages (part comprising in dotted line frame in Fig. 1), one-level the 3rd pipeline stages；With this one-level first pipeline stages, this seven Level the second pipeline stages, this one-level the 3rd pipeline stages connect, respectively for the quantization that this one-level first pipeline stages is exported Signal (digital code), the quantized signal (digital code) of this seven grade of second pipeline stages output, the output of this one-level the 3rd pipeline stages Quantized signal (digital code) enter line delay be aligned and be added process with dislocation, and export treated quantized signal (digital code) Digital correction circuit；With this one-level first pipeline stages, this seven grade of second pipeline stages, this one-level the 3rd pipeline stages and This digital correction circuit connects respectively, for being respectively this one-level first pipeline stages, this seven grade of second pipeline stages, this one-level The clock circuit of the clock control signal of the 3rd pipeline stages and this digital correction circuit biphase non-overlapping of offer.

Wherein, this one-level first pipeline stages is used for output 4 digit numeric codes, and this one-level the 3rd pipeline stages is used for output 3 Digit numeric code, this seven grade of second pipeline stages as shown in figure 1, be respectively connect step by step the first order second pipeline stages, second Level the second pipeline stages, the third level second pipeline stages, the fourth stage second pipeline stages, level V second pipeline stages, the 6th Level the second pipeline stages and the 7th grade of the second pipeline stages, each of which level second pipeline stages are used to export 2 digit numeric codes, Above-mentioned digital correction circuit is used for above-mentioned one-level first pipeline stages, seven grade of second pipeline stages, one-level the 3rd pipeline stages The quantized signal (digital code) of output is entered line delay be aligned and is added process to export 13 quantized signals (digital code) with dislocation.

Below in conjunction with accompanying drawing and specific embodiment to above-mentioned one-level first pipeline stages of the present invention, at different levels second Pipeline stages, the structure of one-level the 3rd pipeline stages and at different levels between annexation elaborate：

This one-level first pipeline stages is as shown in Fig. 2 include：First sub-adc converter, the first multiplying digital-to-analog converter, For the sampling capacitance array in the first multiplying digital-to-analog converter is carried out with the dynamic element matching circuit of dynamic random selection, that is, DEM circuit；Wherein, this first sub-adc converter includes the first differential input end 11, the second differential input end 12, the first difference Outfan 13 and the second difference output end 14, this DEM circuit include the 3rd differential input end 21, the 4th differential input end 22, Three difference output ends 23 and the 4th difference output end 24, this first multiplying digital-to-analog converter includes：5th differential input end 31, Six differential input ends 32, the 5th difference output end 33 and the 6th difference output end 34；Wherein, this production line analog-digital converter is defeated Enter signal of telecommunication Vin=1.6 volt, it includes a pair of differential signal, the respectively first differential signal Vin+ (being worth for 0.8 volt) and Second differential signal Vin- (is worth for 0.8 volt), and the value of above-mentioned Vin is the value with the second differential signal for the value of the first differential signal Difference, above-mentioned first differential input end 11 connects this first differential signal Vin+ of this analog-digital converter, and above-mentioned second difference is defeated Enter this second differential signal Vin- of end 12 this analog-digital converter of connection, above-mentioned first difference output end 13 and above-mentioned 3rd difference Input 21 connects, and above-mentioned second difference output end 14 is connected with above-mentioned 4th differential input end 22, above-mentioned first difference output End 13 connection digital correction circuit, for exporting 4 digit numeric codes to above-mentioned digital correction circuit, above-mentioned 3rd difference output end 23 It is connected with above-mentioned 5th differential input end 31, above-mentioned 4th difference output end 24 is connected with above-mentioned 6th differential input end 32.

As shown in figure 3, this first order second pipeline stages, the second level second pipeline stages, the third level second pipeline stages, The fourth stage second pipeline stages, level V second pipeline stages, the 6th grade of the second pipeline stages, the 7th grade of the second pipeline stages are equal Including the second sub-adc converter and the second multiplying digital-to-analog converter；Wherein, this second sub-adc converter includes：7th difference Input 41, the 8th differential input end 42, the 7th difference output end 43 and the 8th difference output end 44；This second multiplication digital-to-analogue turns Parallel operation includes：9th differential input end 51, the tenth differential input end 52, the 9th difference output end 53 and the tenth difference output end 54；7th difference output end 43 connects digital correction circuit, for exporting 2 digit numeric codes to above-mentioned digital correction circuit, should 7th difference output end 43 is connected with the 9th differential input end 51, the 8th difference output end 44 and the tenth differential input end 52 connections；Wherein, the 7th differential input end 41 of this second sub-adc converter of the above-mentioned first order second pipeline stages and In pipeline stage, the 5th difference output end 33 of the first multiplying digital-to-analog converter connects, in this first order second pipeline stages 6th difference of the first multiplying digital-to-analog converter in 8th differential input end 42 of two sub-adc converter and the first pipeline stages Outfan 34 connects；Backward the 7th differential input end 41 of the second subnumber weighted-voltage D/A converter in every one-level second pipeline stage all with In previous stage second pipeline stages, the 9th difference output end 53 of the second multiplying digital-to-analog converter connects, backward every one-level second The second multiplication number all with previous stage second pipeline stages for 8th differential input end 42 of the second sub-adc converter in pipeline stage Tenth outfan 54 of weighted-voltage D/A converter connects.

As shown in figure 4, the 3rd pipeline stages (can be flash type analog-digital converter), including：3rd sub- digital-to-analogue conversion Device, wherein, the 3rd subnumber weighted-voltage D/A converter includes：11st differential input end, the 12nd differential input end 62, the 11st difference Outfan 63 and the 12nd difference output end 64；Wherein, the 11st differential input end and above-mentioned 7th grade of the second pipeline stages In the 9th difference output end 53 of the second multiplying digital-to-analog converter connect, the 12nd differential input end 62 with above-mentioned 7th grade the In two pipeline stages, the tenth difference output end 54 of the second multiplying digital-to-analog converter connects, the 11st difference output end 63 with upper State digital correction circuit to connect, for exporting 3 bit digital code system digital correction circuits.

Inside concrete structure below in conjunction with the first sub-adc converter in the first pipeline stages to the present invention for the accompanying drawing Elaborate：

As shown in figure 5, the first sub-adc converter is by 14 first comparator groups in first pipeline stages of the present invention Become；Wherein, each first comparator includes：First order prime amplifier, second level prime amplifier and the first latch；This first order Prime amplifier includes the first in-phase input end, the first inverting input, the first in-phase output end and the first reversed-phase output；This Two grades of prime amplifiers include the second in-phase input end, the second inverting input, the second in-phase output end and the second reversed-phase output； This first latch includes the 13rd differential input end 71, the 14th differential input end 72, the 13rd difference output end the 73, the tenth Four difference output ends 74；This first reversed-phase output is connected with described second in-phase input end, this first in-phase output end and institute State the second anti-phase access port to connect；This second reversed-phase output is connected with described 13rd differential input end 71, this second homophase Outfan is connected with the 14th differential input end 72；The described 13rd of first latch described in each first comparator is poor Outfan 73 is divided to be connected with described first difference output end 13, the described tenth of described first latch of each first comparator the Four difference output ends 74 are connected with this second difference output end 14；Described first in-phase input end and described first reversed-phase output Connected by the first clock switch Φ 1；When described first inverting input passes through described first with described first in-phase output end Clock switch Φ 1 connects；Described first in-phase input end of each first comparator passes through the first electric capacity C1 and described first difference Input 11 switchs Φ 2 by second clock and connects and by described first electric capacity C1 and the first reference voltage Vref 1+ (value For 1.65 volts) connected by described first clock switch Φ 1；Described first inverting input of each first comparator passes through Second electric capacity C2 passes through described second clock switch Φ 2 with described second differential input end 12 and is connected and by described second electricity Hold C2 to be connected by described first clock switch Φ 1 with the second reference voltage Vref 1- (being worth for 0.85 volt).

Inside below in conjunction with the first multiplying digital-to-analog converter in the first pipeline stages to the present invention for the accompanying drawing is specifically tied Structure elaborates：

As shown in Figure 6, Figure 7, this first multiplying digital-to-analog converter by the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, 6th electric capacity C6, the 7th electric capacity C7, the 8th electric capacity C8, the 9th electric capacity C9, the tenth electric capacity C10, the 11st electric capacity C11, the 12nd Electric capacity C12, the 13rd electric capacity C13, the 14th electric capacity C14, the 15th electric capacity C15, the 16th electric capacity C16, the 17th electric capacity C17, the 18th electric capacity C18, the 19th electric capacity C19, the 20th electric capacity C20, the 21st electric capacity C21, the 22nd electric capacity C22, the 23rd C23 electric capacity, the 24th electric capacity C24, the 25th electric capacity C25, the 26th electric capacity C26, the 27th Electric capacity C27, the 28th electric capacity C28, the 29th electric capacity C29, the 30th electric capacity C30, the 31st electric capacity C31, the 30th Two electric capacity C32, the 33rd electric capacity C33, the 34th electric capacity C34, the 35th electric capacity C35, the 36th electric capacity C36, 37 electric capacity C37, the 38th electric capacity C38 and the first operational amplifier composition；Wherein, described first operational amplifier bag Include an in-phase input end, an inverting input, an in-phase output end and a reversed-phase output；Described in-phase output end is anti-with described Connected to outfan by the first clock switch Φ 1；Described in-phase input end and described reverse input end are all by the 3rd clock Switch Φ 3 connects common-mode voltage Vcm (being worth for 1.25 volts)；Described in-phase output end is with described 5th difference output end 33 even Connect；Described reversed-phase output is connected with described 6th difference output end 34；

The first end of described 3rd electric capacity C3, the first end of described 4th electric capacity C4, the first end of described 5th electric capacity C5, The first end of described 6th electric capacity C6, the first end of described 7th electric capacity C7, the first end of described 8th electric capacity C8, the described 9th The first end of electric capacity C9, the first end of described tenth electric capacity C10, the first end of described 11st electric capacity C11, described 12nd electricity Hold the first end of C12, the first end of described 13rd electric capacity C13, the first end of described 14th electric capacity C14, the described 15th The first end of electric capacity C15, the first end of described 16th electric capacity C16, the first end of described 17th electric capacity C17, the described tenth The first end of the first end of eight electric capacity C18, the first end of described 19th electric capacity C19 and described 20th electric capacity C20 passes through one Buss are connected with described in-phase input end；Second end of described 3rd electric capacity C3, second end of described 4th electric capacity C4, Second end of described 5th electric capacity C5, second end of described 6th electric capacity C6, second end of described 7th electric capacity C7, the described 8th Second end of electric capacity C8, second end of described 9th electric capacity C9, second end of described tenth electric capacity C10, described 11st electric capacity Second end of C11, second end of described 12nd electric capacity C12, second end of described 13rd electric capacity C13, described 14th electricity Hold second end of C14, second end of described 15th electric capacity C15, second end of described 16th electric capacity C16, the described 17th Second end of electric capacity C17, second end of described 18th electric capacity C18, second end and described second of described 19th electric capacity C19 Second end of ten electric capacity C20 is connected by the first clock switch Φ 1 with described 5th differential input end 31 respectively, respectively with first Reference voltage Vref 1+ (being worth for 1.65 volts) connected by described first clock switch Φ 1, respectively with the second reference voltage Vref1- (being worth for 0.85 volt) is connected by described first clock switch Φ 1, passes through second with described reversed-phase output respectively Clock switch Φ 2 connects (in figure is not illustrated)；

The first end of described 21st electric capacity C21, the first end of described 22nd electric capacity C22, the described 23rd The first end of electric capacity C23, the first end of described 24th electric capacity C24, the first end of described 25th electric capacity C25, described The first end of the 26th electric capacity C26, the first end of described 27th electric capacity C27, the first of described 28th electric capacity C28 End, the first end of described 29th electric capacity C29, the first end of described 30th electric capacity C30, described 31st electric capacity C31 First end, the first end of described 32nd electric capacity C32, the first end of described 33rd electric capacity C33, the described 34th The first end of electric capacity C34, the first end of described 35th electric capacity C35, the first end of described 36th electric capacity C36, described It is anti-with described that the first end of the first end of the 37th electric capacity C37 and described 38th electric capacity C38 passes through buss Phase input connects；Second end of described 21st electric capacity C21, second end of described 22nd electric capacity C22, described second Second end of 13 electric capacity C23, second end of described 24th electric capacity C24, second end of described 25th electric capacity C25, Second end of described 26th electric capacity C26, second end of described 27th electric capacity C27, described 28th electric capacity C28 Second end, second end of described 29th electric capacity C29, second end of described 30th electric capacity C30, described 31st electric capacity Second end of C31, second end of described 32nd electric capacity C32, second end of described 33rd electric capacity C33, the described 3rd Second end of 14 electric capacity C34, second end of described 35th electric capacity C35, second end of described 36th electric capacity C36, Second end of second end of described 37th electric capacity C37 and described 38th electric capacity C38 is defeated with described 6th difference respectively Enter end 32 connected by described first clock switch Φ 1, respectively with described first reference voltage Vref 1+ (being worth for 1.65 volts) Connected by described first clock switch Φ 1, pass through institute with described second reference voltage Vref 1- (being worth for 0.85 volt) respectively State the first clock switch Φ 1 to connect, switch Φ 2 with described in-phase output end by described second clock respectively and be connected that (in figure is not Illustrate).

The second submodule below in conjunction with the second pipeline stages at different levels in seven grade of second pipeline stages to the present invention for the accompanying drawing The inside concrete structure of number converter elaborates：

As shown in figure 8, second sub-adc converter is formed by two comparators described in the second pipeline stages at different levels；Its In, each second comparator includes：3rd prime amplifier, the 4th prime amplifier and the second latch；Described 3rd prime amplifier Including the second in-phase input end, the second inverting input, the second in-phase output end and the second reversed-phase output；Described 4th puts in advance Big device includes the 3rd in-phase input end, the 3rd inverting input, the 3rd in-phase output end and the 3rd reversed-phase output；Described second Latch includes the 15th differential input end 81, the 16th differential input end 82, the 15th difference output end 83, the 16th difference Outfan 84；Described second reversed-phase output is connected with described 3rd in-phase input end, described second in-phase output end with described 3rd inverting input connects；Described 3rd reversed-phase output is connected with described 15th differential input end 81, and the described 3rd is same Phase output terminal is connected with described 16th differential input end 82；

Wherein, described second in-phase input end of the 3rd prime amplifier described in each second comparator passes through the 39th Electric capacity C39 switchs Φ 2 with described 7th differential input end 41 by second clock and is connected, and passes through described 39th electric capacity C39 is connected by the first clock switch Φ 1 with the 3rd reference voltage Vref 2+ (being worth for 1.65/2 volt)；Each second comparator Described in described second inverting input of the 3rd prime amplifier pass through the 40th electric capacity C40 and described 8th differential input end 42 Switch Φ 2 by described second clock to connect, and by described 40th electric capacity C40 and the 4th reference voltage Vref 2- (value For 0.85/2 volt) connected by described first clock switch Φ 1；Described in each second comparator, the second latch is described 15th difference output end 83 is connected with described 7th difference output end 43；Second latch described in each second comparator Described 16th difference output end 84 is connected with described 8th difference output end 44.

The second multiplication below in conjunction with the second pipeline stages at different levels in seven grade of second pipeline stages to the present invention for the accompanying drawing The inside concrete structure of digital to analog converter elaborates：

As shown in figure 9, second multiplying digital-to-analog converter is fully differential structure described in described second pipeline stages at different levels (in figure only gives single-side structural schematic diagram), and by the first one-out-three selector, the second one-out-three selector, the second computing Amplifier, the 3rd operational amplifier, the 41st electric capacity C41, the 42nd electric capacity C42, the 43rd electric capacity, the 44th electricity Hold composition；

Wherein, described first one-out-three selector includes：17th differential input end 91, the 18th differential input end 92, 19th differential input end 93, the first control end 94, the 17th difference output end 95；Described second one-out-three selector (in figure Do not illustrate) include：20th differential input end, the 21st differential input end, the 22nd differential input end, the second control End, the 18th difference output end；Described second operational amplifier includes the 4th in-phase input end, the 4th inverting input and the tenth Nine difference output ends 101；Described 3rd operational amplifier (in figure is not illustrated) includes the 5th in-phase input end, the 5th anti-phase input End and the 20th difference output end；

Described 17th differential input end 91, the 20th differential input end respectively with the 3rd reference voltage Vref 2+ (according to Concrete condition goes to set) connect；Described 18th differential input end 92, described 21st differential input end are joined with the 4th respectively Examine voltage Vref2- (going to set according to concrete condition) to connect；Described 19th differential input end 93, described 22nd difference Input connects low level " 0 " respectively；

Described 4th in-phase input end connects common-mode voltage Vcm (being worth for 1.25 volts)；Described 19th difference output end 101 are connected with described common-mode voltage by the first clock switch Φ 1；Described 4th inverting input is respectively with the described 41st The first end of electric capacity C41 is connected and is connected with the first end of described 42nd electric capacity C42；The of described 42nd electric capacity C42 One end is connected with described common-mode voltage also by the 3rd clock switch Φ 3；Second end of described 41st electric capacity C41 passes through the Two clock switch Φ 2 are connected with described 19th difference output end 101；Institute is passed through at second end of described 42nd electric capacity C42 The second end stating the first clock switch Φ 1 with described 41st electric capacity C41 is connected；The second of described 42nd electric capacity C42 End is switched Φ 2 also by described second clock and is connected with described 17th difference output end 95；Wherein, described 42nd electric capacity The second end be connected with described 9th differential input end 51 also by described first clock switch Φ 1；Described second operation amplifier Described 19th difference output end 101 of device is connected with described 9th difference output end 53；

Described 5th in-phase input end connects described common-mode voltage；When described 20th difference output end passes through described first Clock switch Φ 1 is connected with described common-mode voltage；The described 5th inverting input first end with described 43rd electric capacity respectively Connect and be connected with the first end of described 44th electric capacity；When the first end of described 44th electric capacity is also by the described 3rd Clock switch Φ 3 is connected with described common-mode voltage；Second end of described 43rd electric capacity pass through described second clock switch Φ 2 with Described 20 difference output ends connect；Second end of described 44th electric capacity pass through described first clock switch Φ 1 with described Second end of the 43rd electric capacity connects；Second end of described 44th electric capacity also by described second clock switch Φ 2 with Described 18th difference output end connects；Wherein, the second end of described 44th electric capacity is also by described first clock switch Φ 1 is connected with described tenth differential input end 52；20th difference output end and the described tenth of described 3rd operational amplifier Difference output end 54 connects；

Described 15th difference output end 83 of the second latch described in described second subnumber weighted-voltage D/A converters at different levels all with Described in corresponding described second multiplying digital-to-analog converter, the first control end 94 connects；In described second subnumber weighted-voltage D/A converters at different levels Described 16th difference output end 84 of described second latch all with described in corresponding described second multiplying digital-to-analog converter Second control end connects.

Inside below in conjunction with the 3rd sub-adc converter in the 3rd pipeline stages to the present invention for the accompanying drawing is specifically tied Structure elaborates：

As shown in Figure 10, described 3rd subnumber weighted-voltage D/A converter is made up of seven the 3rd comparators；Wherein, each the 3rd compares Device includes：5th prime amplifier, the 6th prime amplifier and the 3rd latch；Described 5th prime amplifier includes the 6th homophase input End, the 6th inverting input, the 6th in-phase output end and the 6th reversed-phase output；Described 6th prime amplifier includes the 7th homophase Input, the 7th inverting input, the 7th in-phase output end and the 7th reversed-phase output；Described 3rd latch includes the 20th One differential input end 201, the 22nd differential input end 202, the 21st difference output end 203, the 22nd difference output End 204；

Described 6th reversed-phase output is connected with described 7th in-phase input end, described 6th in-phase output end and described the Seven inverting inputs connect；Described 7th reversed-phase output is connected with described 21st differential input end 201, and the described 7th is same Phase output terminal is connected with described 22nd differential input end 202；

Wherein, described 6th in-phase input end of the 5th prime amplifier described in each the 3rd comparator passes through the 45th Electric capacity C45 switchs Φ 2 with described 11st differential input end 61 by second clock and is connected, and by described 45th electricity Hold C45 to be connected by the first clock switch Φ 1 with the 5th reference voltage Vref 3+；Described in each the 3rd comparator, the 5th puts in advance Described 6th inverting input of big device passes through the 46th electric capacity C46 and described 12nd differential input end 62 and passes through described the Two clock switch Φ 2 connect, and pass through described first by described 46th electric capacity C46 and the 6th reference voltage Vref 3- Clock switch Φ 1 connects；Described 21st difference output end 203 of the 3rd latch and institute described in each the 3rd comparator State the 11st difference output end 63 to connect；Described 22nd difference output of the 3rd latch described in each the 3rd comparator End 204 is connected with described 12nd difference output end 64.

Explanation will be analyzed to the operation principle of the present invention below：

As shown in figure 11, the clock control signal of biphase non-overlapping is respectively the first clock control signal and second clock control Signal processed, wherein, the 3rd clock control signal and the first clock control signal are compared and are had a time delay.

In conjunction with Figure 12, input signal Vin first passes around the first subnumber weighted-voltage D/A converter and quantifies, and exports 4 digit numeric codes, this first 4 output codes of sub-adc converter first pass through DEM circuit code, and DEM circuit produces a pseudo noise code, random choosing every time Select a kind of combination of capacitor array, the error that average capacitance mismatch brings, improve system linearity degree.

In conjunction with Fig. 2, Fig. 6, Figure 11, Figure 12 (in dotted line frame for the first multiplying digital-to-analog converter), the first multiplication digital-to-analogue turns The work process of parallel operation is as follows：Sampling phase, the first clock control signal is in high potential state, analyzes single-sided conductive paths, and now the One clock switch Φ 1 turns on, and the in-phase input end of the first operational amplifier and reverse input end all connect common-mode voltage Vcm, homophase Outfan and reversed-phase output short circuit, now, this first operational amplifier is in reset state, and the first differential signal Vin+ is adopted To on the 3rd electric capacity C3 to the 18th electric capacity C18, the 19th electric capacity C19 and the 20th electric capacity C20 connects second with reference to electricity to sample respectively Pressure Vref1- and the first reference voltage Vref 1+, at the end of sampling phase, corresponding 3rd clock control letter at the 3rd clock switch Number current potential will be low level prior to the first clock control signal, this sampling time sequence be bottomplanksampling.By this sequential On optimization can effectively reduce by the switch channel electric charge distorted signals that cause of injection.Amplify phase, in conjunction with Fig. 2, Fig. 7, Figure 11, Figure 12, second clock control signal is in high potential, and in the 3rd electric capacity C3 to the 18th electric capacity C18, DEM circuit can be with Machine is selected 4 upset electric capacity and is connected with the reversed-phase output of the first operational amplifier, first in the first multiplying digital-to-analog converter The output result of subnumber weighted-voltage D/A converter is passed through DEM circuit code and is determined the residue in the 3rd electric capacity C3 to the 20th electric capacity C20 14 electric capacity connect the first reference voltage Vref 1+ and still connect the second reference voltage Vref 1-, to complete subtracting each other of signal.

Wherein, the work process quantitative analyses of the first multiplying digital-to-analog converter of the first pipeline stages are as follows：

In sampling phase, analyze single-end circuit, the 3rd electric capacity C3 to the 18th electric capacity C18 adopts to the first differential signal Vin+ Sample, the 19th electric capacity C19 and the 20th electric capacity C20 connects the second reference voltage Vref 1- and the first reference voltage Vref 1+ respectively, First operational amplifier input point X point obtains electric charge and is： Wherein, Qx obtain for X point electric Lotus, Ci is the i-th electric capacity.

Amplify phase, in single-ended 18 electric capacity, according to the pseudo noise code of DEM circuit generation, randomly choose the 3rd electric capacity 4 electric capacity in C3 to the 20th electric capacity C20 are connected to in-phase output end, as feedback capacity；In first pipeline stages 14 Output code remaining 14 sampling capacitances of control of comparator are connected to the first reference voltage Vref 1+ and are still connected to second with reference to electricity Pressure Vref11-, if i-th comparator carry-out bit Di=1, corresponding i-th electric capacity Ci connects the first reference voltage Vref 1+；If Di =0, then corresponding i-th electric capacity Ci connect the second reference voltage Vref 1-, DEM circuit produces one group of random code and Di is encoded, Originally corresponding feedback capacity combination is randomly assigned, recompiles rear Di and correspond to Bi, even if so the coding of Di is identical, After pseudo noise code configuration, Bi is different from Di, and the electric capacity chosen every time is different.By DEM circuit stochastic averagina capacitance mismatch by mistake Difference, analyzes it is assumed that four electric capacity of feedback are the 3rd electric capacity C3 for convenience, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, (actual is to randomly select four electric capacity).The transmission of the first multiplying digital-to-analog converter can be derived by principle of charge conservation Functional expression is：

Wherein, Vref1 is first The difference of the value of the value of reference voltage Vref 1+ and the second reference voltage Vref 1-, C31 is the capacitance of the 3rd electric capacity, C41 for The capacitance of the 4th electric capacity, C51 is the capacitance of the 5th electric capacity, and C61 is the capacitance of the 6th electric capacity.As shown in figure 13, for this The transmission curve figure of the first multiplying digital-to-analog converter, thus figure is it can be seen that the full amplitude of oscillation of the output of the first pipeline stages is due to gain Compress and become the half inputting the full amplitude of oscillation, i.e. Vout=1/2Vin, so the second pipeline stages at different levels in the second pipeline stages Reference voltage be the half of the first pipeline stages reference voltage, i.e. Vref2+=1/2Vref1+, Vref2-=1/ 2Vref1-.

Wherein, in the second pipeline stages, the work process of the second multiplying digital-to-analog converter of gravity flow pipeline stage at different levels is quantitatively divided Analysis is as follows：

Analysis single-sided conductive paths：

In conjunction with Fig. 8, Fig. 9, Figure 11, Figure 14 (being the second multiplying digital-to-analog converter in dotted line frame), the second multiplication digital-to-analogue conversion Device circuit under two non-overlapping clock control signals alternation in sample phase and amplification stage；Its clock signal and first Multiplying digital-to-analog converter is identical., when the first clock control signal is in high potential, input signal is by the 41st for sample phase Electric capacity C41 and the 42nd electric capacity C42 sampling；Amplification stage when second clock control signal is high potential, now the 40th Two electric capacity C42 electric capacity and input signal end disconnect and are connected to the outfan of amplifier, form feedback loop, the 41st electric capacity C41 is connected to the first control of the MUX (MUX) being controlled by the 15th difference output end 83 of the second sub-adc converter End 94.The transfer function of this second multiplying digital-to-analog converter is：Its In, C411 is the capacitance of the 41st electric capacity C41, and C421 is the capacitance of the 42nd electric capacity C42, and S0 is a parameter, Vrefj is the reference voltage level of every grade of second pipeline stages, and the value of this Vrefj is value and the 1/2Vref1- of 1/2Vref1+ Value difference, Voutj is the output voltage of the second multiplying digital-to-analog converter in j-th stage second pipeline stages, and Vinj is j-th stage the The input voltage value of the second sub-adc converter in two pipeline stages, wherein, j is 1,2,3,4,5,6 or 7；For the first order For two pipeline stages, the input voltage of the second sub-adc converter of the first order second pipeline stages is Vin1, as first The output voltage of pipeline stages, i.e. margin voltage Vout, the input voltage of the second level second pipeline stages is that Vin2 is as previous The margin voltage Vout1 of level the second pipeline stages, by that analogy.

Wherein, the capacitance of the 41st electric capacity C41 and this 42 electric capacity C42 is equal, the size of input signal by The value of one parameter S0 determines, S0 has three values, respectively+1,0, -1.Therefore, the transfer function of the second multiplying digital-to-analog converter Can be written as：

Preferably the transmission curve of the second multiplying digital-to-analog converter of the second pipeline stages at different levels should be as shown in figure 15.

The margin voltage of the first pipeline stages output can be carried out continuing to quantify by the first order second pipeline stages, the first order the The margin voltage of two pipeline stages can be continued to quantify by next stage second pipeline stages, by that analogy, the first pipeline stages to the Seven grade of second pipeline stages, the first multiplying digital-to-analog converter in this eight grades and the second multiplying digital-to-analog converter alternation, plus Upper the 3rd last pipeline stages, complete the quantization of signal, export the digital code of 13 finally by digital correction circuit.

The above is only the preferred embodiment of the present invention it is noted that ordinary skill people for the art For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (9)

1. a kind of production line analog-digital converter is it is characterised in that include：

Connect step by step for carrying out to signal quantifying and one-level first pipeline stages of output quantization signal, seven grade of second flowing water Line level, one-level the 3rd pipeline stages；

It is connected respectively with described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages, For described one-level first pipeline stages are exported quantized signal, the quantized signal of described seven grade of second pipeline stages output, The quantized signal of described one-level the 3rd pipeline stages output is entered line delay be aligned and is added process with dislocation, and exports treated The digital correction circuit of quantized signal；

With described one-level first pipeline stages, described seven grade of second pipeline stages, described one-level the 3rd pipeline stages and described Digital correction circuit connects respectively, for being respectively described one-level first pipeline stages, described seven grade of second pipeline stages, described The clock circuit of the clock control signal of one-level the 3rd pipeline stages and the described digital correction circuit biphase non-overlapping of offer.

2. production line analog-digital converter according to claim 1 is it is characterised in that described first pipeline stages include first Multiplying digital-to-analog converter, for the dynamic of dynamic random selection is carried out to the sampling capacitance array in the first multiplying digital-to-analog converter Element matching circuit and the first sub-adc converter；Wherein, described first sub-adc converter includes the first differential input end (11), the second differential input end (12), the first difference output end (13) and the second difference output end (14)；Described dynamic element Distribution road includes the 3rd differential input end (21), the 4th differential input end (22), the 3rd difference output end (23) and the 4th difference Outfan (24)；Described first multiplying digital-to-analog converter include the 5th differential input end (31), the 6th differential input end (32), Five difference output ends (33) and the 6th difference output end (34)；Wherein, described first differential input end (11) connects analog digital conversion First differential voltage of device, described second differential input end (12) connects the second differential voltage of analog-digital converter；Described first Difference output end (13) is connected with described 3rd differential input end (21), and described second difference output end (14) is poor with the described 4th Input (22) is divided to connect；Described first difference output end (13) is connected with described digital correction circuit；Described 3rd difference is defeated Go out end (23) to be connected with described 5th differential input end (31), described 4th difference output end (24) and described 6th Differential Input End (32) connects.

3. production line analog-digital converter according to claim 2 is it is characterised in that described seven grade of second pipeline stages are distinguished For：The first order second pipeline stages, the second level second pipeline stages, the third level second pipeline stages, the fourth stage second streamline Level, level V second pipeline stages, the 6th grade of the second pipeline stages, the 7th grade of the second pipeline stages；Wherein, the second flowing water at different levels Line level all includes the second sub-adc converter and the second multiplying digital-to-analog converter；

Wherein, described second subnumber weighted-voltage D/A converter includes the 7th differential input end (41), the 8th differential input end (42), the 7th poor Divide outfan (43) and the 8th difference output end (44)；Described second multiplying digital-to-analog converter includes：9th differential input end (51), the tenth differential input end (52), the 9th difference output end (53) and the tenth difference output end (54)；Described 7th difference is defeated Go out end (43) to be connected with described numeral emphasizer circuit；Described 7th difference output end (43) and described 9th differential input end (51) Connect；Described 8th difference output end (44) is connected with described tenth differential input end (52)；

Wherein, described 7th differential input end (41) of described second sub-adc converter of the described first order second pipeline stages It is connected with described 5th difference output end (33), the institute of described second sub-adc converter of the described first order second pipeline stages State the 8th differential input end (42) to be connected with described 6th difference output end (34)；Every one-level second pipeline stage is described backward Described second multiplication all with previous stage second pipeline stages for described 7th differential input end (41) of the second sub-adc converter Described 9th difference output end (53) of digital to analog converter connects, backward the described second submodule number of every one-level second pipeline stage Described second multiplying digital-to-analog converter all with previous stage second pipeline stages for described 8th differential input end (42) of transducer Described tenth difference output end (54) connect.

4. production line analog-digital converter according to claim 3 is it is characterised in that described 3rd pipeline stages include：

3rd subnumber weighted-voltage D/A converter；Wherein, described 3rd subnumber weighted-voltage D/A converter include the 11st differential input end (61), the 12nd Differential input end (62), the 11st difference output end (63) and the 12nd difference output end (64)；Described 11st measurement shoutage is divided into Described 9th difference output end of the second multiplying digital-to-analog converter described in end (61) and described 7th grade of the second pipeline stages (53) connect, described 12nd differential input end (62) is turned with the second multiplication digital-to-analogue described in described 7th grade of the second pipeline stages Described tenth difference output end (54) of parallel operation connects；Described 11st difference output end (63) is with described digital correction circuit even Connect.

5. production line analog-digital converter according to claim 2 is it is characterised in that described first sub-adc converter is by ten Four first comparator compositions；Wherein, each first comparator includes：First order prime amplifier, second level prime amplifier and One latch；Described first order prime amplifier include the first in-phase input end, the first inverting input, the first in-phase output end and First reversed-phase output；It is defeated that described second level prime amplifier includes the second in-phase input end, the second inverting input, the second homophase Go out end and the second reversed-phase output；Described first latch includes the 13rd differential input end (71), the 14th differential input end (72), the 13rd difference output end (73), the 14th difference output end (74)；Described first reversed-phase output is same with described second Phase input connects, and described first in-phase output end is connected with the described second anti-phase access port；Described second reversed-phase output with Described 13rd differential input end (71) connects, and described second in-phase output end is with described 14th differential input end (72) even Connect；Described 13rd difference output end (73) of the first latch described in each first comparator and described first difference output End (13) connects, described 14th difference output end (74) and described second of described first latch of each first comparator Difference output end (14) connects；Described first in-phase input end passes through the first clock switch (Φ with described first reversed-phase output 1) connect；Described first inverting input is connected by described first clock switch (Φ 1) with described first in-phase output end；Often Described first in-phase input end of individual first comparator is passed through with described first differential input end (11) by the first electric capacity (C1) Second clock switch (Φ 2) is connected and is opened by described first clock by described first electric capacity (C1) and the first reference voltage Close (Φ 1) to connect；Described first inverting input of each first comparator passes through the second electric capacity (C2) and described second difference Input (12) passes through described second clock switch (Φ 2) and connects and by described second electric capacity (C2) and the second reference voltage Connected by described first clock switch (Φ 1).

6. production line analog-digital converter according to claim 2 is it is characterised in that described first multiplying digital-to-analog converter By：

3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, 11st electric capacity, the 12nd electric capacity, the 13rd electric capacity, the 14th electric capacity, the 15th electric capacity, the 16th electric capacity, the 17th electric capacity, 18th electric capacity, the 19th electric capacity, the 20th electric capacity, the 21st electric capacity, the 22nd electric capacity, the 23rd electric capacity, second 14 electric capacity, the 25th electric capacity, the 26th electric capacity, the 27th electric capacity, the 28th electric capacity, the 29th electric capacity, 30 electric capacity, the 31st electric capacity, the 32nd electric capacity, the 33rd electric capacity, the 34th electric capacity, the 35th electric capacity, 36 electric capacity, the 37th electric capacity, the 38th electric capacity and the first operational amplifier composition；Wherein, described first computing Amplifier includes an in-phase input end, an inverting input, an in-phase output end and a reversed-phase output；Described in-phase output end It is connected by the first clock switch (Φ 1) with described inverse output terminal；Described in-phase input end is all logical with described reverse input end Cross the 3rd clock switch (Φ 3) and connect common-mode voltage；Described in-phase output end is connected with described 5th difference output end (33)；Institute State reversed-phase output to be connected with described 6th difference output end (34)；

The first end of described 3rd electric capacity, the first end of described 4th electric capacity, the first end of described 5th electric capacity, described 6th electricity The first end of appearance, the first end of described 7th electric capacity, the first end of described 8th electric capacity, the first end of described 9th electric capacity, institute State the first end of the tenth electric capacity, the first end of described 11st electric capacity, the first end of described 12nd electric capacity, described 13rd electricity Hold first end, the first end of described 14th electric capacity, the first end of described 15th electric capacity, the first of described 16th electric capacity End, the first end of described 17th electric capacity, the first end of described 18th electric capacity, the first end of described 19th electric capacity and described The first end of the 20th electric capacity is connected with described in-phase input end by buss；Second end of described 3rd electric capacity, Second end of described 4th electric capacity, the second end of described 5th electric capacity, the second end of described 6th electric capacity, described 7th electric capacity Second end, the second end of described 8th electric capacity, the second end of described 9th electric capacity, the second end of described tenth electric capacity, described Second end of 11 electric capacity, the second end of described 12nd electric capacity, the second end of described 13rd electric capacity, described 14th electric capacity The second end, the second end of described 15th electric capacity, the second end of described 16th electric capacity, the second of described 17th electric capacity Second end of end, the second end of described 18th electric capacity, the second end of described 19th electric capacity and described 20th electric capacity is respectively Be connected by the first clock switch (Φ 1) with described 5th differential input end (31), respectively with the first reference voltage pass through described First clock switch (Φ 1) connected, is connected by described first clock switch (Φ 1) with the second reference voltage respectively, respectively with Described reversed-phase output is connected by second clock switch (Φ 2)；

The first end of described 21st electric capacity, the first end of described 22nd electric capacity, the first of described 23rd electric capacity End, the first end of described 24th electric capacity, the first end of described 25th electric capacity, the first of described 26th electric capacity End, the first end of described 27th electric capacity, the first end of described 28th electric capacity, the first of described 29th electric capacity End, the first end of described 30th electric capacity, the first end of described 31st electric capacity, the first end of described 32nd electric capacity, The first end of described 33rd electric capacity, the first end of described 34th electric capacity, the first end of described 35th electric capacity, institute First end, the first end of described 37th electric capacity and the first end of described 38th electric capacity of stating the 36th electric capacity are passed through One buss are connected with described inverting input；Second end of described 21st electric capacity, described 22nd electric capacity Second end, the second end of described 23rd electric capacity, the second end of described 24th electric capacity, the of described 25th electric capacity Two ends, the second end of described 26th electric capacity, the second end of described 27th electric capacity, the second of described 28th electric capacity End, the second end of described 29th electric capacity, the second end of described 30th electric capacity, the second end of described 31st electric capacity, Second end of described 32nd electric capacity, the second end of described 33rd electric capacity, the second end of described 34th electric capacity, institute State the second end, the second end of described 36th electric capacity, the second end of described 37th electric capacity and the institute of the 35th electric capacity Described first clock switch (Φ 1) is passed through even with described 6th differential input end (32) respectively in the second end stating the 38th electric capacity Connect, be connected by described first clock switch (Φ 1) with described first reference voltage respectively, respectively with described second reference voltage Connected by described first clock switch (Φ 1), pass through described second clock switch (Φ 2) even with described in-phase output end respectively Connect.

7. production line analog-digital converter according to claim 3 it is characterised in that

Second sub-adc converter described in second pipeline stages at different levels is by two the second comparator compositions；Wherein, each Two comparators include：3rd prime amplifier, the 4th prime amplifier and the second latch；It is same that described 3rd prime amplifier includes second Phase input, the second inverting input, the second in-phase output end and the second reversed-phase output；Described 4th prime amplifier includes Three in-phase input ends, the 3rd inverting input, the 3rd in-phase output end and the 3rd reversed-phase output；Described second latch includes 15th differential input end (81), the 16th differential input end (82), the 15th difference output end (83), the 16th difference output End (84)；Described second reversed-phase output is connected with described 3rd in-phase input end, described second in-phase output end and described the Three inverting inputs connect；Described 3rd reversed-phase output is connected with described 15th differential input end (81), and the described 3rd is same Phase output terminal is connected with described 16th differential input end (82)；

Wherein, described second in-phase input end of the 3rd prime amplifier described in each second comparator passes through the 39th electric capacity (C39) it is connected by second clock switch (Φ 2) with described 7th differential input end (41), and by described 39th electricity Hold (C39) to be connected by the first clock switch (Φ 1) with the first reference voltage；3rd pre-amplification described in each second comparator Described second inverting input of device passes through the 40th electric capacity (C40) and passes through described second with described 8th differential input end (42) Clock switch (Φ 2) connects, and is opened by described first clock with the second reference voltage by described 40th electric capacity (C40) Close (Φ 1) to connect；Described 15th difference output end (83) of the second latch described in each second comparator and described the Seven difference output ends (43) connect；Described 16th difference output end (84) of the second latch described in each second comparator It is connected with described 8th difference output end (44).

8. production line analog-digital converter according to claim 7 is it is characterised in that institute in described second pipeline stages at different levels State the second multiplying digital-to-analog converter by the first one-out-three selector, the second one-out-three selector, the second operational amplifier, the 3rd Operational amplifier, the 41st electric capacity (C41), the 42nd electric capacity (C42), the 43rd electric capacity, the 44th electric capacity composition；

Wherein, described first one-out-three selector includes：17th differential input end (91), the 18th differential input end (92), 19th differential input end (93), the first control end (94), the 17th difference output end (95)；Described second one-out-three selector Including：20th differential input end, the 21st differential input end, the 22nd differential input end, the second control end, the 18th Difference output end；It is defeated that described second operational amplifier includes the 4th in-phase input end, the 4th inverting input and the 19th difference Go out end (101)；Described 3rd operational amplifier includes the 5th in-phase input end, the 5th inverting input and the 20th difference output End；

Described 17th differential input end (91), the 20th differential input end are connected with the 3rd reference voltage respectively；Described tenth Eight differential input ends (92), described 21st differential input end are connected with the 4th reference voltage respectively；Described 19th difference Input (93), described 22nd differential input end connect low level respectively；

Described 4th in-phase input end connects common-mode voltage；Described 19th difference output end (101) passes through the first clock switch (Φ 1) is connected with described common-mode voltage；The described 4th inverting input first end with described 41st electric capacity (C41) respectively Connect and be connected with the first end of described 42nd electric capacity (C42)；The first end of described 42nd electric capacity (C42) also by 3rd clock switch (Φ 3) is connected with described common-mode voltage；Second clock is passed through at second end of described 41st electric capacity (C41) Switch (Φ 2) is connected with described 19th difference output end (101)；Institute is passed through at second end of described 42nd electric capacity (C42) The second end stating the first clock switch (Φ 1) with described 41st electric capacity (C41) is connected；Described 42nd electric capacity (C42) The second end switch (Φ 2) also by described second clock and be connected with described 17th difference output end (95)；Wherein, described Second end of 42 electric capacity is connected with described 9th differential input end (51) also by described first clock switch (Φ 1)；Institute Described 19th difference output end (101) stating the second operational amplifier is connected with described 9th difference output end (53)；

Described 5th in-phase input end connects common-mode voltage；Described 20th difference output end passes through described first clock switch (Φ 1) is connected with described common-mode voltage；Described 5th inverting input is connected with the first end of described 43rd electric capacity respectively, It is connected with the first end of described 44th electric capacity；The first end of described 44th electric capacity is also by described 3rd clock switch (Φ 3) is connected with described common-mode voltage；Described second clock switch (Φ 2) and institute are passed through in second end of described 43rd electric capacity State 20 difference output ends to connect；Second end of described 44th electric capacity pass through described first clock switch (Φ 1) with described Second end of the 43rd electric capacity connects；Second end of described 44th electric capacity switchs (Φ 2) also by described second clock It is connected with described 18th difference output end；Wherein, the second end of described 44th electric capacity is opened also by described first clock Close (Φ 1) to be connected with described tenth differential input end (52)；20th difference output end of described 3rd operational amplifier and institute State the tenth difference output end (54) to connect；

Described 15th difference output end (83) of the second latch described in described second subnumber weighted-voltage D/A converters at different levels all with right First control end (94) described in described second multiplying digital-to-analog converter answered connects；In described second subnumber weighted-voltage D/A converters at different levels Described 16th difference output end (84) of described second latch all with institute in corresponding described second multiplying digital-to-analog converter State the second control end to connect.

9. production line analog-digital converter according to claim 4 is it is characterised in that described 3rd subnumber weighted-voltage D/A converter is by seven Individual 3rd comparator composition；Wherein, each the 3rd comparator includes：5th prime amplifier, the 6th prime amplifier and the 3rd latch Device；It is anti-phase that described 5th prime amplifier includes the 6th in-phase input end, the 6th inverting input, the 6th in-phase output end and the 6th Outfan；Described 6th prime amplifier includes the 7th in-phase input end, the 7th inverting input, the 7th in-phase output end and the 7th Reversed-phase output；Described 3rd latch include the 21st differential input end (201), the 22nd differential input end (202), 21st difference output end (203), the 22nd difference output end (204)；

Described 6th reversed-phase output is connected with described 7th in-phase input end, and described 6th in-phase output end is anti-with the described 7th Phase input connects；Described 7th reversed-phase output is connected with described 21st differential input end (201), described 7th homophase Outfan is connected with described 22nd differential input end (202)；

Wherein, described 6th in-phase input end of the 5th prime amplifier described in each the 3rd comparator passes through the 45th electric capacity (C45) it is connected by second clock switch (Φ 2) with described 11st differential input end (61), and pass through the described 45th Electric capacity (C45) is connected by the first clock switch (Φ 1) with the 5th reference voltage；Described in each the 3rd comparator, the 5th puts in advance Described 6th inverting input of big device passes through the 46th electric capacity (C46) and passes through institute with described 12nd differential input end (62) State second clock switch (Φ 2) to connect, and pass through described the by described 46th electric capacity (C46) and the 6th reference voltage One clock switch (Φ 1) connects；Described 21st difference output end of the 3rd latch described in each the 3rd comparator (203) it is connected with described 11st difference output end (63)；Described the second of 3rd latch described in each the 3rd comparator 12 difference output ends (204) are connected with described 12nd difference output end (64).