WO2004062108A1 - Analog/digital converter and electronic circuit - Google Patents

Abstract

A pipeline analog/digital converter having a relatively simple circuit structure. The pipeline ADC (analog/digital converter) comprises a plurality of stages. The error of the output voltage of the digital/analog converting circuit of at least one of the stages and the gain error of the amplifier of the stage can be corrected. The analog/digital converter has a stage for A/D converting an analog input signal and outputting the converted data and a residual signal, a timing adjusting circuit (10) for giving a delay to the converted data, a DAC error correcting circuit (20) for correcting the error of the output voltage of the D/A conversion at the stage, a gain error correcting circuit (30) for correcting the gain error of the amplifier of the stage, an error correction data generating circuit (40) for calculating the error of the output voltage of the D/A conversion and the gain error by using the digital output signal outputted from the gain error correcting circuit (30) and supplying the errors to a DAC error correcting circuit and a gain error correction circuit, and a calibration control circuit (50) for supplying a DAC control signal to the stage.

Description

 Analog / digital converter and electronic circuit

Technical field

 The present invention relates to a pipelined analog-to-digital converter (ADC) for converting an analog signal into a digital signal in a plurality of stages and an electronic circuit. Food

Background art.

 In recent years, the resolution of an image display device such as a liquid crystal display (LCD) or a plasma display panel (PDP) that receives a digital image signal as input is increasing year by year. Has improved. Accordingly, high-precision and high-speed operation is also required for an image ADC for converting an analog image signal into a digital image signal.

 A flash ADC that uses a basic configuration to compare the input voltage with multiple reference voltages generated by a resistor ladder to determine the value of the input voltage is used. In order to achieve high-precision ADC, the flash ADC is configured in two stages, and the input voltage value is obtained by finely dividing one section of the reference voltage in the first stage ADC in the subsequent ADC. Type ADC has been developed. Also, a pipelined ADC that performs the same operation as the two-step ADC in many stages has been put into practical use.

Figure 29 shows the operating principle of the pipeline ADC. As shown in Figure 29, the pipelined ADC first, in the first stage, The voltage of an analog input signal having a dynamic range is classified into one of a plurality of voltage ranges, and the corresponding voltage range is expanded. Further, in the next stage, the voltage of the analog input signal in the expanded voltage range is classified into one of a plurality of voltage ranges, and the corresponding voltage range is expanded. By repeating this operation, high-precision AZD conversion can be realized.

Figure 30 shows the circuit configuration for one stage of a conventional pipelined AD. In this stage, the A / D converter A / D converts the analog input signal V _IN of the corresponding stage and outputs conversion data D _OUT , and the conversion data D output from the ADC 201. A digital-to-analog converter (DAC) 202 that converts _UT to DZA, a sample-and-hold circuit 203 that samples and holds an analog input signal, and an analog input signal that is held in the sample-and-hold circuit 203 D A subtractor 204 for calculating a difference from the analog signal output from AC 202, and an analog output signal V that is a residual signal of the stage by widening the difference obtained by subtractor 204. _And an amplifier ₂₀₅ for outputting _UT .

Figure 31 shows the overall configuration of a conventional pipelined ADC. This pipeline ADC has five stages as shown in FIG. Here, stage 1 generates the conversion data on the MSB side, and stage 5 generates the conversion data on the LSB side. The converted data output from stage 1 to stage 5 is delayed by delay elements 2 11 to 2 15 having delay times T (1) to T (5), respectively, and the output timing is adjusted. The converted data output from the delay elements 211 to 215 are added by the adders 221 to 224 to obtain a final digital output signal. By adopting such a pipeline configuration, each stage can be configured with a small-scale circuit and high-speed operation can be realized. However, if a conversion error occurs in each stage of the pipeline ADC, high-precision A / D conversion cannot be realized. The possible causes of the AZD conversion error are as follows. The circuit for one stage shown in FIG. 30 will be described. In the DAC 202, a variation force S of a resistor or a capacitor used for generating an analog signal may cause an error in A / D conversion. Such a variation in the passive element causes an error in the output voltage of the DAC and affects an analog signal output to the next stage, thereby causing an error in the AZD conversion result. The amplifier 205 is generally configured by an operational amplifier that performs negative feedback using a passive element. In the amplifier 205, the AZD conversion error is caused by the variation of the passive element that determines the gain or the gain error caused by the finite open loop gain of the operational amplifier used for the amplifier.

Figure 32 shows the effect of an error in the DAC output voltage on the input / output characteristics of one stage of the pipeline ADC. Fig. 32 (a) shows the input / output characteristics of one stage of a pipelined AD with no error in the DAC. Fig. 32 (b) shows the error in the DAC. FIG. 4 is a diagram showing input / output characteristics of one stage of a pipeline type ADC having the above-mentioned configuration. On the horizontal axis, the analog input voltage V! _N , and the vertical axis represents the output voltage V _OUT . V _REF and one V _REF are reference potentials at both ends. Thus, if an error occurs in the DAC in one stage of the pipeline type ADC, an error occurs in the output to the next stage.

Figure 33 shows the effect of the gain error of the amplifier on the input / output characteristics of the pipeline ADC stage. Figure 33 (a) shows the input / output characteristics of one stage of a pipelined ADC with no amplifier gain error. Figure 33 (b) shows the amplifier with gain error. pipeline FIG. 7 is a diagram showing input / output characteristics of one stage of a type ADC. The horizontal axis is the analog input voltage V _IN , and the vertical axis is the output voltage V. Takes _UT . _Here,]ぴ_] ^ and- _11] ^ are reference potentials at both ends which are the reference of the conversion range of the A / D conversion. As described above, when a gain error occurs in an amplifier in one stage of a pipelined ADC, a miss code in which a specific code is not output occurs, and the nonlinearity of the AZD conversion characteristic increases. By the way, US Pat. No. 5,635,933 discloses a high-speed and high-precision pipelined multistage ADC. According to Patent Document 1, the error of the output voltage of the DAC in the first stage and the gain error of the amplifier are digitally corrected. However, since the correction of the gain error is performed using only the subtractor, the gain error of the ADC as a whole remains.

 In addition, Japanese Patent Application Publication JP-A-11-274 927 describes that capacitor mismatch, capacitor non-linearity, amplifier gain, and amplifier non-linearity can be corrected. A digital self-calibration scheme for a possible pipelined ADC is disclosed. However, in this calibration method, the circuit scale increases because an operation is performed on the output of each stage after that stage in order to correct an error of a certain stage.

Further, U.S. Pat. No. 6,384,757 discloses a calibration method and apparatus using a DAC for calibration, which determines an error in the output voltage of the DAC in each stage of the pipeline type ADC. Is disclosed. In this method, multiple stages of calibration are performed using one calibration-dedicated DAC, which increases the accuracy and circuit scale required for the DAC. Disclosure of the invention In view of the above, it is an object of the present invention to provide a comparatively simple circuit configuration that can reduce the error in the output voltage of the digital Z analog conversion circuit and the gain error in the amplifier in at least one stage of the pipeline ADC. It is an object of the present invention to provide an analog / digital converter and an electronic circuit that can correct the above.

 In order to solve the above problems, an analog-to-digital converter according to the present invention includes: a stage that receives an analog input signal, performs analog / digital conversion of the analog input signal, and outputs converted data and a residual signal; A timing adjustment circuit that adjusts the timing by giving each output conversion data a delay of an appropriate number of cycles, a DAC error correction circuit that corrects the output voltage of digital analog conversion in the stage, and an amplifier in the stage A gain error correction circuit that corrects the gain error of the DAC, and a digital Z analog conversion output voltage error and gain error are calculated based on the digital output signal output from the gain error correction circuit, and the DAC error correction is performed. Error correction data that supplies the error correction data to the circuit and the gain error correction circuit It includes a generation circuit and a calibration control circuit that outputs a calibration control signal to control the calibration operation and supplies a DAC control signal to the stage.

 According to the present invention, by adding a relatively simple circuit, the error of the output voltage of the digital / analog conversion circuit of the stage and the error of the gain of the amplifier are corrected, thereby achieving high conversion accuracy and low power consumption. An analog digital converter can be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing a configuration of a pipeline ADC as an analog / digital converter according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration example of an error correction data generation circuit, a DAC error correction circuit, and a gain error correction circuit in the pipelined ADC of FIG.

 FIG. 3 is a block diagram showing another configuration example of the pipeline ADC. FIG. 4 is a diagram illustrating a method of approximation calculation in the gain error correction operation circuit.

 FIG. 5 is a diagram showing simplification of calculation in the DAC error correction arithmetic circuit.

 FIG. 6 is a block diagram showing a configuration of each of stage 1 to stage (N-1) of the pipeline type ADC shown in FIG.

 FIG. 7 is a diagram showing a specific circuit example used for each of the stage 1 to the stage (N-1) of the pipeline type ADC shown in FIG.

 FIG. 8 is a diagram showing another circuit used in any one of the stages 1 to (N-1) of the pipeline type ADC.

 FIG. 9 is a diagram showing another example of a circuit used in any one of the stages 1 to (N-1) of the pipeline ADC.

 FIG. 10 is a diagram showing still another example of a circuit used in any one of the stages 1 to (N-1) of the pipeline ADC.

Figure 1 1 is a diagram showing a wire carrier calibration control signal and the switch control signal S E及Pi S ₂ of the waveform at the time of non-calibration.

Figure 1 2 is a diagram in which the stage showing the wire carrier calibration control signal and Suitsuchi control signal S及Pi S ₂ of the waveform at if that is the target of Canon calibration.

 FIG. 13 is a diagram showing a configuration of a stage having no calibration function of the pipeline type ADC shown in FIG.

Figure 14 shows the configuration of the final stage of the pipelined ADC shown in Figure 1. FIG.

 FIG. 15 is a diagram showing another configuration used for each of the stage 1 to the stage (N-1) having the calibration function of the pipeline type ADC shown in FIG.

 FIG. 16 is a diagram showing a specific circuit example of the stage of the pipeline type ADC shown in FIG.

 FIG. 17 is a diagram illustrating a circuit example of a stage in which the configuration of the switched capacitor circuit is different from that of FIG. .

Figure 18 is a diagram showing the case where there is an error with respect to the actual DAC output voltage V ₃ ′ output S and the ideal DAC output voltage v ₃ .

 FIG. 19 is a diagram showing the effect of the output voltage error of the DAC 63 on the input / output characteristics of the stage and the A / D conversion result.

 FIG. 20 is a diagram illustrating a configuration example of a switched capacitor circuit. ■ Figure 21 shows the effect of gain error on A / D conversion results. FIG. 22 is a diagram illustrating a method (first half) of a calibration method for a pipeline ADC according to an embodiment of the present invention.

 FIG. 23 is a diagram showing a second half of the pipeline-type ADC calibration method according to the embodiment of the present invention.

 FIG. 24 is a diagram illustrating a more accurate calibration method (first half) of the pipeline ADC according to the embodiment of the present invention.

 FIG. 25 is a diagram illustrating a more accurate calibration method (second half) of the pipeline ADC according to the embodiment of the present invention.

 FIG. 26 is a diagram for describing a method of AZD conversion during the calibration operation.

FIG. 27 is a diagram for describing a method of A / D conversion during normal operation. FIG. 28 is a diagram for explaining a procedure of error correction in the pipeline ADC according to the present embodiment.

 FIG. 29 is a diagram illustrating the operation principle of the pipeline ADC.

 FIG. 30 is a diagram showing a circuit configuration for one stage of a conventional pipelined ADC.

 FIG. 31 is a diagram showing the overall configuration of a conventional pipelined ADC. FIG. 32 is a diagram illustrating the effect of an error in the output voltage of the DAC on the AZD conversion characteristics of the pipeline ADC.

 FIG. 33 is a diagram showing the effect of the gain error of the amplifier on the input / output characteristics of the stage of the pipeline ADC. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same components are denoted by the same reference numerals, and description thereof will be omitted.

 FIG. 1 is a block diagram showing a configuration of a pipeline ADC as an analog Z-to-digital converter according to one embodiment of the present invention. As shown in FIG. 1, the pipeline ADC has stages 1 to N for performing A / D conversion.

The first stage 1 is supplied from the other circuit receives the analog input signal V E _N (1), which was converted A / D, conversion data D. Outputs _UT (1) and residual signal V _IN (2). The next stage 2 receives the residual signal V _IN (2) of the previous stage as an analog input signal, converts it to AZD, converts the converted data D _OUT (2) and the residual signal V _IN (3). Is output. The same operation is performed in the following stages. However, the last stage N converts the residual signal V _IN (N) of the previous stage into an analog input signal. A / D converted and converted data D. Output only _UT (N).

Furthermore, this ADC adjusts the timing by giving the appropriate number of clock cycle delays to the conversion data D _OUT (1) to D _OUT (N-1) output from stage 1 to stage (N-1). Timing adjustment circuit 10, DAC error correction circuit 20 that corrects DAC output voltage errors in stage 1 to stage (N-1), and amplifier gain in stage 1 to stage (N-1) The DAC error and the gain error are calculated based on the digital output signal output from the gain error correction circuit 30 and the gain error correction circuit 30 which corrects the error, and the DAC error and the gain error correction circuit 30 are respectively calculated. Error correction data generation circuit 40 that supplies error correction data, and outputs a calibration control signal to control the calibration operation and DAC control for each stage. And a wire carrier calibration control circuit 50 supplies the No..

DAC error correction circuit 20, D AC error correction data DE (1 that put on the stage 1 stage (N- 1), k J ~DE (N- 1, k N - DAC error correction data for storing J Memory 21 and (ki… k _N — are variables) and conversion data D _OUT (1) to D. DAC error correction data DE (1, D _OUT ) corresponding to the conversion data value from _UT (N-1) (1)) to DE (N-1, D. _UT (N-1)) are subtracted respectively, and the converted data D l _OUT (1) to D l _OUT (N-1) corrected for the DAC error are output. (N-1) DAC error correction arithmetic circuits 22. Here, the DAC error correction data memory 21 is provided in stages 1 to (N-1). It is composed of a plurality of memories for storing DAC error correction data corresponding to each DAC output value.

The gain error correction circuit 30 is connected between stage 1 and stage (N-1). (N-1) gain error correction data memories 31 (1) that respectively store gain error correction data GE (1) to GE (N-1) to correct the gain error of the amplifier 1) gain error correction arithmetic circuits 3 2

(N— 1) adders 3′3.

For i = l to (N-1), the ith gain error correction arithmetic circuit converts the converted data D2. Conversion data D3 in which the gain error is corrected by multiplying or approximately multiplying the gain error correction data GE (i) of stage i by _UT (i + 1). Generate _UT (i + 1). However, for stage N, conversion data D 2 _OUT (N) = D. _UT (N).

For i = l to (N_l), the i-th adder converts the conversion data D3 output from the i-th gain error correction operation circuit. Conversion data D1 to _UT (i + 1). _UT (i) is added and the conversion data D 2 _OUT

Generate (i).

The error correction data generation circuit 40 includes a DAC error correction data generation circuit 41 and a gain error correction data generation circuit 42. The DAC error correction data generation circuit ₄₁ calculates the DAC error in the stage based on the digital output signal D 2 _ουτ (1) of the AZD converter, and converts the data for correcting the DAC error into DAC error data. Output to the correction circuit 20. The gain error correction data generation circuit 42 calculates the gain error of the amplifier based on the digital output signal D 20 _UT (1) of the AZD converter, and outputs data for correcting the gain error to the gain error correction circuit 3. Output to 0. The pipeline type ADC described above includes a plurality of stages, a timing adjustment circuit 10, a DAC error correction circuit 20, and a gain error correction circuit 30, and includes a data generation circuit 40 for error correction and a calibration. The control circuit 50 may be incorporated in arithmetic and control means connected to the outside of the ADC to constitute an electronic circuit as a whole. Fig. 2 shows the configuration of the error correction data generation circuit, DAC error correction circuit, and gain error correction circuit. In FIG. 2, the influence of noise can be reduced by arranging averaging circuits 43 and 44 on the input side or output side of the error correction data generation circuit. In the error measurement result averaging circuit 43 placed on the input side, the measurement value D 2 generated in the A / D converter. By averaging _UT (1), the effect of noise during measurement in calibration can be reduced. On the other hand, the error correction data averaging circuit 44 disposed on the output side averages the error correction data output by the gain error correction data generation circuit or DAC error correction data generation circuit. In addition, the influence of noise during calibration can be reduced. According to this method, since only the error correction data is averaged, the amount of memory required for averaging can be reduced. Multiplexers 23 and 34 are placed at the inputs of the DAC error correction arithmetic circuit 22 and the gain error correction arithmetic circuit 32 of each stage, respectively, so that the correction result is equivalent to the case where no correction is applied. Input of appropriate data for correction. This configuration has the advantage that, when recalibrating the calibrated device, the calibration can be executed while the error correction data is held in the memory. This configuration is effective, for example, in reducing the amount of memory when averaging the calibration results using the calibration results stored in the error correction data memory.

Also, by arranging the multiplexer 24 at the input of the DAC error correction arithmetic circuit, the stage output D _{OUT is set} to 0 so that the stage output is not added to the calculation result at the time of calibration. For example, when stage k is calibrating, output D of stage 1 to stage k. _{Assuming that UT} (k) is 0, depending on the stages after stage k + 1 Only the A / D conversion result is sent to the error correction data generation circuit. With this configuration, the A / D conversion results D 2 up to and after each stage during calibration. _Wiring for connecting _{配線 τ} to the error correction data generation circuit can be reduced.

 FIG. 3 is a block diagram showing another configuration example of the pipeline ADC. As shown in FIG. 3, this pipeline type ADC has stages 1 to 10 for performing A / D conversion, and only stage 1 of these stages has a calibration function. . Stage 1 with the calibration function consists of the stage with the calibration function of the pipelined ADC shown in Figure 1 as shown in Figure 10 or Figure 10 or Figure 16 to Figure 17 from Figure 16 Each of stages 2 to 9 without calibration function is composed of the stage circuit of Fig. 13 or other general pipeline type ADC, and the final stage 10 is shown in Fig. 14 It consists of the circuit as shown.

The DAC error correction circuit 20 includes a DAC error correction data memory 21 that stores the DAC error correction data DE (l, k) (k = 1, 2,...) In stage 1. , DAC error correction data DE (1, k) is subtracted from conversion data D _OUT (1), and DAC error correction arithmetic circuit that outputs conversion data _D1ουτ (1) corrected for DAC error Includes 22 and.

The gain error correction circuit 30 includes a gain error correction data memory 31 for storing gain error correction data GE (1) for correcting a gain error in the stage 1, and a gain error correction arithmetic circuit 32. And a plurality of adders 33 for adding the AZD conversion result of each stage. The ninth adder adds the stage 9 conversion data D _OUT (9) to the stage 10 conversion data D _OUT (1 0) = D 2 _OUT (10), and Outputs converted data D 2 _OUT (9) for stage 9 or later. The eighth adder is the conversion data D2 for stage 9 and later. The converted data D of stage 8 is _{obtained at υτ} (9). _UT (8) is added, and converted data D 2 _ουτ (8) after stage 8 is output. The seventh adder converts the stage 7 conversion data D 2 OUT (8) to the stage 7 conversion data D 2 OUT (8). _UT (7) is added, and the converted data D2 after stage 7 is added. _υτ (7) is output. The same applies hereinafter. The gain error correction arithmetic circuit 32 corrects the gain error by correcting the gain error by using the gain correction data GE (1) of stage 1 for the converted data D 2 OUT (2) after stage 2. The converted data _{D3 ουτ} (2) from the stage 2 onward is output. The first adder adds the conversion data D l _OUT (1) of stage 1 to the conversion data D 3 _ουτ (2) of stage 2 and after, which has corrected the gain error, and A / D conversion result D 2 _ουτ (1) is output.

 As described above, if the conversion accuracy does not decrease without performing calibration at one or more stages on the LS Β side, the calibration on the LS Β side is not performed within the range where the conversion accuracy does not decrease. With this configuration, the circuit scale can be reduced without lowering the conversion accuracy of the pipelined ADC as a whole.

 Fig. 4 shows the approximate calculation method in the gain error correction operation circuit. Assuming that the correct gain in design is Α and the actual gain is Α, the gain error correction data GE (X) = Α, 求 め obtained by measurement is used to correct the AZD conversion result. This is realized by division. However, when the divider 35 is used, the scale becomes large, so that the power consumption and the area increase.

Since the ADC is usually designed so that the difference between A 'and Α is small, the reciprocal of the gain error correction data 1 ZG E (X) is A' = A If (1 + mu A), it can be approximated as 1 / GE (X) = A / A '1-one ΔΑ + ΔΑ ² —. Here, if the gain error correction data is GE '(X) = 1 / GE (X) ^ 1— Δ A + Δ A ² …, the operation in gain error correction can be replaced by multiplication instead of division. . In the calibration of the ADC, the power consumption and the area can be reduced by using the approximate calculation and replacing the divider 35 with the multiplier 36.

 Also, the gain error correction data 1- is converted to GE '' (X) = A / A '1 1 1

 Four

By setting Δ Α + 'Δ Α ² ···, the operation can be decomposed into addition and multiplication. Usually, in the ADC, since the error between A ′ and A is small, the value of μm A is small, and the circuit scale of the multiplier 36 having a large area and large power consumption can be suppressed. In this configuration, the area and power consumption can be further reduced by using the multiplier 37 and the adder 38 to correct the gain error.

 Figure 5 shows the simplification of calculations in the DAC error correction arithmetic circuit. In the DAC error correction circuit, the DAC error is corrected by adding the DAC error correction data and the AZD conversion result of the stage. If the error occurring in the DAC is considered to be small, the value of the DAC error correction data DE (X) is small, and only affects the lower bits of the final A / D conversion result. Absent. In the first stage of determining the AZD conversion result on the LSB side of the pipelined ADC, the AZD conversion result of the stage affects only the upper bits of the entire A / D conversion result. Therefore, in the first stage of the pipeline ADC, the subtracter 39 for subtracting the A / D conversion result of the stage from the DAC error correction data in the DAC error correction arithmetic circuit can be omitted.

FIG. 6 is a block diagram showing a configuration of each of the stages 1 to (N-1) of the pipeline type ADC shown in FIG. This circuit is The ADC 6 1 for outputting converted data D _OUT having M bits by AZD converting an analog input signal V _IN of stages, a multiplexer 6 2, D AC 63 having a conversion accuracy (M + 1) bit , A multiplexer 64, a sump-no-horno redo circuit 66, and a subtractor 6 7 for calculating the difference between the analog signal output to the sump-no-rehono-redo circuit 66 and the analog signal output from the DAC 63. And the difference obtained by the subtracter 67 is amplified by the gain A to obtain the residual signal V of the stage. _And an amplifier ₆₈ outputting as _UT .

According to the calibration control signal 1 that can be output from the calibration control circuit 50 (FIG. 1), the multiplexer 62 controls the stage to be calibrated during non-calibration or calibration. If not, the conversion data D _ουτ output from the ADC ₆₁ is selected and output. If the stage is subject to calibration, it is output from the calibration control circuit 50. Select and output the DAC control signal. The DAC 63 converts the output of the multiplexer 62 from analog to digital and outputs an analog signal V _DA .

The multiplexer 64 operates according to the calibration control signal 2 output from the calibration control circuit 50 (FIG. 1). If the stage is not to be calibrated, multiplexer 64 provides analog input signal V! _N is output to the sample hold circuit 66. The sample hold circuit 66 samples and holds the analog input signal V _IN of the stage. If the stage is the subject of a carry-over, multiplexer 64 connects the output of DAC 63 to the input of sample-and-hold circuit 66. The sample hold circuit ₆₆ samples the _analog signal V _{D 出力} output from the DAC 63 Do it.

 Here, the operation of the circuit shown in FIG. 6 will be described in detail. First, the normal AD conversion operation during non-calibration will be described. The same applies to the case where this stage is not subject to calibration at the time of calibration.

AD C 6 1 are the Anna port grayed input signal V t _N of the stage to convert A / D, obtains the conversion data D _OUT of the M bit. The conversion data D _OUT is supplied to the DAC 63 via the multiplexer 62. The DAC 63 is used with the number of conversion bits of M bits, and performs D / A conversion on the conversion data D _OUT of M bits output from the ADC 61 and outputs it as an analog signal V _DA .

The sample and hold circuit 6 6 receives the analog input signal V! Sample and hold _N. The subtracter 67 obtains a difference between the analog input signal V _IN held by the sample and hold circuit ₆₆ and the analog signal V _DA output from the DAC 63. The amplifier 68 amplifies the difference obtained by the subtractor 67 to generate a residual signal V. _Output to the next stage as _UT .

 Next, a description will be given of the operation when the stage is a target of the calibration during the calibration.

ADC61 is not used because AZD conversion is not performed on the stage targeted for calibration. At the time of calibration, DAC 63 is used with the number of converted bits of (M + 1) bits. First, the DAC 6 3, performing a first D AC control signal given Ete A converter via the multiplexer 6 2, and outputs a first calibration Ana port grayed signal V _{D A1.} The sample hold circuit 65 samples and holds the output V _DA of the DAC 63. Next, the second D which is obtained by adding or subtracting the value corresponding to 1 LSB of the M + 1-bit DAC 63 to the first DAC control signal to the DAC 63 through the multiplexer 62 An AC control signal is applied to perform D / A conversion, and a second calibration analog signal V _DA2 is output. The subtracter ₆₇ obtains the difference between the analog signal V _{DA1 held} by the sample hold circuit ₆₆ and the analog signal V _DA2 output from the DAC ₆₃ . This difference corresponds to 1/2 LSB or 1/2 LSB of M bits of the number of A / D conversion bits of the stage, and the difference is determined by the amplifier 68 in the next stage of the stage. Subsequent to the full scale of the dynamic range of the ADC configured below. The difference between the amplified analog signals indicates the difference between the output voltages of the M + 1-bit DAC 63, and the difference is measured by the ADC after the next stage of the stage. Calculate the output voltage error of D AC 63. Here, this difference is amplified by the amplifier 68, and the measurement is performed using the full scale of the A / D conversion range in the next stage, so that highly accurate calibration is realized.

 By repeating the above measurement for a plurality of DAC control signals, the DAC error and amplifier gain error in the next stage are corrected based on the data obtained in the ADC after the next stage. .be able to.

 Furthermore, by performing two measurements by changing the order in which the first and second DAC control signals are supplied, and averaging these measurements, the ADC error after the next stage can be corrected. The effect on the translation results can be reduced.

According to the present embodiment, as compared with the conventional pipelined AD-type stage configuration shown in FIG. Calibration of a pipelined ADC can be realized by adding only two cavities. However, the M + 1-bit DAC 63 does not necessarily have to have the number of conversion bits of M + 1 bits, but may have any number of conversion bits larger than M bits.

 FIG. 7 is a diagram showing a specific circuit example used for each of the stage 1 to the stage (N-1) of the pipeline ADC shown in FIG. In this example, calibration is performed in each of the stages 1 to (N-1), and the number of A / D conversion bits in each stage is 2 bits.

ADC 61 includes a plurality of analog input voltage V Ϊ _N, DAC 6 3 reference potential V ₂ generated at resistor ladder 72 which constitute _{the, V 4, V 6, V} 8 Tooso respectively compared comparator 71, the first encoder 75 that calculates the AZD conversion result based on the comparison result output from the comparator 71, and the A / D conversion result calculated by the first encoder 75 is converted to binary data. And a second encoder 76.

The reference voltage V ₂ , V ₄ , V or V ₈ of ADC 61

By using a resistor ladder 72 that is shared with 63, the amount of hardware is reduced, and the same level of the reference voltage of the comparator 71 is generated by the DAC 63 during calibration so that calibration is performed. Since it is used, there is an advantage that a calibration result can be obtained in consideration of the influence of a reference voltage error.

 The DAC 63 has a resistor ladder consisting of multiple resistors connected in series.

A resistor ladder type DAC that selects and outputs one of the potentials at the terminals of these resistors in accordance with the input data is used. Generated by dividing the reference potential + V _REF and 1 V _REF and the potential difference between these reference potentials by eight resistors in DAC 63. From among a total of nine potential Vi Vg of the seven potential which is, by only one of the plurality of Suitsuchi 7 3 is turned on in response to the input data, one potential is selected and V _DA Is output as

At the time of calibration, first, by inputting the first DAC control signal to the DAC 63 via the multiplexer 62, V ₂ , V ₄ , V ₆ , which are used as the reference voltage of the ADC 61, One of V ₈ is output from DAC 63 and is used as the first calibration analog signal V _DA1 . Then, by inputting the second D AC control signals via the multiplexer 6 2 to DAC 6 3, V have V ₃ used at the time of AZD conversion at the time of non Canon calibration as the output of the DAC 6 3, V ₅ , V ₇ , or V ₉ are output from the DAC 63 and are used as the second calibration analog signal V _DA2 .

 In addition, the manoplexer 64, the sump-no-hold circuit 66, the subtracter 67, and the amplifier 68 shown in FIG. 6 are realized by one switch capacitor circuit 80 in FIG. The switched capacitor circuit 80 includes an operational amplifier 81, two capacitors C1 and C2, and switches SW1 to SW2.

If the non-wire carrier calibration and during wire carrier relevant stage during calibration is not the Kiyari play Deployment subject switch preparative capacity Sita circuit 8 0 samples and holds the analog input signal V zeta _N, analog input signal V The difference between _IN and the analog output signal V _DA of DAC 63 is amplified and output to the next stage as residual signal V _OUT .

If the stage is to be calibrated, the switched capacitor circuit 80 sets the reference voltages V ₂ , V ₄ , V ₆ , and V ₆ of the ADC 61 output by the DAC 63. ₈ sample and hold the first calibration analog output signal V _DA 3 Analog output signals V _DA1 and DAC 63 output from DAC 63 used during AZD conversion V Any of V ₃ , V ₅ , V ₇ , V ₉ The difference from the second calibration analog output signal V _DA2 is amplified and output to the next stage. The output of the switched capacitor circuit 80 is subjected to A / D conversion in the next stage and thereafter, and the digital value of the difference between V _DA2 and V _DA1 is obtained. Measure the value to achieve calibration.

Also, by inverting the procedure of inputting the first DAC control signal and the second DAC control signal to the DAC 63, the output level of the DAC used during A / D conversion is V ₃ , V ₅ , V _{5 7,} one of the V ₉ and first Canon Ribureshiyo analog signal emissions, either a second calibration of the AD C 6 1 reference voltage _{V 2, V 4, V 6} , V 8 It is also possible to measure the voltage value between each level output by DAC as an analog signal for analog. By inverting the input procedure of the D AC control signal, the voltage value output from the switch capacitor circuit 80 is inverted with reference to the analog ground level. Inverting and non-inverting enable measurement at different voltage levels, and averaging the measured values when inverting and when not inverting allows for the measurement of A / D conversion errors after the next stage. The effect on the result of the application can be reduced.

According to the present embodiment, as an analog circuit, calibration of a pipelined ADC becomes possible only by adding one bit to the DAC of the stage. The only cost required to increase the DAC conversion accuracy by 1 bit is the switch, which is less hardware than a method in which a calibration DAC is placed outside the stage. Less increase. In addition, the DAC to be measured generates the calibration voltage itself. Therefore, there is no characteristic difference between DACs, which is problematic in a configuration in which another calibration DAC is arranged outside the stage. Furthermore, since the reference voltage of the comparator is used as an analog signal for calibration at the time of calibration, calibration is performed in consideration of the influence of the error of the reference voltage of the comparator.

 In addition, by using a resistor ladder type DAC for the DAC 63, the number of capacitors required in the switch capacitor circuit can be reduced as compared with the case of using a switch capacitor type DAC, and the switch capacitor circuit can be used. The requirements of matching accuracy required for the capacity of the capacitor can be relaxed. Furthermore, in the ADC 61, by sharing the resistor ladder used for generating the reference voltage of the comparator with the resistor ladder 72 of the DAC 63, the number of resistive elements can be reduced. FIG. 8 is a diagram showing another circuit used in any of the stages 1 to (N-1) of the pipeline type ADC. In this circuit, the ADC 61, the DAC 63, and the switched capacitor circuit 80 have a differential configuration, and perform differential input / output. In other respects, it is the same as the circuit described above.

 The ADC 61 receives the outputs of the differential comparators 71 operating on differential inputs, the first encoder 75 operating on the outputs of these comparators, and the first encoder 75. And a second encoder 76 and operable. The first encoder 75 and the second encoder 76 perform the same operation as the first encoder 75 and the second encoder 76 in one embodiment.

In the DAC 63, two switches are connected to the connection point between two adjacent resistors in the resistance ladder 72 or the connection point between the reference potential and the resistance, and supplied from the multiplexer 62. Based on these- By selectively turning on / off the switch 73, a pair of output voltages V _DA and V _DA are generated.

The switched capacitor circuit 80 includes two sets of switches SW11 and SW12 of the first set, switches SW21 and SW22 of the second set, and switches SW31 and SW32 of the third set. And the differential input / output type operational amplifier 8 1. Switch-capacitor circuit 8 0, the analog input signal V _IN及Pi - and V _IN, the output voltage of the D AC 6 3 V _DA and - based on the V _DA, switching operation, the sample-and-hold operation, a subtraction process, amplification And the residual signal V. _UT and one V. Differential output of _UT .

 Thus, the influence of noise can be reduced by forming each circuit in a differential configuration. In addition, when using a resistor ladder type DAC with each circuit in a differential configuration, the number of passive elements increases less than when using a switch capacitor type DAC with a differential configuration. Has advantages.

 FIG. 9 is a diagram showing another example of a circuit used in any one of the stages 1 to (N-1) of the pipeline ADC. This circuit has a differential configuration like the circuit of FIG. 8, but the number of switches used for the DAC 63 and the switched capacitor circuit 80 is reduced.

In DAC 6 3, switch SW 2 1 between the reference potential V ₅ ~ switches SW 1 capacitor C 1 which are connected to one of the four switches and switch-capacitor circuit 8 0 flanked each V ₉ is The switch SW31 is connected between the four switches connected to the reference potential VVS and the capacitor C1 connected to the switch SW11 of the switched capacitor circuit 80.

Further, the reference potential V ₅ ~V 4 single flanked respectively ₉ switches the switch-capacitor circuit 8 0 of switch SW1 2 connected to the Capacity A switch SW22 is connected between the switch SW22 and the capacitor C1 connected to the switch SW12 of the switched capacitor circuit 80 and four switches respectively adjacent to the reference potential Vi Vs. Switch SW32 is connected between them.

 In this way, the switches SW21, SW22, SW31, and SW32 are shared between the DAC 130 and the switched capacitor circuit 80, so that the number of switches is reduced as a whole and the DAC 63 The time until the output stabilizes can be shortened.

 FIG. 10 is a diagram showing still another example of a circuit used in any one of the stages 1 to (N-1) of the pipeline ADC. This circuit also has a differential configuration similar to the circuit of FIG. 8, but the number of switches included in the DAC 63 is reduced.

 In the present embodiment, the data output from the multiplexer 62 is supplied to the switch control circuit 100 instead of the DAC 63. The switch control circuit 100 outputs a switch control signal S for controlling the switches SW 11 and SW 12 in the switched capacitor circuit 80 based on the calibration control signal and the data output from the multiplexer 62. And outputs switch control signals S2-S10 for controlling the switches SW21-SW101 and SW22-SW102 in the DAC 63. By reducing the number of switches as a whole, wiring can be simplified and the chip area can be reduced.

Here, the operation of the switch control circuit 100 in the circuit of FIG. 7 will be described. Switch control circuit 1 0 0, therefore the calibration control signal, the switch control signals S i and S ₂ is supplied to the switch SW1 and SW2, for controlling these switches. Figure 11 shows the calibration control signal and the switch control signals S and S ₂ during normal operation. FIG. 12 shows the waveforms of the calibration control signal and the switch control signals S i and S ₂ when the stage is a target of calibration.

During non-calibration, as shown in FIG. 1 1, and inputs the analog input signal V t _N during the sample, the analog output signal V _DA of D AC 6 3 to sweep rate Tutsi-capacitor circuit 8 0 during holding Thus, the switches SW1 and SW2 are controlled. When the stage is the target of calibration, as shown in Figure 12, the sampling analog output _VDA1 and _VDA2 of the DAC 63 are sampled and held at the time of sampling and holding. The switches SW1 and SW2 are controlled so that they are sequentially input to the switch capacitor circuit 80.

 The calibration may be performed in at least one of the stages 1 to (N-1) of the pipeline ADC. In that case, the calibration function can be omitted in other stages. Figure 13 shows an example of a stage circuit without the calibration function. In this circuit, the multiplexer 62 is omitted from the circuit shown in FIG. 7, and the conversion accuracy of the DAC 63 is M bits (M = 2).

FIG. 14 is a diagram showing an example of a circuit used in the final stage of the pipeline ADC shown in FIG. This circuit consists of a 2-bit flash ADC 61. In the ADC 61, the reference potential + V _REF and −V _REF, and the three potentials generated by dividing the potential difference between these reference potentials by four resistors, a total of five potentials VV ₃ , V ₅ , V ₇ , and V ₉ are generated. The ADC 61 has a plurality of comparators 91 that compare the analog input voltage V _IN with the potentials V ₃ , V ₅ , V ₇ , and V ₉ , respectively, and a comparison result output from these comparators. And an encoder 95 for obtaining an AZD conversion result based on the data and outputting the result as binary data.

FIG. 15 shows another example of a circuit used for each of the stage 1 to the stage (N-1) having the calibration function of the pipeline type ADC shown in FIG. This circuit converts the analog input signal V _IN of the corresponding stage into an AZD and has converted data D having M bits. ADC 61 outputting _UT , multiplexer 62, first DAC 63 having M conversion bits, and second DAC 63 having M conversion bits 5, a multiplexer 64, a sample-and-hold circuit 66, and a subtractor 67 for calculating the difference between the analog signal held in the sample-and-hold circuit 66 and the analog signal output from the DAC 63. And an amplifier 68 that amplifies the difference obtained by the subtracter 67 with a gain A and outputs the result as a residual signal _VOUT of the stage.

 The operation of the circuit shown in FIG. 15 will be described. First, normal operation will be described. The same applies to the case where the stage is not subjected to calibration during the calibration operation.

The ADC 61 performs AZD conversion on the analog input signal V _IN of the relevant stage to obtain M-bit conversion data D _OUT . Conversion data D. _{The UT} is supplied to the first DAC 63 via the multiplexer 62. The first DAC 63 is the conversion data D output from the ADC 61. _DZA converts _Dτ and outputs analog signal V _DA1 .

The sample hold circuit 66 samples and holds the analog input signal V j _N of the stage. The subtracter ₆₇ obtains a difference between the analog input signal V _IN held by the sample and hold circuit ₆₆ and the analog signal V _DA1 output from the first DAC ₆₃ . The amplifier 68 amplifies the difference obtained by the subtractor 67 and generates a residual signal V. Next stay as _UT Output to the printer.

Next, the operation in the case where the stage is a target of calibration will be described. ADC 61 is not used at the stage targeted for calibration because AZD conversion is not performed. First, the DAC control signal 2 is supplied to the second DAC 65. The second DAC 65 converts the DAC control signal 2 into a DZA signal, and outputs a calibration analog signal V _DA2 . Multiplexer 64 connects the output of the second DAC 65 to the input of the sample and hold circuit. The sample hold circuit 66 samples and holds the calibration analog signal V _DA2 output from the second DAC 65.

Next, the DAC control signal 1 is supplied to the first DAC 63 via the multiplexer 62. The first DAC 63 converts the DAC control signal 1 into a DZA signal, and outputs a calibration analog signal V _DA1 . The subtracter 67 obtains the difference between the calibration analog signal V _DA2 held by the sample hold circuit 66 and the calibration analog signal V _DA1 output from the first DAC 63. The amplifier 68 amplifies the difference obtained by the subtractor 67 and generates a residual signal V. Output to the next stage as _UT .

 According to the present embodiment, as compared with the stage configuration of the conventional pipelined ADC shown in FIG. 30, by adding one DAC and two multiplexers to the stage, The ADC calibration can be realized. However, the second DAC 65 need not necessarily have the number of conversion bits of M bits, but may have any number of conversion bits of M bits or more than M bits.

FIG. 16 is a diagram showing a specific circuit example of the stage of the pipeline type ADC shown in FIG. The circuit in this stage uses the analog input signal M-bit ADC 61 for A / D conversion of _N , M-bit DAC 65, M-bit DAC 63, multiplexer 64, sample-and-hold circuit 66, and subtractor in Figure 15 It comprises a switch capacitor circuit 110 having the functions of an amplifier 67 and an amplifier 68, two encoders 77 and 78, a manoplexer 79, and a switch control circuit 100.

The M-bit DAC 65 selects one of the resistor ladders 72 consisting of multiple resistors connected in series and one of the potentials at the terminals of these resistors in response to the DAC control signal 2. And a switch 73 for output. In DAC 65, the reference potential + V _REF and -V _REF and the seven potentials generated by dividing the potential difference between these reference potentials by eight resistors are used. The potential V ₂ , V ₄ , V ₆ , or V _{8 of} one of the plurality of switches 73 is turned on in response to the DAC control signal 2, and the analog signal for calibration is turned on.

Select and output as V _DA2 .

AD C 6 1 includes an analog input voltage V t _N, DAC.6 5 reference voltage V ₂ generated at resistor ladder 7 2 constituting _{the, V 4, V 6, V} 8 Tooso respectively compared A plurality of comparators 71, an encoder 77 for obtaining A / D conversion results based on the comparison results output from these comparators 71, and a switch capacitor circuit 11 1 for comparing the comparison results output from the comparator 71. And an encoder 78 for converting the data into data for controlling the function of the DAC included in 0. In AD C 6 1, by utilizing the potential _{V 2, V 4, V 6} , V 8 of the potential resistance ladder 7 2 to share with DAC 6 5 outputs, AZD conversion.

In the circuit example shown in FIG. 16, the DAC 63 shown in FIG. 15, the multiplexer 64, the sample-and-hold circuit 66, the subtractor 67, and the amplifier 68 are connected to one switch. Realized by the capacitor circuit 110 I have. The switch capacitor circuit 110 includes an operational amplifier 111, a plurality of capacitors 112, and a switch 113.

When the stage is not calibrated, the switch carrier circuit 110 receives the analog input signal V! _N is sampled and held, the analog input signal V _IN and the DAC function of the switched capacitor circuit 110 are generated, and the potentials generated by the resistance ladder 72 of the DAC 65, V ₃ , V ₅ , V ₇ amplifies the difference between the output voltage V _DA1 of DAC 6 5 corresponding to one of V _9, to force out it to the next stage as the residual signal V _OUT.

When the stage is to be calibrated, the switch capacitor circuit 110 outputs the calibration analog signal V _DA2 output from the DAC 65 based on the DAC control signal 2. Sample hold, this calibration analog signal V _DA2 and the calibration capacitor analog signal V _DA1 generated by the DAC function of the switch capacitor circuit 110 that operates by inputting the DAC control signal 1 And amplifies the difference and outputs it to the next stage.

 FIG. 17 is a diagram illustrating a circuit example of a stage in which the configuration of the switched capacitor circuit is different from that of FIG. The circuit in this stage consists of an M-bit ADC 61 that performs A / D conversion of the input signal, an M-bit DAC 65, an M-bit DAC 63 and a multiplexer 64 shown in Figure 15. It comprises a switch capacitor circuit 110 having the functions of a sample-and-hold circuit 66, a subtractor 67 and an amplifier 68. In the circuit of Fig. 17, compared to the circuit of Fig. 16, the number of capacitors 1 1 and 2 used for the switched capacitor circuit 110 increases, but the advantage that the analog ground level is not required for the input is provided. Having.

In the following, the configuration of the stage circuit shown in This section describes the effects of the error of the amplifier and the error of the amplifier gain on the A / D conversion. The same applies to the circuit configurations of the stages in FIGS. 8 to 10, 16, and 17, as described below.

If the DAC output voltage in one stage has an error with respect to the ideal DAC output voltage, an error occurs in the residual signal output to the next stage. FIG. 18 shows a case in which there is an error with respect to the actual output voltage V ₃ ′ of the DAC and the ideal output voltage V ₃ of the DAC. V _3, - causing an error of V _x) - V _x) one (V _3.

FIG. 19 shows the effect of an error in the output voltage of the DAC 63 on the input / output characteristics of the stage and the A / D conversion result. The horizontal axis shows the voltage of the analog input signal, and the vertical axis shows the voltage of the residual signal and the output code of ADC, respectively. In stage i, changes from the analog input signal V _IN (i) gar V _REF (i) to V _REF (i), the residual signal V. _UT (i) should change between one _VREF (i + 1) force and _VREF (i + 1), but due to the error of DAC 63, A (i) · (V ₃ '-V -A (i) · (V ₃ -VJ). This causes the ADC output, which will be obtained from the next stage onward, to have an error E 1 Occurs.

E 1 = AD {A (i). · (V ₃ ,-V _x )}

Here, AD {V} means the value represented by the data obtained by A / D converting the voltage V output to the next stage.

If a gain error exists in one stage, the amplitude of the residual signal output to the next stage is different from the ideal value. A / D conversion result The linearity of the AZD conversion characteristics at the voltage at which the voltage changes is deteriorated.

FIG. 20 shows a configuration example of the above-described switch capacitor circuit. This switched capacitor circuit alternately inputs an analog input signal V _IN and an output voltage V _DA of D AC, and generates an output voltage V _OUT represented by the following equation.

V _OUT = C 1 / C 2 (V _IN -V _DA )

That is, the ideal gain A is represented by A = C 1 ZC 2. Here, assuming that the capacitance of the capacitor becomes C 1 ′ and C 2 ′ due to variations, the actual gains A and A are expressed as A, = C 1 and / C 2 ′.

Figure 21 shows the effect of gain error on A / D conversion results. The horizontal axis shows the voltage of the analog input signal, and the vertical axis shows the voltage of the residual signal and the output code of ADC. In stage i, when the analog input signal V _IN (i) changes from one V _REF (i) to V _REF (i), the residual signal V _OUT (i) becomes one V _REF (i + 1) _It should change up to _REF (i + 1), but due to the effect of gain error, the error of V _REF (i + 1) • (1 A '(i) / A (i)) Occurs. This results in an error E2 in each step of the ADC output voltage at the next stage, which is expressed by the following equation.

E 2 = AD (V _REF (i + 1)

 · (1 -A '(i) / A (i))}

Here, Digitally Le value SUB ~ SUB ₄ of the potential difference between the two output voltages in the actual DAC is expressed as follows.

S UB _x = AD {A '(i) · (V ₂ -Vj}

-AD {A ⁵ (i) · (V ₂ -V ₃ )}

S UB ₂ = AD {A '(i) · (V ₄ -V ₃ )}

-AD {A '(i)-(V ₄ -V ₅ )} SUB ₃ = AD {A, (i) · (V ₆ -V ₅ )}

-AD {A '(i) · (V ₆ -V ₇ )}

S UB ₄ = AD {A '(i) · (V ₈ -V ₇ )}

-AD {A '(i) · (V ₈ -V ₉ )}

 Therefore, the sum S 'of the digital values of the potential difference between the two output voltages in the actual DAC is expressed by the following equation.

S '-Σ (j = l.~4) {AD {Α' (i) · (V 2 "

V _{2 j} — J} one AD {A, (i) · (V _{2 j} -V _{2 j + 1} )}} On the other hand, the sum S of the digital value of the potential difference between the two output voltages of the ideal DAC is It is expressed by the following equation.

S = Σ (j = l~4) {AD {A (i) · (V 2 j - V 2 DOO J} one AD {A (i) · ( V 2 j -V 2 j +1)}}

 Therefore, these differences (S_S,) are differences due to the effects of gain errors.

 Next, a pipeline type ADC calibration method included in the semiconductor device according to the present embodiment will be described with reference to FIGS. 22 and 23. FIG.

 FIG. 22 shows an example of a procedure of a calibration method for a pipeline ADC. As shown in FIG. 22, when the calibration is started, an initial setting is performed in step S11. Here, it is assumed that calibration is performed for an arbitrary stage i (i <N), and measurement is started from the first resistor included in the DAC (k == l). No calibration is performed for the last stage.

In Step S 1 2, at stage i the (M + 1) D AC output voltage having a conversion accuracy of bits set to V _{2 k,} sampling the voltage by sweep rate Tchitokyapa Sita circuit. Step S 13 smell Then, set the output voltage of the DAC to V _{2 k} — i and input it to the switched capacitor circuit.

In Step S 1 4, the output voltage of the switch-capacitor circuit A (i) · - a _{(V 2 k! V 2 k} _) as a result of AZD converted by AD C in the subsequent stage, AD {A (i) - - obtaining _{(V 2 k V 2 k _} 1)}. Here, AD {V} means the value represented by the data obtained by AZD converting the voltage V output to the next stage. ―

In step S 1 5, at stage i the (M + 1) D AC output voltage having a conversion accuracy of bits set to V _{2 k,} sampling the voltage by switch preparative capacity Sita circuit. In step S16, the output voltage of the DAC is set to V2k _{+ 1} and input to the switched capacitor circuit.

In Step S 1 7, switch preparative output voltage A (i) · capacitor circuits - as a result of the A / D conversion _{(V 2 k V 2 k +} 1) of the subsequent stage AD C, AD {A ( i) · (V _{2 k} -V _{2 k + 1} )}.

In step S 1 8, Step S 1 4 and S 1 to 7 results of A / D conversion in, Digitally Le value of the potential difference between two output voltages in _{D AC SUB k = AD {A} (i) · (V 2 _k — V _{2 k} — J} — Calculate AD {A (i) · (V _{2 k} -V _{2 k + 1} )} in the DAC error correction data generation circuit.

In step S 19, the sum of the digital values up to the previous time and the digital value obtained this time are added to obtain the sum S SUB j of the digital values of the potential difference between the two output voltages in the DAC, j = l Ask for ~ k. In step S20, it is determined whether or not all the resistance measurements have been completed. If the measurement of all the resistances has not been completed, in step S21, the setting for measuring the next resistance is made, and the value of k is incremented. After that, the process proceeds to step S12. On the other hand, when the measurement of all the resistances is completed, the process proceeds to step S22 in FIG.

 As shown in FIG. 23, in step S22, from the sum ∑S UBj obtained in step S19 and its ideal value (design value), the stage i and the stage (i The gain error correction data GE (i) between the data and (+1) is obtained by the gain error correction data generation circuit and stored in the gain error correction data memory. In step S23, the calculation of the DAC error correction data is initialized, and k is set to l.

In step S24, a value corresponding to the digital value of the DAC output GE (i) ∑ S UB from the product of the sum of the output voltage steps of the DAC AC SUB j and the data GE (i) for gain error correction. j is calculated in the DAC error correction data generation circuit. - In step S 2 5, and a digital value of digital value GE (i) Σ S UB ₅ and an ideal DAC output of the DAC output, D in the AC error correction data generating circuit, the output D of the AD C at stage i _{When O UT} (i) (k + 1), that is, when DAC output is V _{2 k + 1} , DAC error correction data DE (i, k + 1) is calculated, and DAC error is calculated. The data is stored in the correction data memory.

 In step S26, it is determined whether or not calculation of all correction data has been completed. If calculation of all correction data has not been completed, the process proceeds to step S27, where the settings for calculating the next DAC error correction data are made, and the value of k is incremented. Then, the process proceeds to step S24. On the other hand, when the calculation of all the data for correction is completed, the calibration ends.

Next, a more accurate calibration method will be described with reference to FIGS. 24 and 25. As shown in FIG. 24 setting, after the initial setting was carried out in step S 1 1, in step S 3 1, at stage i the (M + 1) D AC output voltage having a conversion accuracy of bits in V _{2 k} This voltage is sampled by the switched capacitor circuit. In step S32, the output voltage of the DAC is set to V _{2 k} and input to the switched capacitor circuit. .

In step S 3 3, switch-capacitor circuit Me output voltage A (i) · - as a result of AZD converted by AD C of _{(V 2 k V 2 k _} x) stage (i + 1), AD { A (i) · (V _{2 k} _V _{2 k} } is obtained.

In step S34, the output voltage of the DAC is set to V _{2 k} in stage i, and this voltage is sampled by the switched capacitor circuit. In step S35, the output voltage of the DAC is set to V2k _{+ 1} and input to the switched capacitor circuit.

In step S 3 6, switch preparative output voltage A (i) · capacitor circuits - as a result of A / D conversion in the AD C of _{(V 2 k V 2 k +} 1) stage (i + 1), AD obtain {a (i) · (V 2 k -V 2 k + 1)}.

In step S 3 7, Step S 3 3 and the results of the AD conversion in S 36, the digital value of the potential difference between two output voltages in _{DAC S UB l k = AD {} A (i) · (V 2 k - V _{2 k} — ₁ )}-AD {A (i) · (V _{2 k} − V _{2 k + 1} )} is calculated in the DAC error correction data generation circuit.

Next, as shown in FIG. 25, in step S38, the output voltage of the DAC is set to V _{2 k} in stage i, and this voltage is sampled by a switched capacitor circuit. In step S39, the output voltage of the DAC is set to V _{2 k} and input to the switched capacitor circuit. In step S 40, the output voltage A (i) · a switch-capacitor circuit - as a result of A / D conversion in the AD C of (V _{2 k} one V _{2 k)} stage (i + 1), AD { A obtaining a _{- (V 2 k V 2 k} _ x)} (i) ·. In step S41, the output voltage of DAC is set to V2k _{+ 1} in stage i, and this voltage is sampled by a switched capacitor circuit. In Step S 4 2, and set the D AC output voltage V _{2 k,} and inputs the switch-capacitor circuit. .

In Step S 4 3, switch-capacitor circuit of the output voltage A (i) · - as a result of A / D conversion in the ADC _{(V 2 k + 1 V 2} k) stage (i + 1), AD { A (i) · (V _{2 k + 1} -V _{2 k} )} '. In step S 44, the result of AZD transformation in Step S 40 and S 4 3, Digitally Le value of the potential difference between two output voltages in _{DAC S UB 2 k = AD {} A (i) · (V 2 k + 1 — V _{2 k} )} _AD {A (i) · (V _2k — — V _{2 k} )} is calculated in the DAC error correction data generation circuit.

In Step S 4 5, the average value _{S UB k = (SUB 1 k} + S UB 2 k) Z2 of two measurements, calculate Te DAC error correction data generating circuit odor. In step S46, the sum of the average values up to the previous time and the average value obtained this time are added to obtain the sum ∑ SU Bj of the output voltage steps of the DAC for j = 1 to k.

In step S20, it is determined whether or not all the resistance measurements have been completed. The following steps are the same as those shown in FIGS. 22 and 23. According to this calibration method, the calibration error caused by the device variation of the ADC after the next stage is reduced by averaging the results obtained from two measurements with different procedures. be able to. Next, a method of AZD conversion during the calibration operation will be described with reference to FIG.

As shown in FIG. 26, when A / D conversion is started, in step S51, the DAC of stage i to be calibrated is controlled by the calibration control circuit, and the (M + 1) -bit The output voltage V of stage i by amplifying the potential difference between two output voltages in DAC with conversion accuracy. Output as _UT (i) and perform AZD conversion sequentially from stage (i + 1).

In step S52, a desired delay is given to the conversion data D _OUT (i) of each stage by the digital delay circuit 10 shown in FIG. This conversion data D. _UT (i) is output to a DAC error correction circuit 20 for a stage having a calibration function, and is output to a gain error correction circuit 30 for a stage without a calibration function. In step S53, conversion data D is obtained for stage i having a calibration function. _The DAC error correction data DE (i, D _OUT (i)) corresponding to _UT (i) is output from the DAC error correction data memory to the DAC error correction arithmetic circuit 22 of the DAC error correction circuit 20. . This operation is not performed for the stage without calibration function.

In step S54, for the stage i having the calibration function, the DAC error correction arithmetic circuit of the DAC error correction circuit obtains conversion data _D1OUT (i) of the stage in which the DAC error has been corrected, Output to the gain error correction circuit 30. This operation is not performed for the stage without the calibration function.

In step S55, for the stage i having the calibration function, the stage from the stage N to the stage Using the conversion data D 2 _OUT (i + 1) up to (i + 1) and the gain error correction data GE (i) output from the gain error correction data memory, a gain error correction arithmetic circuit Conversion data D3 from stage N to stage (i + 1) with the gain error corrected by correcting the gain error. _UT (i + 1) = GE (i) XD2 _OUT (i + 1) is obtained. This operation is not performed for the stage without calibration function.

In step S56, conversion data D3 from stage N to stage (i + 1) with the gain error corrected for stage i having a calibration function. The converted data D1 at stage i after correcting the DAC error to _UT (i + 1). _UT (i) is added by an adder to obtain conversion data D 2 _OUT (i) = D 1 _ουτ (i) + D 3 _ουτ (i + 1) from stage N to stage i. On the other hand, for stage i without the calibration function, the converted data D2 from stage N to stage (i + 1). _UT (i + 1) and conversion data D at stage i. _UT (i) is added by an adder to obtain conversion data D 2 _OUT (i) = D _OUT (i) + D 2 _OUT (i + 1) from stage N to stage i.

 In step S57, it is determined whether addition of the conversion data has been completed for all stages. If the addition of the converted data has not been completed, the process proceeds to step S55. On the other hand, when the conversion data addition is completed for all stages, the A / D conversion ends.

 Next, a method of AZD conversion during normal operation will be described with reference to FIG. Here, it is assumed that each of stage 1 to stage (N-1) has a calibration function.

When A / D conversion starts, in step S61, the pipeline type Input analog signal V _IN (1) to ADC and start A / D conversion in each stage sequentially. In step S62, the conversion data D _OUT (i) of each stage is given a desired delay by the timing adjustment circuit 10 shown in FIG. 1 and is output to the DAC error correction circuit 20.

In step S63, conversion data D from the DAC error memory for stage i = l ~ (N-1). _The DAC error correction data DE (i, D. _UT (i)) corresponding to _UT (i) is output to the DAC error correction operation circuit 22 of the DAC error correction circuit 20.

In step S64, the conversion data D 1 _OUT of the stage i = l to (N−1) whose DAC error has been corrected by the DAC error correction operation circuit 22 of the DAC error correction circuit 20 _{(i) = D OUT (i} ) -DE seeking _{(i, D. UT (i)} ), and outputs the gain error. correction circuit 3 0.

In step S65, conversion data D2 from stage N to stage (i + 1) in order from the stage on the LSB side. _{By using UT} (i + 1) and gain error correction data GE (i) output from the gain error correction data memory, the gain error is calculated by the gain error correction arithmetic circuit. , obtained from the stage N with the corrected gain error stage (i + 1) to the Hen缘data _{D 3 OUT (i + 1)} = GE (i) XD 2 OUT (i + 1).

In step S66, conversion data D3 from stage N to stage (i + 1) from which the gain error has been corrected. Stage i after correcting the DAC error in _UT (i + 1). The conversion data D1 in step 1. _UT (i) is added by an adder, and the conversion data from stage N to stage i is _D2ουτ (i) = _D1ουτ (i) + _D3ουτ (i + 1) Get.

In step S67, add conversion data for all stages Is determined. If the conversion data addition has not been completed, the process moves to step S65. On the other hand, when the conversion data addition is completed for all stages, the A / D conversion ends. 'Next, a procedure of error correction in the pipeline ADC according to the present embodiment will be described with reference to FIG. FIG. 28 shows the relationship between the analog input signal, the residual signal, and the ADC output.

 As shown in (a) of Fig. 28, when the DAC error and the gain error of the amplifier etc. occur in the pipelined ADC, the gain error is corrected first by removing it. Then, the characteristics as shown in (b) of Fig. 28 are obtained. In the characteristics shown in (b) of Fig. 28, the A / D conversion characteristics show non-linearity due to the DAC error. However, by correcting the DAC error, As shown in c), the non-linearity of the AZD conversion characteristics is corrected, and ideal AZD conversion characteristics can be realized.

 As described above, according to the present invention, in at least one stage of a pipelined ADC, an analog / digital conversion circuit having a conversion accuracy of M bits and a digital node having a conversion accuracy higher than M bits are provided. By using an analog conversion circuit or a plurality of M-bit digital Z-to-analog conversion circuits, the output voltage error of the digital-to-analog conversion circuit and the amplifier, etc., at the relevant stage can be realized with a relatively simple circuit configuration. Can be corrected. Industrial applicability

 INDUSTRIAL APPLICABILITY The present invention can be used in a pipeline type analog Z-to-digital converter and an electronic circuit that convert an analog signal into a digital signal in a plurality of stages.

Claims

 Claims range i. A stage which receives an analog input signal, converts the analog input signal into analog-to-digital data, and outputs converted data and a residual signal.

 A timing adjustment circuit for adjusting the timing by giving a delay of an appropriate number of cycles to each of the conversion data output from the stage;

 A DAC error correction circuit for correcting an output voltage error of digital / analog conversion in the stage;

 A gain error correction circuit for correcting a gain error of the amplifier in the stage;

 Based on the digital output signal output from the gain error correction circuit, an error in the output voltage of digital / analog conversion and a gain error are calculated.

An error correction data generation circuit that supplies respective error correction data to the DAC error correction circuit and the gain error correction circuit;

 A calibration control circuit that outputs a calibration control signal to control the calibration operation and supplies a DAC control signal to the stage;

Analog to digital converter with

 2. The DAC error correction circuit stores a DAC error correction data memory used to correct an error in the output voltage of the digital analog conversion in the stage, and a DAC error correction data memory based on the converted data. 2. The analog-digital converter according to claim 1, further comprising: a DAC error correction arithmetic circuit that outputs conversion data obtained by correcting the error in the output voltage of the digital-to-analog conversion by subtracting the respective data for use.

3. The DAC error correction circuit according to claim 1, wherein the DAC error correction circuit includes a DAC error correction data memory that stores DAC error correction data in a stage. Analog z-digital converter.

 4. The gain error correction circuit includes: a gain error correction data memory for storing gain error correction data for correcting a gain error of the amplifier in the stage; a gain error correction operation circuit; and an adder. An analog / digital converter according to claim 1.

 5. The error correction data generation circuit calculates the error amount of the output voltage of the digital Z analog conversion in the stage, and converts the data for correcting the error of the output voltage of the digital / analog conversion into a DAC. Calculates the DAC error correction data generation circuit output to the error correction circuit and / or the gain error of the amplifier, and generates the gain error correction data to output the data for correcting the gain error to the gain error correction circuit The analog-to-digital converter according to claim 1, comprising a circuit.

 6. The error correction data generation circuit is an error measurement result averaging circuit for averaging the digital output signal, and / or a gain error correction data generation circuit and a correction error output from the DAC error correction data generation circuit. The analog-to-digital converter according to claim 1, further comprising an error correction data generation circuit that averages data.

 7. The DAC error correction circuit includes a multiplexer for disabling digital / analog conversion error correction by a calibration control signal, wherein the multiplexer includes the DAC error correction data memory and the DAC error correction operation. 4. The analog-Z digital converter according to claim 2, which is disposed between circuits.

 8. The analog-to-digital converter according to claim 2, wherein the DAC error correction circuit includes a multiplexer that outputs a digital output signal from a stage as a zero signal by a calibration control signal.

9. The gain error correction circuit is operated by the calibration control signal. The analog Z-digital converter according to claim 4, further comprising a multiplexer for invalidating the gain error correction, wherein the multiplexer is disposed between the gain error correction data memory and the gain error correction operation circuit.

 .

10. The analog-to-digital converter according to claim 4, wherein the error correction in the gain error correction operation circuit is performed by an approximate calculation using a multiplier.

11. The analog-to-digital converter according to claim 4, wherein the error correction in the gain error correction operation circuit is performed by an approximate calculation using a multiplier and an adder.

 12. The calibration control circuit measures the difference between the reference voltage in the analog-to-digital conversion of the stage and the digital-to-analog conversion voltage during non-calibration in the forward and reverse directions. The analog Z-digital converter according to claim 1, further comprising a voltage measuring means for averaging the result.

 13. The analog-to-digital converter according to claim 1, wherein said stages are multistage.

 1 4. The stage is

 An M-bit analog-to-digital converter that outputs conversion data by converting an analog input signal to analog-Z digital;

 A plurality of data used for calibration at the time of calibration is sequentially converted into a plurality of analog signals for calibration with a greater number of conversion bits than M bits, and the analog / digital signals are obtained at the time of non-calibration. A digital-to-analog conversion circuit for converting the output signal of the conversion circuit into an analog signal,

At the time of calibration, the DAC control signal is A first multiplexer that outputs to the conversion circuit, and outputs the output signal of the analog / digital conversion circuit to the digital / analog conversion circuit during non-calibration;

 A second multiplexer that outputs an output signal of the digital-Z analog conversion circuit to the sample-and-hold circuit during calibration and outputs an analog input signal to the sample-and-hold circuit during non-calibration; A sample and hold circuit that samples and holds the output signal;

 A subtracter for subtracting the output signal of the digital / analog conversion circuit from the output signal of the sample-hold circuit;

 An amplifier for amplifying an output signal from the subtractor;

 The analog / digital converter according to claim 1, comprising:

 1 5. The stage is

 An analog / digital conversion circuit that outputs conversion data by converting an analog input signal from analog to digital;

 The first digital / analog conversion that performs digital-to-analog conversion during calibration and outputs the first calibration analog signal, and performs digital / analog conversion of the conversion result of the analog / digital conversion circuit during non-calibration. An analog conversion circuit,

 A second digital / analog conversion circuit for performing digital / analog conversion at the time of calibration and outputting a second calibration analog signal;

Outputs the DAC control signal to the first digital-to-analog converter during calibration, and outputs the output signal of the analog-to-digital converter to the first digital-to-analog converter during non-calibration. A first multiplexer to

 A second multiplexer that outputs an output signal of the second digital / analog conversion circuit to the sample and hold circuit during calibration and outputs an analog input signal to the sample and hold circuit during non-calibration;

 A sample and hold circuit that samples and holds the output signal of the second multiplexer;

 A subtractor for subtracting the output signal of the first digital analog conversion circuit from the output signal of the sample and hold circuit;

 An amplifier for amplifying the output from the subtractor;

The analog / digital converter according to claim 1, comprising:

 16. The analog Z-to-digital converter according to claim 14 or 15, wherein said stage is constituted by a multiplexer, a sample and hold circuit, a subtractor, and a switched capacitor circuit including an amplifier.

 17. The fan according to claim 14, wherein the stage is constituted by a digital Z-analog conversion circuit, a multiplexer, a sample-and-hold circuit, a subtractor, and a switched capacitor circuit including an amplifier. Analog / digital converter.

 18. The analog-to-digital converter according to claim 14, wherein the digital Z-to-analog conversion circuit includes a resistance ladder-type digital / analog conversion circuit. 18.

19. The analog / digital conversion circuit includes a plurality of resistors connected in series, and the resistor is used as a resistor of the digital / analog conversion circuit, and outputs an output signal from the resistor to the analog / digital converter. 19. The reference voltage of the conversion circuit, wherein the reference voltage is used as an analog signal for calibration during calibration. Analog / digital converter as described.

 20. The analog-to-digital converter according to claim 1, wherein each of the analog-Z digital conversion circuit, the digital / analog conversion circuit, and the signal processing circuit has a differential configuration.

2 1. A stage for inputting an analog input signal, converting the analog input signal to analog Z digital, and outputting conversion data and a residual signal;

 A timing adjustment circuit for adjusting the timing by giving a delay of an appropriate number of cycles to each of the conversion data output from the stage;

 A DAC error correction circuit for correcting an error in the output voltage of the digital-to-analog conversion in the stage;

 A gain error correction circuit for correcting an amplifier gain error in the stage;

An analog / digital converter, including

 Based on the digital output signal output from the gain error correction circuit, an output voltage error and a gain error of digital-to-analog conversion are calculated, and the DAC error correction circuit and the gain error correction circuit respectively provide error correction data. Error correction data generating means for supplying

 A calibration control means for outputting a calibration control signal to control the calibration operation and for supplying a DAC control signal to the stage;

An electronic circuit comprising: