CN116961655B - Chopper sampling circuit applied to high-precision ADC - Google Patents
Chopper sampling circuit applied to high-precision ADC Download PDFInfo
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- CN116961655B CN116961655B CN202311219136.7A CN202311219136A CN116961655B CN 116961655 B CN116961655 B CN 116961655B CN 202311219136 A CN202311219136 A CN 202311219136A CN 116961655 B CN116961655 B CN 116961655B
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- 238000005070 sampling Methods 0.000 title claims abstract description 96
- 239000003990 capacitor Substances 0.000 claims description 42
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 claims description 17
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 claims description 16
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 claims description 15
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 claims description 15
- 238000012423 maintenance Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000000342 Monte Carlo simulation Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000000523 sample Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a chopper sampling circuit applied to a high-precision ADC (analog to digital converter), and belongs to the field of analog integrated circuit design. The sampling circuit is an indispensable part of the ADC, and the accuracy of sampling in a high-accuracy ADC directly affects the subsequent processing result. In order to reduce the influence of noise and offset voltage and improve the sampling precision, the invention applies a chopping technology to sampling, designs a chopping sampling circuit which can be applied to a high-precision ADC, uses fewer circuits and switches, reduces the influence of additional circuits and switching noise on signal quality, can effectively reduce offset voltage and realize more accurate sampling.
Description
Technical Field
The invention belongs to the field of analog integrated circuit design, and particularly relates to a chopping sampling circuit applied to a high-precision ADC.
Background
The chopping technique (Chopper Technique) is a design that employs a modem principle to shift low frequency noise and offset to the high frequency part, and then filters the low frequency noise and offset using a low pass filter. Typically used in fully differential op-amps. This has the advantage that offset errors can be significantly eliminated, but certain switching noise is introduced.
In the sampling of a high-precision analog-to-digital converter (ADC), the integrity of a sampled signal is ensured to the greatest extent by using techniques such as a bootstrap sampling circuit and the like due to higher requirements on precision, so that the realization of high precision is ensured. The conventional differential sampling circuit structure is shown in fig. 2, and the sampling circuits of both paths are controlled by a unified clock MCLK. The input signals are INP and INN, the output signals are OUTP and OUTN, and the input signals and the output signals are directly sampled outgoing modes. The oversampling mode is used in the high-precision ADC, so MCLK of the high-precision ADC is generally equal to 1MHz-16MHz. Simulation of the sampling process is shown in fig. 3, and the monte carlo simulation result of the offset voltage is shown in fig. 4.
The input signal INP and the input signal INN are sine waves with the same amplitude and opposite phases, red is a sampling result of the output signal OUTP, and green is a sampling result of the output signal OUTN, so that a conventional non-chopping sampling circuit can be seen, and a sampling function can be realized functionally. However, through Monte Carlo simulation of the offset voltage, the maximum offset voltage of the traditional differential sampling circuit reaches-16.45 mV. The offset voltage value is too large for a high-precision ADC.
Noise and offset voltages present in conventional sampling circuits can cause deviations in the sampled voltage from the sampled analog voltage.
Disclosure of Invention
The chopping technology used by the differential operational amplifier can periodically correct offset voltage and reduce noise, so that very small 1/f noise and nV-level offset voltage are realized, and the characteristics are very suitable for input sampling of the high-precision oversampling ADC. Meanwhile, the high-precision oversampling ADC has a large number of digital filters to generate group delay with a certain size, so the speed is generally not very fast, and the matching degree with the chopping technology is also relatively high.
Therefore, in order to reduce the influence of offset voltage and noise on sampling precision in the sampling process, the invention provides a chopping sampling circuit applied to a high-precision ADC:
the circuit comprises a bootstrap sampling circuit A, a bootstrap sampling circuit B, a bootstrap sampling circuit C and a bootstrap sampling circuit D; the input signals are INP and INN, the output signals are OUTP and OUTN, and the clock signal CLK is an intermittent clock control signal CLK1 and an intermittent clock control signal CLK2;
the input signal INP and the intermittent clock control signal CLK1 are connected to the bootstrap sampling circuit a, the input signal INP and the intermittent clock control signal CLK2 are connected to the bootstrap sampling circuit B, the input signal INN and the intermittent clock control signal CLK2 are connected to the bootstrap sampling circuit C, and the input signal INN and the intermittent clock control signal CLK1 are connected to the bootstrap sampling circuit D; the output ends of the bootstrap sampling circuit A and the bootstrap sampling circuit C output a signal OUTP, and the output ends of the bootstrap sampling circuit B and the bootstrap sampling circuit D output a signal OUTN;
the bootstrap sampling circuit A, the bootstrap sampling circuit B, the bootstrap sampling circuit C and the bootstrap sampling circuit D are the same bootstrap sampling circuit, and the single bootstrap sampling circuit specifically comprises an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6, an NMOS tube M8, an NMOS tube 9, an NMOS tube M10, an NMOS tube M11 and an NMOS tube M12; a PMOS tube M5 and a PMOS tube M7; a capacitor C1, a capacitor C2, and a capacitor C3; and an inverter 1, an inverter 2;
the specific connection mode of the bootstrap sampling circuit is as follows: the gate end of the NMOS tube M1 is connected with the source end of the NMOS tube 2, the drain end is connected with the power supply voltage VDD, and the source end is connected with the other end of the capacitor C1; the gate end of the NMOS tube M2 is connected with the source end of the NMOS tube M1, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor C2; the gate end of the NMOS tube M3 is connected with the gate end of the NMOS tube M2, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor C3; the gate end of the NMOS tube M4 is connected with the other end of the capacitor C2 through the inverter 2, the drain end is connected with the other end of the capacitor C3, and the source end is grounded; the gate end of the PMOS tube M5 is connected with the gate end of the NMOS tube M6, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the NMOS tube M6; the source end of the NMOS tube M6 is connected with the drain end of the NMOS tube M4; the gate end of the PMOS tube M7 is connected with the drain end of the NMOS tube M8, the source end is connected with the source end of the NMOS tube M3, and the drain end is connected with the drain end of the NMOS tube M9; the gate end of the NMOS tube M8 is connected with the gate end of the NMOS tube M11, the drain end is connected with the drain ends of the PMOS tube M5 and the NMOS tube M6, and the source end is connected with the drain end of the NMOS tube M4; the gate end of the NMOS tube M9 is connected with the power supply voltage VDD, and the source end is connected with the drain end of the NMOS tube M10; the gate end of the NMOS tube M10 is connected with the gate end of the NMOS tube M4, the drain end is connected with the gate ends of the NMOS tube M8 and the NMOS tube M11, and the source end is connected with the ground potential; the source end of the NMOS tube M11 is connected with the drain end of the NMOS tube M4, and the drain end is connected with the source end of the NMOS tube M12; the gate end of the NMOS tube M12 is connected with the gate end of the NMOS tube M11, the source end is connected with a corresponding input signal, and the drain end is connected with a corresponding output signal; the corresponding intermittent clock control signals are connected with the gate ends of the PMOS tube M5 and the NMOS tube M6, and are connected with the gate ends of the NMOS tube M4 and the NMOS tube M10 and one end of the capacitor C1 through the inverter 1.
The invention uses only the clock as a main tool for chopping and merging signals, uses fewer circuits and switches, and reduces the influence of additional circuits and switching noise on the signal quality; and offset voltage can be effectively reduced, and more accurate sampling is realized.
Drawings
FIG. 1 is a block diagram of a chopper sampling circuit of the present invention;
FIG. 2 is a schematic diagram of a conventional differential sampling circuit;
FIG. 3 is a simulation diagram of a sampling result of a conventional differential sampling circuit;
FIG. 4 is a schematic diagram of a sampling offset voltage of a conventional differential sampling circuit;
FIG. 5 is a timing diagram of conventional differential sampling and chopped sampling of the present invention;
FIG. 6 is a simulation diagram of the sampling result of the chopper sampling circuit;
fig. 7 is a schematic diagram of a chopper sampling circuit sampling offset voltage.
Detailed Description
The embodiments will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the chopper sampling circuit of the present embodiment is configured such that an intermittent clock control signal CLK1 is connected to gate ends of a PMOS transistor Ma5, an NMOS transistor Ma6, a PMOS transistor Md5, and an NMOS transistor Md6, and is connected to gate ends of an NMOS transistor Ma4, an NMOS transistor Ma10, and one end of a capacitor Ca1 through an inverter a1, and is connected to gate ends of an NMOS transistor Md4, an NMOS transistor Md10, and one end of a capacitor Cd1 through an inverter d 1; the intermittent clock control signal CLK2 is connected with the gate ends of the PMOS tube Mb5 and the NMOS tube Mb6, the gate ends of the PMOS tube Mc5 and the NMOS tube Mc6, the gate ends of the NMOS tube Mb4 and the NMOS tube Mb10 and one end of the capacitor Cb1 through the inverter b1, and the gate ends of the NMOS tube Mc4 and the NMOS tube Mc10 and one end of the capacitor Cc1 through the inverter c 1; the input signal INP is connected with the source ends of the NMOS tube Ma12 and the NMOS tube Mb12, and the input signal INN is connected with the source ends of the NMOS tube Mc12 and the NMOS tube Md 12; the output signal OUTP is connected with the drain ends of the NMOS tube Ma12 and the NMOS tube Mc12, and OUTN is connected with the drain ends of the NMOS tube Mb12 and the NMOS tube Md 12;
the gate end of the NMOS tube Ma1 is connected with the source end of the NMOS tube Ma2, the drain end is connected with the power supply voltage VDD, and the source end is connected with the other end of the capacitor Ca 1; the gate end of the NMOS tube Ma2 is connected with the source end of the NMOS tube Ma1, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Ca 2; the gate end of the NMOS tube Ma3 is connected with the gate end of the NMOS tube Ma2, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Ca 3; the gate end of the NMOS tube Ma4 is connected with the other end of the capacitor Ca2 through the inverter a2, the drain end is connected with the other end of the capacitor Ca3, and the source end is grounded; the gate end of the PMOS tube Ma5 is connected with the gate end of the NMOS tube Ma6, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the NMOS tube Ma 6; the source end of the NMOS tube Ma6 is connected with the drain end of the NMOS tube Ma 4; the gate end of the PMOS tube Ma7 is connected with the drain end of the NMOS tube Ma8, the source end is connected with the source end of the NMOS tube Ma3, and the drain end is connected with the drain end of the NMOS tube Ma 9; the gate end of the NMOS tube Ma8 is connected with the gate end of the NMOS tube Ma11, the drain end is connected with the drain ends of the PMOS tube Ma5 and the NMOS tube Ma6, and the source end is connected with the drain end of the NMOS tube Ma 4; the gate end of the NMOS tube Ma9 is connected with the power supply voltage VDD, and the source end is connected with the drain end of the NMOS tube Ma 10; the gate end of the NMOS tube Ma10 is connected with the gate end of the NMOS tube Ma4, the drain end is connected with the gate ends of the NMOS tube Ma8 and the NMOS tube Ma11, and the source end is connected with the ground potential; the source end of the NMOS tube Ma11 is connected with the drain end of the NMOS tube Ma4, and the drain end is connected with the source end of the NMOS tube Ma 12; the gate end of the NMOS tube Ma12 is connected with the gate end of the NMOS tube Ma11, the source end is connected with the input signal INP, and the drain end is connected with the output signal OUTP;
the gate end of the NMOS tube Mb1 is connected with the source end of the NMOS tube Mb2, the drain end is connected with the power supply voltage VDD, and the source end is connected with the other end of the capacitor Cb 1; the gate end of the NMOS tube Mb2 is connected with the source end of the NMOS tube Mb1, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Cb 2; the gate end of the NMOS tube Mb3 is connected with the gate end of the NMOS tube Mb2, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Cb 3; the gate end of the NMOS tube Mb4 is connected with the other end of the capacitor Cb2 through the inverter b2, the drain end is connected with the other end of the capacitor Cb3, and the source end is grounded; the gate end of the PMOS tube Mb5 is connected with the gate end of the NMOS tube Mb6, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the NMOS tube Mb 6; the source end of the NMOS tube Mb6 is connected with the drain end of the NMOS tube Mb 4; the gate end of the PMOS tube Mb7 is connected with the drain end of the NMOS tube Mb8, the source end is connected with the source end of the NMOS tube Mb3, and the drain end is connected with the drain end of the NMOS tube Mb 9; the gate end of the NMOS tube Mb8 is connected with the gate end of the NMOS tube Mb11, the drain end is connected with the drain ends of the PMOS tube Mb5 and the NMOS tube Mb6, and the source end is connected with the drain end of the NMOS tube Mb 4; the gate end of the NMOS tube Mb9 is connected with the power supply voltage VDD, and the source end is connected with the drain end of the NMOS tube Mb 10; the gate end of the NMOS tube Mb10 is connected with the gate end of the NMOS tube Mb4, the drain end is connected with the gate ends of the NMOS tube Mb8 and the NMOS tube Mb11, and the source end is connected with the ground potential; the source end of the NMOS tube Mb11 is connected with the drain end of the NMOS tube Mb4, and the drain end is connected with the source end of the NMOS tube Mb 12; the gate end of the NMOS tube Mb12 is connected with the gate end of the NMOS tube Mb11, the source end is connected with the input signal INP, and the drain end is connected with the output signal OUTN;
the gate end of the NMOS tube Mc1 is connected with the source end of the NMOS tube Mc2, the drain end is connected with the power supply voltage VDD, and the source end is connected with the other end of the capacitor Cc 1; the gate end of the NMOS tube Mc2 is connected with the source end of the NMOS tube Mc1, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Cc 2; the gate end of the NMOS tube Mc3 is connected with the gate end of the NMOS tube Mc2, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Cc 3; the gate end of the NMOS tube Mc4 is connected with the other end of the capacitor Cc2 through the inverter c2, the drain end is connected with the other end of the capacitor Cc3, and the source end is grounded; the gate end of the PMOS tube Mc5 is connected with the gate end of the NMOS tube Mc6, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the NMOS tube Mc 6; the source end of the NMOS tube Mc6 is connected with the drain end of the NMOS tube Mc 4; the gate end of the PMOS tube Mc7 is connected with the drain end of the NMOS tube Mc8, the source end is connected with the source end of the NMOS tube Mc3, and the drain end is connected with the drain end of the NMOS tube Mc 9; the gate end of the NMOS tube Mc8 is connected with the gate end of the NMOS tube Mc11, the drain end is connected with the drain ends of the PMOS tube Mc5 and the NMOS tube Mc6, and the source end is connected with the drain end of the NMOS tube Mc 4; the gate end of the NMOS tube Mc9 is connected with the power supply voltage VDD, and the source end is connected with the drain end of the NMOS tube Mc 10; the gate end of the NMOS tube Mc10 is connected with the gate end of the NMOS tube Mc4, the drain end is connected with the gate ends of the NMOS tube Mc8 and the NMOS tube Mc11, and the source end is connected with the ground potential; the source end of the NMOS tube Mc11 is connected with the drain end of the NMOS tube Mc4, and the drain end is connected with the source end of the NMOS tube Mc 12; the gate end of the NMOS tube Mc12 is connected with the gate end of the NMOS tube Mc11, the source end is connected with the input signal INN, and the drain end is connected with the output signal OUTP;
the gate end of the NMOS tube Md1 is connected with the source end of the NMOS tube Md2, the drain end is connected with the power supply voltage VDD, and the source end is connected with the other end of the capacitor Cd 1; the gate end of the NMOS tube Md2 is connected with the source end of the NMOS tube Md1, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Cd 2; the gate end of the NMOS tube Md3 is connected with the gate end of the NMOS tube Md2, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor Cd 3; the gate end of the NMOS tube Md4 is connected with the other end of the capacitor Cd2 through the inverter d2, the drain end is connected with the other end of the capacitor Cd3, and the source end is grounded; the gate end of the PMOS tube Md5 is connected with the gate end of the NMOS tube Md6, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the NMOS tube Md 6; the source end of the NMOS tube Md6 is connected with the drain end of the NMOS tube Md 4; the gate end of the PMOS tube Md7 is connected with the drain end of the NMOS tube Md8, the source end is connected with the source end of the NMOS tube Md3, and the drain end is connected with the drain end of the NMOS tube Md 9; the gate end of the NMOS tube Md8 is connected with the gate end of the NMOS tube Md11, the drain end is connected with the drain ends of the PMOS tube Md5 and the NMOS tube Md6, and the source end is connected with the drain end of the NMOS tube Md 4; the gate end of the NMOS tube Md9 is connected with the power supply voltage VDD, and the source end is connected with the drain end of the NMOS tube Md 10; the gate end of the NMOS tube Md10 is connected with the gate end of the NMOS tube Md4, the drain end is connected with the gate ends of the NMOS tube Md8 and the NMOS tube Md11, and the source end is connected with the ground potential; the source end of the NMOS tube Md11 is connected with the drain end of the NMOS tube Md4, and the drain end is connected with the source end of the NMOS tube Md 12; the gate end of the NMOS tube Md12 is connected with the gate end of the NMOS tube Md11, the source end is connected with the input signal INN, and the drain end is connected with the output signal OUTN.
When the intermittent clock control signal CLK1 is at a high level, the Ma12 and the Md12 are conducted, and at the moment, the output signal OUTP is synchronous with the input signal INP, and the output signal OUTN is synchronous with the input signal INN; the intermittent clock control signals CLK1 are turned off at Ma12 and Md12 when low, and the output signals OUTP and OUTN hold the last sampled voltages for the hold period, which is not changed with the input signal. When the intermittent clock control signal CLK2 is at a high level, mb12 and Mc12 are conducted, and at the moment, the output signal OUTP is synchronous with the input signal INN, and the output signal OUTN is synchronous with the input signal INP; when the intermittent clock control signal CLK2 is at a low level, the Mb12 and the Mc12 are turned off, and at this time, the output signal OUTP and the output signal OUTN hold the last sampled voltage, which is not changed with the input signal, for the hold period.
In contrast to the conventional sampling circuit, the clock control signal no longer employs a continuous clock, becoming an intermittent clock, as shown in fig. 5. Because if the continuous signal is reused, the signal samples will be cross-overlapped, corrupting the original signal. The signal must be chopped and then synthesized so the signal is sampled using an intermittent clock. MCLK shown in fig. 5 is a single continuous clock used for conventional sampling. The intermittent clock control signal CLK1 and the intermittent clock control signal CLK2 are intermittent clocks used in the chopper sampling circuit of the present invention. The need to generate such a clock in the system design necessitates the introduction of a clock divider system to generate a second lower frequency clock, which in turn generates the intermittent clock control signal CLK1 and the intermittent clock control signal CLK2 via combinational logic. In particular, due to the limitation of the oversampling rate of the high-precision oversampling ADC, the clock maintenance periods of the intermittent clock control signal CLK1 and the intermittent clock control signal CLK2 used herein may be 64 MCLK clock periods or 32,128 clock periods. In an oversampling ADC the oversampling rate OSR would be set to 32,64,128, etc., with higher oversampling rates resulting in more performance improvement but also in slower sampling rates.
In combination with the above clock signals, it is assumed that the intermittent clock control signal CLK1 is preferentially used for sampling the signal, the output signal OUTP is used for sampling the input signal INP, the output signal OUTN is used for sampling the input signal INN, and after 64 times of sampling, the intermittent clock control signal CLK1 is turned off and the intermittent clock control signal CLK2 is turned on. At this time, the output signal OUTP samples the input signal INN, the output signal OUTN samples the input signal INP, the intermittent clock control signal CLK2 is turned off after sampling for 64 times again, and the intermittent clock control signal CLK1 works and sequentially circulates to realize final sampling. The sampled signal is fully automatically combined onto the output signal OUTP and the output signal OUTN without requiring additional adder circuitry. Clock is used as the primary tool for signal chopping and combining. Fewer circuits and switches are used, reducing the impact of additional circuits and switching noise on signal quality.
The simulated waveforms of the present invention are shown in fig. 6, where dark and light signals are seen to be separated by a gap and combined. The sampling of the signal achieves complete chopper sampling.
The offset voltage of the chopper sampling circuit is subjected to Monte Carlo simulation, and as shown in a result of fig. 7, the maximum offset voltage is 126.45uV after chopper sampling is used, and compared with the maximum offset voltage which is reduced by more than 100 times without chopper sampling, the offset voltage is effectively reduced, and more accurate sampling is realized.
Claims (3)
1. The chopper sampling circuit is characterized by comprising a bootstrap sampling circuit A, a bootstrap sampling circuit B, a bootstrap sampling circuit C and a bootstrap sampling circuit D; the input signals are INP and INN, the output signals are OUTP and OUTN, and the clock signals are an intermittent clock control signal CLK1 and an intermittent clock control signal CLK2;
the input signal INP and the intermittent clock control signal CLK1 are connected to the bootstrap sampling circuit a, the input signal INP and the intermittent clock control signal CLK2 are connected to the bootstrap sampling circuit B, the input signal INN and the intermittent clock control signal CLK2 are connected to the bootstrap sampling circuit C, and the input signal INN and the intermittent clock control signal CLK1 are connected to the bootstrap sampling circuit D; the output ends of the bootstrap sampling circuit A and the bootstrap sampling circuit C output a signal OUTP, and the output ends of the bootstrap sampling circuit B and the bootstrap sampling circuit D output a signal OUTN.
2. The chopper sampling circuit applied to the high-precision ADC according to claim 1, wherein the bootstrap sampling circuit A, the bootstrap sampling circuit B, the bootstrap sampling circuit C and the bootstrap sampling circuit D are the same bootstrap sampling circuit, and the single bootstrap sampling circuit specifically comprises an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6, an NMOS tube M8, an NMOS tube 9, an NMOS tube M10, an NMOS tube M11 and an NMOS tube M12; a PMOS tube M5 and a PMOS tube M7; a capacitor C1, a capacitor C2, and a capacitor C3; and an inverter 1, an inverter 2;
the specific connection mode of the bootstrap sampling circuit is as follows: the gate end of the NMOS tube M1 is connected with the source end of the NMOS tube M2, the drain end is connected with the power supply voltage VDD, and the source end is connected with the other end of the capacitor C1; the gate end of the NMOS tube M2 is connected with the source end of the NMOS tube M1, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor C2; the gate end of the NMOS tube M3 is connected with the gate end of the NMOS tube M2, the drain end is connected with the power supply voltage VDD, and the source end is connected with one end of the capacitor C3; the gate end of the NMOS tube M4 is connected with the other end of the capacitor C2 through the inverter 2, the drain end is connected with the other end of the capacitor C3, and the source end is grounded; the gate end of the PMOS tube M5 is connected with the gate end of the NMOS tube M6, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the NMOS tube M6; the source end of the NMOS tube M6 is connected with the drain end of the NMOS tube M4; the gate end of the PMOS tube M7 is connected with the drain end of the NMOS tube M8, the source end is connected with the source end of the NMOS tube M3, and the drain end is connected with the drain end of the NMOS tube M9; the gate end of the NMOS tube M8 is connected with the gate end of the NMOS tube M11, the drain end is connected with the drain ends of the PMOS tube M5 and the NMOS tube M6, and the source end is connected with the drain end of the NMOS tube M4; the gate end of the NMOS tube M9 is connected with the power supply voltage VDD, and the source end is connected with the drain end of the NMOS tube M10; the gate end of the NMOS tube M10 is connected with the gate end of the NMOS tube M4, the drain end is connected with the gate ends of the NMOS tube M8 and the NMOS tube M11, and the source end is connected with the ground potential; the source end of the NMOS tube M11 is connected with the drain end of the NMOS tube M4, and the drain end is connected with the source end of the NMOS tube M12; the gate end of the NMOS tube M12 is connected with the gate end of the NMOS tube M11, the source end is connected with a corresponding input signal, and the drain end is connected with a corresponding output signal; the corresponding intermittent clock control signals are connected with the gate ends of the PMOS tube M5 and the NMOS tube M6, and are connected with the gate ends of the NMOS tube M4 and the NMOS tube M10 and one end of the capacitor C1 through the inverter 1.
3. A chopper sampling circuit for a high-precision ADC as recited in claim 2, wherein the intermittent clock control signal CLK1 and the intermittent clock control signal CLK2 have a clock maintenance period of 32,64 or 128 clock cycles.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311219136.7A CN116961655B (en) | 2023-09-21 | 2023-09-21 | Chopper sampling circuit applied to high-precision ADC |
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| CN202311219136.7A CN116961655B (en) | 2023-09-21 | 2023-09-21 | Chopper sampling circuit applied to high-precision ADC |
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| CN116961655A CN116961655A (en) | 2023-10-27 |
| CN116961655B true CN116961655B (en) | 2023-12-08 |
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Citations (8)
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| CN116232331A (en) * | 2023-05-08 | 2023-06-06 | 中山大学 | Dynamic error elimination integrator applied to high-precision Sigma-Delta ADC |
| CN116488655A (en) * | 2023-05-08 | 2023-07-25 | 电子科技大学 | Sampling switch circuit suitable for charge redistribution type DAC |
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| US10163521B2 (en) * | 2016-10-11 | 2018-12-25 | Microchip Technology Incorporated | High voltage bootstrap sampling circuit |
| US10608654B2 (en) * | 2017-10-27 | 2020-03-31 | Analog Devices, Inc. | Track and hold circuits for high speed and interleaved ADCS |
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| CN103023469A (en) * | 2011-09-23 | 2013-04-03 | 国民技术股份有限公司 | Grid voltage bootstrap switching circuit |
| WO2018036475A1 (en) * | 2016-08-26 | 2018-03-01 | 无锡华润上华科技有限公司 | Clock voltage step-up circuit |
| US10833691B1 (en) * | 2019-11-26 | 2020-11-10 | Bae Systems Information And Electronic Systems Integration Inc. | Signal chopping switch circuit with shared bootstrap capacitor |
| CN111614356A (en) * | 2020-04-22 | 2020-09-01 | 北方工业大学 | Grid voltage bootstrap sampling circuit |
| WO2022032987A1 (en) * | 2020-08-10 | 2022-02-17 | 中国电子科技集团公司第二十四研究所 | Follow-hold switch circuit |
| CN114374388A (en) * | 2022-01-21 | 2022-04-19 | 芯聚威科技(成都)有限公司 | Two-step-established bootstrap sampling switch circuit and integrated circuit |
| CN116232331A (en) * | 2023-05-08 | 2023-06-06 | 中山大学 | Dynamic error elimination integrator applied to high-precision Sigma-Delta ADC |
| CN116488655A (en) * | 2023-05-08 | 2023-07-25 | 电子科技大学 | Sampling switch circuit suitable for charge redistribution type DAC |
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