CN115314057B - Analog baseband circuit based on inverter technology - Google Patents
Analog baseband circuit based on inverter technology Download PDFInfo
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
- H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention discloses an analog baseband circuit based on an inverter technology, which comprises an analog-to-digital converter and a controllable gain amplifier fused with at least one low-pass filter, wherein the controllable gain amplifier fused with the at least one low-pass filter is connected between the input end of the analog baseband circuit and the input end of the analog-to-digital converter, the output end of the analog-to-digital converter corresponds to the output end of the analog baseband circuit, and all operational amplifiers adopted in the controllable gain amplifier fused with the at least one low-pass filter and delay units in the analog-to-digital converter respectively adopt an inverter structure. The invention solves the problem that the existing analog baseband circuit occupies higher power consumption when part of the analog baseband circuit processes broadband signals.
Description
Technical Field
The invention relates to the technical field of analog baseband circuits, in particular to an analog baseband circuit based on a phase inverter technology.
Background
Ultra Wideband (UWB) technology is increasingly being used in the fields of ranging and indoor positioning by virtue of its high positioning accuracy and safety. The bandwidth of data transmission of the technology is larger than or equal to 500MHz, a receiver circuit structure with enough bandwidth processing capacity needs to be selected, the zero intermediate frequency receiver scheme is more and more widely adopted due to the characteristics of large bandwidth and easiness in integration, and the circuit also has the capacity of low power consumption as the technology is more and more popularized on wearable equipment powered by a battery.
The conventional analog Baseband circuit structure applied in the wideband zero-if receiver system is shown in fig. 1, and comprises an LPF (low pass filter circuit), a PGA (controllable gain amplifier circuit), a DCOC (direct current cancellation circuit), and a SAR-ADC (successive approximation analog-to-digital converter circuit), where an input SfM (Signal from Mixer) of the analog Baseband circuit sequentially passes through the LPF (low pass filter circuit), the PGA (controllable gain amplifier circuit), and the SAR-ADC (successive approximation analog-to-digital converter circuit) and then goes to an output StB (Signal to Baseband), and the output outputs go to Baseband, and the DCOC (direct current cancellation circuit) is connected in parallel to an input end and an output end of the PGA (controllable gain amplifier circuit). Because the signal bandwidth required by the system is large, the LPF and the PGA of the traditional structure respectively need to occupy higher power consumption to realize a gain bandwidth level (GBW) with GHz level; in addition, in order to enable the SAR-ADC to operate in GHz level, the sampling rate of the SAR-ADC is often increased by using, for example, clock interleaving or different comparator layout techniques inside the SAR-ADC circuit, which not only results in the loss of the original low power consumption advantage of the SAR-ADC, but also increases the complexity and area of the circuit.
The above background disclosure is only for the purpose of assisting understanding of the concept and technical solution of the present invention and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed at the filing date of the present patent application.
Disclosure of Invention
The invention provides an analog baseband circuit based on an inverter technology, which aims to solve the problem that the existing analog baseband circuit occupies higher power consumption when part of the existing analog baseband circuit processes broadband signals.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention discloses an analog baseband circuit based on an inverter technology, including an analog-to-digital converter, and a controllable gain amplifier fused with at least one low-pass filter, where the controllable gain amplifier fused with at least one low-pass filter is connected between an input end of the analog baseband circuit and an input end of the analog-to-digital converter, an output end of the analog-to-digital converter corresponds to an output end of the analog baseband circuit, and all operational amplifiers used in the controllable gain amplifier fused with at least one low-pass filter and delay units in the analog-to-digital converter respectively adopt an inverter structure.
Preferably, all operational amplifiers used in the controllable gain amplifier incorporating at least one low-pass filter adopt a single-stage inverter structure of a common-mode feedback type.
Preferably, the common-mode feedback type single-stage inverter structure includes first to second PMOS transistors, first to third NMOS transistors, and an operational amplifier module, wherein gates of the first PMOS transistor and the first NMOS transistor are respectively connected to a first voltage input terminal, gates of the second PMOS transistor and the second NMOS transistor are respectively connected to a second voltage input terminal, drains of the first PMOS transistor and the first NMOS transistor are respectively connected to a first voltage output terminal, drains of the second PMOS transistor and the second NMOS transistor are respectively connected to a second voltage output terminal, sources of the first PMOS transistor and the second PMOS transistor are respectively connected to a current source, sources of the first NMOS transistor and the second NMOS transistor are respectively connected to a drain of the third NMOS transistor, a source of the third NMOS transistor is grounded, the first voltage output terminal and the second voltage output terminal are respectively connected to two input terminals of the operational amplifier module, and an output terminal of the operational amplifier module is connected to a gate of the third NMOS transistor.
Preferably, the analog-to-digital converter adopts an analog-to-digital converter based on a time-to-digital converter.
Preferably, the analog-to-digital converter includes a sampler, a voltage-to-time converter and a time-to-digital conversion module, wherein the input end of the sampler inputs a signal and a clock, the sampler samples the input signal according to the input clock and outputs the sampled signal to the voltage-to-time converter, the voltage-to-time converter converts the voltage domain-based signal into a time domain-based signal and outputs the time domain-based signal to the time-to-digital conversion module, and the time-to-digital conversion module converts the time domain-based signal into a corresponding digital signal and outputs the digital signal.
Preferably, the time-to-digital conversion module includes a signal summing unit、2p(2 n -1) delay units and 2 n A stage D flip-flop, wherein each of the delay units respectively adopts an inverter structure, 2p (2) n -1) said delay units are sequentially connected in series at the start output terminal of the voltage-time converter, the signal input terminal of the D flip-flop of level 0 is connected at the start output terminal of the voltage-time converter, 1 st to 2 nd n -the signal input ends of the 1-stage D flip-flops are respectively connected to the output ends of the delay units, 2p delay units are connected between the signal input ends of every two adjacent stages of D flip-flops, the clock input end of each stage of D flip-flop is respectively connected to the termination output end of the voltage-time converter, the clear end of each stage of D flip-flop is respectively connected to the clear output end of the voltage-time converter, the signal output end of each stage of D flip-flop is respectively connected to the input end of the signal summing unit, and the signal summing unit is used for summing 2 stages of D flip-flops n And processing the n-bit digital signal output by the D trigger to generate an output signal, wherein n and p are positive integers respectively.
Preferably, the time-to-digital conversion module includes a signal summing unit, 2 (2 q-1) (2) n -1) delay units and 2 n The level D flip-flop comprises delay units, wherein each delay unit adopts an inverter structure, (2 q-1) × n delay units are sequentially connected in series with a start output end of a voltage-time converter to form a first delay unit path, (2 q-1) × n delay units are sequentially connected in series with a reverse start output end of the voltage-time converter to form a second delay unit path, and a signal input end and a reverse signal input end of a level 0D flip-flop are respectively connected with the start output end and the reverse start output end of the voltage-time converter, wherein the levels 1, 3, 8230, 2 n The signal input ends of the D flip-flops of the 1 level are respectively connected with the output ends of the delay units on the path of the second delay unit, 1 st, 3 rd, 8230, 2 nd n The inverted signal input terminals of the D flip-flops in the 1-stage are respectively connected with the output terminals of the delay units on the first delay unit path, 2 nd, 4 th, 8230 \ 8230;, 2 nd n -2 stages of said D flip-flops having their signal inputs respectively connected to said first delay cell pathDelay unit outputs, 2 nd, 4 th, 823060 th, 8230th, 2 nd n -the reverse signal input ends of the 2 stages of D flip-flops are respectively connected to the output ends of the delay units on the second delay unit path, and 2q-1 delay units are connected to the first delay unit path between every two adjacent stages of D flip-flops, 2q-1 delay units are connected to the second delay unit path between every two adjacent stages of D flip-flops, the clock input ends of the respective stages of D flip-flops are respectively connected to the termination output end of the voltage-time converter, the clear ends of the respective stages of D flip-flops are respectively connected to the clear output end of the voltage-time converter, the signal output ends of the respective stages of D flip-flops are respectively connected to the input end of the signal summing unit, and the signal summing unit is configured to connect 2 stages of D flip-flops to the input end of the signal summing unit n And processing the n-bit digital signal output by the D trigger to generate an output signal, wherein n and q are positive integers respectively.
Preferably, the low-pass filter includes an operational amplifier, two input resistors, two feedback resistors, and two adjustable circuit broadband capacitors, two input ends of the operational amplifier are respectively connected to one of the input resistors, and each of the feedback resistors and each of the adjustable circuit broadband capacitors are respectively connected in parallel between an input end and an output end of the operational amplifier.
Preferably, the analog baseband circuit further comprises a dc cancellation circuit, and two ends of the dc cancellation circuit are connected between the input end of the analog baseband circuit and the output end of the controllable gain amplifier incorporating the at least one low-pass filter.
Preferably, the dc cancellation circuit includes a gain amplification module, two first adjustable resistors, two second adjustable resistors, and two first capacitors, wherein the first ends of the first adjustable resistors are respectively connected to two output ends of the controllable gain amplifier integrated with at least one low-pass filter, the second ends of the first adjustable resistors are respectively connected to two input ends of the gain amplification module, the two output ends of the gain amplification module are respectively connected to the first ends of the second adjustable resistors, the second ends of the second adjustable resistors are respectively connected to two input ends of the analog baseband circuit, and the first ends of the first capacitors are respectively connected to the second ends of the first adjustable resistors, and the second ends of the first capacitors are respectively connected to ground.
Preferably, the controllable gain amplifier fusing at least one low-pass filter comprises a controllable gain amplifier and at least one low-pass filter, the at least one low-pass filter is connected between the input end of the analog baseband circuit and the input end of the controllable gain amplifier in series, the output end of the controllable gain amplifier is connected with the input end of the analog-to-digital converter, wherein the controllable gain amplifier and the at least one low-pass filter are made into a single design, so that the at least one low-pass filter and the controllable gain amplifier are fused together and have at least one-order low-pass filtering and gain-adjustable functions; not only is enough out-of-band rejection capability realized, but also enough gain adjustment range and adjustment precision are possessed.
In a second aspect, the invention discloses a broadband low-power consumption analog baseband circuit suitable for operating below a 1V voltage domain, which adopts the analog baseband circuit of the first aspect.
In a third aspect, the present invention discloses an analog baseband circuit suitable for being applied in an ultra-wideband system, which employs the analog baseband circuit of the first aspect.
Compared with the prior art, the invention has the beneficial effects that: according to the analog baseband circuit based on the inverter technology, all operational amplifiers adopted in the controllable gain amplifier fused with at least one low-pass filter and the delay units in the analog-to-digital converter respectively adopt the inverter structure, so that the analog baseband circuit can give consideration to high speed and low power consumption.
In a further scheme, the analog-to-digital converter adopts an analog-to-digital converter based on a time-to-digital converter, and further, a delay unit of a main body part of the analog-to-digital converter adopts a digital logic inverter, so that the unit power consumption of the analog-to-digital converter at the working speed under GHz frequency is the lowest, the area of the analog-to-digital converter is the smallest, and the conversion process does not need obvious parameter change; and further unify with low-pass filter and controllable gain amplifier and adopt the single-stage inverter structure, make the whole analog baseband circuit be the design structure based on inverter technology, make it not only possess the advantage that the speed is high, stability is good, and also be suitable for and work under the voltage domain less than 1V, therefore its power consumption has reduced apparently compared with the traditional structure, can not increase the extra area at the same time, very suitable for using in the zero intermediate frequency receiver of broadband, such as the Ultra Wide Band (UWB) system that is more and more widely used at present.
Drawings
Fig. 1 is a schematic diagram of an analog baseband circuit structure applied in a broadband zero intermediate frequency receiver system in a conventional manner;
FIG. 2 is a schematic diagram of an analog baseband circuit based on inverter technology according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of a common mode feedback type single stage inverter configuration according to a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a time-to-digital converter-based analog-to-digital converter with a delay unit connected by a single-sided even inverter according to a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of the structure of a time-to-digital converter based analog-to-digital converter with a delay unit connected by differential odd inverters according to a preferred embodiment of the present invention;
fig. 6 is a schematic structural diagram of an analog baseband circuit according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary in nature and is in no way intended to limit the scope of the invention or its applications.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element. In addition, the connection may be for either a fixed or circuit/signal communication role.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.
As shown in fig. 2, a preferred embodiment of the present invention discloses an analog Baseband circuit based on inverter technology, comprising a controllable gain amplifier fusing at least one low pass filter, a dc cancellation circuit DCOC, and a time-to-digital converter based analog-to-digital converter TDC-ADC, wherein the controllable gain amplifier fusing at least one low pass filter comprises at least one low pass filter (LPF 1, \8230; \ 8230; LPFm) and a controllable gain amplifier PGA, at least one low pass filter (LPF 1, \ 8230; \ LPFm, LPFm) is connected in series between an input terminal SfM (Signal from Mixer) of the analog Baseband circuit and an input terminal of the controllable gain amplifier PGA, both ends of the dc cancellation circuit DCOC are connected between the input terminal of the analog Baseband circuit and an output terminal of the controllable gain amplifier PGA, the analog-to-digital converter TDC-ADC based on the time-to-digital converter is connected between the output end of the controllable gain amplifier PGA and the output end StB (Signal to Baseband, the output end outputs signals to Baseband), and at least one low-pass filter (LPF 1, \8230 \ 8230;, LPFm) and the operational amplifier in the controllable gain amplifier PGA and the delay unit in the analog-to-digital converter TDC-ADC based on the time-to-digital converter respectively adopt inverter structures, so that the at least one low-pass filter (LPF 1, \8230;, LPFm), the controllable gain amplifier PGA, the direct current eliminating circuit DCOC and the analog-to-digital converter TDC-ADC based on the time-to-digital converter jointly form a broadband analog Baseband circuit structure which gives consideration to high speed and low power consumption.
Compared with the common low-pass filter LPF and the controllable gain amplifier PGA which are separately designed and then cascaded in the prior art, the low-pass filter LPF is used for filtering, and the controllable gain amplifier PGA is used for adjusting the gain, in the scheme, at least one low-pass filter (LPF 1, \8230 \ 8230;, LPFm) and the operational amplifier in the controllable gain amplifier PGA both adopt a common-mode feedback single-STAGE inverter structure (1-STAGE INVAMP), so that at least one low-pass filter (LPF 1, \8230;, LPFm) is fused with the controllable gain amplifier PGA to form a single design (two independent circuits are fused together), the controllable gain amplifier PGA has the effects of multi-STAGE low-pass filtering and gain adjustment, and not only has enough out-band rejection capability, but also has enough gain adjustment range and adjustment precision, and also saves area and power consumption.
Specifically, the common-mode feedback type single-stage inverter structure is shown in fig. 3, and includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a first NMOS transistor Mn1, a second NMOS transistor Mn2, a third NMOS transistor Mn3, and an operational amplifier module Amp, wherein gates of the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are respectively connected to a first voltage input terminal Vinq, gates of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 are respectively connected to a second voltage input terminal Vinm, drains of the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are respectively connected to a first voltage output terminal Voutm, drains of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 are respectively connected to a second voltage output terminal Voutq, sources of the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are respectively connected to a current source (after managing a voltage current source Id shown in fig. 3, sources of the first PMOS transistor Mp1 and the second NMOS transistor Mp2 are respectively connected to a current source), sources of the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are respectively connected to a second voltage output terminal Voutm, drains of the second PMOS transistor Mn2, and a third NMOS transistor Mn3 are respectively connected to a gate of the operational amplifier module Mn, and a third NMOS transistor Mn. In the common-mode feedback type single-stage phase inverter structure, a first PMOS tube Mp1 and a first NMOS tube Mn1 form a single-stage phase inverter, a second PMOS tube Mp2 and a second NMOS tube Mn2 form another single-stage phase inverter, a third NMOS tube Mn3 is an active current source, an input signal is output to a first voltage output end Voutm and a second voltage output end Voutq through a first voltage input end Vinq and a second voltage input end Vinm, a common-mode signal part of an output signal is amplified by an operational amplification module Amp and then is connected to a grid electrode of the third NMOS tube Mn3, and common-mode feedback CMFB is formed.
The time-to-digital converter based analog-to-digital converter TDC-ADC includes a sampler 11, a voltage-to-time converter 12, and a time-to-digital conversion module 13, wherein a signal and a clock are input to an input terminal of the sampler 11, the sampler 11 samples the input signal according to the input clock and outputs the sampled signal to the voltage-to-time converter 12, the voltage-to-time converter 12 converts a voltage domain-based signal into a time domain-based signal and outputs the time domain-based signal to the time-to-digital conversion module 13, and the time-to-digital conversion module 13 converts the time domain-based signal into a corresponding digital signal and outputs the digital signal. The time-to-digital conversion module 13 includes a delay unit 131, a D flip-flop 132, and a signal summation unit 133, wherein a signal based on a time domain is converted into a corresponding digital signal through the delay unit 131 and the D flip-flop 132, and finally the digital signal is processed through the signal summation unit 133 to generate an output signal. In the embodiment, the delay unit of the TDC-ADC main body part of the analog-to-digital converter based on the time-to-digital converter adopts a digital logic inverter, so that the unit power consumption of the TDC-ADC main body part is the lowest, the area of the TDC-ADC main body part is the smallest, and the conversion process does not need obvious parameter change; furthermore, the low-pass filter (LPF 1, \8230 \ 8230;, LPFm) and the controllable gain amplifier PGA are unified by adopting a single-stage inverter structure, so that the whole analog baseband circuit is a design structure based on an inverter technology, and is not only high in speed and good in stability, but also suitable for working in a voltage domain smaller than 1V, so that the power consumption of the analog baseband circuit is remarkably reduced compared with the traditional structure, and meanwhile, the analog baseband circuit does not increase extra area, and is very suitable for being applied to a broadband zero intermediate frequency receiver, such as an Ultra Wide Band (UWB) system which is more and more widely used at present.
The delay unit may be a single-side even inverter connection, as shown in fig. 4, the delay of two inverters is the shortest unit delay; it is also possible to have a differential odd inverter connection, as shown in fig. 5, with a single inverter delay as the shortest unit delay, wherein the inverter structure is included in the delay unit. The differential odd inverter connected delay cell in fig. 5 can double the accuracy of the delay time compared to the single-sided even inverter connected delay cell in fig. 4.
Specifically, as shown in fig. 4, in some embodiments, the time-to-digital conversion module 13 includes a signal summing unit 133, 2p (2) n -1) delay units 131 and 2 n Stage D flip-flop 132 in which each delay cell 131 has an inverter structure, 2p (2) n -1) delay units 131 are sequentially connected in series at the Start output Start of the voltage-time converter 12, and the signal input D of the 0 th stage D flip-flop is connected at the Start output Start, 1 st to 2 nd stages of the voltage-time converter 12 n The signal input terminals D of the 1-stage D flip-flops 132 are respectively connected to the output terminals of the delay units 131, and 2p delay units 131 are connected between the signal input terminals D of every two adjacent stages of D flip-flops 132, the clock input terminals of the D flip-flops 132 are respectively connected to the Stop output terminal Stop of the voltage-time converter 12, the clear terminals CLR of the D flip-flops 132 are respectively connected to the clear output terminals of the voltage-time converter 12, the signal output terminals Q of the D flip-flops 132 are respectively connected to the input terminals of the signal summing unit 133, and the signal summing unit 133 is configured to sum the signals 2 and 2 n The n-bit digital signal output by the stage D flip-flop 132 is processed to generate an output signal, where n and p are positive integers, respectively. In the present embodiment, p =1, and each stage of D flip-flops 132 includes one D flip-flop 132.
Specifically, as shown in FIG. 5, in other embodiments, the time-to-digital conversion module 13 includes signal summing units 133, 2 (2 q-1) (2) n -1) delay units 131 and 2 n A stage D flip-flop 132, in which each delay unit 131 respectively adopts an inverter structure, and (2 q-1) × n delay units 131 are sequentially connected in series to the Start output Start of the voltage-time converter 12 to form a first delay unit path, and (2 q-1) × n delay units 131 are sequentially connected in series to the reverse Start output of the voltage-time converter 12
To form a second extensionA time cell path; signal input terminal D, inverted signal input terminal of 0 th stage D flip-flop 132
Respectively connected to the Start output terminal Start and the reverse Start output terminal of the voltage-time converter 12
1, 3, 823060, 8230, 2 n The signal input terminals D of the-1 stage D flip-flop 132 are respectively connected to the output terminals 1, 3, 8230of the delay unit 131 on the second delay unit path, 8230, 2 n Inverting signal input terminal of-1 stage D flip-flop 132
Outputs of the delay cells 131 respectively connected to the first delay cell paths, no. 2, no. 4, \8230;. 2 n The signal input terminals D of the 2-level D flip-flop 132 are respectively connected to the output terminals of the delay cells 131 on the first delay cell path, 2 nd, 4 th, 8230 \ 8230;, 2 nd n -inverting signal input of stage 2D flip-flop 132
The output ends of the delay units 131 are respectively connected to the paths of the second delay units, 2q-1 delay units 131 are connected to the first delay unit path between every two adjacent stages of D flip-flops 132, and 2q-1 delay units 131 are connected to the second delay unit path between every two adjacent stages of D flip-flops 132; the clock input terminal of each stage of D flip-flop 132 is connected to the Stop output terminal Stop of the voltage-time converter 12, the clear terminal CLR of each stage of D flip-flop 132 is connected to the clear output terminal of the voltage-time converter 12, the signal output terminal Q of each stage of D flip-flop 132 is connected to the input terminal of the signal summing unit 133, and the signal summing unit 133 is configured to sum 2 signals to the Stop output terminal Stop of the voltage-time converter 12 n The n-bit digital signal output by the stage D flip-flop 132 is processed to generate an output signal, where n and q are positive integers respectively. In this embodiment, q =1, and each stage of D flip-flops 132 includes one D flip-flop 132.
In the analog baseband circuit based on the inverter technology provided in the preferred embodiment of the present invention, on one hand, the low pass filter (LPF 1, \8230;, LPFm) and the controllable gain amplifier PGA adopt an operational amplifier based on a common mode feedback type single-stage inverter, which has the advantages of high speed and good stability, the gain bandwidth stage can be designed to be very high, and only one pole is provided; on the other hand, the low pass filter LPF is made into a single design by combining the controllable gain amplifier PGA, and the time-to-digital converter based analog-to-digital converter TDC-ADC is adopted, and further combined with the low pass filter (LPF 1, \8230;, LPFm) adopting an inverter structure, the controllable gain amplifier PGA and the time-to-digital converter TDC-ADC adopting an inverter structure, so that the power consumption area of the whole analog baseband circuit is very small, and the whole analog baseband circuit can even work below a 1V voltage domain, and therefore, compared with the traditional structure, the analog baseband circuit has a very obvious advantage of low power consumption.
Therefore, the analog baseband circuit based on the inverter technology proposed in the preferred embodiment of the present invention can be applied not only to a wideband low power consumption analog baseband circuit operating in a voltage domain of 1V or less, but also to an analog baseband circuit applied to an ultra wideband system.
The analog baseband circuit based on inverter technology proposed by the preferred embodiment of the present invention is further described below with reference to a specific embodiment.
As shown in fig. 6, the multi-STAGE low-pass filter based on the common-mode feedback single-STAGE inverter structure (1-STAGE INV AMP) in the analog baseband circuit can be configured into different orders and architectures according to different application scenarios, so as to meet the requirements of different circuits on parameters such as performance, area, power consumption, and the like.
In this embodiment, the low pass filter LPF includes an operational amplifier, two input resistors Rin, two feedback resistors Rfb, and two adjustable circuit broadband capacitors Cbw, where two input ends of the operational amplifier are respectively connected to one input resistor Rin, and each feedback resistor Rfb and each adjustable circuit broadband capacitor Cbw are respectively connected in parallel between the input end and the output end of the operational amplifier. I.e. two voltage inputs of the analog baseband circuitThe ends Vinn and Vinp are respectively connected with the input end of the operational amplifier through an input resistor Rin, and two output ends of the operational amplifier are respectively connected with the operational amplifier of the next low-pass filter LPF after passing through an input resistor Rin in the next low-pass filter LPF, so that the low-pass filters (LPF 1, 8230; LPFm) are sequentially connected in series and then connected with the input end of the controllable gain amplifier PGA. In the multi-stage low-pass filter circuit exemplified in FIG. 6, by changing
Is gain adjusted by varying
The value can adjust the bandwidth, and the Q value of the low-pass filter (the Q value is the quality factor of the filter, and the larger the Q value, the better the frequency selection capability of the filter is represented) is also flexibly configurable. The final stage of the multi-stage filter is a controllable gain amplifier based on a common-mode feedback single-stage inverter structure, and the controllable gain amplifier and the common-mode feedback single-stage inverter structure form a signal amplification link which is wide in adjustable gain range (-50 dB) and high in stepping precision (-1 dB).
In this embodiment, the dc cancellation circuit DCOC includes a gain amplification module 21, two first adjustable resistors R1, two second adjustable resistors R2, and two first capacitors C1, first ends of the two first adjustable resistors R1 are respectively connected to two output ends of the controllable gain amplifier PGA, second ends of the two first adjustable resistors R1 are respectively connected to two input ends of the gain amplification module 21, two output ends of the gain amplification module 21 are respectively connected to first ends of the two second adjustable resistors R2, second ends of the two second adjustable resistors R2 are respectively connected to two voltage input ends Vinn and Vinp of the analog baseband circuit, first ends of the two first capacitors C1 are respectively connected to second ends of the two first adjustable resistors R1, and second ends of the two first capacitors C1 are respectively grounded; the outputs of the m low-pass filters (LPF 1, \8230;, LPFm) and the controllable gain amplifier PGA are fed back to the input via a dc cancellation circuit DCOC, which ensures the cancellation of the dc component in the signal chain,
the value of (c) determines the low-pass bandwidth characteristics of the circuit (where,
equal to a frequency which is a cut-off frequency of a low-pass filter unit formed by the first adjustable resistor R1 and the first capacitor C1 in the dc cancellation circuit DCOC), the bandwidth of the feedback signal and the settling time of the dc cancellation can be adjusted by matching with the value of the adjustable resistor R2, and β is a gain of the operational amplifier 21.
A time-to-digital converter (TDC-ADC) based analog-to-digital converter, in which a sampling capacitor Csample corresponds to the sampler 11 in fig. 4 and 5, and the oversampling capacitor Csample charges and discharges an input signal; the VTC is equivalent to a voltage-time converter 12, converts different input signal amplitudes into delay time Δ T of corresponding magnitude, converts the delay time Δ T into digital signals by using inverter delay units (an 8230a 1 and bn 8230b 1 in the figure) based on digital logic, and outputs the digital signals from two voltage output terminals Voutn and Voutp.
The background section of the present invention may contain background information related to the problem or environment of the present invention rather than the description of the prior art by others. Accordingly, the inclusion in this background section is not an admission by the applicant that prior art is available.
The foregoing is a more detailed description of the invention in connection with specific/preferred embodiments and is not intended to limit the practice of the invention to those descriptions. It will be apparent to those skilled in the art that numerous alterations and modifications can be made to the described embodiments without departing from the inventive concepts herein, and such alterations and modifications are to be considered as within the scope of the invention. In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "preferred embodiments," "example," "specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent. Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by the appended claims.
Claims (10)
1. An analog baseband circuit based on an inverter technology is characterized by comprising an analog-to-digital converter and a controllable gain amplifier fused with at least one low-pass filter, wherein the controllable gain amplifier fused with at least one low-pass filter is connected between the input end of the analog baseband circuit and the input end of the analog-to-digital converter, the output end of the analog-to-digital converter corresponds to the output end of the analog baseband circuit, and all operational amplifiers adopted in the controllable gain amplifier fused with at least one low-pass filter and delay units in the analog-to-digital converter respectively adopt an inverter structure.
2. The analog baseband circuit of claim 1, wherein all operational amplifiers used in the controllable gain amplifier incorporating at least one low pass filter are of a single-stage inverter structure of a common-mode feedback type.
3. The analog baseband circuit according to claim 2, wherein the common-mode feedback single-stage inverter structure comprises first to second PMOS transistors, first to third NMOS transistors, and an operational amplifier module, wherein gates of the first PMOS transistor and the first NMOS transistor are respectively connected to the first voltage input terminal, gates of the second PMOS transistor and the second NMOS transistor are respectively connected to the second voltage input terminal, drains of the first PMOS transistor and the first NMOS transistor are respectively connected to the first voltage output terminal, drains of the second PMOS transistor and the second NMOS transistor are respectively connected to the second voltage output terminal, sources of the first PMOS transistor and the second PMOS transistor are respectively connected to the current source, sources of the first NMOS transistor and the second NMOS transistor are respectively connected to the drain of the third NMOS transistor, a source of the third NMOS transistor is grounded, the first voltage output terminal and the second voltage output terminal are respectively connected to two input terminals of the operational amplifier module, and an output terminal of the operational amplifier module is connected to a gate of the third NMOS transistor.
4. The analog baseband circuit of claim 1, wherein said analog-to-digital converter is a time-to-digital converter based analog-to-digital converter.
5. The analog baseband circuit of claim 4, wherein the analog-to-digital converter comprises a sampler, a voltage-to-time converter and a time-to-digital conversion module, wherein a signal and a clock are input to an input terminal of the sampler, the sampler samples the input signal according to the input clock and outputs the sampled signal to the voltage-to-time converter, the voltage-to-time converter converts the voltage domain-based signal into a time domain-based signal and outputs the time domain-based signal to the time-to-digital conversion module, and the time-to-digital conversion module converts the time domain-based signal into a corresponding digital signal and outputs the corresponding digital signal.
6. The analog baseband circuit of claim 5,
the time-digital conversion module comprises a signal summation unit and a 2p (2) n -1) delay units and 2 n The number of the stage D flip-flops,
wherein each delay unit adopts an inverter structure, 2p (2) n -1) said delay cells are connected in series in sequence at the start output of the voltage-to-time converter,
the signal input terminal of the D flip-flop of the 0 th stage is connected to the start output terminal of the voltage-time converter, the second stage1 to 2 n The signal input ends of the D flip-flops of the 1 stage are respectively connected with the output ends of the delay units, and 2p delay units are connected between the signal input ends of the D flip-flops of each adjacent two stages,
the clock input end of each stage of D trigger is respectively connected with the termination output end of the voltage-time converter, the zero clearing end of each stage of D trigger is respectively connected with the zero clearing output end of the voltage-time converter, the signal output end of each stage of D trigger is respectively connected with the input end of the signal summation unit, and the signal summation unit is used for summing 2 signals n And processing an output signal of the D trigger to generate an n-bit digital signal and outputting the n-bit digital signal, wherein n and p are positive integers respectively.
7. The analog baseband circuit according to claim 5, wherein said time-to-digital conversion module comprises a signal summing unit, 2 (2 q-1) (2) n -1) delay units and 2 n A stage D flip-flop is provided,
wherein each delay unit respectively adopts an inverter structure, the (2 q-1) n delay units are sequentially connected in series at the starting output end of the voltage-time converter to form a first delay unit path, the (2 q-1) n delay units are sequentially connected in series at the reverse starting output end of the voltage-time converter to form a second delay unit path,
the signal input terminal and the reverse signal input terminal of the D flip-flop of the 0 th stage are respectively connected with the start output terminal and the reverse start output terminal of the voltage-time converter, 1 st, 3 rd, 8230, 2 nd n Signal input terminals of the D flip-flops in the 1-stage are respectively connected with output terminals of the delay units on the second delay unit path, 1 st, 3 rd, 8230, (8230), 2 nd n The inverted signal input ends of the D flip-flops of the 1 level are respectively connected with the output ends of the delay units on the first delay unit path, 2 nd, 4 th, 8230, 2 nd n Signal input terminals of the 2-stage D flip-flops are respectively connected with output terminals of the delay units on the first delay unit path, 2 nd, 4 th, 8230, (8230) and 2 nd n The reverse signal input ends of the D flip-flops of the 2 stages are respectively connected2q-1 delay units are connected to the output end of the delay unit on the path of the second delay unit and the first delay unit path between every two adjacent stages of the D triggers, 2q-1 delay units are connected to the second delay unit path between every two adjacent stages of the D triggers,
the clock input end of each stage of D trigger is respectively connected with the termination output end of the voltage-time converter, the zero clearing end of each stage of D trigger is respectively connected with the zero clearing output end of the voltage-time converter, the signal output end of each stage of D trigger is respectively connected with the input end of the signal summation unit, and the signal summation unit is used for summing 2 signals n And processing an output signal of the D trigger to generate an n-bit digital signal and outputting the n-bit digital signal, wherein n and q are positive integers respectively.
8. The analog baseband circuit according to any one of claims 1 to 7, wherein the controllable gain amplifier incorporating at least one low pass filter comprises a gain amplifier and at least one low pass filter, the at least one low pass filter is connected in series between the input of the analog baseband circuit and the input of the controllable gain amplifier, the output of the gain amplifier is connected to the input of the analog-to-digital converter, wherein the gain amplifier and the at least one low pass filter are made into a single design, so that the at least one low pass filter and the controllable gain amplifier are combined together and have at least one-order low pass filtering and gain adjustable functions.
9. A wideband low power consumption analog baseband circuit adapted to operate below the 1V voltage domain, characterized in that the analog baseband circuit of any of claims 1 to 8 is used.
10. An analog baseband circuit suitable for use in ultra-wideband systems, characterized in that an analog baseband circuit according to any one of claims 1 to 8 is used.
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| CN106788511A (en) * | 2016-12-30 | 2017-05-31 | 北京时代民芯科技有限公司 | A kind of wideband radio receiver |
| CN109828240A (en) * | 2019-03-21 | 2019-05-31 | 中国电子科技集团公司第三十八研究所 | A kind of analog baseband circuitry and 77GHz car radar |
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| US7242334B2 (en) * | 2005-12-09 | 2007-07-10 | Sirific Wireless Corporation | Wireless receiver circuit with merged ADC and filter |
| JP4771422B2 (en) * | 2006-09-14 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | Receiver |
| JP2010278718A (en) * | 2009-05-28 | 2010-12-09 | Renesas Electronics Corp | Semiconductor integrated circuit |
| KR20130069147A (en) * | 2011-12-16 | 2013-06-26 | 삼성전자주식회사 | Apparatus and circuit for amplifying baseband signal |
| CN111865344B (en) * | 2020-06-23 | 2021-07-23 | 复旦大学 | Analog baseband circuit with variable gain and bandwidth |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106788511A (en) * | 2016-12-30 | 2017-05-31 | 北京时代民芯科技有限公司 | A kind of wideband radio receiver |
| CN109828240A (en) * | 2019-03-21 | 2019-05-31 | 中国电子科技集团公司第三十八研究所 | A kind of analog baseband circuitry and 77GHz car radar |
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