CN114710124A - Rail-to-rail input and output operational transconductance amplifier based on low ripple charge pump - Google Patents

Rail-to-rail input and output operational transconductance amplifier based on low ripple charge pump Download PDF

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CN114710124A
CN114710124A CN202210318563.XA CN202210318563A CN114710124A CN 114710124 A CN114710124 A CN 114710124A CN 202210318563 A CN202210318563 A CN 202210318563A CN 114710124 A CN114710124 A CN 114710124A
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pmos
input
charge pump
nmos
stage
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白春风
齐敏
张骥
孙树全
乔东海
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Yongnian Semiconductor Wuxi Co ltd
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Yongnian Semiconductor Wuxi Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/70—Charge amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45051—Two or more differential amplifiers cascade coupled

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  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an operational transconductance amplifier based on a low ripple charge pump, which has simple and reasonable circuit structure design, can improve the voltage fluctuation flattening effect of the equivalent input transconductance, can meet the application requirement of wide temperature range, the differential transconductance input stage comprises a low ripple charge pump, a first current mirror and a differential pair, two input ends of the low ripple charge pump are respectively connected with an external input clock signal and a voltage source VDD, an output end of the low ripple charge pump is connected with a power supply end of the first current mirror, an output end of the first current mirror is connected with a source electrode of the differential pair, a drain electrode of the differential pair is connected with the differential to single-ended transimpedance stage, the first current mirror comprises PMOS tubes P9-P12 and a resistor R3, the differential pair comprises PMOS tubes P13 and P14, and an output end of the push-pull output stage is an output end of the operational transconductance amplifier.

Description

Rail-to-rail input and output operational transconductance amplifier based on low ripple charge pump
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a rail-to-rail input operational transconductance amplifier based on a low ripple charge pump.
Background
The operational transconductance amplifier is a commonly used unit in the design of an analog CMOS integrated circuit, and is used for converting an input differential voltage signal into an output current, and can realize various analog signal operations by combining with a negative feedback network thereof, which is also commonly referred to as an operational amplifier for short. In the application of low working voltage analog circuit with limited signal swing, it is often required that the input and output of the operational transconductance amplifier can realize rail-to-rail to obtain the maximum voltage signal swing, that is: (1) the common-mode input level of the designed operational transconductance amplifier can approximately span the whole range from the negative power supply voltage to the positive power supply voltage, namely, the input rail to the rail; (2) the output voltage swing of the designed operational transconductance amplifier reaches approximately the full range from negative to positive supply voltages, i.e., output rail to rail.
When the two targets are realized, the small signal parameters such as equivalent input transconductance of the operational transconductance amplifier and the like need to be maintained to be basically constant so as to ensure the stability of the operational amplifier in various working states, and in addition, the dependence of the small signal parameters of the operational amplifier on input voltage is a non-linear main source. In the circuit structure of the operational transconductance amplifier with rail-to-rail input and output commonly used at present, rail-to-rail output is realized by push-pull output (i.e. class AB amplifier), and the main differences of the existing operational transconductance amplifier are as follows: the rail-to-rail input and the substantially constant equivalent input transconductance are implemented differently. However, most of the existing rail-to-rail inputs and substantially constant equivalent input transconductance have complicated circuit structures, and the variation of the equivalent input transconductance can be controlled only within a small range.
At present, a mode for solving the problem of small common mode input range is to simultaneously set a PMOS differential pair transistor and an NMOS differential pair transistor, and to expand the allowable common mode input voltage range through the mutual matching of two pairs of differential pair transistors, but in the actual working process, it is necessary to ensure that the two pairs of differential pair transistors can be perfectly connected in opening and closing, which greatly increases the process difficulty. Thus, a practical conventional rail-to-rail input stage typically needs to incorporate a triple current mirror: when the PMOS differential pair is closed, amplifying the tail current of the PMOS differential pair by three times and then sending the amplified tail current to the NMOS differential pair; when the NMOS differential pair is closed, the tail current of the NMOS differential pair is amplified by three times and then is sent to the PMOS differential pair. This enables an approximately flat equivalent input transconductance over the entire input voltage range, but the triple current mirror technique suffers from the following disadvantages: (1) the equivalent input transconductance changes along with the change of the input voltage, the fluctuation of the equivalent input transconductance can be controlled within 15% generally under the condition of introducing a triple current mirror, and the fluctuation flattening effect of the equivalent input transconductance is poor; (2) the triple current mirror technology enables the bias current of the input transconductance stage to change along with the change of the input voltage, and the design of a rear-stage circuit becomes more complex. This problem is exacerbated in applications over a wide temperature range.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a rail-to-rail input and output operational transconductance amplifier based on a low ripple charge pump, which has simple and reasonable circuit structure design, can improve the voltage fluctuation flattening effect of equivalent input transconductance and can meet the application requirement of a wide temperature range.
In order to achieve the purpose, the invention adopts the following technical scheme:
a rail-to-rail input and output operational transconductance amplifier based on a low ripple charge pump comprises a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage and a push-pull output stage which are connected in sequence,
the bias circuit is used for providing a bias voltage and a bias current;
the differential transconductance input stage is used for converting a differential input voltage into a differential current;
the differential-to-single-ended transimpedance stage is used for converting differential current into single-ended current;
the push-pull output stage converts the single-ended current into current output in a push-pull mode;
the differential transconductance input stage is characterized in that the differential transconductance input stage comprises a charge pump, a first current mirror and a differential pair, the charge pump is a low-ripple charge pump, the charge pump is used for raising a voltage source VDD and supplying power to the first current mirror, the first current mirror is used for mirroring a bias current generated by the bias circuit, two input ends of the charge pump are respectively connected with an external input clock signal and the voltage source VDD, an output end of the charge pump is connected with a power supply end of the first current mirror, outputs of the first current mirror are respectively connected with source electrodes of the differential pair, a drain electrode of the differential pair is connected with a differential to single-ended transimpedance stage, an output of the differential to single-ended transimpedance stage is connected with an input of the push-pull output stage, the first current mirror comprises PMOS tubes P9-P12, the differential pair comprises PMOS tubes P13 and P14, a voltage output end of the charge pump is respectively connected with the differential pair, a voltage output end of the charge pump is connected with the differential pair through the first current mirror, The bias circuit.
It is further characterized in that the method further comprises the steps of,
the low-ripple charge pump comprises a PMOS tube N17, capacitors C3, C4, C5, a single-stage charge pump CP1 and CP2, wherein a 1 pin of the single-stage charge pump CP1 is respectively connected with the voltage source VDD and the single-stage charge pump CP2, a 2 pin of the single-stage charge pump CP2 is respectively connected with one end of the capacitor C3 and a source of the PMOS tube N17, a 2 pin of the single-stage charge pump CP2 is respectively connected with one end of the capacitor C4, a drain of the PMOS tube N17 is connected with one end of the capacitor C5, the other ends of the capacitors C3, C4 and C5 are grounded, and 3 pins of the single-stage charge pump CP1 and CP2 are connected with an external input clock signal;
the single-stage charge pump CP1 comprises a PMOS tube P20, P21, P22, P23, an NMOS tube N18, N19, N20, N21, a capacitor C6 and a capacitor C7, the PMOS tube P20 is connected with the grid electrode of the NMOS tube N18 and the drain electrode of the PMOS tube P21, the PMOS transistor P21 is connected with the grid electrode of the NMOS transistor N19 and the drain electrode of the PMOS transistor P20, the sources of the NMOS transistors N18 and N19 are connected with a voltage source VDD, the sources of the PMOS transistors P20 and P21 are voltage output ends, the sources of the NMOS transistors N18 and N19 are correspondingly connected with one ends of the capacitors C6 and C7, the other end of the capacitor C6 is respectively connected with the grids of a PMOS tube P22, a PMOS tube P23, an NMOS tube N20 and an NMOS tube N21, the other end of the capacitor C7 is respectively connected with the drain electrode of the PMOS tube P23 and the drain electrode of the NMOS tube N21, the grid of the PMOS pipe P22 and the grid of the NMOS pipe N21 are connected with an external input clock signal, the sources of the PMOS tubes P23 and P22 are respectively connected with a voltage source VDD, and the sources of the NMOS tubes N20 and N23 are respectively grounded; the structure of the single-stage charge pump CP2 is identical to that of the single-stage charge pump CP 1;
the bias circuit comprises a first bias voltage generating unit and a first switch unit, wherein the first bias voltage generating unit is used for generating a bias voltage VB2, the first switch unit is used for conducting and controlling the bias voltage and the bias current, the first bias voltage generating unit comprises PMOS tubes P1 and P5, the first switch unit comprises NMOS tubes N1-N4, N7-N10 and resistors R1 and R2, the input end of the first bias voltage generating unit is connected with a voltage source VDD, the output end of the first bias voltage generating unit is connected with the first switch unit, and meanwhile, the voltage source VDD is connected with the first switch unit after being connected with a resistor R1 in series;
the differential-to-single-ended transimpedance stage comprises a second bias voltage generation unit, a second current mirror, a second switch unit, a current buffer unit and a third switch unit, wherein the second bias voltage generation unit is used for generating a first bias voltage VB, the second current mirror is used for mirroring the bias current of the second bias voltage generation unit, the second switch unit and the third switch unit are used for conducting control, the current buffer unit is used for providing push-pull voltage, the second bias voltage generation unit comprises PMOS tubes P16 and P17, the second current mirror comprises PMOS tubes P2, P3, P6 and P7, the second switch unit comprises PMOS tubes P18, P19, N16, N15 and N14, the third switch unit comprises PMOS tubes P4 and P8, the current buffer unit comprises NMOS tubes N5, N6, N11 and N12, and the second bias voltage generation unit and the second current mirror unit, The input ends of the third switching units are connected with a voltage source VDD and the input end of the charge pump, the outputs of the second bias voltage generating unit, the second current mirror and the third switching unit are connected with the second switching unit, the output of the second switching unit is connected with the input of the current buffering unit, and the output of the current buffering unit is connected with the control end of the push-pull output stage;
the push-pull output stage comprises a PMOS tube P15, an NMOS tube N13, capacitors C1, C2, resistors R4 and R5, the drain electrode of the PMOS tube P15 and the drain electrode of the NMOS tube N13 are connected and are an output end OUT of the operational transconductance amplifier, the source electrode of the NMOS tube N13 is grounded, the other end of the resistor R4 is connected with the output end OUT after being connected with the capacitor C1 in series, and the other end of the resistor R5 is connected with the output end OUT after being connected with the capacitor C2 in series.
The structure and the method of the invention can achieve the following beneficial effects: according to the differential transconductance input stage of the operational transconductance amplifier, the low ripple charge pump is arranged in the differential transconductance input stage of the operational transconductance amplifier and has the characteristics of simple design and small influence by temperature change, so that a higher-voltage power supply is provided for the first current mirror of the differential transconductance input stage through the low ripple charge pump, and the problem that the common-mode input voltage range allowed by the differential transconductance input stage cannot reach rail-to-rail is solved.
In addition, the output end of the charge pump is provided with the first current mirror, and the first current mirror can inhibit the fluctuation of the output voltage of the charge pump, so that the bias current of the input stage is hardly influenced by the input clock signal of the charge pump, therefore, the requirement of constant equivalent input transconductance of the differential transconductance input stage can be met without arranging a triple current mirror, namely, the constant transconductance can be obtained without designing a complex additional auxiliary circuit structure to inhibit the voltage fluctuation, and the circuit structure is simplified. And the arrangement of the low ripple charge pump and the first current mirror ensures that the bias current of the differential transconductance input stage does not change along with the change of the common-mode input voltage, thereby being beneficial to simplifying the design of a post-stage circuit to adapt to a wide working temperature range and further meeting the application requirement of the wide temperature range.
Drawings
FIG. 1 is a schematic circuit diagram of two differential pairs of a conventional operational transconductance amplifier;
FIG. 2 is a graph of equivalent input transconductance versus input voltage source VDD;
FIG. 3 is a schematic circuit diagram of a rail-to-rail input stage of a conventional operational transconductance amplifier;
FIG. 4 is a circuit schematic of an operational transconductance amplifier of the present invention;
FIG. 5 is a schematic circuit diagram of the low ripple charge pump of the present invention;
fig. 6 is a schematic circuit diagram of the single-stage charge pump CP 1/electrode charge pump CP2 in the low ripple charge pump of the present invention.
Detailed Description
For a better understanding of the present invention, and for the purpose of promoting an understanding thereof, reference will now be made to the embodiments of the present invention which are illustrated in the accompanying drawings and described below, wherein the terms "include" and "have" and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The operational transconductance amplifier can realize various analog signal operations by combining with a negative feedback network, certain application occasions of the operational transconductance amplifier (operational amplifier) require that the input and the output of the operational transconductance amplifier can realize rail-to-rail, the traditional rail-to-rail input is realized mainly by mutually matching a pair of PMOS tube differential pairs and a pair of NMOS tube differential pairs, as shown in figure 1, when the voltage value of an input voltage source VDD (namely, a voltage source VDD) is lower, the PMOS tube differential pair consisting of MP10 and MP20 realizes the function of differential transconductance conversion; when the voltage value of an input voltage source VDD is higher, an NMOS tube differential pair consisting of MN10 and MN20 realizes the function of differential transconductance conversion; if the input voltage source VDD is at the middle value, two pairs of differential pairs will input transconductance simultaneously, as shown in FIG. 2, and the vertical axis g in FIG. 2mRepresenting the equivalent input transconductance and the horizontal axis the voltage of the voltage source VDD. As can be seen from fig. 2, the equivalent input transconductance has a large variation amplitude with the variation of the input voltage source VDD, unless the value of the power voltage is just to perfectly connect the turn-off of the NMOS differential pair and the turn-on of the PMOS differential pair, but the prior art cannot achieve such perfect connection.
The dependence of operational amplifier small signal parameters on the input voltage source VDD is a major source of nonlinearity, so that a conventional rail-to-rail input stage usually needs to be matched with a triple current mirror to achieve approximately flat equivalent input transconductance in the whole input voltage range. As shown in fig. 3, the conventional rail-to-rail input stage implementation circuit includes three current mirrors, namely PMOS transistors MP3 and MP5, MP1 and MP2, and NMOS transistors MN4 and MN5, where the duplication multiple of the current mirror is three because the relationship between the transconductance of the MOS transistor MP4 and the bias current thereof is the relationship of the second root opening.
In summary, the conventional rail-to-rail input stage has the following drawbacks: (1) the equivalent input transconductance changes along with the change of an input voltage source VDD, and the fluctuation of the equivalent input transconductance can only be controlled within 15% under the condition of introducing a triple current mirror, which is an important source of nonlinearity.
(2) The triple current mirror technology enables the bias current of the input transconductance stage to change along with the change of the input voltage, and the design of a rear-stage circuit becomes more complex. In wide temperature range applications, this problem is more severe because: the threshold voltages of the PMOS tube and the NMOS tube have larger negative temperature coefficients, the threshold voltages of the PMOS tube and the NMOS tube at 125 ℃ are 200-300 mV lower than those of the PMOS tube and the NMOS tube at minus 50 ℃, but the amplitude of the drain-source saturation voltage of the PMOS tube and the NMOS tube which changes along with the temperature change is very small; meanwhile, the carrier mobility of the PMOS tube and the NMOS tube also has a negative temperature coefficient, namely the higher the temperature is, the lower the carrier mobility is. Thus, the conventional triple current mirror technique described above is highly challenging for wide temperature range applications.
Since carrier mobility decreases with increasing temperature, wide temperature range integrated circuit designs typically employ constant transconductance biasing techniques, i.e., a negative temperature coefficient in which the bias current has a positive temperature coefficient to compensate for carrier mobility. The small-signal transconductance of the PMOS transistor and the NMOS transistor is a core parameter concerned in designing a circuit, so that the positive temperature coefficient of the tail current source is superimposed with the amplification effect of the triple current mirror, which causes a great challenge in designing a current buffer stage for converting the differential current output by the first stage into the single-ended current in the conventional rail-to-rail operational amplifier: the gate bias voltage of the common-gate MOS transistor is ensured to work in a saturation region when the bias current is minimum (namely VGS of the differential-to-single-ended current mirror is minimum), and the differential-to-single-ended current mirror is ensured to fully work in the saturation region to ensure the gain of the operational amplifier. The two requirements are opposite to each other, so that the space for designing is small, and even no solution is possible under the condition of considering a complicated process corner.
In order to solve the problems and realize the good work of the rail-to-rail input and output operational transconductance amplifier in a wide temperature range, the invention provides the following technical scheme: referring to fig. 4, the rail-to-rail input and output operational transconductance amplifier based on the low ripple charge pump includes a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage, which are connected in sequence. The bias circuit is used for providing bias voltage and bias current, the differential transconductance input stage is used for converting the differential component of the input voltage from a common-mode input voltage rail to a rail into differential current, the differential-to-single-ended transimpedance stage is used for converting the differential current into single-ended voltage, and the push-pull output stage converts a voltage signal into current output in a push-pull mode.
The differential transconductance input stage comprises a low ripple charge pump, a first current mirror and a differential pair, wherein the low ripple charge pump is used for supplying power to the first current mirror after a voltage source VDD is boosted, and the first current mirror is used for mirroring a bias current in a bias circuit so as to provide a tail current required by the differential pair. The input end of the low ripple charge pump is respectively connected with the differential-to-single-ended trans-impedance stage and the voltage source VDD, the output end of the low ripple charge pump is connected with the first current mirror and used for supplying power to the first current mirror, the first current mirror is connected with the source electrode of the differential pair, and the drain electrode of the differential pair is connected with the differential-to-single-ended trans-impedance stage. The first current mirror comprises PMOS tubes P9-P12, and the differential pair comprises PMOS tubes P13 and P14.
Referring to fig. 5, the specific circuit structure of the low ripple charge pump is as follows: the single-stage charge pump circuit comprises an NMOS tube N17, capacitors C3, C4, C5, a single-stage charge pump CP1 and CP2, wherein a 1 pin of the single-stage charge pump CP1 is respectively connected with a voltage source VDD and the single-stage charge pump CP2, a 2 pin of the single-stage charge pump CP2 is respectively connected with one end of the capacitor C3 and a source of the NMOS tube N17, a 2 pin of the single-stage charge pump CP2 is respectively connected with one end of the capacitor C4, a drain of the NMOS tube N17 is connected with one end of the capacitor C5, the other ends of the capacitors C3, C4 and C5 are grounded, and 3 pins of the single-stage charge pump CP1 and CP2 are connected with an external input clock signal.
Referring to fig. 6, the single-stage charge pump CP1 includes PMOS transistors P20, P21, P22, P23, NMOS transistor N18, N19, N20, N21, capacitors C6, and C7, the PMOS transistor P20 is connected to the gate of the NMOS transistor N18 and the drain of the PMOS transistor P21, the PMOS transistor P21 is connected to the gate of the NMOS transistor N19 and the drain of the PMOS transistor P20, the sources of the NMOS transistors N18 and N18 are connected to a voltage source VDD, the sources of the PMOS transistors P18 and P18 are voltage output terminals, the sources of the NMOS transistors N18 and N18 are connected to the gates of the capacitors C18 and C18 in one-to-one-to-one correspondence, the drains of the NMOS transistors N18 and N18 are independent substrate NMOS transistors with a deep N well, the other ends of the capacitors C18 and N18 are connected to the gates of the PMOS transistors P18, P18 and N18, the drains of the NMOS transistors N18, the drains of the capacitors C18 are connected to the drains of the PMOS transistors P18 and N18, the drains of the NMOS transistors P18 and the drains of the NMOS 18, the NMOS transistors P18 are connected to the NMOS transistors P18, the drains of the NMOS transistors P18, and the drains of the NMOS transistors P18, and the drains of the NMOS transistors are connected to the drains of the NMOS transistors P18, and the NMOS 18, and the drains of the NMOS transistors are connected to the drains of the NMOS transistors, and the drains of the NMOS transistors, and the NMOS transistors P18, and the N18, and the drains of the NMOS transistors, and the NMOS transistors P18, and the drains of the NMOS transistors, and the drains of the N18, respectively, and the drains of the NMOS transistors are connected to the NMOS transistors, and the drains of the NMOS transistors, and the N18, respectively, and the N18, and the drains of the NMOS transistors are connected to the NMOS transistors, and the drains of the NMOS transistors, and the N18, and the NMOS are connected to the NMOS transistors, respectively, and the N18, and the drains of the NMOS are connected to the drains of the NMOS transistors, respectively, and the NMOS transistors, and the NMOS 18, and the drains of the N18, and the NMOS 18, respectively, and the drains of the NMOS transistors, respectively, and the N18, and the drains of the NMOS are connected to the drains of the NMOS are connected to the NMOS tubes, and the NMOS tubes, respectively, and the NMOS tubes, and; the structure of the single-stage charge pump CP2 is identical to that of the single-stage charge pump CP 1.
This low ripple charge pump circuit is low ripple boost circuit, and in this circuit, the capacitance value of electric capacity C3 ~ C5 (the capacitance value is pF magnitude) is very little can guarantee the low ripple of charge pump circuit output voltage to the chip area that little electric capacity occupy is less, thereby is favorable to practicing thrift the occupation space of charge pump in whole fortune is put. In the case where the input clock frequency (i.e., the frequency of the external input clock signal) is fixed, the output voltage ripple of the charge pump is related to the output capacitance and the load current, and the larger the output capacitance, the smaller the load current, and the smaller the output voltage ripple. The single-stage charge pump CP1 needs to provide output current to the voltage output terminal through the NMOS transistor N17, and therefore, the output voltage ripple is large; the single stage charge pump CP2 need not provide output current, and thus the output voltage ripple is very small. Since the NMOS transistor N17 operates in the saturation region, as long as the output voltage ripple of the single-stage charge pump CP1 is not so large as to force the NMOS transistor N17 to enter the linear region, the voltage ripple at the source end of the NMOS transistor N17 (i.e., at the output end of the low-ripple charge pump) is kept very small, so as to ensure that the voltage output of the low-ripple charge pump is kept in a relatively stable low-ripple state (i.e., in a state where the voltage ripple is small), thereby reducing the negative effects (requiring a relatively large area to implement the capacitor, and the output voltage ripple affecting the operation of the operational amplifier main circuit through the feedthrough) caused by the introduction of the charge pump to a very low level.
The specific structure of the differential transconductance input stage is as follows: the source electrodes of the PMOS tubes P9 and P10 are connected with the output end of the charge pump, the grid electrode of the PMOS tube P9 is respectively connected with the grid electrode of the PMOS tube P10, one end of the resistor R3 and the drain electrode of the PMOS tube P11, the grid electrode of the PMOS tube P11 is respectively connected with the grid electrode of the PMOS tube P12, the other end of the resistor R3 and the drain electrode of the NMOS tube N3 in the bias circuit, the drain electrode of the PMOS tube P12 is respectively connected with the source electrodes of the PMOS tubes P13 and P14, the drain electrode of the PMOS tube P13 is respectively connected with the NMOS tubes N5 and N11 in the differential transconductance input stage, the drain electrode of the PMOS tube P14 is respectively connected with the NMOS tubes N6 and N12 in the differential transconductance input stage, the grid electrode of the PMOS tube P13 is an inverting input end, and the grid electrode of the PMOS tube P14 is an non-inverting input end.
In the differential transconductance input stage, a low ripple charge pump drives a voltage source V under the action of an input clock signalDDIs raised to about 2 x VDD-VGSAnd the output end of the first current mirror is connected with the source electrode of the differential pair, and the drain electrode of the differential pair is connected with the trans-impedance stage of the differential-to-single end. A pair of input differential pairs (in the embodiment, a PMOS tube differential pair: PMOS tube P13 and PMOS tube P14) are adopted as input stages, and the current drawn by a tail current source (PMOS tube P10) comes from a low-ripple charge pump. The local characteristic means that the input-output characteristic of the first current mirror has little relation to the ripple of the voltage source because the source of the PMOS transistor P9 and the source of the PMOS transistor P10 are connected together due to the local characteristic of the first current mirror. Even if external interference such as ripples and the like exists, all devices in the first current mirror are interfered together, and the grid-source voltages of the PMOS tube P9 and the PMOS tube P10 are ensured to be the same, so that the output voltage ripples (namely, voltage fluctuations) of the charge pump have almost no influence on the first current mirror comprising the PMOS tubes P9 and P10. The current provided by the tail current source (PMOS transistor P10) is constant, the current of the tail current source is determined by the reference current IREF and the size ratio of the PMOS transistor and the NMOS transistor which are matched with each other, therefore,the charge pump can meet the requirement of equivalent input transconductance fluctuation flatness, and the bias current of the input stage hardly changes along with the change of the common-mode input voltage. In addition, due to the adoption of the low-ripple charge pump, the negative effects (the capacitor needs to be realized in a larger area, and the output voltage ripple influences the operation of the operational amplifier main body circuit through feed-through) caused by the additional introduction of the charge pump are also very low.
The low-ripple charge pump and the first current mirror (comprising PMOS tubes P9-P12 and a resistor R3) provide tail current sources for the input differential pair (comprising PMOS tubes P13 and P14). The first current mirror of the tail current source is in a cascode structure, so that the constancy of input bias current in the whole input voltage range is ensured; and secondly, the PMOS pipe P10 is prevented from bearing excessive drain-source voltage under extreme conditions, so that the device is prevented from being damaged or the service life of the device is reduced.
The bias circuit comprises a first bias voltage generating unit and a first switch unit, wherein the first bias voltage generating unit is used for generating a bias voltage VB2, the first switch unit is used for conducting control on the bias voltage and the bias current, the first bias voltage generating unit comprises PMOS tubes P1 and P5, the first switch unit comprises NMOS tubes N1-N4, N7-N10 and a resistor R1, the input end of the first bias voltage generating unit is connected with a voltage source VDD, the output end of the first bias voltage generating unit is connected with the first switch unit, and meanwhile, the voltage source VDD is connected with the first switch unit after being connected with a resistor R1 in series. The specific structure of the bias circuit is as follows: the source electrode of the PMOS tube P1 is respectively connected with a voltage source VDD, one end of a resistor R1, the grid electrodes of NMOS tubes N1 and N2, the drain electrode of the PMOS tube P1 is respectively connected with the grid electrode of a PMOS tube P1 and the source electrode of the PMOS tube P5, the grid electrode of the PMOS tube P5 is respectively connected with the grid electrode of the PMOS tube P5 and the source electrode of the NMOS tube N2, the other end of the resistor R1 is respectively connected with the source electrode of NMOS tube N1 and the grid electrode of NMOS tube N7, the grid electrodes of NMOS tubes N1-N4 are connected, the grid electrodes of NMOS tubes N7-N10 are connected, the source electrodes of NMOS tubes N1, N2, N3 and N4 are correspondingly connected with the drain electrodes of NMOS tubes N7, N8, N9 and N10, and the source electrodes of NMOS tubes N7, N8, N9 and N10 are grounded.
In the bias circuit, a voltage source VDD generates bias voltages VB2 and VB3 through PMOS tubes P1 and P5 and is connected with a reference current IREFActing together on the first switchThe control ends of NMOS transistors N1-N4 and N7-N10 in the switch unit are also transmitted to NMOS transistors N1-N4 and N7-N10 through currents of PMOS transistors P16 and P17, so that the NMOS transistors N1-N4 and N7-N10 are conducted to work, and driving voltage is provided for the PMOS transistors P18 and P19 in the differential-to-single-ended transimpedance stage.
The differential-to-single-ended trans-impedance stage comprises a second bias voltage generation unit, a second current mirror, a second switch unit, a current buffer unit and a third switch unit, wherein the second bias voltage generation unit is used for generating a first bias voltage VB, the second current mirror is used for mirroring the bias current of the second bias voltage generation unit, the second switch unit and the third switch unit are used for conducting control, the current buffer unit is used for providing push-pull voltage, the second bias voltage generation unit comprises PMOS tubes P16 and P17, the second current mirror comprises PMOS tubes P2, P3, P6 and P7, the second switch unit comprises PMOS tubes P18, P19, N16, N15 and N14, the third switch unit comprises PMOS tubes P4 and P8, the current buffer unit comprises NMOS tubes N5, N6, N11 and N12, the input ends of the second bias voltage generation unit, the second current mirror and the third switch unit are all connected with the input end of a voltage source and the input end of a charge pump VDD, the output ends of the second bias voltage generating unit, the second current mirror and the third switching unit are connected with the second switching unit, the output end of the second switching unit is connected with the input end of the current buffering unit, and the output end of the current buffering unit is connected with the control end of the push-pull output stage.
The specific circuit structure of the trans-impedance stage for converting the difference into the single end is as follows: the source electrodes of the PMOS tubes P, P and P are respectively connected with a voltage source VDD, the input end of the charge pump, the other end of the capacitor C, the source electrode of the PMOS tube P in the push-pull output stage, the grid electrodes of the PMOS tubes P, P and P are connected, the drain electrodes of the PMOS tubes P and P are correspondingly connected with the source electrodes of the PMOS tubes P and P one by one, the grid electrodes of the PMOS tubes P, P and P are connected, the drain electrode of the PMOS tube P is connected with the source electrode of the PMOS tube P, the grid electrodes of the PMOS tubes P are connected with the drain electrode and the grid electrode of the PMOS tube P, the drain electrodes of the NMOS tubes N and N are connected, the source electrode of the NMOS tube N is respectively connected with the drain electrode of the PMOS tube P, the source electrode of the NMOS tube N and the NMOS tube N in the push-pull output stage, the grid electrode of the NMOS tube N is respectively connected with the grid electrode of the NMOS tube N and the drain electrode of the PMOS tube P, the NMOS transistors N11, N12, N14 are grounded.
In the differential-to-single-ended trans-impedance stage, the NMOS tubes N5, N6, N11 and N12 form a current buffer stage of the differential-to-single-ended trans-impedance stage (namely the trans-impedance stage for converting differential current into single-ended current), only 1 current buffer stage is needed in the invention, while 2 current mirrors are needed in the traditional rail-to-rail operational amplifier, and the upper current mirror and the lower current mirror are respectively 1 current buffer stage, so that compared with the traditional rail-to-rail operational amplifier, the circuit structure of the differential-to-single-ended trans-impedance stage is simplified. The current signal output by the NMOS transistor N6 is converted into a voltage signal with the same phase and amplitude at the drain of the NMOS transistor N6 and the drain of the PMOS transistor P7, and the NMOS transistor N13 and the PMOS transistor P15 in the subsequent push-pull output stage are driven to be conducted and output in a push-pull mode.
The push-pull output stage comprises a PMOS tube P15, an NMOS tube N13, capacitors C1, C2, a resistor R4 and a resistor R5, the drain electrode of the PMOS tube P15 and the drain electrode of the NMOS tube N13 are connected and are an output end OUT of the operational transconductance amplifier, the source electrode of the NMOS tube N13 is grounded, the other end of the resistor R4 is connected with the capacitor C1 in series and then is connected with the output end OUT, and the other end of the resistor R5 is connected with the capacitor C2 in series and then is connected with the output end OUT.
The implementation conditions of the rail-to-rail input of the present application are: the voltage source VDD of the whole circuit meets VDD>VGS+VGSP13-14+2Vdsat, where VGSN17Refers to the gate-source voltage, VGS, of the NMOS transistor N17P13-14The gate-source voltages of PMOS tubes P13 and P14 are indicated, Vddsat indicates the drain-source saturation voltage drop of the PMOS tubes P10 and P12 (assuming that the drain-source saturation voltage drop is equal), and if the voltage source VDD is small, the gate bias voltages of the PMOS tubes P11 and P12 are the same as the bias voltages of the NMOS tubes N1-N4, so that the reliable rail-to-rail input of the operational transconductance amplifier can be realized. The current of a voltage source VDD is subjected to voltage conversion through a charge pump, the converted voltage (or current) is mirrored to PMOS tubes P1 and P5 under the action of a first current mirror (comprising PMOS tubes P9-P12) so as to provide bias current for a post-stage circuit, similarly, the current at the input end of the low-ripple charge pump is mirrored to the PMOS tubes P4 and P8 through a second current mirror (comprising PMOS tubes P2, P3, P6 and P7) so as to provide current for NMOS tubes N15, N16 and PMOS tubes P18 and P19, so that voltage generated by NMOS tubes N5, N6, N11 and N12 is pushedAnd driving a push-pull output stage to output current in a voltage push-pull mode, thereby realizing analog signal operation.
In the operational transconductance amplifier, the bias current of the PMOS tubes P13 and P14 (transconductance stage) of the differential input pair and the bias current of the current buffer stage for converting the differential current into the single-ended current are from the same reference current IREFAnd the differential input pair can always work normally. The bias current does not change along with the change of the common-mode input voltage, and only increases along with the increase of the temperature so as to compensate the negative temperature coefficient of the carrier mobility; from the voltage perspective, when the temperature increases, the threshold voltages of the PMOS transistor and the NMOS transistor become smaller, but the overdrive voltage increases, and the temperature coefficient of VGS decreases, so that the bias voltage VB3 has a sufficient design space.
The invention has the characteristics of simple circuit and low ripple wave charge pump, and fundamentally solves the problem of small common mode input voltage range allowed by the differential input stage of the traditional operational transconductance amplifier. Therefore, a large amount of auxiliary circuits such as a triple current mirror and the like do not need to be introduced; in addition, although the output voltage of the charge pump has small ripples (voltage fluctuation), the influence of the voltage fluctuation is shielded by the first current mirror to a great extent, under the action of the low-ripple charge pump and the first current mirror, the common-mode input voltage range of the differential transconductance input stage is enlarged, and the basic constancy of the equivalent input transconductance and the basic constancy of the input stage bias current are ensured, so that the working temperature range which can be adapted by the whole rail-to-rail input-output operational transconductance amplifier is enlarged.
In summary, the rail-to-rail input operational transconductance amplifier of the present invention has the following advantages:
(1) the main circuit part for amplifying signals adopts a mature traditional structure, and the additionally introduced low-ripple charge pump only provides power for a group of current mirrors to generate a tail current source required by a rail-to-rail input stage, so that the equivalent input transconductance in the whole common-mode input voltage range is almost constant, and a transconductance compensation circuit is not required like a traditional rail-to-rail input and output operational transconductance amplifier. Under the action of a charge pump, the bias current of the differential transconductance input stage hardly changes along with the change of the common-mode input voltage, so that the differential transconductance input stage has the characteristic of constant transconductance and does not need to design a complex additional auxiliary circuit;
(2) the bias current of the differential transconductance input stage hardly changes along with the change of the common-mode input voltage, which is beneficial to simplifying the design of a post-stage circuit to adapt to the requirement of a wide working temperature range;
(3) the charge pump works in a switch mode, is less influenced by temperature change, and is further favorable for meeting the application requirement of a wide temperature range;
(4) the low ripple charge pump utilizes the characteristic of an NMOS tube biased in a saturation region, and the voltage fluctuation influence brought by the charge pump can be reduced to a very low level by 3 pF stage capacitors, so that the cost for additionally introducing the charge pump is reduced.
The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (9)

1. An input and output operational transconductance amplifier based on a low ripple charge pump comprises a biasing circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage and a push-pull output stage which are sequentially connected;
the bias circuit is used for providing a bias voltage and a bias current;
the differential transconductance input stage is used for converting a differential input voltage into a differential current;
the differential-to-single-ended trans-impedance stage is used for converting differential current into single-ended current;
the push-pull output stage converts the single-ended current into current in a push-pull mode and outputs the current;
the differential transconductance input stage is characterized in that the differential transconductance input stage comprises a low ripple charge pump, a first current mirror and a differential pair, the low ripple charge pump is used for generating a voltage source higher than a voltage source VDD and supplying power to the first current mirror, the first current mirror is used for mirroring a bias current generated by the bias circuit, two input ends of the low ripple charge pump are respectively connected with an external input clock signal and the voltage source VDD, an output end of the low ripple charge pump is connected with a power supply end of the first current mirror, an output of the first current mirror is connected with a source electrode of the differential pair, a drain electrode of the differential pair is connected with a differential to single-ended transimpedance stage, an output of the differential to single-ended transimpedance stage is connected with an input of the push-pull output stage, the first current mirror comprises PMOS tubes P9-P12 and a resistor R3, the differential pair comprises PMOS tubes P13 and P14, and an output end of the low ripple charge pump is respectively connected with the differential pair through the first current mirror, The bias circuit.
2. The input-output operational transconductance amplifier based on the low-ripple charge pump according to claim 1, wherein the low-ripple charge pump comprises a PMOS transistor N17, capacitors C3, C4, C5, single-stage charge pumps CP1 and CP2, wherein 1 pin of the single-stage charge pump CP1 is respectively connected to the voltage source VDD and the single-stage charge pump CP2, 2 pins of the single-stage charge pump CP2 are respectively connected to one end of a capacitor C3 and a source of the PMOS transistor N17, 2 pins of the single-stage charge pump CP2 are respectively connected to one end of a capacitor C4, a drain of the PMOS transistor N17 is connected to one end of a capacitor C5, the other ends of the capacitors C3, C4 and C5 are grounded, and 3 pins of the single-stage charge pumps CP1 and CP2 are connected to an external input clock signal.
3. The input-output operational transconductance amplifier based on the low-ripple charge pump according to claim 2, wherein the single-stage charge pump CP comprises PMOS transistors P, NMOS transistors N, and capacitors C, wherein the PMOS transistor P is connected to a gate of the NMOS transistor N and a drain of the PMOS transistor P, sources of the NMOS transistors N, N are connected to a voltage source VDD, sources of the PMOS transistors P, P are voltage output terminals, sources of the NMOS transistors N, N are correspondingly connected to one ends of the capacitors C, the other end of the capacitor C is connected to a gate of the PMOS transistor P, NMOS transistor N, respectively, the other end of the capacitor C is connected to a drain of the PMOS transistor P and a drain of the NMOS transistor N, and gates of the PMOS transistor P and NMOS transistor N are connected to an external input clock signal, the sources of the PMOS tubes P23 and P22 are respectively connected with a voltage source VDD, and the sources of the NMOS tubes N20 and N23 are respectively grounded; the structure of the single-stage charge pump CP2 is identical to that of the single-stage charge pump CP 1.
4. The input-output operational transconductance amplifier based on the low-ripple charge pump according to claim 3, wherein sources of PMOS transistors P9 and P10 of the first current mirror are connected to an output end of the charge pump, gates of the PMOS transistors P9 are respectively connected to a gate of the PMOS transistor P10, one end of a resistor R3 and a drain of a PMOS transistor P11, gates of the PMOS transistors P11 are respectively connected to a gate of the PMOS transistor P12, the other end of the resistor R3 and a drain of an NMOS transistor N3 in the bias circuit, drains of the PMOS transistors P12 are respectively connected to sources of the PMOS transistors P13 and P14, drains of the PMOS transistors P13 are respectively connected to NMOS transistors N5 and N11 in the differential transconductance input stage, drains of the PMOS transistors P14 are respectively connected to NMOS transistors N6 and N12 in the differential transconductance input stage, gates of the PMOS transistors P13 are inverting input terminals, and gates of the PMOS transistors P14 are in-phase.
5. The input-output operational transconductance amplifier based on the low ripple charge pump according to claim 4, wherein the bias circuit comprises a first bias voltage generating unit and a first switching unit, the first bias voltage generating unit is configured to generate a bias voltage VB2, the first switching unit is configured to conduct and control a bias voltage and a bias current, the first bias voltage generating unit comprises PMOS transistors P1 and P5, the first switching unit comprises NMOS transistors N1-N4, N7-N10 and resistors R1 and R2, an input end of the first bias voltage generating unit is connected to a voltage source VDD, an output end of the first bias voltage generating unit is connected to the first switching unit, and the voltage source VDD is connected to the first switching unit after being connected to a resistor R1 in series.
6. The input-output operational transconductance amplifier based on the low-ripple charge pump according to claim 5, wherein a source of the PMOS transistor P1 is connected to a voltage source VDD, one end of a resistor R1, a gate of an NMOS transistor N1 and a gate of an N2, a drain of the PMOS transistor P1 is connected to a source of the PMOS transistor P5, a gate of the PMOS transistor P5 is connected to a source of the NMOS transistor N5 and one end of a resistor R5, the other end of the resistor R5 is connected to a drain of the PMOS transistor P5 and a gate of the PMOS transistor P5, the other end of the resistor R5 is connected to a source of the NMOS transistor N5 and a gate of the NMOS transistor N5, gates of the NMOS transistors N5-N5, the gates of the NMOS transistors N5-N5 and N5, and the sources of the NMOS transistors N5, N5 and N5 are connected to the ground, and the sources of the NMOS transistors N5 and N5.
7. The low-ripple charge pump-based input-output operational transconductance amplifier of claim 6, wherein the differential-to-single-ended transimpedance stage comprises a second bias voltage generation unit for generating the first bias voltage VB, a second current mirror for mirroring the bias current of the second bias voltage generation unit, a second switching unit for conducting control, a current buffer unit for providing a push-pull voltage, and resistors R4 and R5, the second bias voltage generation unit comprises PMOS tubes P16 and P17, the second current mirror comprises PMOS tubes P2, P3, P6 and P7, the second switching unit comprises PMOS tubes P18, P19, N16, N15 and N14, and the third switching unit comprises PMOS tubes P4 and P4, P8, the current buffer unit includes NMOS pipe N5, N6, N11, N12, the input end of second bias voltage generating unit, second current mirror, third switch unit all connect voltage source VDD, the input end of charge pump, the output of second bias voltage generating unit, second current mirror, third switch unit connect the second switch unit, the output of second switch unit connects the input of current buffer unit, and the output of current buffer unit connects the control end of push-pull output stage.
8. The input-output operational transconductance amplifier according to claim 7, wherein the sources of the PMOS transistors P2, P3, and P4 are connected to a voltage source VDD, the input terminal of the charge pump, the source of the PMOS transistor P16, and the source of the PMOS transistor P15 in the push-pull output stage, the gates of the PMOS transistors P2, P3, and P3 are connected, the drains of the PMOS transistors P3 and P3 are connected to the sources of the PMOS transistors P3, and P3 in a one-to-one correspondence, the gates of the PMOS transistors P3, and P3 are connected, the drain of the PMOS transistor P3 is connected to the source of the PMOS transistor P3, the gates of the PMOS transistors P3, and P3 are connected, the sources of the PMOS transistors P3, N3 and N3 are connected to the gates of the NMOS transistors P3, and the drains of the PMOS transistors P3, N3 are connected to the gates of the NMOS 3, and the drains of the N3, and the gates of the N3 are connected to the drains of the NMOS 3, and the drains of the PMOS transistors P3, the N3, and the drains of the N3 are connected to the sources of the N3, respectively, The source electrode of the NMOS tube N16, the grid electrode of an NMOS tube N13 in the push-pull output stage and one end of a resistor R5 are connected, the grid electrode of the NMOS tube N16 is respectively connected with the grid electrode of the NMOS tube N15 and the drain electrode of a PMOS tube P8, the source electrode of the PMOS tube P8 is connected with the drain electrode of the PMOS tube P4, the drain electrode of the PMOS tube P7 is respectively connected with one end of the resistor R4, the source electrode of the PMOS tube P19 and the drain electrode of the NMOS tube N6, and the NMOS tubes N11, N12 and N14 are grounded.
9. The input-output operational transconductance amplifier based on the low-ripple charge pump according to claim 8, wherein the push-pull output stage comprises the PMOS transistor P15, an NMOS transistor N13, capacitors C1, C2, resistors R4 and R5, a drain of the PMOS transistor P15 and a drain of the NMOS transistor N13 are connected and are an output terminal OUT of the operational transconductance amplifier, a source of the NMOS transistor N13 is grounded, the other end of the resistor R4 is connected in series with the capacitor C1 and then connected with the output terminal OUT, and the other end of the resistor R5 is connected in series with the capacitor C2 and then connected with the output terminal OUT.
CN202210318563.XA 2022-03-29 2022-03-29 Rail-to-rail input and output operational transconductance amplifier based on low ripple charge pump Pending CN114710124A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115733447A (en) * 2022-11-16 2023-03-03 北京无线电测量研究所 Rail-to-rail operational amplifier with temperature compensation
CN115955205A (en) * 2023-01-16 2023-04-11 无锡众享科技有限公司 Transconductance amplifier for power over Ethernet
CN117411445A (en) * 2023-12-12 2024-01-16 成都明夷电子科技有限公司 Broadband variable gain amplifier for optical receiver

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115733447A (en) * 2022-11-16 2023-03-03 北京无线电测量研究所 Rail-to-rail operational amplifier with temperature compensation
CN115733447B (en) * 2022-11-16 2024-05-03 北京无线电测量研究所 Rail-to-rail operational amplifier with temperature compensation
CN115955205A (en) * 2023-01-16 2023-04-11 无锡众享科技有限公司 Transconductance amplifier for power over Ethernet
CN115955205B (en) * 2023-01-16 2023-11-28 无锡众享科技有限公司 Transconductance amplifier for power over Ethernet
CN117411445A (en) * 2023-12-12 2024-01-16 成都明夷电子科技有限公司 Broadband variable gain amplifier for optical receiver
CN117411445B (en) * 2023-12-12 2024-03-12 成都明夷电子科技有限公司 Broadband variable gain amplifier for optical receiver

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