CN114710124A - Rail-to-rail input and output operational transconductance amplifier based on low ripple charge pump - Google Patents

Abstract

The invention discloses an operational transconductance amplifier based on a low ripple charge pump, which has simple and reasonable circuit structure design, can improve the voltage fluctuation flattening effect of the equivalent input transconductance, can meet the application requirement of wide temperature range, the differential transconductance input stage comprises a low ripple charge pump, a first current mirror and a differential pair, two input ends of the low ripple charge pump are respectively connected with an external input clock signal and a voltage source VDD, an output end of the low ripple charge pump is connected with a power supply end of the first current mirror, an output end of the first current mirror is connected with a source electrode of the differential pair, a drain electrode of the differential pair is connected with the differential to single-ended transimpedance stage, the first current mirror comprises PMOS tubes P9-P12 and a resistor R3, the differential pair comprises PMOS tubes P13 and P14, and an output end of the push-pull output stage is an output end of the operational transconductance amplifier.

Description

Rail-to-Rail Input-Output Operational Transconductance Amplifier Based on Low Ripple Charge Pump

technical field

The invention relates to the technical field of integrated circuits, in particular to a rail-to-rail input operational transconductance amplifier based on a low-ripple charge pump.

Background technique

The operational transconductance amplifier is a common unit in the design of analog CMOS integrated circuits. It is used to convert the input differential voltage signal into an output current. Combined with its negative feedback network, it can realize various analog signal operations. It is also often referred to as "op amp". In the application of low operating voltage analog circuit with limited signal swing, it is often required that the input and output of the operational transconductance amplifier can achieve rail-to-rail to obtain the maximum voltage signal swing, namely: (1) The designed operation The common-mode input level of the transconductance amplifier can approximately span the entire range from the negative supply voltage to the positive supply voltage, that is, input rail-to-rail; (2) the output voltage swing of the designed operational transconductance amplifier can reach approximately from The entire range from the negative supply voltage to the positive supply voltage, that is, output rail-to-rail.

When achieving the above two goals, it is necessary to keep the small signal parameters such as the equivalent input transconductance of the operational transconductance amplifier basically constant to ensure the stability of the operational amplifier under various working conditions. Voltage dependence is the main source of nonlinearity. In the current common circuit structure of rail-to-rail input and output operational transconductance amplifiers, rail-to-rail output is realized by push-pull output (ie, class AB amplifier). The main difference between existing operational transconductance amplifiers is: rail-to-rail output Rail input and substantially constant equivalent input transconductance are implemented differently. However, most of the existing rail-to-rail inputs and substantially constant equivalent input transconductance have complicated circuit structures, and can only control the variation of the equivalent input transconductance within a small range.

At present, the solution to the above-mentioned small common-mode input range is to set up PMOS differential pair transistors and NMOS differential pair transistors at the same time, and expand the allowable common-mode input voltage range through the mutual cooperation of the two pairs of differential pair transistors. However, in the actual working process, It is necessary to ensure that the opening and closing of the two pairs of differential pair tubes can be perfectly connected, which greatly increases the difficulty of the process. Therefore, the actual traditional rail-to-rail input stage usually needs to be equipped with a triple current mirror: when the PMOS differential pair is turned off, the tail current of the PMOS differential pair is amplified by three times and then sent to the NMOS differential pair; when the NMOS differential pair is turned off, The tail current of the NMOS differential pair is amplified by three times and then sent to the PMOS differential pair. In this way, the equivalent input transconductance can be approximately flat in the entire input voltage range, but the triple current mirror technology has the following disadvantages: (1) The equivalent input transconductance changes with the input voltage. Under normal circumstances, the fluctuation of the equivalent input transconductance can only be controlled within 15%, and the fluctuation of the equivalent input transconductance has a poor effect of flattening; (2) The triple current mirror technology makes the bias current of the input transconductance stage vary with The input voltage changes, which makes the design of the post-stage circuit more complicated. This problem is exacerbated in wide temperature range applications.

SUMMARY OF THE INVENTION

In view of the above problems existing in the prior art, the present invention provides a rail-to-rail input-output operational transconductance amplifier based on a low-ripple charge pump, whose circuit structure design is simple and reasonable, and can improve the voltage fluctuation of the equivalent input transconductance Flat effect, while meeting the application requirements of a wide temperature range.

To achieve the above object, the present invention adopts the following technical solutions:

A rail-to-rail input-output operational transconductance amplifier based on a low-ripple charge pump, comprising a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage, which are connected in sequence,

the bias circuit is used for providing bias voltage and bias current;

the differential transconductance input stage is used to convert the differential input voltage into a differential current;

The differential-to-single-ended transimpedance stage is used to convert the differential current into a single-ended current;

The push-pull output stage converts the single-ended current into a current output in a push-pull manner;

It is characterized in that, the differential transconductance input stage includes a charge pump, a first current mirror, and a differential pair, the charge pump is a low-ripple charge pump, and the charge pump is used to boost the voltage source VDD and provide The first current mirror is used for power supply, and the first current mirror is used to mirror the bias current generated by the bias circuit. The two input ends of the charge pump are respectively connected to the external input clock signal and the voltage source VDD. The output terminal of the charge pump is connected to the power terminal of the first current mirror, the output of the first current mirror is respectively connected to the source of the differential pair, and the drain of the differential pair is connected to the differential-to-single-ended transimpedance stage , the output of the differential-to-single-ended transimpedance stage is connected to the input of the push-pull output stage, the first current mirror includes PMOS transistors P9 to PMOS transistors P12, and the differential pair includes PMOS transistors P13 and PMOS transistors P14. The voltage output terminal of the charge pump is respectively connected to the differential pair and the bias circuit through the first current mirror.

It is further characterized in that,

The low-ripple charge pump includes a PMOS transistor N17, capacitors C3, C4, and C5, and single-stage charge pumps CP1 and CP2. Pin 1 of the single-stage charge pump CP1 is respectively connected to the voltage source VDD and the single-stage charge pump. CP2, the 2 pins of the single-stage charge pump CP2 are respectively connected to one end of the capacitor C3 and the source of the PMOS transistor N17, the 2 pins of the single-stage charge pump CP2 are respectively connected to one end of the capacitor C4, the drain of the PMOS transistor N17 The pole is connected to one end of the capacitor C5, the other end of the capacitors C3, C4, and C5 is grounded, and the 3 pins of the single-stage charge pumps CP1 and CP2 are connected to the external input clock signal;

The single-stage charge pump CP1 includes PMOS transistors P20, P21, P22, P23, NMOS transistors N18, N19, N20, N21, capacitors C6, C7, the gates of the PMOS transistor P20 and the NMOS transistor N18, and the PMOS transistors. The drain of P21 is connected to the drain, the PMOS transistor P21 is connected to the gate of the NMOS transistor N19 and the drain of the PMOS transistor P20, the sources of the NMOS transistors N18 and N19 are connected to the voltage source VDD, the PMOS transistors P20, The source of P21 is the voltage output terminal, the sources of the NMOS transistors N18 and N19 are connected to one end of the capacitors C6 and C7 in a one-to-one correspondence, and the other end of the capacitor C6 is respectively connected to the PMOS transistors P22, P23, NMOS transistors N20, The gate of N21, the other end of the capacitor C7 is connected to the drain of the PMOS transistor P23 and the drain of the NMOS transistor N21 respectively, the gate of the PMOS transistor P22 and the gate of the NMOS transistor N21 are connected to an external input clock signal, The sources of the PMOS transistors P23 and P22 are respectively connected to the voltage source VDD, and the sources of the NMOS transistors N20 and N23 are respectively grounded; the structure of the single-stage charge pump CP2 is consistent with the structure of the single-stage charge pump CP1;

The bias circuit includes a first bias voltage generation unit and a first switch unit, the first bias voltage generation unit is used for generating the bias voltage VB2, and the first switch unit is used for The first bias voltage generating unit includes PMOS transistors P1 and P5, the first switching unit includes NMOS transistors N1-N4, N7-N10, and resistors R1 and R2. The input end of the voltage generating unit is connected to the voltage source VDD, the output end is connected to the first switch unit, and at the same time, the voltage source VDD is connected to the first switch unit after being connected in series with the resistor R1;

The differential-to-single-ended transimpedance stage includes a second bias voltage generation unit, a second current mirror, a second switch unit, a current buffer unit, and a third switch unit, and the second bias voltage generation unit is used to generate the first bias voltage. a bias voltage VB, the second current mirror is used for mirroring the bias current of the second bias voltage generating unit, the second switch unit and the third switch unit are used for conduction control, the current buffer unit is used for For providing a push-pull voltage, the second bias voltage generating unit includes PMOS transistors P16 and P17, the second current mirror includes PMOS transistors P2, P3, P6, and P7, and the second switching unit includes PMOS transistors P18, P19, N16, N15, N14, the third switch unit includes PMOS transistors P4, P8, the current buffer unit includes NMOS transistors N5, N6, N11, N12, the second bias voltage generating unit, the second current The input terminals of the mirror and the third switch unit are all connected to the voltage source VDD and the input terminal of the charge pump, and the outputs of the second bias voltage generation unit, the second current mirror and the third switch unit are connected to the second switch a unit, the output of the second switch unit is connected to the input of the current buffer unit, and the output of the current buffer unit is connected to the control terminal of the push-pull output stage;

The push-pull output stage includes the PMOS transistor P15, the NMOS transistor N13, the capacitors C1, C2, and the resistors R4, R5. The drain of the PMOS transistor P15 and the drain of the NMOS transistor N13 are connected to each other and are the source of the operational transconductance amplifier. Output terminal OUT, the source of the NMOS transistor N13 is grounded, the other end of the resistor R4 is connected in series with the capacitor C1 and then connected to the output terminal OUT, and the other end of the resistor R5 is connected in series with the capacitor C2 and then connected to the output terminal OUT.

By adopting the above structure and method of the present invention, the following beneficial effects can be achieved: the present application is provided with a low-ripple charge pump in the differential transconductance input stage of the operational transconductance amplifier, and the low-ripple charge pump has the advantages of simple design and little influence by temperature changes. Therefore, the low-ripple charge pump provides a higher voltage power supply for the first current mirror of the differential transconductance input stage, which solves the problem that the allowable common-mode input voltage range of the differential transconductance input stage cannot reach rail-to-rail.

In addition, the output end of the charge pump is provided with a first current mirror, which can suppress the fluctuation of the output voltage of the charge pump, so that the bias current of the input stage is hardly affected by the input clock signal of the charge pump, so it does not need Setting the triple current mirror satisfies the requirement of constant equivalent input transconductance of the differential transconductance input stage, that is, a constant transconductance can be obtained without designing a complicated additional auxiliary circuit structure to suppress voltage fluctuation, which simplifies the circuit structure. In addition, the setting of the low ripple charge pump and the first current mirror makes the bias current of the differential transconductance input stage not change with the change of the common mode input voltage, which is beneficial to simplify the design of the subsequent stage circuit to adapt to a wide operating temperature range, so as to meet the application requirements for a wide temperature range.

Description of drawings

Figure 1 is a circuit schematic diagram of two differential pairs in a traditional operational transconductance amplifier;

Figure 2 is a graph of the equivalent input transconductance as a function of the input voltage source VDD;

Fig. 3 is the circuit schematic diagram of the rail-to-rail input stage in the conventional operational transconductance amplifier;

4 is a circuit schematic diagram of an operational transconductance amplifier of the present invention;

Fig. 5 is the circuit schematic diagram of the low ripple charge pump of the present invention;

FIG. 6 is a schematic circuit diagram of the single-stage charge pump CP1/electrode charge pump CP2 in the low-ripple charge pump of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be noted that the The terms "comprising" and "having" and any variations thereof in the description and claims and the above-mentioned drawings are intended to cover non-exclusive inclusion, for example, a process, method, apparatus, product comprising a series of steps or units Or apparatus is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to the process, method, product or apparatus.

The operational transconductance amplifier combined with the negative feedback network can realize various analog signal operations. Some applications of the operational transconductance amplifier (op amp) require that the input and output of the operational transconductance amplifier can achieve rail-to-rail, traditional rail-to-rail input It is mainly realized by a pair of differential pairs of PMOS transistors and a pair of differential pairs of NMOS transistors. As shown in Figure 1, when the voltage value of the input voltage source VDD (ie, the voltage source VDD) is relatively low, the PMOS transistors composed of MP10 and MP20 The differential pair realizes the function of differential transconductance conversion; when the voltage value of the input voltage source VDD is relatively high, the differential pair of NMOS transistors composed of MN10 and MN20 realizes the function of differential transconductance conversion; if the input voltage source VDD is in the middle value, the two pairs The differential pair will input transconductance at the same time, as shown in Figure 2. In Figure 2, the vertical axis g _m represents the equivalent input transconductance, and the horizontal axis represents the voltage of the voltage source VDD. It can be seen from Figure 2 that the equivalent input transconductance varies greatly with the change of the input voltage source VDD, unless the value of the power supply voltage just makes the closing of the differential pair of NMOS transistors and the opening of the differential pair of PMOS transistors perfectly connected, but The existing technology cannot achieve this perfect connection.

The dependence of the op amp's small-signal parameters on the input voltage source VDD is the main source of nonlinearity, so traditional rail-to-rail input stages usually require a triple current mirror to achieve an approximation of the equivalent input transconductance over the entire input voltage range. flat. The implementation circuit of the traditional rail-to-rail input stage is shown in Figure 3. The triple current mirror includes PMOS transistors MP3 and MP5, MP1 and MP2, and NMOS transistors MN4 and MN5. The replication multiple of the current mirror is selected as three because the MOS transistor MP4 The relationship between the transconductance and its bias current is the relationship of the square root.

To sum up, the traditional rail-to-rail input stage has the following defects: (1) The equivalent input transconductance changes with the change of the input voltage source VDD. Generally, the equivalent input transconductance can only be changed when the triple current mirror is introduced. The fluctuation of is controlled within 15%, which is an important source of nonlinearity.

(2) The triple current mirror technology makes the bias current of the input transconductance stage change with the input voltage, which makes the design of the subsequent stage circuit more complicated. In applications with a wide temperature range, this problem is more serious because the threshold voltages of PMOS and NMOS tubes have a large negative temperature coefficient, and the threshold voltages of PMOS and NMOS tubes at 125°C are compared with those at -50°C. It will be 200-300mV lower, but the variation of the drain-source saturation voltage of the PMOS tube and the NMOS tube with the temperature change is very small; at the same time, the carrier mobility of the PMOS tube and the NMOS tube also has a negative temperature coefficient, that is, the higher the temperature higher, the lower the carrier mobility. Therefore, the above-mentioned traditional triple current mirror technology is greatly challenged in wide temperature range applications.

Since the carrier mobility decreases with increasing temperature, the IC design with a wide temperature range generally adopts a bias technique of constant transconductance, that is, the bias current has a positive temperature coefficient to compensate for the negative temperature coefficient of the carrier mobility. . The small-signal transconductance of PMOS transistors and NMOS transistors is the core parameter that is concerned when designing circuits. Therefore, the positive temperature coefficient of the tail current source superimposes the amplification effect of the triple current mirror, which leads to the traditional rail-to-rail operational amplifier. The design of the current buffer stage that converts differential current into single-ended current faces great challenges: the gate bias voltage of the common-gate MOS transistor must be at the minimum bias current (that is, the VGS of the differential-to-single-ended current mirror is minimum). Ensure that the common gate tube works in the saturation region, and also ensure that the differential to single-ended current mirror fully works in the saturation region to ensure the gain of the operational amplifier. The above two requirements have opposite requirements on the gate bias voltage of the common-gate MOS transistor, resulting in a very small design space, and there may even be no solution when considering complex process angles.

In order to solve the above-mentioned problems and realize the good operation of the rail-to-rail input-output operational transconductance amplifier under a wide temperature range, the present invention provides the following technical solutions. A conduction amplifier includes a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage, which are connected in sequence. Among them, the bias circuit is used to provide bias voltage and bias current, the differential transconductance input stage is used to convert the differential component of the input voltage from rail to rail of the common mode input voltage into differential current, and the differential to single-ended transimpedance stage is used for In order to convert the differential current into a single-ended voltage, the push-pull output stage uses a push-pull method to convert the voltage signal into a current output.

The differential transconductance input stage includes a low-ripple charge pump, a first current mirror, and a differential pair. The low-ripple charge pump boosts the voltage source VDD to supply power to the first current mirror, which is used for the mirror bias circuit bias current in to provide the tail current required for the differential pair. The input terminal of the low-ripple charge pump is respectively connected to the differential-to-single-ended transimpedance stage and the voltage source VDD, and the output terminal of the low-ripple charge pump is connected to the first current mirror, which is used to supply power to the first current mirror, and the first current mirror is connected to The source of the differential pair and the drain of the differential pair are connected to the differential-to-single-ended transimpedance stage. The first current mirror includes PMOS transistors P9 to PMOS transistors P12, and the differential pair includes PMOS transistors P13 and PMOS transistors P14.

As shown in Figure 5, the specific circuit structure of the low ripple charge pump includes: NMOS transistor N17, capacitors C3, C4, C5, single-stage charge pumps CP1, CP2, and the 1 pin of single-stage charge pump CP1 is respectively connected to the voltage source VDD, Single-stage charge pump CP2, the 2-pin of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C3 and the source of the NMOS transistor N17, the 2-pin of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C4, and the drain of the NMOS transistor N17 is connected One end of the capacitor C5, the other ends of the capacitors C3, C4, and C5 are grounded, and the 3 pins of the single-stage charge pumps CP1 and CP2 are connected to the external input clock signal.

As shown in Figure 6, the single-stage charge pump CP1 includes PMOS transistors P20, P21, P22, P23, NMOS transistors N18, N19, N20, N21, capacitors C6, C7, the gates of PMOS transistor P20 and NMOS transistor N18, and the gates of PMOS transistor P21. The drains are connected, the PMOS transistor P21 is connected to the gate of the NMOS transistor N19 and the drain of the PMOS transistor P20, the sources of the NMOS transistors N18 and N19 are connected to the voltage source VDD, the sources of the PMOS transistors P20 and P21 are the voltage output terminals, and the NMOS transistors The sources of N18 and N19 are connected to one end of the capacitors C6 and C7 in one-to-one correspondence. The NMOS transistors N18 and N19 are independent substrate NMOS transistors with deep N wells, and the other end of the capacitor C6 is respectively connected to the PMOS transistors P22, P23, and NMOS transistors N20. , the gate of N21, the other end of capacitor C7 is connected to the drain of PMOS transistor P23 and the drain of NMOS transistor N21 respectively, the gate of PMOS transistor P22 and the gate of NMOS transistor N21 are connected to the external input clock signal, PMOS transistors P23, P22 The sources of the NMOS transistors are respectively connected to the voltage source VDD, and the sources of the NMOS transistors N20 and N23 are respectively grounded; the structure of the single-stage charge pump CP2 is consistent with that of the single-stage charge pump CP1.

The low-ripple charge pump circuit is a low-ripple boost circuit. In this circuit, the capacitance value of capacitors C3 to C5 (capacitor value is in the order of pF) is very small to ensure low ripple of the output voltage of the charge pump circuit. And the chip area occupied by the small capacitor is small, which is beneficial to save the space occupied by the charge pump in the entire operational amplifier. When the input clock frequency (that is, the frequency of the external input clock signal) is fixed, the output voltage ripple of the charge pump is related to the output capacitor and the load current. The larger the output capacitor, the smaller the load current and the smaller the output voltage ripple. The single-stage charge pump CP1 needs to provide output current to the voltage output terminal through the NMOS transistor N17, so the output voltage ripple is large; the single-stage charge pump CP2 does not need to provide output current, so the output voltage ripple is very small. Since the NMOS transistor N17 works in the saturation region, as long as the output voltage ripple of the single-stage charge pump CP1 is not large enough to force the NMOS transistor N17 into the linear region, the source terminal of the NMOS transistor N17 (ie, the output terminal of the low-ripple charge pump) will The voltage ripple will be kept very small, thus ensuring that the voltage output of the low-ripple charge pump remains in a relatively stable low-ripple state (that is, a state with less voltage fluctuation), thereby reducing the negative impact of the introduction of the charge pump. (A large area is required to realize the capacitance, and the output voltage ripple affects the operation of the main circuit of the op amp through feedthrough) to a very low level.

The specific structure of the differential transconductance input stage is as follows: the sources of the PMOS transistors P9 and P10 are connected to the output end of the charge pump, the gate of the PMOS transistor P9 is respectively connected to the gate of the PMOS transistor P10, one end of the resistor R3, and the drain of the PMOS transistor P11. , the gate of the PMOS transistor P11 is respectively connected to the gate of the PMOS transistor P12, the other end of the resistor R3, and the drain of the NMOS transistor N3 in the bias circuit, and the drain of the PMOS transistor P12 is respectively connected to the sources of the PMOS transistors P13 and P14. The drain of the PMOS transistor P13 is respectively connected to the NMOS transistors N5 and N11 in the differential transconductance input stage, the drain of the PMOS transistor P14 is respectively connected to the NMOS transistors N6 and N12 in the differential transconductance input stage, and the gate of the PMOS transistor P13 is inverted. The input terminal, the gate of the PMOS transistor P14 is the non-inverting input terminal.

In the differential transconductance input stage, the low ripple charge pump under the action of the input clock signal boosts the voltage of the voltage source V _DD to about 2*V _DD -V _GS and then provides it to the first current mirror, the first current mirror The input of the first current mirror is connected to the bias circuit, the output of the first current mirror is connected to the source of the differential pair, and the drain of the differential pair is connected to the differential-to-single-ended transimpedance stage. A pair of input differential pairs (PMOS transistor differential pair in this case: PMOS transistor P13, PMOS transistor P14) is used as the input stage, and the current drawn by the tail current source (PMOS transistor P10) comes from a low-ripple charge pump. Due to the local characteristics of the first current mirror, the local characteristics mean that the input and output characteristics of the first current mirror have almost nothing to do with the ripple of the voltage source, because the source of the PMOS transistor P9 and the source of the PMOS transistor P10 are connected together. Even if there is external interference such as ripple, all the devices in the first current mirror are interfered together, which ensures that the gate-source voltages of the PMOS transistor P9 and the PMOS transistor P10 are the same, so the output voltage ripple (ie voltage fluctuation) of the charge pump is not enough. The first current mirror including PMOS transistors P9 and P10 has little effect. The current provided by the tail current source (PMOS transistor P10) is constant, and the current of the tail current source is determined by the reference current IREF and the size ratio of the matched PMOS and NMOS transistors. Therefore, the use of a charge pump can satisfy the equivalent input span. The requirements of the conduction wave flatness, and the bias current of the input stage is almost invariant with the common-mode input voltage. In addition, due to the adoption of a low-ripple charge pump, the negative effects of the additional introduction of the charge pump in the present invention (the need for a larger area to realize the capacitance, and the output voltage ripple affecting the operation of the main circuit of the op amp through feedthrough) are also very important. Low.

The low-ripple charge pump and the first current mirror (including PMOS transistors P9-P12 and resistor R3) provide a tail current source for the input differential pair (including PMOS transistors P13 and P14). The first current mirror that provides the tail current source here adopts a cascode structure, one is to ensure the constant input bias current in the entire input voltage range; the other is to prevent the PMOS transistor P10 from carrying excessive leakage in extreme cases source voltage to prevent damage to the device or reduce device life.

The bias circuit includes a first bias voltage generation unit and a first switch unit, the first bias voltage generation unit is used to generate the bias voltage VB2, and the first switch unit is used to conduct conduction control on the bias voltage and bias current , the first bias voltage generating unit includes PMOS transistors P1, P5, the first switching unit includes NMOS transistors N1-N4, N7-N10, and a resistor R1, the input end of the first bias voltage generating unit is connected to the voltage source VDD, and the output end The first switch unit is connected, and at the same time, the voltage source VDD is connected in series with the resistor R1 and then connected to the first switch unit. The specific structure of the bias circuit is as follows: the source of the PMOS transistor P1 is respectively connected to the voltage source VDD, one end of the resistor R1, the gates of the NMOS transistors N1 and N2, and the drain of the PMOS transistor P1 is respectively connected to the gate of the PMOS transistor P1 and the PMOS transistor P5. The source of the PMOS transistor P5 is connected to the gate of the PMOS transistor P5 and the source of the NMOS transistor N2 respectively, and the other end of the resistor R1 is respectively connected to the source of the NMOS transistor N1, the gate of the NMOS transistor N7, the NMOS transistor N1 The gates of ~N4 are connected, the gates of NMOS transistors N7~N10 are connected, the sources of NMOS transistors N1, N2, N3, and N4 are connected to the drains of NMOS transistors N7, N8, N9, and N10 in one-to-one correspondence, and NMOS transistor N7 , the sources of N8, N9, and N10 are grounded.

In the bias circuit, the voltage source VDD generates bias voltages VB2 and VB3 through the PMOS transistors P1 and P5, and acts together with the reference current I _REF on the control terminals of the NMOS transistors N1-N4 and N7-N10 in the first switch unit. At the same time, the currents passing through the PMOS transistors P16 and P17 are also delivered to the NMOS transistors N1~N4, N7~N10, so that the NMOS transistors N1~N4, N7~N10 are turned on, thereby converting the differential to single-ended transimpedance stage PMOS transistor P18 , P19 provides driving voltage.

The differential-to-single-ended transimpedance stage includes a second bias voltage generation unit, a second current mirror, a second switch unit, a current buffer unit and a third switch unit, and the second bias voltage generation unit is used to generate the first bias voltage VB, the second current mirror is used to mirror the bias current of the second bias voltage generating unit, the second switch unit and the third switch unit are used for conduction control, the current buffer unit is used to provide the push-pull voltage, the second bias The voltage generating unit includes PMOS transistors P16 and P17, the second current mirror includes PMOS transistors P2, P3, P6, and P7, the second switching unit includes PMOS transistors P18, P19, N16, N15, and N14, and the third switching unit includes PMOS transistor P4. , P8, the current buffer unit includes NMOS transistors N5, N6, N11, N12, the input terminals of the second bias voltage generating unit, the second current mirror, and the third switching unit are all connected to the voltage source VDD and the input terminal of the charge pump. The outputs of the two bias voltage generating units, the second current mirror and the third switching unit are connected to the second switching unit, the output of the second switching unit is connected to the input of the current buffer unit, and the output of the current buffer unit is connected to the control of the push-pull output stage end.

The specific circuit structure of the differential-to-single-ended transimpedance stage is as follows: the sources of the PMOS transistors P2, P3, and P4 are respectively connected to the voltage source VDD, the input end of the charge pump, the other end of the capacitor C1, the source of the PMOS transistor P16, and the push-pull output. The source of the PMOS transistor P15 in the stage is connected to the gates of the PMOS transistors P2, P3 and P4. The drains of the PMOS transistors P2 and P3 are connected to the sources of the PMOS transistors P6 and P7 one by one. The PMOS transistors P6, P7, The gate of P8 is connected, the drain of PMOS transistor P6 is connected to the source of PMOS transistor P18, the gates of PMOS transistors P17, P18 and P19 are connected, and the source of PMOS transistor P17 is connected to the drain and gate of PMOS transistor P16 respectively. The drain of the PMOS transistor P18 is connected to the source of the NMOS transistor N5 and the gates of the NMOS transistors N11 and N12 respectively. The gates of the NMOS transistors N5 and N6 are connected to each other. The source of the transistor N16, the NMOS transistor N13 in the push-pull output stage, the gate of the NMOS transistor N16 is connected to the gate of the NMOS transistor N15 and the drain of the PMOS transistor P8 respectively, and the source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P4. pole, NMOS transistors N11, N12, N14 are grounded.

In the differential-to-single-ended transimpedance stage, NMOS transistors N5, N6, N11, and N12 constitute the current buffer stage of the differential-to-single-ended transimpedance stage (ie, the transimpedance stage of differential current-to-single-ended current). The present invention only needs this 1, while traditional rail-to-rail op amps need two when using triple current mirrors, one for each upper and lower one. Therefore, compared with traditional rail-to-rail op amps, the circuit structure of the present application is simplified. The current signal output by the NMOS transistor N6 is converted into a voltage signal of approximately the same phase and the same amplitude at the drain of the NMOS transistor N6 and the drain of the PMOS transistor P7, and drives the NMOS transistors N13 and N13 in the subsequent push-pull output stage in a push-pull manner. The PMOS transistor P15 turns on and outputs.

The push-pull output stage includes PMOS transistor P15, NMOS transistor N13, capacitors C1, C2, resistors R4, R5. The drain of PMOS transistor P15 and the drain of NMOS transistor N13 are connected and are the output terminals of the operational transconductance amplifier OUT, NMOS transistor The source of N13 is grounded, the other end of the resistor R4 is connected in series with the capacitor C1 and then connected to the output terminal OUT, and the other end of the resistor R5 is connected in series with the capacitor C2 and then connected to the output terminal OUT.

The implementation condition of the rail-to-rail input of the present application is: the voltage source VDD of the entire circuit satisfies VDD>VGS+VGS _P13-14 +2Vdsat, wherein VGS _N17 refers to the gate-source voltage of the NMOS transistor N17, and VGS _P13-14 refers to the PMOS transistor P13 and the gate-source voltage of P14, Vdsat refers to the drain-source saturation voltage drop of PMOS transistors P10 and P12 (assuming they are equal). If the voltage source VDD is small, the gate bias voltage of PMOS transistors P11 and P12 will be the same as that of NMOS transistors N1~ With the same bias voltage for N4, a reliable rail-to-rail input to the operational transconductance amplifier can be achieved. The current of the voltage source VDD is converted into a voltage by the charge pump, and the converted voltage (or current) is mirrored to the PMOS transistors P1 and P5 under the action of the first current mirror (including the PMOS transistors P9-P12), so as to facilitate the subsequent circuit Provide bias current. Similarly, the current at the input of the low-ripple charge pump is mirrored to the PMOS transistors P4 and P8 through the second current mirror (including the PMOS transistors P2, P3, P6, and P7), so as to provide the NMOS transistors N15, N16, The PMOS transistors P18 and P19 provide current, so that the NMOS transistors N5, N6, N11, and N12 generate voltage push-pull, and drive the output current of the push-pull output stage in a voltage push-pull manner, thereby realizing analog signal operation.

In the operational transconductance amplifier, the bias current of the differential input pair PMOS transistors P13 and P14 (transconductance stage) and the bias current of the current buffer stage of the differential current to single-ended current come from the same reference current I _REF , and the differential input pair Always works fine. The bias current does not change with the change of the common mode input voltage, but only increases with the increase of temperature to compensate for the negative temperature coefficient of carrier mobility; from the perspective of voltage, when the temperature increases, the threshold value of PMOS tube and NMOS tube The voltage becomes smaller, but the overdrive voltage increases, which reduces the temperature coefficient of VGS, so the bias voltage VB3 has sufficient design space.

The invention has the characteristics of simple circuit and low ripple charge pump setting, which fundamentally solves the problem that the differential input stage of the traditional operational transconductance amplifier allows the common mode input voltage range to be small. Therefore, there is no need to introduce a large number of auxiliary circuits such as triple current mirrors; moreover, although the output voltage of the charge pump has a small ripple (voltage fluctuation), the influence of the voltage fluctuation is largely shielded by the first current mirror. Under the action of the low-ripple charge pump and the first current mirror, the common-mode input voltage range of the differential transconductance input stage is increased, and at the same time, the equivalent input transconductance and the bias current of the input stage are basically constant, so that Improves the operating temperature range that the entire rail-to-rail input and output operational transconductance amplifier can accommodate.

To sum up, the rail-to-rail input operational transconductance amplifier of the present invention has the following advantages:

(1) The main circuit part of the amplifying signal follows the mature traditional structure, and the additional low-ripple charge pump introduced only provides power to a group of current mirrors to generate the tail current source required for the rail-to-rail input stage. The equivalent input transconductance is almost constant over the range of the modulo input voltage, unlike traditional rail-to-rail input-output operational transconductance amplifiers that require a transconductance compensation circuit. Under the action of the charge pump, the bias current of the differential transconductance input stage hardly changes with the change of the common-mode input voltage, so it has the characteristics of constant transconductance, and there is no need to design complicated additional auxiliary circuits;

(2) The bias current of the differential transconductance input stage hardly changes with the change of the common-mode input voltage, which is beneficial to simplify the design of the subsequent stage circuit to meet the requirements of a wide operating temperature range;

(3) The charge pump works in the form of a switch, and is less affected by temperature changes, which is further beneficial to meet the application requirements of a wide temperature range;

(4) The low-ripple charge pump utilizes the characteristics of the NMOS transistor biased in the saturation region, and can reduce the influence of the voltage fluctuation caused by the charge pump to a very low level with 3 pF capacitors, which not only reduces the extra charge introduced the cost of the pump.

The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or thought of by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims (9)

1. An input-output operational transconductance amplifier based on a low-ripple charge pump, comprising a bias circuit, a differential transconductance input stage, a differential-to-single-ended transimpedance stage, and a push-pull output stage connected in sequence; the bias circuit is used for providing bias voltage and bias current; the differential transconductance input stage is used to convert the differential input voltage into a differential current; The differential-to-single-ended transimpedance stage is used to convert the differential current into a single-ended current; The push-pull output stage adopts a push-pull method to convert the single-ended current into a current and output it; It is characterized in that, the differential transconductance input stage includes a low-ripple charge pump, a first current mirror, and a differential pair, and the low-ripple charge pump is used to generate a voltage source higher than the voltage source VDD, and supply it to the first current mirror. A current mirror supplies power, the first current mirror is used to mirror the bias current generated by the bias circuit, the two input terminals of the low-ripple charge pump are respectively connected to an external input clock signal and a voltage source VDD, the The output terminal of the low-ripple charge pump is connected to the power terminal of the first current mirror, the output of the first current mirror is connected to the source of the differential pair, and the drain of the differential pair is connected to the differential-to-single-ended transimpedance stage, the output of the differential-to-single-ended transimpedance stage is connected to the input of the push-pull output stage, the first current mirror includes PMOS transistors P9 to P12 and a resistor R3, and the differential pair includes PMOS transistors P13, PMOS transistor P14, the output end of the low-ripple charge pump is respectively connected to the differential pair and the bias circuit through the first current mirror. 2. The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 1, wherein the low-ripple charge pump comprises a PMOS transistor N17, capacitors C3, C4, C5, a single-stage charge pump CP1, CP2, the 1-pin of the single-stage charge pump CP1 is respectively connected to the voltage source VDD and the single-stage charge pump CP2, the 2-pin of the single-stage charge pump CP2 is respectively connected to one end of the capacitor C3, the PMOS transistor N17 The source, the 2 pins of the single-stage charge pump CP2 are respectively connected to one end of the capacitor C4, the drain of the PMOS transistor N17 is connected to one end of the capacitor C5, the other ends of the capacitors C3, C4, and C5 are grounded, and the single-stage charge The 3 pins of the pumps CP1 and CP2 are connected to the external input clock signal. 3. The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 2, wherein the single-stage charge pump CP1 comprises PMOS transistors P20, P21, P22, P23, and NMOS transistors N18 and N19 , N20, N21, capacitors C6, C7, the PMOS transistor P20 is connected to the gate of the NMOS transistor N18 and the drain of the PMOS transistor P21, the PMOS transistor P21 is connected to the gate of the NMOS transistor N19, and the PMOS transistor The drains of P20 are connected to the drains, the sources of the NMOS transistors N18 and N19 are connected to the voltage source VDD, the sources of the PMOS transistors P20 and P21 are voltage output terminals, and the sources of the NMOS transistors N18 and N19 are connected to the capacitor C6 One end of the capacitor C7 is connected in a one-to-one correspondence, the other end of the capacitor C6 is connected to the gates of the PMOS transistors P22, P23, NMOS transistors N20 and N21 respectively, and the other end of the capacitor C7 is connected to the drain of the PMOS transistor P23, NMOS transistors respectively. The drain of the transistor N21, the gate of the PMOS transistor P22 and the gate of the NMOS transistor N21 are connected to the external input clock signal, the sources of the PMOS transistors P23 and P22 are respectively connected to the voltage source VDD, the NMOS transistors N20 and N23 The sources of the single-stage charge pump CP2 are grounded respectively; the structure of the single-stage charge pump CP2 is the same as that of the single-stage charge pump CP1. 4. The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 3, wherein the sources of the PMOS transistors P9 and P10 of the first current mirror are connected to the output end of the charge pump , the gate of the PMOS transistor P9 is respectively connected to the gate of the PMOS transistor P10, one end of the resistor R3, and the drain of the PMOS transistor P11, and the gate of the PMOS transistor P11 is respectively connected to the gate of the PMOS transistor P12, The other end of the resistor R3, the drain of the NMOS transistor N3 in the bias circuit, the drain of the PMOS transistor P12 are respectively connected to the sources of the PMOS transistors P13 and P14, and the drain of the PMOS transistor P13 is respectively connected to The NMOS transistors N5 and N11 in the differential transconductance input stage and the drain of the PMOS transistor P14 are respectively connected to the NMOS transistors N6 and N12 in the differential transconductance input stage, and the gate of the PMOS transistor P13 is inverted. Input terminal, the gate of the PMOS transistor P14 is the non-inverting input terminal. 5 . The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 4 , wherein the bias circuit comprises a first bias voltage generating unit, a first switching unit, and the first The bias voltage generating unit is used for generating the bias voltage VB2, the first switch unit is used for conducting conduction control on the bias voltage and bias current, and the first bias voltage generating unit includes PMOS transistors P1, P5, The first switch unit includes NMOS transistors N1-N4, N7-N10, resistors R1, R2, the input end of the first bias voltage generating unit is connected to the voltage source VDD, the output end is connected to the first switch unit, and at the same time , the voltage source VDD is connected in series with the resistor R1 and then connected to the first switch unit. 6 . The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 5 , wherein the source of the PMOS transistor P1 is respectively connected to the voltage source VDD, one end of the resistor R1 , and the NMOS transistors N1 and N2 . Gate, the drain of the PMOS transistor P1 is connected to the source of the PMOS transistor P5, the gate of the PMOS transistor P5 is respectively connected to the source of the NMOS transistor N2, one end of the resistor R2, and the other end of the resistor R2 are respectively connected to the drain of the PMOS transistor P5 and the gate of the PMOS transistor P1, the other end of the resistor R1 is respectively connected to the source of the NMOS transistor N1 and the gate of the NMOS transistor N7, the NMOS transistors N1-N4 The gates of the NMOS transistors N7 to N10 are connected to each other, and the sources of the NMOS transistors N1, N2, N3, and N4 are connected to the drains of the NMOS transistors N7, N8, N9, and N10 in one-to-one correspondence. , the sources of the NMOS transistors N7, N8, N9, and N10 are grounded. 7. The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 6, wherein the differential-to-single-ended transimpedance stage comprises a second bias voltage generating unit, a second current mirror, The second switch unit, the current buffer unit, the third switch unit and the resistors R4 and R5, the second bias voltage generating unit is used for generating the first bias voltage VB, and the second current mirror is used for mirroring the second bias voltage Set the bias current of the voltage generation unit, the second switch unit and the third switch unit are used for conduction control, the current buffer unit is used to provide a push-pull voltage, and the second bias voltage generation unit includes a PMOS transistor P16 and P17, the second current mirror includes PMOS transistors P2, P3, P6, and P7, the second switch unit includes PMOS transistors P18, P19, N16, N15, and N14, and the third switch unit includes PMOS transistor P4 , P8, the current buffer unit includes NMOS transistors N5, N6, N11, N12, the input terminals of the second bias voltage generating unit, the second current mirror, and the third switching unit are all connected to the voltage source VDD, the charge The input end of the pump, the outputs of the second bias voltage generating unit, the second current mirror, and the third switching unit are connected to the second switching unit, and the output of the second switching unit is connected to the input of the current buffer unit , and the output of the current buffer unit is connected to the control terminal of the push-pull output stage. 8. The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 7, wherein the sources of the PMOS transistors P2, P3, and P4 are respectively connected to the voltage source VDD, the source of the charge pump The input terminal, the source of the PMOS transistor P16, the source of the PMOS transistor P15 in the push-pull output stage, the gates of the PMOS transistors P2, P3, and P4 are connected, and the drains of the PMOS transistors P2 and P3 are connected to The sources of the PMOS transistors P6, P7, and P8 are connected in one-to-one correspondence, the gates of the PMOS transistors P6, P7, and P8 are connected, and the drain of the PMOS transistor P6 is connected to the source of the PMOS transistor P18. The gates of the PMOS transistors P17, P18, and P19 are connected to each other, the source of the PMOS transistor P17 is connected to the drain and gate of the PMOS transistor P16, respectively, and the drain of the PMOS transistor P18 is connected to the NMOS transistor N5. The source of the NMOS transistors N11 and N12, the gates of the NMOS transistors N5 and N6 are connected, and the source of the NMOS transistor N6 is respectively connected to the drain of the PMOS transistor P19 and the source of the NMOS transistor N16. , the gate of the NMOS transistor N13 and one end of the resistor R5 in the push-pull output stage, the gate of the NMOS transistor N16 is respectively connected to the gate of the NMOS transistor N15, the drain of the PMOS transistor P8, the PMOS transistor P8 The source of the PMOS transistor P4 is connected to the drain of the PMOS transistor P4, the drain of the PMOS transistor P7 is connected to one end of the resistor R4, the source of the PMOS transistor P19, the drain of the NMOS transistor N6, the NMOS transistors N11, N12, N14 ground. 9 . The input-output operational transconductance amplifier based on a low-ripple charge pump according to claim 8 , wherein the push-pull output stage comprises the PMOS transistor P15 , the NMOS transistor N13 , the capacitors C1 , C2 , the resistors R4, R5, the drain of the PMOS transistor P15 and the drain of the NMOS transistor N13 are connected and are the output terminal OUT of the operational transconductance amplifier, the source of the NMOS transistor N13 is grounded, and the other end of the resistor R4 is connected in series with the The capacitor C1 is connected to the output terminal OUT, and the other end of the resistor R5 is connected to the output terminal OUT in series with the capacitor C2.

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