CN116846353A - comparator circuit - Google Patents

comparator circuit Download PDF

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Publication number
CN116846353A
CN116846353A CN202210305664.3A CN202210305664A CN116846353A CN 116846353 A CN116846353 A CN 116846353A CN 202210305664 A CN202210305664 A CN 202210305664A CN 116846353 A CN116846353 A CN 116846353A
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CN
China
Prior art keywords
tube
current
circuit
pmos tube
nmos tube
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CN202210305664.3A
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Chinese (zh)
Inventor
孙德臣
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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Priority to CN202210305664.3A priority Critical patent/CN116846353A/en
Publication of CN116846353A publication Critical patent/CN116846353A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45192—Folded cascode stages

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The application discloses a comparator circuit which comprises a folding common-source common-gate input stage circuit, a current mirror circuit, a gate bias circuit, a Class AB floating bias circuit, a push-pull common-source output stage circuit and a clamp circuit, wherein the clamp circuit is respectively connected with a first node of the current mirror circuit, a second node of the folding common-source common-gate input stage circuit and the push-pull common-source output stage circuit and is used for adjusting the potentials of the first node and the second node according to the output feedback of the push-pull common-source output stage circuit, so that MOS devices in the folding common-source common-gate input stage circuit, the current mirror circuit and the push-pull common-source output stage circuit always work in a saturation region, and the overall response speed of the circuit is greatly improved.

Description

Comparator circuit
Technical Field
The present application relates to the field of integrated circuit technology, and more particularly, to a comparator circuit.
Background
The operational amplifier is a device capable of amplifying the voltage or power of an input signal, and is widely applied to the fields of communication, PC, consumption, automobiles, industry and the like.
Fig. 1 shows a circuit schematic of an operational amplifier according to the prior art. The operational amplifier can be further divided into a single-stage operational amplifier, a two-stage operational amplifier, a multi-stage operational amplifier and the like. When the operational amplifier 100 of fig. 1 is used as a comparator, the voltage of the node a is raised to around the positive power supply voltage Vdd or the voltage of the node B is lowered to around the negative power supply voltage Vss due to a large difference between the positive side input signal Inp and the negative side input signal Inn, which in turn causes the PMOS transistor MP4 or the NMOS transistor MN2 to enter the linear region. At the same time, the difference between the positive input signal Inp and the negative input signal Inn also causes the output to swing between the positive and negative power sources, which in turn causes the PMOS output pipe MP12 or the NMOS output pipe MN10 to enter the linear region. Therefore, when the differential input signals Inp and Inn are inverted constantly, the four MOS devices described above are switched constantly back and forth between the saturation region and the linear region, which in turn affects the response speed of the entire circuit.
Therefore, there is a need for an improvement in the operational amplifier of the related art to increase the response speed when it is used as a comparator.
Disclosure of Invention
In view of the above, an object of the present application is to provide a comparator circuit capable of improving the response speed of the whole circuit.
According to an embodiment of the present application, there is provided a comparator circuit including: a folded cascode input stage circuit which receives an input positive input signal and a negative input signal; the current mirror circuit is connected with the folding common-source common-gate input stage circuit; the gate bias circuit is connected with the current mirror circuit and the folding common-source common-gate input stage circuit respectively and is connected with a first node and a second node; the Class AB floating bias circuit is connected with the gate bias circuit; the push-pull common source output stage circuit is connected with the Class AB floating bias circuit to realize rail-to-rail output; and the clamping circuit is connected with the first node, the second node and the push-pull common-source output stage circuit and is used for adjusting the potentials of the first node and the second node according to the output feedback of the push-pull common-source output stage circuit.
Optionally, the folded cascode input stage circuit includes: the first end of the first current source is connected with positive power supply voltage; the first current ends of the first PMOS tube and the second PMOS tube are connected with the second end of the first current source; the control end of the first PMOS tube is connected with the positive end input signal, and the control end of the second PMOS tube is connected with the negative end input signal; the first current ends of the first NMOS tube and the second NMOS tube are respectively connected with the second current end of the second PMOS tube and the second current end of the first PMOS tube; the second current ends of the first NMOS tube and the second NMOS tube are connected with negative power supply voltage; the control ends of the first NMOS tube and the second NMOS tube are connected with the first current end of the third NMOS tube; the second current end of the third NMOS tube is connected with the first current end of the first NMOS tube; the second current end of the fourth NMOS tube is connected with the first current end of the second NMOS tube; the control ends of the third NMOS tube and the fourth NMOS tube are connected with a first bias voltage; and the first current ends of the third NMOS tube and the fourth NMOS tube are respectively used for folding the cascade signal output.
Optionally, the current mirror circuit includes: the third PMOS tube is connected with the positive power supply voltage; the control ends of the third PMOS tube and the fourth PMOS tube are connected with a second bias voltage; the second current end of the third PMOS tube is connected with the first current end of the fifth PMOS tube; the second current end of the fourth PMOS tube is connected with the first current end of the sixth PMOS tube; the control ends of the fifth PMOS tube and the sixth PMOS tube are connected with a third bias voltage; the second current end of the fifth PMOS tube is used as the signal input of the current mirror circuit and is connected with the first current end of the third NMOS tube; and the second current end of the sixth PMOS tube is used as the signal output of the current mirror circuit.
Optionally, the gate bias circuit includes: the first current end of the fifth NMOS tube is connected with the second current end of the sixth PMOS tube; the second current end of the fifth NMOS tube is connected with the first current end of the fourth NMOS tube; the control end of the fifth NMOS tube is connected with the Class AB floating bias circuit so as to provide an NMOS gate bias signal for the Class AB floating bias circuit; the first current end of the seventh PMOS tube is connected with the first node between the fourth PMOS tube and the sixth PMOS tube; the control end of the seventh PMOS tube is connected with the third bias voltage; the second current end of the seventh PMOS tube is connected with the first current end of the eighth PMOS tube; the control end of the eighth PMOS tube is connected with the Class AB floating bias circuit so as to provide a PMOS gate bias signal for the Class AB floating bias circuit; the second current end of the eighth PMOS tube is connected with the first current end of the sixth NMOS tube; the control end of the sixth NMOS tube is connected with the first bias voltage; and a second current end of the sixth NMOS tube is connected with the second node between the second NMOS tube and the fourth NMOS tube.
Optionally, the Class AB floating bias circuit includes: the first end of the second current source is connected with the positive power supply voltage; the first current end and the control end of the seventh NMOS tube are connected with the second end of the second current source; the second current end of the seventh NMOS tube is connected with the first current end and the control end of the eighth NMOS tube; the second current end of the eighth NMOS tube is connected with the negative power supply voltage; the first current end of the ninth NMOS tube and the second current end of the sixth PMOS tube are connected to a third node; the second current end of the ninth NMOS tube and the first current end of the sixth NMOS tube are connected to a fourth node; the control end of the ninth NMOS tube is connected with the control end of the fifth NMOS tube and the second end of the second current source; the first current end of the tenth PMOS tube is connected with the positive power supply voltage; the second current end and the control end of the tenth PMOS tube are connected with the first current end of the eleventh PMOS tube; the second current end of the eleventh PMOS tube is connected with the first end of the third current source; a second end of the third current source is connected with the negative power supply voltage; the first current end of the ninth PMOS tube is connected with the third node; the second current end of the ninth PMOS tube is connected with the fourth node; and the control end of the ninth PMOS tube is connected with the control end of the eighth PMOS tube and the first end of the third current source.
Optionally, the push-pull common source output stage circuit includes: a twelfth PMOS tube and a tenth NMOS tube, wherein a first current end of the twelfth PMOS tube is connected with the positive power supply voltage; the second current end of the twelfth PMOS tube is connected with the first current end of the tenth NMOS tube; the second current end of the tenth NMOS tube is connected with the negative power supply voltage; the control end of the twelfth PMOS tube is connected with the third node so as to receive the control signal of the PMOS output tube; the control end of the tenth NMOS tube is connected with the fourth node to receive an NMOS output tube control signal; and the intermediate node of the twelfth PMOS tube and the tenth NMOS tube is used as the output of the push-pull common source output stage circuit.
Optionally, the clamping circuit includes: an eleventh NMOS tube and a thirteenth PMOS tube, wherein a first current end of the eleventh NMOS tube is connected with the first node; the second current end of the eleventh NMOS tube is connected with the output of the push-pull common source output stage circuit; the control end of the eleventh NMOS tube is connected with a fourth bias voltage; the first current end of the thirteenth PMOS tube is connected with the output of the push-pull common-source output stage circuit; the second current end of the thirteenth PMOS tube is connected with the second node; and the control end of the thirteenth PMOS tube is connected with a fifth bias voltage.
In summary, the comparator circuit in the embodiment of the application includes the folded cascode input stage circuit, the current mirror circuit, the gate bias circuit, the Class AB floating bias circuit, the push-pull cascode output stage circuit, and the clamp circuit, which are respectively connected with the current mirror circuit, the folded cascode input stage circuit, and the push-pull cascode output stage circuit, and by feeding back the node potentials of the clamp current mirror circuit and the folded cascode input stage circuit according to the output of the push-pull cascode output stage circuit, MOS devices in the folded cascode input stage circuit, the current mirror circuit, and the push-pull cascode output stage circuit can always operate in a saturation region, thereby greatly improving the overall response speed of the circuit. In addition, the comparator circuit can overcome the problem of slow response speed of the differential input signal with larger input of the operational amplifier without excessively improving the circuit structure of the existing operational amplifier, and has lower improvement cost.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
fig. 1 shows a circuit schematic of an operational amplifier according to the prior art;
FIG. 2 shows a schematic diagram of a comparator circuit according to an embodiment of the application;
fig. 3 shows a circuit schematic of a comparator circuit according to an embodiment of the application.
Detailed Description
Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
In the present application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal Oxide semiconductor field effect transistor) includes a first terminal, a second terminal, and a control terminal, and in an on state of the MOSFET, a current flows from the first terminal to the second terminal. The first current end, the second current end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first current end, the second current end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.
The application will be further described with reference to the drawings and examples.
Fig. 2 shows a schematic diagram of the structure of an operational amplifier according to an embodiment of the present application. As shown in fig. 2, the comparator circuit 200 of the embodiment of the present application includes a folded cascode input stage circuit 210, a current mirror circuit 220, a gate bias circuit 230, a Class AB floating bias circuit 240, a push-pull cascode output stage circuit 250, and a clamp circuit 260.
The input stage circuit 210 is also called a pre-stage circuit, and is typically a high-performance differential amplifier circuit with two inputs, and includes a PMOS differential pair tube for receiving the input positive input signal Inp and the input negative input signal Inn. The substrate of the differential pair tube can be connected to the common source end by adopting the PMOS differential pair tube, so that the substrate bias effect is eliminated, and the linearity is improved. Further, the input stage circuit 210 also adopts a folded cascode cascade structure, which can provide higher gain and larger input and output swing, and provide fast setup time and higher unity gain bandwidth.
The current mirror circuit 220 is connected to the folded cascode input stage circuit 210, and is configured to convert two output signals output by the folded cascode input stage circuit 210 into one output signal.
The gate bias circuit 230 is connected to the current mirror circuit 220 and the folded cascode input stage circuit at node a and node B, respectively, and functions to provide, on the one hand, another output signal from the folded cascode input stage circuit 210 and, on the other hand, a gate bias signal for the Class AB floating bias circuit.
The output stage circuit 250 may employ a push-pull common source structure that provides an approximately full swing output, with a floating bias structure of Class AB being employed as the bias. Specifically, the Class AB floating bias circuit 240 is connected to the gate bias circuit 230 and the push-pull common-source output stage circuit 250, and is configured to control a static working current of the push-pull common-source output stage circuit 250 and implement a Class AB working mode, where the push-pull common-source output stage circuit 250 provides a rail-to-rail output signal OUT according to two output signals of the folded common-source common-gate input stage circuit 210.
The working mode for realizing class AB refers to: the static state has smaller static current flowing through the output stage circuit, and the dynamic state can output larger current to the load, and has higher output efficiency and smaller crossover distortion.
The clamping circuit 260 is respectively connected to the node a, the node B and the output terminal OUT of the push-pull common-source output stage circuit 250, and is used for adjusting the potentials of the node a and the node B according to the output feedback of the push-pull common-source output stage circuit, so that the MOS devices in the folded common-source common-gate input stage circuit 210 and the push-pull common-source output stage circuit 250 always work in a saturation region, and the overall response speed of the circuit is improved.
Fig. 3 shows a circuit schematic of a comparator circuit according to an embodiment of the application. As shown in fig. 3, the input stage circuit 210 is a folded cascode input stage, and includes PMOS transistors MP1 to MP2, NMOS transistors MN1 to MN4, and a current source I1. The sources of the PMOS pipes MP1 and MP2 are connected, the drains of the PMOS pipes MP1 and MP2 are respectively connected with the drains of the NMOS pipes MN1 and MN2, the grid of the PMOS pipe MP1 is connected with the positive input signal Inp, and the grid of the PMOS pipe MP2 is connected with the negative input signal Inn to form a differential input pair pipe. The first end of the current source I1 is connected with the positive power supply voltage Vdd, and the second end is connected with the sources of the PMOS tubes MP1 and MP 2. The source of the NMOS transistors MN1 and MN2 serving as the PMOS input pair of active loads is connected with a negative power supply voltage VSS, the grid is connected with the drain of the NMOS transistor MN3, and the drain is respectively connected with the sources of the NMOS transistors MN3 and MN 4. The NMOS transistors MN3 and MN4 are used as single-tube cascode amplifiers, the gates thereof are connected to the bias voltage Vb1, and the drains thereof are respectively folded cascode signal output terminals.
The current mirror circuit 220 includes PMOS transistors MP 3-MP 6. The PMOS tubes MP3 and MP5 are connected by self-bias cascode, the PMOS tubes MP4 and MP6 are connected by self-bias cascode, and the PMOS tubes MP 3-MP 6 form a self-bias cascode current mirror. Specifically, the sources of the PMOS transistors MP3 and MP4 are connected to the positive power supply voltage Vdd, the gates are connected to the bias voltage Vb2, the drains are connected to the sources of the PMOS transistors MP5 and MP6, respectively, the gates of the PMOS transistors MP5 and MP6 are connected to the bias voltage Vb3, the drain of the PMOS transistor MP5 is connected to the drain of the NMOS transistor MN3, and the drain of the PMOS transistor MP6 is used as the signal output end of the current mirror for outputting a differential amplified signal.
The gate bias circuit 230 includes NMOS transistors MN 5-MN 6 and PMOS transistors MP 7-MP 8. The drain electrode of the NMOS transistor MN5 is connected to the drain electrode of the PMOS transistor MP6, and the node C therebetween is configured to provide a differential amplification signal of the common-source common-gate amplifying circuit, the source electrode of the NMOS transistor MN5 is connected to the drain electrode of the NMOS transistor MN4, and the gate electrode of the NMOS transistor MN5 is connected to the gate electrode of the NMOS transistor MN9 in the Class AB floating bias circuit 240. The source of the PMOS tube MP7 is connected with a node A between the PMOS tubes MP4 and MP6, the grid electrode of the PMOS tube MP7 is connected with a bias voltage Vb3, the drain electrode of the PMOS tube MP7 is connected with the source electrode of the PMOS tube MP8, the grid electrode of the PMOS tube MP8 is connected with the grid electrode of a PMOS tube MP9 in the Class AB floating bias circuit 240, the drain electrode of the PMOS tube MP8 is connected with the drain electrode of an NMOS tube MN6, a node D between the two is used for providing another path of differential amplification signal of the common-source common-gate amplification circuit, the grid electrode of the NMOS tube MN6 is connected with a bias voltage Vb1, and the source electrode of the NMOS tube MN6 is connected with a node B between the NMOS tubes MN2 and MN 4.
The Class AB floating bias circuit 240 includes current sources I2 and I3, NMOS transistors MN7 through MN9, and PMOS transistors MP9 through MP11. The NMOS tube MN9 and the PMOS tube MP9 are floating biases formed by NMOS and PMOS tubes which are connected in parallel, the current source I2 and the NMOS tubes MN7 and MN8 form a bias circuit of the NMOS tube MN9, and the current source I3 and the PMOS tubes MP10 and MP11 form a bias circuit of the PMOS tube MP 9. Specifically, the first end of the current source I2 is connected to the positive power supply voltage Vdd, the second end is connected to the drain and the gate of the NMOS transistor MN7, the source of the NMOS transistor MN7 is connected to the drain and the gate of the NMOS transistor MN8, the source of the NMOS transistor MN8 is connected to the negative power supply voltage Vss, the drain of the NMOS transistor MN9 is connected to the node C, the source of the NMOS transistor MN9 is connected to the node D, and the gate of the NMOS transistor MN9 is connected to the second end of the current source I2. The source electrode of the PMOS tube MP10 is connected with the positive power supply voltage Vdd, the drain electrode and the grid electrode are connected with the source electrode of the PMOS tube MP11, the drain electrode and the grid electrode of the PMOS tube MP11 are connected with the first end of the current source I3, the second end of the current source I3 is connected with the negative power supply voltage Vss, the source electrode of the PMOS tube MP9 is connected with the node C, the drain electrode of the PMOS tube MP9 is connected with the node D, and the grid electrode of the PMOS tube MP9 is connected with the first end of the current source I3.
The push-pull common source output stage circuit 250 comprises a PMOS transistor MP12 and an NMOS transistor MN10, wherein the drains of the PMOS transistor MP12 and the NMOS transistor MN10 are push-pull output terminals OUT, the source of the PMOS transistor MP12 is connected with a positive power supply voltage Vdd, the gate is connected with a PMOS output tube control signal terminal of a Class AB floating bias, the source of the NMOS transistor MN10 is connected with a negative power supply voltage Vss, and the gate is connected with an NMOS output tube control signal terminal of the Class AB floating bias.
The clamp circuit 260 includes an NMOS transistor MN11 and a PMOS transistor MP13. The drain electrode of the NMOS tube MN11 is connected with the node A, the grid electrode is connected with the bias voltage Vb4, the source electrode is connected with the push-pull output end OUT, the drain electrode of the PMOS tube MP13 is connected with the node B, the grid electrode is connected with the bias voltage Vb5, and the source electrode is connected with the push-pull output end OUT. By adjusting the potential of the bias voltages Vb4 and Vb5 and adjusting the sizes of the NMOS transistor MN11 and the PMOS transistor MP13, the potential of the node A, B and the output terminal are equal, so that when the difference between the differential input signals Inp and Inn is large, the NMOS transistor MN2, the PMOS transistor MP4, and the output transistors MP12 and MN10 do not enter a linear region, and the response speed of the overall circuit can be greatly improved.
In summary, the comparator circuit in the embodiment of the application includes the folded cascode input stage circuit, the current mirror circuit, the gate bias circuit, the Class AB floating bias circuit, the push-pull cascode output stage circuit, and the clamp circuit, which are respectively connected with the current mirror circuit, the folded cascode input stage circuit, and the push-pull cascode output stage circuit, and by feeding back the node potentials of the clamp current mirror circuit and the folded cascode input stage circuit according to the output of the push-pull cascode output stage circuit, MOS devices in the folded cascode input stage circuit, the current mirror circuit, and the push-pull cascode output stage circuit can always operate in a saturation region, thereby greatly improving the overall response speed of the circuit. In addition, the comparator circuit can overcome the problem of slow response speed of the differential input signal with larger input of the operational amplifier without excessively improving the circuit structure of the existing operational amplifier, and has lower improvement cost.
It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present application. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.
Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The scope of the application should be determined by the following claims.

Claims (7)

1. A comparator circuit comprising:
a folded cascode input stage circuit which receives an input positive input signal and a negative input signal;
the current mirror circuit is connected with the folding common-source common-gate input stage circuit;
the gate bias circuit is connected with the current mirror circuit and the folding common-source common-gate input stage circuit respectively and is connected with a first node and a second node;
the Class AB floating bias circuit is connected with the gate bias circuit; and
the push-pull common source output stage circuit is connected with the Class AB floating bias circuit to realize rail-to-rail output; and
and the clamping circuit is connected with the first node, the second node and the push-pull common-source output stage circuit and is used for adjusting the potentials of the first node and the second node according to the output feedback of the push-pull common-source output stage circuit.
2. The comparator circuit of claim 1, wherein the folded cascode input stage circuit comprises: a first current source, a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a fourth NMOS tube,
a first end of the first current source is connected with a positive power supply voltage;
the first current ends of the first PMOS tube and the second PMOS tube are connected with the second end of the first current source;
the control end of the first PMOS tube is connected with the positive end input signal, and the control end of the second PMOS tube is connected with the negative end input signal;
the first current ends of the first NMOS tube and the second NMOS tube are respectively connected with the second current end of the second PMOS tube and the second current end of the first PMOS tube;
the second current ends of the first NMOS tube and the second NMOS tube are connected with negative power supply voltage;
the control ends of the first NMOS tube and the second NMOS tube are connected with the first current end of the third NMOS tube;
the second current end of the third NMOS tube is connected with the first current end of the first NMOS tube;
the second current end of the fourth NMOS tube is connected with the first current end of the second NMOS tube;
the control ends of the third NMOS tube and the fourth NMOS tube are connected with a first bias voltage;
and the first current ends of the third NMOS tube and the fourth NMOS tube are respectively used for folding the cascade signal output.
3. The comparator circuit of claim 2, wherein the current mirror circuit comprises: a third to a sixth PMOS tube,
the first current ends of the third PMOS tube and the fourth PMOS tube are connected with the positive power supply voltage;
the control ends of the third PMOS tube and the fourth PMOS tube are connected with a second bias voltage;
the second current end of the third PMOS tube is connected with the first current end of the fifth PMOS tube;
the second current end of the fourth PMOS tube is connected with the first current end of the sixth PMOS tube;
the control ends of the fifth PMOS tube and the sixth PMOS tube are connected with a third bias voltage;
the second current end of the fifth PMOS tube is used as the signal input of the current mirror circuit and is connected with the first current end of the third NMOS tube;
and the second current end of the sixth PMOS tube is used as the signal output of the current mirror circuit.
4. A comparator circuit according to claim 3, wherein the gate bias circuit comprises: a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube and an eighth PMOS tube,
the first current end of the fifth NMOS tube is connected with the second current end of the sixth PMOS tube;
the second current end of the fifth NMOS tube is connected with the first current end of the fourth NMOS tube;
the control end of the fifth NMOS tube is connected with the Class AB floating bias circuit so as to provide an NMOS gate bias signal for the Class AB floating bias circuit;
the first current end of the seventh PMOS tube is connected with the first node between the fourth PMOS tube and the sixth PMOS tube;
the control end of the seventh PMOS tube is connected with the third bias voltage;
the second current end of the seventh PMOS tube is connected with the first current end of the eighth PMOS tube;
the control end of the eighth PMOS tube is connected with the Class AB floating bias circuit so as to provide a PMOS gate bias signal for the Class AB floating bias circuit;
the second current end of the eighth PMOS tube is connected with the first current end of the sixth NMOS tube;
the control end of the sixth NMOS tube is connected with the first bias voltage;
and a second current end of the sixth NMOS tube is connected with the second node between the second NMOS tube and the fourth NMOS tube.
5. The comparator circuit of claim 4, wherein the Class AB floating bias circuit comprises: a second current source, a third current source, seventh to ninth NMOS transistors, and ninth to eleventh PMOS transistors,
a first end of the second current source is connected with the positive power supply voltage;
the first current end and the control end of the seventh NMOS tube are connected with the second end of the second current source;
the second current end of the seventh NMOS tube is connected with the first current end and the control end of the eighth NMOS tube;
the second current end of the eighth NMOS tube is connected with the negative power supply voltage;
the first current end of the ninth NMOS tube and the second current end of the sixth PMOS tube are connected to a third node;
the second current end of the ninth NMOS tube and the first current end of the sixth NMOS tube are connected to a fourth node;
the control end of the ninth NMOS tube is connected with the control end of the fifth NMOS tube and the second end of the second current source;
the first current end of the tenth PMOS tube is connected with the positive power supply voltage;
the second current end and the control end of the tenth PMOS tube are connected with the first current end of the eleventh PMOS tube;
the second current end of the eleventh PMOS tube is connected with the first end of the third current source;
a second end of the third current source is connected with the negative power supply voltage;
the first current end of the ninth PMOS tube is connected with the third node;
the second current end of the ninth PMOS tube is connected with the fourth node;
and the control end of the ninth PMOS tube is connected with the control end of the eighth PMOS tube and the first end of the third current source.
6. The comparator circuit of claim 5, wherein the push-pull common-source output stage circuit comprises: a twelfth PMOS tube and a tenth NMOS tube,
the first current end of the twelfth PMOS tube is connected with the positive power supply voltage;
the second current end of the twelfth PMOS tube is connected with the first current end of the tenth NMOS tube;
the second current end of the tenth NMOS tube is connected with the negative power supply voltage;
the control end of the twelfth PMOS tube is connected with the third node so as to receive the control signal of the PMOS output tube;
the control end of the tenth NMOS tube is connected with the fourth node to receive an NMOS output tube control signal;
and the intermediate node of the twelfth PMOS tube and the tenth NMOS tube is used as the output of the push-pull common source output stage circuit.
7. The comparator circuit of claim 6, wherein the clamp circuit comprises: an eleventh NMOS tube and a thirteenth PMOS tube,
the first current end of the eleventh NMOS tube is connected with the first node;
the second current end of the eleventh NMOS tube is connected with the output of the push-pull common source output stage circuit;
the control end of the eleventh NMOS tube is connected with a fourth bias voltage;
the first current end of the thirteenth PMOS tube is connected with the output of the push-pull common-source output stage circuit;
the second current end of the thirteenth PMOS tube is connected with the second node;
and the control end of the thirteenth PMOS tube is connected with a fifth bias voltage.
CN202210305664.3A 2022-03-25 2022-03-25 comparator circuit Pending CN116846353A (en)

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Application Number Priority Date Filing Date Title
CN202210305664.3A CN116846353A (en) 2022-03-25 2022-03-25 comparator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210305664.3A CN116846353A (en) 2022-03-25 2022-03-25 comparator circuit

Publications (1)

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CN116846353A true CN116846353A (en) 2023-10-03

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Family Applications (1)

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CN202210305664.3A Pending CN116846353A (en) 2022-03-25 2022-03-25 comparator circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117478108A (en) * 2023-12-11 2024-01-30 深圳市微源半导体股份有限公司 Comparison circuit and comparator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117478108A (en) * 2023-12-11 2024-01-30 深圳市微源半导体股份有限公司 Comparison circuit and comparator
CN117478108B (en) * 2023-12-11 2024-03-12 深圳市微源半导体股份有限公司 Comparison circuit and comparator

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