CN112636729A - Power dynamic comparator circuit with ultra-low power consumption - Google Patents
Power dynamic comparator circuit with ultra-low power consumption Download PDFInfo
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- CN112636729A CN112636729A CN202011475723.9A CN202011475723A CN112636729A CN 112636729 A CN112636729 A CN 112636729A CN 202011475723 A CN202011475723 A CN 202011475723A CN 112636729 A CN112636729 A CN 112636729A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2409—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors
- H03K5/2418—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors with at least one differential stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2409—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors
- H03K5/2427—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors using clock signals
Abstract
The invention discloses a power supply dynamic comparator with ultra-low power consumption, and belongs to the technical field of integrated circuits. The ultra-low power consumption power supply dynamic comparator comprises a preamplifier circuit, a cross coupler circuit and a regenerative latch circuit, wherein the preamplifier circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first output node capacitor and a second output node capacitor; the cross-coupler circuit includes an eighth transistor and a ninth transistor; the regenerative latch includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor. The invention can prevent the comparator from completely discharging smaller differential input signals, reduce energy consumption, improve the working efficiency of the comparator and save area.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a power supply dynamic comparator circuit with ultra-low power consumption.
Background
The output node capacitor of the preamplifier of the prior power supply dynamic comparator can completely discharge electricity in the capacitor to the ground after finishing signal amplification. When the circuit works again, the output node capacitor must be recharged to the working voltage, which causes energy waste and consumes electric energy.
In the prior art, although the function of power supply dynamic comparison can be realized through the double-tail latch, the energy consumption is high, the energy requirement is high, and the requirement of energy saving is not met.
Disclosure of Invention
Aiming at the problems in the prior art, the invention mainly provides a power supply dynamic comparator circuit with ultra-low power consumption.
In order to solve the above problems, one technical solution adopted by the present invention is to provide an ultra-low power consumption power dynamic comparator circuit, including a preamplifier circuit, where the preamplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first output node capacitor, and a second output node capacitor;
a cross-coupler circuit including an eighth transistor and a ninth transistor;
the grid electrodes of the first transistor, the second transistor, the third transistor and the fourth transistor are connected with a first clock signal, the source electrode of the first transistor is connected with a power supply, the drain electrode of the first transistor is connected with the drain electrode of the fifth transistor, the drain electrode of the second transistor is connected with the drain electrode of the sixth transistor, the drain electrode of the third transistor is connected with the drain electrode of the eighth transistor, and the drain electrode of the fourth transistor is connected with the drain electrode of the ninth transistor; the grid electrode of the fifth transistor is connected with the first input signal, and the source electrode of the fifth transistor is connected with the drain electrode of the eighth transistor; a grid electrode of the sixth transistor is connected with the second input signal, and a source electrode of the sixth transistor is connected with a drain electrode of the ninth transistor; the drain electrode of the seventh transistor is connected with the source electrodes of the eighth transistor and the ninth transistor, the source electrode of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with the first clock signal; one end of the first output node capacitor is connected to the drain electrode of the first transistor and connected to the first end of the regenerative latch, and the other end of the first output node capacitor is grounded; one end of the second output node capacitor is connected to the drain electrode of the second transistor and connected to the second end of the regenerative latch, and the other end of the second output node capacitor is grounded; the gate of the eighth transistor is connected to the drain of the sixth transistor, and the gate of the ninth transistor is connected to the drain of the fifth transistor.
The technical scheme of the invention can achieve the following beneficial effects: the invention designs a power supply dynamic comparator circuit with ultra-low power consumption. The power dynamic comparator with ultra-low power consumption carries out simple cross coupling aiming at the input differential signals, can prevent the internal nodes of the comparator from completely discharging lower differential input signals, can reduce the energy consumption, improves the working efficiency, saves the area and reduces the cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of one embodiment of an ultra low power dynamic comparator circuit of the present invention;
FIG. 2 is a schematic diagram of one embodiment of an ultra low power dynamic comparator circuit of the present invention;
the components in fig. 2 are labeled as follows: m1-a first transistor, M2-a second transistor, M3-a third transistor, M4-a fourth transistor, M5-a fifth transistor, M6-a sixth transistor, M7-a seventh transistor, M8-an eighth transistor, M9-a ninth transistor, M10-a tenth transistor, M11-an eleventh transistor, M12-a twelfth transistor, M13-a thirteenth transistor, M14-a fourteenth transistor, M15-a fifteenth transistor, M16-a sixteenth transistor, M17-a seventeenth transistor, CP 1-a first output node capacitance, CP 2-a second output node capacitance, Clk-a first clock signal, Clkb-a second clock signal.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 shows an embodiment of an ultra-low power consumption power dynamic comparator circuit according to the present invention.
In this embodiment, the power dynamic comparator circuit with ultra-low power consumption of the present invention mainly includes a preamplifier circuit, where the preamplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first output node capacitor, and a second output node capacitor;
a cross-coupler circuit including an eighth transistor and a ninth transistor;
the grid electrodes of the first transistor, the second transistor, the third transistor and the fourth transistor are connected with a first clock signal, the source electrode of the first transistor is connected with a power supply, the drain electrode of the first transistor is connected with the drain electrode of the fifth transistor, the drain electrode of the second transistor is connected with the drain electrode of the sixth transistor, the drain electrode of the third transistor is connected with the drain electrode of the eighth transistor, and the drain electrode of the fourth transistor is connected with the drain electrode of the ninth transistor; the grid electrode of the fifth transistor is connected with the first input signal, and the source electrode of the fifth transistor is connected with the drain electrode of the eighth transistor; a grid electrode of the sixth transistor is connected with the second input signal, and a source electrode of the sixth transistor is connected with a drain electrode of the ninth transistor; the drain electrode of the seventh transistor is connected with the source electrodes of the eighth transistor and the ninth transistor, the source electrode of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with the first clock signal; one end of the first output node capacitor is connected to the drain electrode of the first transistor and connected to the first end of the regenerative latch, and the other end of the first output node capacitor is grounded; one end of the second output node capacitor is connected to the drain electrode of the second transistor and connected to the second end of the regenerative latch, and the other end of the second output node capacitor is grounded; the gate of the eighth transistor is connected to the drain of the sixth transistor, and the gate of the ninth transistor is connected to the drain of the fifth transistor.
In one embodiment of the present invention, the addition of the third transistor and the fourth transistor is beneficial to the stability of the circuit; the increase of the cross coupler can increase the speed of pre-amplification, but the increase of the cross coupler only can reduce a part of power consumption, but can affect the response speed and stability of the circuit.
This embodiment, through the reasonable relation of connection that sets up between the transistor, can reduce energy consumption, improve work efficiency, save the area, reduce cost increases the speed that cross coupler can accelerate to enlarge in advance.
In this embodiment, the power dynamic comparator circuit with ultra-low power consumption further includes a regenerative latch circuit, where the regenerative latch circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, where sources of the twelfth transistor and the thirteenth transistor are connected to a power supply, a gate of the twelfth transistor is connected to a gate of the fourteenth transistor, and a drain of the twelfth transistor is connected to a source of the tenth transistor; a gate of the thirteenth transistor is connected with a gate of the fifteenth transistor, and a drain of the thirteenth transistor is connected with a source of the eleventh transistor; a grid electrode of the tenth transistor is connected with the first output node capacitor, a source electrode of the tenth transistor is connected with a drain electrode of the twelfth transistor, a drain electrode of the tenth transistor is interconnected with a drain electrode of the fourteenth transistor, a drain electrode of the sixteenth transistor, a grid electrode of the thirteenth transistor and a grid electrode of the fifteenth transistor; a gate of the eleventh transistor is connected with the capacitor of the second output node, a source of the eleventh transistor is connected with a drain of the thirteenth transistor, and a drain of the eleventh transistor is connected with a drain of the fifteenth transistor, a drain of the seventeenth transistor, and gates of the twelfth transistor and the fourteenth transistor; a gate of the sixteenth transistor is connected with the second clock signal, a drain of the sixteenth transistor is connected with drains of the tenth transistor and the fourteenth transistor and gates of the thirteenth transistor and the fifteenth transistor, and a source of the sixteenth transistor is connected with sources of the fourteenth transistor, the fifteenth transistor and the seventeenth transistor; the drain electrode of the fourteenth transistor is connected with the drain electrodes of the tenth transistor and the sixteenth transistor and the grid electrodes of the thirteenth transistor and the fifteenth transistor, the grid electrode of the fourteenth transistor is connected with the grid electrode of the twelfth transistor and the drain electrodes of the eleventh transistor and the seventeenth transistor, and the source electrode of the fourteenth transistor is connected with the source electrodes of the sixteenth transistor and the fifteenth transistor; the drain electrode of the fifteenth transistor is connected with the drain electrodes of the eleventh transistor, the seventeenth transistor and the gate electrode of the twelfth transistor, the gate electrode of the fifteenth transistor is connected with the gate electrode of the thirteenth transistor, the drain electrode of the tenth transistor, the drain electrode of the fourteenth transistor and the drain electrode of the sixteenth transistor, and the source electrode of the fifteenth transistor is connected with the source electrodes of the fourteenth transistor, the sixteenth transistor and the seventeenth transistor; the grid electrode of the seventeenth transistor is connected with the second clock signal, the drain electrode of the seventeenth transistor is connected with the drain electrodes of the eleventh transistor and the fifteenth transistor and the grid electrodes of the twelfth transistor and the fourteenth transistor, and the source electrode of the seventeenth transistor is connected with the source electrodes of the fourteenth transistor, the fifteenth transistor and the sixteenth transistor.
In this embodiment, the regenerative latch circuit is used as a basis for the power dynamic comparator circuit to operate under the condition of ultra-low power consumption.
In one embodiment of the present invention, the ultra low power dynamic comparator circuit of the present invention, as shown in FIG. 2, mainly comprises an improved preamplifier, cross-coupled devices and regenerative latches. The improved preamplifier consists of M1, M2, M3, M4, M5, M6, M7, CP1, CP2 and Clk, the cross-coupling device consists of M8 and M9, and the regenerative latch consists of M10, M11, M12, M13, M14, M15, M16, M17 and Clkb. The input signals of the ultra-low power consumption power dynamic comparator are input from M5 and M6 gates, wherein the non-inverting input terminal is connected with the gate of M5, and the inverting input terminal is connected with the gate of M6. The preamplifier amplifies the input signal, inputs the amplified signal to the regenerative latch through intN and intP, and the regenerative latch processes the signal and outputs the processed signal through outN and outP.
In one embodiment of the present invention, when CLK is low, M3 and M4 pull the voltage at N1 and P1 points high to VDD; when CLK is high, the drain pin voltage VDD of M8 and M9 discharges directly through M3 and M4. When M3 and M4 are not present in the circuit, the drains of M8 and M9 also need to be discharged by an input signal, which affects the response speed of the circuit.
The specific embodiment can ensure that the input ultra-low power consumption power dynamic comparator circuit can stably carry out signal comparison work.
In a specific embodiment of the present invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are first type transistors; the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are another type of transistor.
In a specific embodiment of the invention, the first type of transistor is a complementary type of transistor to the other type of transistor.
In a specific example of the present invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are PMOS; the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are NMOS. And the first transistor, the second transistor, the third transistor, the fourth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are complementary transistors.
This embodiment makes use of the different properties of the transistors of different nature to achieve a comparison of the input signals.
In a specific embodiment of the present invention, the drains of the third transistor and said eighth transistor, and the source of the fifth transistor are the first internal nodes of the preamplifier; the drains of the fourth transistor and said ninth transistor, and the source of the sixth transistor are a second internal node of the preamplifier.
In an embodiment of the present invention, as shown in fig. 2, if the third transistor M3 and the fourth transistor M4 are not added to the circuit, the voltages of the first internal node N1 and the second internal node P1 will be determined by the last comparison result of the comparator, which will add an unstable factor to the next comparison, and it is possible to have a longer pre-amplification time, i.e., a large jump of the node voltage between 0 and VDD in the next comparison.
In this embodiment, the working state of the circuit can be adjusted in time by knowing the state information of the node.
In a specific embodiment of the present invention, the drain of the first transistor, the drain of the fifth transistor, and the gate of the ninth transistor are the first output node of the preamplifier; the drain of the second transistor, the drain of the sixth transistor, and the gate of the eighth transistor are a second output node of the preamplifier.
This embodiment enables to know the state information of the preamplifier in time by knowing the state information of the first output node and the second output node.
In one embodiment of the invention, the second internal node, the second output node and the first input signal of the preamplifier are non-inverting input/output terminals of the comparator; said first internal node, first output node and second input signal of the preamplifier are the inverting input/output terminals of the comparator.
In the embodiment, the working state of the comparator can be adjusted in time by knowing the information of each node in time and utilizing the state relationship among the nodes, so that the performance of the comparator is better.
In a specific embodiment of the invention, the first input signal and the second input signal are differential input signals.
According to the specific embodiment, the differential input signal is used as the input signal of the preamplifier, so that the anti-interference capability of the ultra-low power consumption power supply dynamic comparator can be enhanced, and the common mode noise can be better suppressed.
In one embodiment of the present invention, the comparator performs a reset operation when the first clock signal and the second clock signal are at a low level; when the first clock signal and the second clock signal are at a high level, the comparator performs an amplification operation.
In one embodiment of the present invention, as shown in fig. 2, in the power dynamic comparator circuit with ultra-low power consumption, when the circuit needs to be reset, the clocks Clk and Clkb are at low level, the transistors M1, M2, M3 and M4 reset the nodes intN, intP, N1 and P1 to VDD, and the transistors M16 and M17 reset the regenerative latch output nodes outP and outN. Transistor M7 is off and no current flows directly from the power supply to ground.
In one embodiment of the present invention, as shown in fig. 2, in the power dynamic comparator circuit with ultra-low power consumption, when the circuit needs to amplify, the clocks Clk and Clkb are at high level, the nodes intP, intN, P1 and N1 are disconnected from VDD, and M3 provides a discharge path to ground. At the beginning of amplification, when the gate voltages of M8 and M9 are VDD, the node N1 is discharged to a low voltage through the transistors M7 and M8. Node P1 is discharged to a low voltage through transistors M7 and M9.
After amplification starts, the transistors M1 and M2 start conducting, and M8 and M9 operate as resistors in the linear region. The magnitude of the vinP and vinN input voltages affects the current of transistors M1 and M2, which determines intP, intN, node discharge speed, and the decrease in intP and intN voltages causes the voltages at nodes N1 and P1 to slowly increase.
This embodiment changes the effective VGS of the input differential pair and reduces transconductance.
In one embodiment of the present invention, as shown in fig. 2, in the power dynamic comparator circuit with ultra-low power consumption, when the input differential voltage vinP is greater than vinN, the voltage drop speed of the node intN is faster than that of the node intP. When the voltage value of node intN reaches the threshold voltage of M9, the voltage drop rate of node intP decreases, and eventually the voltage of intP will become static with the transistor M9 fully turned off. When the node intP reaches quiescent state, the transistor M9 is completely turned off, and the transistors M1 and M9 become cascaded current sources. Since node intP is static, the gate of transistor M8 is fixed, so node intN discharges at a lower rate. The voltages of the nodes P1 and N1 increase as the voltages of the nodes intP and intN decrease, because the on-resistances of the transistors M8 and M9 increase as their gate potentials decrease.
This embodiment reduces the energy consumption. The power efficiency is improved, no extra capacitor or more complex logic is used, the occupied area is small, and the noise is low.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A power supply dynamic comparator circuit with ultra-low power consumption, comprising:
a preamplifier circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first output node capacitance, and a second output node capacitance;
a cross-coupler circuit including an eighth transistor and a ninth transistor;
wherein the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor are connected to a first clock signal, the source is connected to a power supply, the drain of the first transistor is connected to the drain of the fifth transistor, the drain of the second transistor is connected to the drain of the sixth transistor, the drain of the third transistor is connected to the drain of the eighth transistor, and the drain of the fourth transistor is connected to the drain of the ninth transistor; a grid electrode of the fifth transistor is connected with a first input signal, and a source electrode of the fifth transistor is connected with a drain electrode of the eighth transistor; a grid electrode of the sixth transistor is connected with a second input signal, and a source electrode of the sixth transistor is connected with a drain electrode of the ninth transistor; the drain electrode of the seventh transistor is connected with the source electrodes of the eighth transistor and the ninth transistor, the source electrode of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with a first clock signal; one end of the first output node capacitor is connected to the drain of the first transistor and to a first end of a regenerative latch, and the other end of the first output node capacitor is grounded; one end of the second output node capacitor is connected to the drain of the second transistor and to the second end of the regenerative latch, and the other end of the second output node capacitor is grounded; the gate of the eighth transistor is connected to the drain of the sixth transistor, and the gate of the ninth transistor is connected to the drain of the fifth transistor.
2. The ultra-low power dynamic comparator circuit for a power supply of claim 1, further comprising:
a regenerative latch circuit including a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, wherein sources of the twelfth transistor and the thirteenth transistor are connected to a power supply, a gate of the twelfth transistor is connected to a gate of the fourteenth transistor, and a drain of the twelfth transistor is connected to a source of the tenth transistor; a gate of the thirteenth transistor is connected to a gate of the fifteenth transistor, and a drain of the thirteenth transistor is connected to a source of the eleventh transistor; a gate of the tenth transistor is connected to the first output node capacitance, a source of the tenth transistor is connected to a drain of the twelfth transistor, a drain of the tenth transistor and a drain of the fourteenth transistor, a drain of the sixteenth transistor, and a gate of the thirteenth transistor and a gate of the fifteenth transistor are interconnected; a gate of the eleventh transistor is connected to the capacitor of the second output node, a source of the eleventh transistor is connected to a drain of the thirteenth transistor, and a drain of the eleventh transistor is connected to a drain of the fifteenth transistor, a drain of the seventeenth transistor, and gates of the twelfth transistor and the fourteenth transistor; a gate of the sixteenth transistor is connected to a second clock signal, a drain of the sixteenth transistor is connected to drains of the tenth transistor and the fourteenth transistor and gates of the thirteenth transistor and the fifteenth transistor, and a source of the sixteenth transistor is connected to sources of the fourteenth transistor, the fifteenth transistor and the seventeenth transistor; a drain of the fourteenth transistor is connected to drains of the tenth transistor and the sixteenth transistor and gates of a thirteenth transistor and a fifteenth transistor, a gate of the fourteenth transistor is connected to a gate of the twelfth transistor, drains of the eleventh transistor and the seventeenth transistor, and a source of the fourteenth transistor is connected to sources of the sixteenth transistor, the fifteenth transistor and the seventeenth transistor; a drain of the fifteenth transistor is connected to drains of the eleventh transistor and the seventeenth transistor and gates of the twelfth transistor and the fourteenth transistor, a gate of the fifteenth transistor is connected to a gate of the thirteenth transistor, a drain of the tenth transistor, a drain of the fourteenth transistor and a drain of the sixteenth transistor, and a source of the fifteenth transistor is connected to sources of the fourteenth transistor, the sixteenth transistor and the seventeenth transistor; a gate of the seventeenth transistor is connected to a second clock signal, a drain of the seventeenth transistor is connected to drains of the eleventh transistor and the fifteenth transistor, and gates of the twelfth transistor and the fourteenth transistor, and a source of the seventeenth transistor is connected to sources of the fourteenth transistor, the fifteenth transistor and the sixteenth transistor.
3. The ultra low power consumption power supply dynamic comparator circuit as claimed in claim 2,
the first transistor, the second transistor, the third transistor, the fourth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are first-type transistors; the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are another type of transistor.
4. The ultra-low power consumption power supply dynamic comparator circuit as claimed in claim 3,
the first type of transistor is a complementary type of transistor to the other type of transistor.
5. The ultra-low power consumption power supply dynamic comparator circuit as claimed in claim 1,
drains of the third transistor and the eighth transistor, and a source of the fifth transistor are first internal nodes of the preamplifier; drains of the fourth transistor and the ninth transistor, and a source of the sixth transistor are a second internal node of the preamplifier.
6. The ultra-low power consumption power supply dynamic comparator circuit as claimed in claim 5,
the drain electrode of the first transistor, the drain electrode of the fifth transistor and the grid electrode of the ninth transistor are first output nodes of the preamplifier; and the drain electrode of the second transistor, the drain electrode of the sixth transistor and the grid electrode of the eighth transistor are second output nodes of the preamplifier.
7. The ultra-low power consumption power supply dynamic comparator circuit as claimed in claim 6,
said second internal node, second output node and said first input signal of said preamplifier are non-inverting input/output terminals of said comparator; said first internal node, first output node and said second input signal of said preamplifier are inverting input/output terminals of said comparator.
8. The ultra-low power consumption power supply dynamic comparator circuit as claimed in claim 1,
the first input signal and the second input signal are differential input signals.
9. The ultra-low power consumption power supply dynamic comparator circuit as claimed in claim 1,
when the first clock signal and the second clock signal are at a low level, the comparator performs reset operation; when the first clock signal and the second clock signal are at a high level, the comparator performs an amplification operation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113517882A (en) * | 2021-07-21 | 2021-10-19 | 北京百瑞互联技术有限公司 | High-speed low-power consumption comparison circuit, converter and electronic equipment |
| CN113556105A (en) * | 2021-07-21 | 2021-10-26 | 北京百瑞互联技术有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment for wireless communication |
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| CN113517882B (en) * | 2021-07-21 | 2024-03-08 | 北京百瑞互联技术股份有限公司 | High-speed low-power consumption comparison circuit, converter and electronic equipment |
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