CN112953496A - High-speed dynamic comparator - Google Patents

High-speed dynamic comparator Download PDF

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Publication number
CN112953496A
CN112953496A CN202110166741.7A CN202110166741A CN112953496A CN 112953496 A CN112953496 A CN 112953496A CN 202110166741 A CN202110166741 A CN 202110166741A CN 112953496 A CN112953496 A CN 112953496A
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tube
nmos tube
nmos
pmos
node
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CN112953496B (en
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唐鹤
仲卓群
熊兴
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Abstract

A high-speed dynamic comparator belongs to the technical field of analog circuits. Compared with the traditional structure, the invention increases the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the seventh PMOS tube and the eighth PMOS tube to improve the comparison speed, and utilizes the seventh PMOS tube, the eighth PMOS tube, the eleventh NMOS tube and the twelfth NMOS tube to generate extra current to discharge the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube, so that a positive feedback loop of the comparator can quickly start to work, thereby effectively improving the quantization speed of the comparator; the drain voltage of the third NMOS tube and the drain voltage of the fourth NMOS tube are different in descending speed in the pre-amplification stage of the comparator, so that the drain current of the first NMOS tube and the drain current of the second NMOS tube are different in discharging extra current, the problem of noise increase caused by the early start of the regeneration stage of the comparator is solved, and the speed and the noise performance of the comparator can be considered at the same time.

Description

High-speed dynamic comparator
Technical Field
The invention belongs to the field of dynamic comparators and data converters, and relates to a two-stage dynamic comparator, which is particularly suitable for a high-speed analog-to-digital converter and is used for comparing an analog input signal and inputting a comparison result into a control logic.
Background
The comparator has a function of comparing the magnitudes of two analog signals and outputting the comparison result in a "1" or "0" manner, so that the comparator is widely applied to various analog-to-digital converters, such as a successive approximation type analog-to-digital converter, a pipeline type analog-to-digital converter, or a flash type analog-to-digital converter. The traditional comparator comprises a static comparator and a dynamic comparator, basically adopts a rail-to-rail input and output static amplifier structure, has the characteristic of higher precision and has the defect of higher power consumption. The dynamic comparator has no static power consumption due to the adoption of a full dynamic structure, and is widely applied to various analog-to-digital converters, but the precision and the speed are the most important factors in the design of the dynamic comparator.
The comparator is used as a core module of the analog-to-digital converter, the speed and the precision of the comparator directly influence the quantization speed and the noise characteristic of the analog-to-digital converter, and the comparator is particularly obvious in a successive approximation type analog-to-digital converter. However, the speed and the noise characteristic of the comparator are often incompatible, so how to effectively increase the comparison speed on the premise of meeting a certain noise requirement or effectively reduce the noise of the comparator on the premise of meeting a certain comparison speed becomes the most important part of the comparator design.
Disclosure of Invention
On the basis of the traditional dynamic comparator, the voltage drop speeds of a first node X and a second node Y and the voltage drop speeds of a third node DIN and a fourth node DIP are increased by introducing drain currents of an eleventh NMOS tube and a twelfth NMOS tube, so that the quantization speed of the comparator is increased; in addition, the invention achieves the effect of improving the noise of the comparator by increasing the gain of the input stage of the comparator, thereby giving consideration to the speed and the noise performance of the comparator.
The technical scheme of the invention is as follows:
a high-speed dynamic comparator comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor,
the grid electrode of the first NMOS tube is used as a first input end of the high-speed dynamic comparator, and the drain electrode of the first NMOS tube is used as a first node and connected with the source electrode of the third NMOS tube;
the grid electrode of the second NOMS tube is used as a second input end of the high-speed dynamic comparator, and the drain electrode of the second NOMS tube is used as a second node and connected with the source electrode of the fourth NMOS tube;
the grid electrode of the third PMOS tube is used as a third node and is connected with the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the seventh NMOS tube and the source electrode of the fifth PMOS tube;
the grid electrode of the fourth PMOS tube is used as a fourth node and is connected with the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the eighth NMOS tube and the source electrode of the sixth PMOS tube;
the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the tenth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the sixth PMOS tube and serves as a first output end of the high-speed dynamic comparator, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the sixth PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the ninth NMOS tube and serves as a second output end of the high-speed dynamic comparator;
the grid electrodes of the first PMOS tube, the second PMOS tube, the third NMOS tube and the fourth NMOS tube are all connected with a first clock signal, the grid electrodes of the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are all connected with a second clock signal, and the first clock signal and the second clock signal are opposite in phase;
the source electrodes of the first NMOS tube, the second NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are all grounded, and the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with power supply voltage;
the high-speed dynamic comparator also comprises an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a seventh PMOS tube and an eighth PMOS tube,
the grid electrode of the seventh PMOS tube is connected with the third node, and the drain electrode of the seventh PMOS tube is connected with the grid electrode of the eleventh NMOS tube and the drain electrode of the thirteenth NMOS tube;
the grid electrode of the eighth PMOS tube is connected with the fourth node, and the drain electrode of the eighth PMOS tube is connected with the grid electrode of the twelfth NMOS tube and the drain electrode of the fifteenth NMOS tube;
the drain electrode of the eleventh NMOS tube is connected with the first node, the source electrode of the eleventh NMOS tube is connected with the source electrode of the twelfth NMOS tube and the drain electrode of the fourteenth NMOS tube, and the drain electrode of the twelfth NMOS tube is connected with the second node;
the grid electrodes of the thirteenth NMOS tube and the fifteenth NMOS tube are connected with the second clock signal, and the grid electrode of the fourteenth NMOS tube is connected with the first clock signal; the source electrodes of the thirteenth NMOS tube, the fourteenth NMOS tube and the fifteenth NMOS tube are all grounded, and the source electrodes of the seventh PMOS tube and the eighth PMOS tube are all connected with power supply voltage.
The working principle of the invention is as follows: according to the invention, the voltages of the third node DIN and the fourth node DIP are reduced to zero from the power voltage VDD through the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3 and the fourth NMOS tube MN4, so that the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are controlled to enable the fifth node DP and the sixth node DN to be increased to the power voltage VDD from zero, and further, the voltage reduction speeds of the first node X and the second node Y and the voltage reduction speeds of the third node DIN and the fourth node DIP are accelerated through the drain currents of the eleventh NMOS tube and the twelfth NMOS tube, so that the third PMOS tube and the fourth PMOS tube can start to work earlier, and the quantization speed of the comparator is accelerated. Meanwhile, due to the fact that the voltage drop speeds of the third node DIN and the fourth node DIP are different, the charging speeds of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 on the fifth node DP and the sixth node DN are different, the discharging speeds of the eleventh NMOS tube and the twelfth NMOS tube on the first node X and the second node Y are also different, and therefore the gain of the input stage of the comparator is increased equivalently, and the noise of the comparator is improved.
The invention has the beneficial effects that: the speed and the noise performance of the comparator are considered, the speed of the comparator is increased by adding an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a seventh PMOS tube MP7 and an eighth PMOS tube MP8, and the noise of the comparator is reduced; in addition, the invention has simple structure and better adaptability with the traditional comparator, is suitable for being applied to high-speed and medium-precision analog-to-digital converters, does not introduce very large kickback noise, and can remarkably improve the performance of the comparator of the pipeline-successive approximation type analog-to-digital converter.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a schematic diagram of a conventional two-stage dynamic comparator.
Fig. 2 is a schematic structural diagram of a high-speed dynamic comparator according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be noted that, in the present invention, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
As shown in fig. 1, which is a schematic structural diagram of a conventional two-stage dynamic comparator, the comparator designed by the present invention introduces a structure capable of increasing speed on the basis, and as seen in fig. 1 and 2, the basic structure of the comparator includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6, a gate of the first NMOS transistor MN1 serves as a first input end of the high-speed dynamic comparator, and a drain thereof serves as a first node X and is connected to a source of the third NMOS transistor MN 3; the grid electrode of the second NOMS tube is used as a second input end of the high-speed dynamic comparator, and the drain electrode of the second NOMS tube is used as a second node Y and is connected with the source electrode of a fourth NMOS tube MN 4; the grid electrode of the third PMOS pipe MP3 is used as a third node DIN and is connected with the drain electrode of the first PMOS pipe MP1 and the drain electrode of the third NMOS pipe MN3, and the drain electrode of the third PMOS pipe MP3 is connected with the drain electrode of the seventh NMOS pipe MN7 and the source electrode of the fifth PMOS pipe MP 5; the gate of the fourth PMOS transistor MP4 is used as a fourth node DIP and is connected to the drain of the second PMOS transistor MP2 and the drain of the fourth NMOS transistor MN4, and the drain is connected to the drain of the eighth NMOS transistor MN8 and the source of the sixth PMOS transistor MP 6; the drain electrode of the fifth PMOS transistor MP5 is connected to the drain electrode of the fifth NMOS transistor MN5, the drain electrode of the tenth NMOS transistor MN10, the gate electrode of the sixth NMOS transistor MN6 and the gate electrode of the sixth PMOS transistor MP6 and serves as the first output end of the high-speed dynamic comparator, and the gate electrode thereof is connected to the gate electrode of the fifth NMOS transistor MN5, the drain electrode of the sixth PMOS transistor MP6, the drain electrode of the sixth NMOS transistor MN6 and the drain electrode of the ninth NMOS transistor MN9 and serves as the second output end of the high-speed dynamic comparator; the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are all connected to a first clock signal CKP, the gates of the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are all connected to a second clock signal CKN, and the first clock signal CKP and the second clock signal CKN are in opposite phase; the source electrodes of the first NMOS transistor MN1, the second NMOS transistor MN2, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 are all grounded, and the source electrodes of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are all connected to the power supply voltage VDD.
The comparator provided by the invention is additionally provided with an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a seventh PMOS tube MP7 and an eighth PMOS tube MP8 on the basis of the graph 1, wherein the grid electrode of the seventh PMOS tube MP7 is connected with a third node DIN, and the drain electrode of the seventh PMOS tube MP7 is connected with the grid electrode of the eleventh NMOS tube MN11 and the drain electrode of the thirteenth NMOS tube MN 13; the gate of the eighth PMOS transistor MP8 is connected to the fourth node DIP, and the drain thereof is connected to the gate of the twelfth NMOS transistor MN12 and the drain of the fifteenth NMOS transistor MN 15; the drain electrode of the eleventh NMOS transistor MN11 is connected with the first node X, the source electrode of the eleventh NMOS transistor MN11 is connected with the source electrode of the twelfth NMOS transistor MN12 and the drain electrode of the fourteenth NMOS transistor MN14, and the drain electrode of the twelfth NMOS transistor MN12 is connected with the second node Y; the gates of the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor MN15 are connected to the second clock signal CKN, and the gate of the fourteenth NMOS transistor MN14 is connected to the first clock signal CKP; the sources of the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, and the fifteenth NMOS transistor MN15 are all grounded, and the sources of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are all connected to the power supply voltage VDD.
The invention provides a two-stage structure, wherein a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a first PMOS tube MP1 and a second PMOS tube MP2 form the input stage of a comparator, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5 and a sixth PMOS tube MP6 form the second-stage structure of the comparator, and an eleventh NMOS tube MN11, a twelfth NMOS tube MN12, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifteenth NMOS tube MN15, a seventh PMOS tube MP7 and an eighth PMOS tube MP8 are newly added structures for improving the speed and the noise performance of the comparator.
The high-speed comparator provided by the present invention includes two input terminals, and the comparator is used for comparing a voltage input by the first input terminal (hereinafter, referred to as a first input voltage VIP) with a voltage input by the second input terminal (hereinafter, referred to as a second input voltage VIN) and outputting a comparison result.
Firstly, when the first clock signal CKP is changed from a low level to a high level, the second clock signal CKN is changed from a high level to a low level, the comparator starts to work, and at the moment, the comparator is in a pre-amplification stage, because the first clock signal CKP is at the high level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are cut off, and the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fourteenth NMOS transistor MN14 are turned on; since the second clock signal CKN is at a low level, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the thirteenth NMOS transistor MN13, and the fifteenth NMOS transistor MN15 are turned off; therefore, the voltages of the third node DIN and the fourth node DIP drop from the power supply voltage VDD at different speeds, and since the first input voltage VIP is greater than the second input voltage VIN in this embodiment, the voltage of the third node DIN drops faster than the voltage of the fourth node DIP, and the voltage of the third node DIN is lower than the voltage of the fourth node DIP. Meanwhile, since the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on and in the deep linear region, the voltages of the first node X and the second node Y are respectively raised to be close to the voltage values of the third node DIN and the fourth node DIP.
When the common mode voltage of the third node DIN drops to VDD-V with the drop of the third node DIN and the fourth node DIP voltageTHMP7When the common mode voltage of the fourth node DIP is reduced to VDD-V, the seventh PMOS transistor MP7 starts to workTHMP8When | the eighth PMOS transistor MP8 starts to work, where VTHMP7Is the threshold voltage, V, of the seventh PMOS transistor MP7THMP8Is the threshold voltage of the eighth PMOS transistor MP 8. The threshold voltages of the seventh and eighth PMOS transistors MP7 and MP8 are the same, and the voltage drop speed of the third node DIN is faster than that of the fourth node DIP, so the common mode voltage of the third node DIN is first dropped to VDD-VTHMP7The seventh PMOS transistor MP7 starts to operate first, and then the eighth PMOS transistor MP8 starts to operate. Since the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor MN15 are turned off, voltages of the fifth node DP (i.e., the drain of the thirteenth NMOS transistor MN 13) and the sixth node DN (i.e., the drain of the fifteenth NMOS transistor MN 15) start to increase, and as the voltages of the fifth node DP and the sixth node DN increase, the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 discharge the first node X and the second node Y, so that the voltage drop speeds of the first node X and the second node Y are increased, and further, the voltage drop speeds of the third node DIN and the fourth node DIP are increased by the third NMOS transistor MN3 and the fourth NMOS transistor MN 4. And because the voltage drop speeds of the third node DIN and the fourth node DIP are different, the charging speeds of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 to the fifth node DP and the sixth node DN, and the discharging speeds of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 to the fifth node X and the sixth node Y are different, which is equivalent to increasing the transconductance of the input stage of the comparator.
Then, as the voltage of the third node DIN and the voltage of the fourth node DIP continue to decrease, the common mode voltage of the third node DIN decreases to VDD-VTHMP3When the fourth node is in the fourth node, the third PMOS transistor MP3 starts to workCommon mode voltage of DIP drops to VDD-VTHMP4When | V, the fourth PMOS tube MP4 starts to workTHMP3And VTHMP4The threshold voltages of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are respectively. Because the voltage of the third node DIN and the voltage of the fourth node DIP have different falling speeds, the voltage of the seventh node QP (i.e., the drain of the third PMOS transistor MP 3) and the voltage of the eighth node QN (i.e., the drain of the fourth PMOS transistor MP 4) have different rising speeds, wherein the voltage of the seventh node QP is greater than the voltage of the eighth node QN. The accelerated voltage drop of the first node X and the second node Y accelerates the voltage drop speed of the third node DIN and the fourth node DIP, and finally accelerates the voltage rise speed of the seventh node QP and the eighth node QN. Since the first input voltage VIP is greater than the second input voltage VIN in this embodiment, the voltage of the seventh node QP is greater than the voltage of the eighth node QN, and when the voltage of the seventh node QP increases to | VTHMP5| when the fifth PMOS transistor MP5 is turned on, where VTHMP5Is the threshold voltage of the fifth PMOS transistor MP5, the comparator is in the regeneration phase, which makes the voltage VOUTP at the first output terminal of the comparator increase. As the voltages of the seventh node QP and the eighth node QN increase, the voltage VOUTP of the first output terminal of the comparator and the voltage VOUTN of the second output terminal of the comparator continue to increase, where VOUTP is greater than VOUTN. When VOUTP increases to VTHMN6Then, the sixth NMOS transistor MN6 is turned on, VTHMN6Is the threshold voltage of the sixth NMOS transistor MN 6. Since VOUTP continues to increase, the drain current of the sixth PMOS transistor MP6 decreases and the drain current of the sixth NMOS transistor MN6 increases, which decreases the voltage increase speed of VOUTN. As VOUTP is gradually increased, the voltage of VOUTN begins to decrease. Finally, the latch composed of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 establishes VOUTP to the supply voltage, and VOUTN to ground.
The above embodiment takes the first input voltage VIP greater than the second input voltage VIN as an example, but the same principle is also used when the first input voltage VIP is less than the second input voltage VIN, which is distinguished in that the voltage of the third node DIN decreases at a slower speed than that of the fourth node DIP, but the decreasing speeds of the third node DIN and the fourth node DIP can be uniformly increased by an increased structure, so that the comparison speed is increased, and finally VOUTP is established to ground and VOUTN is established to the power supply voltage.
In summary, compared with the conventional structure, the two-stage dynamic comparator provided by the present invention adds the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8 to increase the comparison speed, when the first clock signal CKP is set up from low level to high level and the second clock signal CKN is set up from high level to low level, the comparator starts to operate, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are opened and are in a deep linear region, so that the voltages of the first node X and the second node Y are raised to voltages close to the third node DIN and the fourth node DIP when the comparator starts to operate, the falling speeds of the first node X and the second node Y determine the falling speeds of the third node DIN and the fourth node DIP, and therefore determine the falling speeds of the fifth NMOS transistor MN5, the sixth NMOS transistor MN5, the fifth NMOS transistor MP6, and the eighth PMOS transistor MP8, And the time when the latch formed by the sixth PMOS transistor MP6 starts to operate. In the conventional two-stage dynamic comparator, if the descending speeds of the first node X and the second node Y are to be increased, the sizes of the first NMOS transistor MN1 and the second NMOS transistor MN2 can only be increased, but this increases the input capacitance of the comparator and increases the kickback noise of the comparator, thereby limiting the application of the comparator in a high-speed high-precision analog-to-digital converter. However, according to the invention, by introducing the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, when the voltages of the third node DIN and the fourth node DIP start to decrease, the voltages of the fifth node DN and the sixth node DP increase, and the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 discharge the first node X and the second node Y, so that the decreasing speeds of the voltages of the third node DIN and the fourth node DIP are increased, and further the comparison speed of the comparator is increased. Meanwhile, the drain voltage of the third NMOS transistor MN3 and the drain voltage of the fourth NMOS transistor MN4 are different in the reduction speed of the comparator in the pre-amplification stage, that is, the reduction speeds of the voltages of the third node DIN and the fourth node DIP are different, so that the charging speeds of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 on the fifth node DN and the sixth node DP and the discharging speeds of the eleventh NMOS transistor and the twelfth NMOS transistor on the first node X and the second node Y are different, which is equivalent to increasing the gain of the input stage of the comparator and improving the noise of the comparator.
Therefore, according to the working characteristics of the comparator, extra current is generated by introducing the eleventh NMOS tube MN11, the twelfth NMOS tube MN12, the seventh PMOS tube MP7 and the eighth PMOS tube MP8 to discharge the drain electrode of the first NMOS tube MN1 and the drain electrode of the second NMOS tube MN2, namely the first node X and the second node Y, so that the positive feedback loop of the comparator can quickly start to work, the voltage drop speed of the third node DIN and the voltage drop speed of the fourth node DIP are increased, and the comparison speed of the comparator is further remarkably increased.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.

Claims (1)

1. A high-speed dynamic comparator comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor,
the grid electrode of the first NMOS tube is used as a first input end of the high-speed dynamic comparator, and the drain electrode of the first NMOS tube is used as a first node and connected with the source electrode of the third NMOS tube;
the grid electrode of the second NOMS tube is used as a second input end of the high-speed dynamic comparator, and the drain electrode of the second NOMS tube is used as a second node and connected with the source electrode of the fourth NMOS tube;
the grid electrode of the third PMOS tube is used as a third node and is connected with the drain electrode of the first PMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the seventh NMOS tube and the source electrode of the fifth PMOS tube;
the grid electrode of the fourth PMOS tube is used as a fourth node and is connected with the drain electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the eighth NMOS tube and the source electrode of the sixth PMOS tube;
the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the tenth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the sixth PMOS tube and serves as a first output end of the high-speed dynamic comparator, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the sixth PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the ninth NMOS tube and serves as a second output end of the high-speed dynamic comparator;
the grid electrodes of the first PMOS tube, the second PMOS tube, the third NMOS tube and the fourth NMOS tube are all connected with a first clock signal, the grid electrodes of the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are all connected with a second clock signal, and the first clock signal and the second clock signal are opposite in phase;
the source electrodes of the first NMOS tube, the second NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube are all grounded, and the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with power supply voltage;
it is characterized in that the high-speed dynamic comparator also comprises an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a seventh PMOS tube and an eighth PMOS tube,
the grid electrode of the seventh PMOS tube is connected with the third node, and the drain electrode of the seventh PMOS tube is connected with the grid electrode of the eleventh NMOS tube and the drain electrode of the thirteenth NMOS tube;
the grid electrode of the eighth PMOS tube is connected with the fourth node, and the drain electrode of the eighth PMOS tube is connected with the grid electrode of the twelfth NMOS tube and the drain electrode of the fifteenth NMOS tube;
the drain electrode of the eleventh NMOS tube is connected with the first node, the source electrode of the eleventh NMOS tube is connected with the source electrode of the twelfth NMOS tube and the drain electrode of the fourteenth NMOS tube, and the drain electrode of the twelfth NMOS tube is connected with the second node;
the grid electrodes of the thirteenth NMOS tube and the fifteenth NMOS tube are connected with the second clock signal, and the grid electrode of the fourteenth NMOS tube is connected with the first clock signal; the source electrodes of the thirteenth NMOS tube, the fourteenth NMOS tube and the fifteenth NMOS tube are all grounded, and the source electrodes of the seventh PMOS tube and the eighth PMOS tube are all connected with power supply voltage.
CN202110166741.7A 2021-02-04 2021-02-04 High-speed dynamic comparator Expired - Fee Related CN112953496B (en)

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