CN111162786A - Comparator for eliminating kickback noise - Google Patents
Comparator for eliminating kickback noise Download PDFInfo
- Publication number
- CN111162786A CN111162786A CN202010063861.XA CN202010063861A CN111162786A CN 111162786 A CN111162786 A CN 111162786A CN 202010063861 A CN202010063861 A CN 202010063861A CN 111162786 A CN111162786 A CN 111162786A
- Authority
- CN
- China
- Prior art keywords
- tube
- comparator
- input
- nmos
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013139 quantization Methods 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
- H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
Abstract
A comparator for eliminating kickback noise comprises a first reset tube, a second reset tube and a NAND gate, wherein two input ends of the NAND gate are respectively connected with a positive output end and a negative output end of the comparator, and the output ends of the NAND gate are connected with control ends of the first reset tube and the second reset tube; the first reset tube is connected in parallel with two ends of a first input tube of the comparator, and the second reset tube is connected in parallel with two ends of a second input tube of the comparator; a positive input signal of the comparator is input from the first input tube, and a negative input signal of the comparator is input from the second input tube; when the output of the comparator is established in the comparison stage, the first reset tube is conducted with the second reset tube, the first reset tube resets the node from the first input tube to the output end of the comparator, and the second reset tube resets the node from the second input tube to the output end of the comparator. The invention completely eliminates kickback noise from the source electrode and the drain electrode of the input tube to the grid electrode of the input tube by adding the auxiliary reset tube, and can be used for a high-speed SAR ADC adopting a multi-comparator structure.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a comparator for eliminating kickback noise, which can be applied to a high-speed successive approximation type analog-to-digital converter (SAR ADC).
Background
Analog-to-digital converters (ADCs) are a constant topic in analog integrated circuit design, and comparators are widely used in analog-to-digital converters. In application scenarios in many communication fields, the requirement for the speed of the ADC chip is high. In the ultra-high sampling frequency sar ADC, the comparator reset time becomes a major limiting factor for the quantization speed of the ADC. In order to further increase the sampling frequency of the SAR ADC, the SAR ADC with a multi-comparator structure is an effective solution. However, the accuracy of sar adc for multi-comparator architectures is more sensitive to kickback noise of the comparator.
As shown in fig. 1, in the conventional Strong-Arm comparator structure, when the clock signal CLK is low, the comparator is in the reset phase, the MOS transistors M3, M4, M7, M8, M9, and M10 are turned on, and the nodes X, Y, OUTN, OUTP are reset to the power voltage VDD. When the clock signal CLK is high, the comparator is in the comparison stage, if the positive input signal VIP>When the negative-direction output signal VIN is input, the voltage of the node X is decreased faster than that of the node Y, then the voltage of the negative-direction output signal OUTN of the comparator is also rapidly decreased, the decrease of the voltage of the negative-direction output signal OUTN inhibits the conduction of M4 and gradually turns on M6, so that the voltage of the node OUTP is increased, the increase of the voltage of the positive-direction output signal OUTP of the comparator increases the conduction current of M3 and inhibits the conduction of M5, and finally, the output of the negative-direction output signal OUTN is at a low level and the output of the positive-direction output signal OUTP is at a high level. With this configuration, when the clock signal CLK is at a low level, the source-drain voltages of the input transistors M1 and M2 are both pulled up to the power supply voltage VDD. After the clock signal CLK is pulled up to high level, the source voltage of the input transistors M1, M2 is pulled down to the ground level GND, thereby passing through the gate-source overlap capacitance (C) of the input transistorsGS) Kickback noise is generated for the comparator input common mode voltage ((VIP + VIN)/2). If the positive input signal VIP>When the negative input signal VIN is not enough to turn on the input transistor M2, the Y point cannot be pulled down to the ground level GND, and thus, the gate-drain overlap capacitance (C) of the input transistor is not only passed throughGD) Kickback noise is generated for the comparator input common mode voltage and also for the comparator input differential mode voltage (VIP-VIN).
FIG. 2 is the Low kickback noise Strong-Arm ratioThe structure of the device is improved. The circuit differs from the Strong-Arm comparator shown in fig. 1 most significantly in that the input transistors M11, M12 have source ground levels GND, and the clock transistor is positioned above the input transistors. When the clock signal CLK is low, the comparator is in the reset phase, the MOS transistors M15, M16, M19, M20, M21, and M2 are turned on, and the nodes X, Y, OUTN, OUTP are reset to the power voltage VDD. When the clock signal CLK is high, the comparator is in the comparison stage, M13 and M14 are turned on, if the positive input signal VIP>When the negative-direction output signal VIN is input, the node X is decreased faster than the voltage Y, then the voltage of the negative-direction output signal OUTN is also rapidly decreased, and the decrease of the voltage of the negative-direction output signal OUTN inhibits the conduction of M16 and gradually turns on M18, so that the voltage of the positive-direction output signal OUTP is increased, the increase of the voltage of the positive-direction output signal OUTP increases the conduction current of M15 and inhibits the conduction of M17, and finally, the output of the negative-direction output signal OUTN is at a low level and the output of the positive-direction output signal OUTP is at a high level. The idea of the circuit structure for reducing kickback noise is as follows: the source levels of the input tubes M11 and M12 are always grounded at the GND level, and the source voltage of the input tubes cannot change in the process of changing the clock from the low level to the high level, so that kickback noise is greatly reduced. However, this circuit configuration does not eliminate kickback noise from the input tube drain (node A, B). If the positive input signal VIP>When the negative input signal VIN is not enough to turn on the input transistor M12, the node B cannot be pulled down to the ground level GND, and thus the gate-drain overlap capacitance (C) of the input transistor is passed throughGD) Kickback noise is generated on the input differential mode voltage (VIP-VIN) of the comparator, and the quantization precision of the SAR ADC is greatly influenced, especially in the SARADC structure.
Disclosure of Invention
Aiming at the problem of kickback noise existing in the traditional comparator structure, the invention provides the comparator for eliminating the kickback noise, which completely isolates the influence of the kickback noise on ADC quantization by adding the auxiliary reset tube and can be used for the comparator of the high-speed SAR ADC adopting a multi-comparator structure.
The technical scheme of the invention is as follows:
a comparator for eliminating kickback noise, the comparator is a dynamic comparator controlled by a clock;
when the comparator is controlled by a clock signal to be in a reset stage, a positive output end and a negative output end of the comparator are reset;
when the clock signal controls the comparator to be in a comparison stage, the comparator compares a positive input signal with a negative input signal to obtain a comparison result;
the comparator comprises a first reset tube, a second reset tube and a NAND gate,
two input ends of the NAND gate are respectively connected with the positive output end and the negative output end of the comparator, and the output ends of the NAND gate are connected with the control ends of the first reset tube and the second reset tube;
the first reset tube is connected in parallel with two ends of a first input tube of the comparator, and the second reset tube is connected in parallel with two ends of a second input tube of the comparator;
a positive input signal of the comparator is input from the first input tube, and a negative input signal of the comparator is input from the second input tube;
when the output of the comparator in the comparison stage is established, the first reset tube and the second reset tube are conducted, the first reset tube resets the node from the first input tube to the output end of the comparator, and the second reset tube resets the node from the second input tube to the output end of the comparator.
Specifically, the first input tube is a first NMOS tube, the second input tube is a second NMOS tube, the first reset tube is a third NMOS tube, and the second reset tube is a fourth NMOS tube;
the grid electrode of the first NMOS tube is connected with a positive input signal of the comparator, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is a node from the first input tube to the output end of the comparator;
the grid electrode of the third NMOS tube is connected with the output end of the NAND gate, the source electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and is grounded, and the drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the second NMOS tube is connected with a negative input signal of the comparator, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is a node from the second input tube to the output end of the comparator;
the grid of the fourth NMOS tube is connected with the output end of the NAND gate, the source electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube and is grounded, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube.
Specifically, the comparator further comprises a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor,
the grid electrodes of the fifth NMOS transistor, the sixth NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor are connected with the clock signal;
the source electrode of the fifth NMOS tube is connected with the node from the first input tube to the output end of the comparator, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the seventh NMOS tube and the drain electrode of the fifth PMOS tube;
the source electrode of the sixth NMOS tube is connected with the node from the second input tube to the output end of the comparator, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the eighth NMOS tube and the drain electrode of the sixth PMOS tube;
the grid electrode of the first PMOS tube is connected with the drain electrodes of the second PMOS tube, the fourth PMOS tube and the eighth NMOS tube and the grid electrode of the seventh NMOS tube and serves as the positive output end of the comparator, the drain electrode of the first PMOS tube is connected with the drain electrodes of the third PMOS tube and the seventh NMOS tube and the grid electrodes of the second PMOS tube and the eighth NMOS tube and serves as the negative output end of the comparator, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with power voltage.
The invention has the beneficial effects that: the comparator provided by the invention is added with the auxiliary reset tube controlled by the output of the comparator, thereby completely eliminating kickback noise from the source electrode and the drain electrode of the input tube to the grid electrode of the input tube (namely the input of the comparator), and being suitable for the comparator of the high-speed SAR ADC adopting a multi-comparator structure.
Drawings
FIG. 1 is a schematic diagram of a conventional Strong-Arm comparator.
Fig. 2 is a schematic diagram of a modified structure of a low kickback noise Strong-Arm comparator.
Fig. 3 is a circuit configuration diagram of a comparator for eliminating kickback noise according to an embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
In the low kickback noise improvement structure based on the Strong-Arm comparator shown in fig. 2, the basic idea of reducing the kickback noise is that during the transition of the clock signal CLK from 0 to 1, the drain voltages of the input transistors M11 and M12 are both reset to the ground potential GND, thereby reducing the kickback noise of the comparator. However, in the working process of the comparator, the two input signals VIP and VIN of the comparator cannot ensure that the input transistor is in a conducting state, and in order to reduce the equivalent noise input by the comparator, a large transconductance current ratio (Gm/Id) of the input transistor is required, which limits the overdrive voltage of the input transistor, so that the input transistor cannot timely discharge the drain voltage thereof, and the structure may not completely eliminate the kickback noise because the drain voltage of the input transistor cannot be timely reset.
On the basis, two auxiliary reset tubes controlled by the output result of the comparator are added, the reset process is accelerated, and kickback noise of the comparator can be completely eliminated by the mode. As shown in fig. 3, the comparator proposed by the present invention adds a nand gate and two auxiliary reset tubes to the original low kickback noise comparator structure in fig. 2. This design is not only suitable for the improvement of the comparator of the structure of fig. 2, but also suitable for other clocked dynamic comparators. Two input ends of the NAND gate are respectively connected with the positive output end and the negative output end of the comparator, and the output ends of the NAND gate are connected with the control ends of the first reset tube and the second reset tube; the first reset tube is connected in parallel with two ends of a first input tube of the comparator, and the second reset tube is connected in parallel with two ends of a second input tube of the comparator; a positive input signal VIP of the comparator is input from a first input tube, and a negative input signal VIN of the comparator is input from a second input tube; when the output of the comparator is established in the comparison stage, the first reset tube is conducted with the second reset tube, the first reset tube resets the node from the first input tube to the output end of the comparator, and the second reset tube resets the node from the second input tube to the output end of the comparator.
As shown in fig. 3, when the input pair transistors of the comparator are NMOS transistors, the first input transistor is a first NMOS transistor MN1, the second input transistor is a second NMOS transistor MN2, the first reset transistor is a third NMOS transistor MN3, and the second reset transistor is a fourth NMOS transistor MN 4; the grid electrode of the first NMOS transistor MN1 is connected with a positive input signal VIP of the comparator, the source electrode of the first NMOS transistor is grounded, and the drain electrode of the first NMOS transistor is a node from the first input transistor to the output end of the comparator; the grid electrode of the third NMOS transistor MN3 is connected with the output end of the NAND gate, the source electrode of the third NMOS transistor MN3 is connected with the source electrode of the first NMOS transistor MN1 and is grounded, and the drain electrode of the third NMOS transistor MN3 is connected with the drain electrode of the first NMOS transistor MN 1; the grid electrode of the second NMOS tube MN2 is connected with the negative input signal VIN of the comparator, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is a node from the second input tube to the output end of the comparator; the gate of the fourth NMOS transistor MN4 is connected to the output of the nand gate, the source thereof is connected to the source of the second NMOS transistor MN2 and grounded, and the drain thereof is connected to the drain of the second NMOS transistor MN 2.
As shown in fig. 3, the comparator further includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6, wherein gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MP6, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are connected to a clock signal CLK; the source electrode of the fifth NMOS transistor MN5 is connected with the node from the first input transistor to the output end of the comparator, namely the drain electrode of the first NMOS transistor MN1, and the drain electrode of the fifth NMOS transistor MN5 is connected with the source electrode of the seventh NMOS transistor MN7 and the drain electrode of the fifth PMOS transistor MP 5; the source electrode of the sixth NMOS transistor MN6 is connected to the node from the second input transistor to the output end of the comparator, namely the drain electrode of the second NMOS transistor MN2, and the drain electrode of the sixth NMOS transistor MN6 is connected to the source electrode of the eighth NMOS transistor MN8 and the drain electrode of the sixth PMOS transistor MP 6; the grid electrode of the first PMOS transistor MP1 is connected to the drain electrodes of the second PMOS transistor MP2, the fourth PMOS transistor MP4 and the eighth NMOS transistor MN8 and the grid electrode of the seventh NMOS transistor MN7 and serves as the positive output end of the comparator, the drain electrode thereof is connected to the drain electrodes of the third PMOS transistor MP3 and the seventh NMOS transistor MN7 and the grid electrodes of the second PMOS transistor MP2 and the eighth NMOS transistor MN8 and serves as the negative output end of the comparator, and the source electrode thereof is connected to the source electrodes of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 and is connected to the power supply voltage VDD.
The working principle of the comparator for eliminating kickback noise in the present embodiment is described in detail below.
When the clock signal CLK is at a low level, the comparator is in a reset stage, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are turned on, and the negative output node signal OUTN of the comparator and the positive output node signal OUTP of the comparator are reset to the power voltage VDD. When the clock signal CLK is at a high level, the comparator is in a comparison stage, after the output result of the comparator is established, one of the positive output node signal OUTP of the comparator and the negative output node signal OUTN of the comparator is pulled down to the ground level GND, the output result of the nand gate jumps to a high level, and the auxiliary reset transistor MN3 and the auxiliary reset transistor MN4 quickly pull down the node a (the drain terminal of the first NMOS transistor MN 1) and the node B (the drain terminal of the second NMOS transistor MN 2) to the ground level GND. Until the clock signal CLK jumps to a low level again, the positive output node signal OUTP of the comparator and the negative output node signal OUTN of the comparator are pulled up to the power supply voltage VDD, the nand gate outputs a low level, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 of the auxiliary reset transistor are turned off, and the node A, B keeps the ground level GND until the next clock signal CLK jumps. It can be seen that during the transition of the comparator from the reset state to the comparison complete state, the initial state (comparator reset) and the final state (comparison complete) of the voltage at node A, B do not change (both reset to GND). In the working process of the SAR ADC, the comparator can completely eliminate the influence of kickback noise on quantization.
The comparator circuit provided by the invention completely eliminates kickback noise from the source and drain of the input tube to the grid (input of the comparator) due to the addition of the auxiliary reset tube. Therefore, compared with the existing comparator structure with the improved low kickback noise Strong-Arm, the influence of the kickback noise on the quantization precision of the SAR ADC is further eliminated, and the comparator structure is more suitable for the SAR ADC with the high-speed multi-comparator structure.
Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its broader aspects.
Claims (3)
1. A comparator for eliminating kickback noise, the comparator is a dynamic comparator controlled by a clock;
when the comparator is controlled by a clock signal to be in a reset stage, a positive output end and a negative output end of the comparator are reset;
when the clock signal controls the comparator to be in a comparison stage, the comparator compares a positive input signal with a negative input signal to obtain a comparison result;
it is characterized in that the comparator comprises a first reset tube, a second reset tube and a NAND gate,
two input ends of the NAND gate are respectively connected with the positive output end and the negative output end of the comparator, and the output ends of the NAND gate are connected with the control ends of the first reset tube and the second reset tube;
the first reset tube is connected in parallel with two ends of a first input tube of the comparator, and the second reset tube is connected in parallel with two ends of a second input tube of the comparator;
a positive input signal of the comparator is input from the first input tube, and a negative input signal of the comparator is input from the second input tube;
when the output of the comparator in the comparison stage is established, the first reset tube and the second reset tube are conducted, the first reset tube resets the node from the first input tube to the output end of the comparator, and the second reset tube resets the node from the second input tube to the output end of the comparator.
2. The comparator for eliminating kickback noise according to claim 1, wherein the first input transistor is a first NMOS transistor, the second input transistor is a second NMOS transistor, the first reset transistor is a third NMOS transistor, and the second reset transistor is a fourth NMOS transistor;
the grid electrode of the first NMOS tube is connected with a positive input signal of the comparator, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is a node from the first input tube to the output end of the comparator;
the grid electrode of the third NMOS tube is connected with the output end of the NAND gate, the source electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and is grounded, and the drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the second NMOS tube is connected with a negative input signal of the comparator, the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is a node from the second input tube to the output end of the comparator;
the grid of the fourth NMOS tube is connected with the output end of the NAND gate, the source electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube and is grounded, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube.
3. The comparator for eliminating kickback noise of claim 2, wherein the comparator further comprises a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor,
the grid electrodes of the fifth NMOS transistor, the sixth NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor are connected with the clock signal;
the source electrode of the fifth NMOS tube is connected with the node from the first input tube to the output end of the comparator, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the seventh NMOS tube and the drain electrode of the fifth PMOS tube;
the source electrode of the sixth NMOS tube is connected with the node from the second input tube to the output end of the comparator, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the eighth NMOS tube and the drain electrode of the sixth PMOS tube;
the grid electrode of the first PMOS tube is connected with the drain electrodes of the second PMOS tube, the fourth PMOS tube and the eighth NMOS tube and the grid electrode of the seventh NMOS tube and serves as the positive output end of the comparator, the drain electrode of the first PMOS tube is connected with the drain electrodes of the third PMOS tube and the seventh NMOS tube and the grid electrodes of the second PMOS tube and the eighth NMOS tube and serves as the negative output end of the comparator, and the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with power voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010063861.XA CN111162786B (en) | 2020-01-20 | 2020-01-20 | Comparator for eliminating kickback noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010063861.XA CN111162786B (en) | 2020-01-20 | 2020-01-20 | Comparator for eliminating kickback noise |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111162786A true CN111162786A (en) | 2020-05-15 |
| CN111162786B CN111162786B (en) | 2022-03-29 |
Family
ID=70564440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010063861.XA Expired - Fee Related CN111162786B (en) | 2020-01-20 | 2020-01-20 | Comparator for eliminating kickback noise |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111162786B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112953496A (en) * | 2021-02-04 | 2021-06-11 | 电子科技大学 | High-speed dynamic comparator |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944895A (en) * | 2010-09-14 | 2011-01-12 | 复旦大学 | CMOS clocked comparator with low kickback noise |
| CN105763192A (en) * | 2016-02-01 | 2016-07-13 | 东南大学 | Low time-delay comparator suitable for high-speed analog-digital converter |
| US20180069566A1 (en) * | 2016-09-06 | 2018-03-08 | Texas Instruments Incorporated | Inbuilt threshold comparator |
| CN107888171A (en) * | 2017-11-16 | 2018-04-06 | 上海北京大学微电子研究院 | A kind of high speed is low to recalcitrate noise dynamic comparer and circuit |
| US20180262203A1 (en) * | 2017-03-09 | 2018-09-13 | Semiconductor Manufacturing International (Shanghai) Corporation | Comparator and successive approximation analog-to-digital converter thereof |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
| CN109923493A (en) * | 2016-12-05 | 2019-06-21 | 德州仪器公司 | Voltage clamping circuit |
| US20190238150A1 (en) * | 2019-04-04 | 2019-08-01 | Intel Corporation | High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (adc) |
| CN110244832A (en) * | 2018-03-07 | 2019-09-17 | 三星电子株式会社 | Semiconductor circuit and semiconductor system |
-
2020
- 2020-01-20 CN CN202010063861.XA patent/CN111162786B/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944895A (en) * | 2010-09-14 | 2011-01-12 | 复旦大学 | CMOS clocked comparator with low kickback noise |
| CN105763192A (en) * | 2016-02-01 | 2016-07-13 | 东南大学 | Low time-delay comparator suitable for high-speed analog-digital converter |
| US20180069566A1 (en) * | 2016-09-06 | 2018-03-08 | Texas Instruments Incorporated | Inbuilt threshold comparator |
| CN109923493A (en) * | 2016-12-05 | 2019-06-21 | 德州仪器公司 | Voltage clamping circuit |
| US20180262203A1 (en) * | 2017-03-09 | 2018-09-13 | Semiconductor Manufacturing International (Shanghai) Corporation | Comparator and successive approximation analog-to-digital converter thereof |
| CN107888171A (en) * | 2017-11-16 | 2018-04-06 | 上海北京大学微电子研究院 | A kind of high speed is low to recalcitrate noise dynamic comparer and circuit |
| CN110244832A (en) * | 2018-03-07 | 2019-09-17 | 三星电子株式会社 | Semiconductor circuit and semiconductor system |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
| US20190238150A1 (en) * | 2019-04-04 | 2019-08-01 | Intel Corporation | High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (adc) |
Non-Patent Citations (5)
| Title |
|---|
| H. XU: "Analysis and Design of Regenerative Comparators for Low Offset and Noise", 《IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS》 * |
| L. FILIPPINI: "The Adiabatically Driven StrongARM Comparator", 《IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS》 * |
| 何生生: "一种采用冗余位技术的12位SAR ADC的设计与研究", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 * |
| 包晴晴: "一种基于伪随机噪声注入的流水线ADC数字校准算法", 《电子与封装》 * |
| 李靖坤: "高速低功耗CMOS动态锁存比较器的设计", 《华侨大学学报(自然科学版)》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112953496A (en) * | 2021-02-04 | 2021-06-11 | 电子科技大学 | High-speed dynamic comparator |
| CN112953496B (en) * | 2021-02-04 | 2022-04-22 | 电子科技大学 | High-speed dynamic comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111162786B (en) | 2022-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108574489B (en) | Comparator and successive approximation type analog-digital converter | |
| US11095300B2 (en) | Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter | |
| CN111200402B (en) | High-linearity dynamic residual error amplifier circuit capable of improving gain | |
| CN111446966B (en) | Single-phase clock high-speed low-power consumption dynamic comparator applied to SAR ADC | |
| CN108270420B (en) | Comparator and successive approximation type analog-digital converter | |
| CN105763192A (en) | Low time-delay comparator suitable for high-speed analog-digital converter | |
| CN112953503B (en) | High-linearity grid voltage bootstrap switch circuit | |
| Kim et al. | Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages | |
| CN106067822B (en) | High-speed and high-precision CMOS latch comparator | |
| CN110912540A (en) | High-speed pre-amplification latch comparator with low dynamic mismatch | |
| CN115333515A (en) | Dynamic comparator with low kickback noise | |
| CN112671382A (en) | Grid voltage bootstrap switch circuit | |
| CN111162786B (en) | Comparator for eliminating kickback noise | |
| CN114257222A (en) | Single-clock control high-speed comparator circuit | |
| CN114389585A (en) | High-speed low-offset latch comparator | |
| CN112953420B (en) | Dynamic operational amplifier circuit with input tube in linear region | |
| CN113422594B (en) | Dynamic comparator | |
| CN111313871A (en) | Dynamic pre-amplifying circuit and dynamic comparator | |
| CN112953496B (en) | High-speed dynamic comparator | |
| CN215682235U (en) | Circuit and comparator | |
| CN113067557B (en) | High-speed full-differential comparator circuit with voltage conversion | |
| CN107294535B (en) | Comparator and successive approximation type analog-to-digital converter | |
| CN117394858B (en) | Comparator, analog-to-digital converter and device for reducing kickback noise | |
| US11381207B2 (en) | Apparatus and method for an analog to digital converter | |
| Yu et al. | A low kick back noise latched comparator for high speed folding and interpolating ADC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20220329 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |