CN106209098A - A kind of digital to analog converter - Google Patents
A kind of digital to analog converter Download PDFInfo
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- CN106209098A CN106209098A CN201610512520.XA CN201610512520A CN106209098A CN 106209098 A CN106209098 A CN 106209098A CN 201610512520 A CN201610512520 A CN 201610512520A CN 106209098 A CN106209098 A CN 106209098A
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- pmos
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- amplifier
- resistance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Abstract
The invention discloses a kind of digital to analog converter, including decoder, current steer module, current source, the first amplifier, the first resistance；Described current steer module has several switching current cells, and the outfan of each switching current cells is connected to the total current node of described current steer module；Described decoder has several signal output parts connected one to one with several switching current cells described；The normal phase input end of described first amplifier is connected with bias voltage；The voltage output end that outfan is digital to analog converter of described first amplifier, and the negative-phase input of described first amplifier it is connected to by described first resistance；The current output terminal of described current source and the negative-phase input of described first amplifier are connected to described total current node.The present invention can eliminate the bias voltage impact on output voltage swing, reduces the minima of output voltage so that the current steering digital-to-analog converter of Single-end output can be applied in the product of low-voltage and low-power dissipation.
Description
Technical field
The present invention relates to electronic circuit technology field, particularly relate to a kind of digital to analog converter.
Background technology
In battery powered portable equipment, the digital to analog converter of single ended voltage output is one of extremely important module.
Current steering digital-to-analog converter (Current Steering Digital toAnalog Converter) matching precision is high, rings
Answer speed high, be widely used.Use buffer amplifier to convert electrical current into voltage, be that to realize current steering digital-to-analog converter single-ended
A kind of major technique of voltage output.
Fig. 1 is the digital to analog converter based on current steer of a kind of single ended voltage output of prior art.In current steer module
There are several switching current cells.Output amplifier is used to electric current to be converted to output voltage, improves the ability driving load.Instead
Feed resistance Rfb and current-controlled switch are connected to export the negative input end of amplifier.The positive input termination bias voltage of output amplifier
Vp, Vp have a minima, when Vp is less than minima, and switching current cells cisco unity malfunction.
Due to the relation that the void of operational amplifier is short and void is disconnected, the electric current flowing through feedback resistance Rfb is the described electricity of inflow
Total current Io of stream source array, then can be calculated output voltage and be equal to
Vout=Io × Rfb+Vp (1)
Owing to the value of Io depends on digital logic signal, and the minima of Io is 0, then the minima of Vout is Vp.Right
In the switching current cells of the cascode structure using two transistors, the minima of bias voltage Vp is two electricity of overdriving
Pressure.If using 180nm technique, then bias voltage Vp minima is usually 0.4V.It is to say, the current steer type of Single-end output
The minimum output voltage of digital to analog converter is 0.4V.Low-voltage and low-power dissipation application can use the even lower supply voltage of 1.2V, above-mentioned
The minimum output voltage of 0.4V accounts for 1/3rd of 1.2V supply voltage so that the current steering digital-to-analog converter of Single-end output without
Method is applied in the product of low-voltage and low-power dissipation.
Summary of the invention
The embodiment of the present invention proposes a kind of digital to analog converter, it is possible to eliminate the bias voltage impact on output voltage swing,
Reduce the minima of output voltage so that the current steering digital-to-analog converter of Single-end output can apply the product at low-voltage and low-power dissipation
In product.
The digital to analog converter of the embodiment of the present invention includes decoder, current steer module, current source, the first amplifier, the first electricity
Resistance；
Described current steer module has several switching current cells, and the outfan of each switching current cells is connected to institute
State the total current node of current steer module；
Described decoder has several signal output parts connected one to one with several switching current cells described,
For the digital logic signal of input is converted to control signal, control corresponding switching current cells on or off；
The normal phase input end of described first amplifier is connected with bias voltage；The outfan of described first amplifier is digital-to-analogue conversion
The voltage output end of device, and the negative-phase input of described first amplifier it is connected to by described first resistance；Described current source
The negative-phase input of current output terminal and described first amplifier is connected to described total current node.
As it is highly preferred that described current source is voltage-controlled type current source.
In one embodiment, described current source include the second amplifier, the first NMOS tube, the first PMOS, second
PMOS and the second resistance；
The normal phase input end of described second amplifier is connected with controlling voltage；The outfan of described second amplifier and described first
The grid of NMOS tube connects；The negative-phase input of described second amplifier is connected with the source electrode of described first NMOS tube, and passes through institute
State the second resistance eutral grounding；
The drain electrode of described first NMOS tube is connected with the drain electrode of described first PMOS, and with the grid of described first PMOS
Pole, the grid of described second PMOS connect；The source electrode of described first PMOS is connected to the source electrode of described second PMOS
Supply voltage；The drain electrode of the second PMOS is connected with the current output terminal of described current source.
As it is highly preferred that described current source also includes the 3rd PMOS, the 3rd resistance and the 4th resistance；
The drain electrode of described second PMOS is connected with the current output terminal of described current source, particularly as follows:
The drain electrode of described second PMOS is connected with the source electrode of described 3rd PMOS；The drain electrode of described 3rd PMOS with
The current output terminal of described current source connects；The grid of described 3rd PMOS is by described 3rd resistance and described supply voltage
Connect；The grid of described 3rd PMOS passes through described 4th resistance eutral grounding.
As it is highly preferred that described bias voltage is equal to described control voltage.
In another embodiment, described current source include the second amplifier, the first PMOS, the first NMOS tube, second
NMOS tube and the second resistance；
The normal phase input end of described second amplifier is connected with controlling voltage；The outfan of described second amplifier and described first
The grid of PMOS connects；The negative-phase input of described second amplifier is connected with the source electrode of described first PMOS, and passes through institute
State the second resistance to be connected with supply voltage；
The drain electrode of described first PMOS is connected with the drain electrode of described first NMOS tube, and with the grid of described first NMOS tube
Pole, the grid of described second NMOS tube connect；The source electrode of described first NMOS tube and the source ground of described second NMOS tube；The
The drain electrode of two NMOS tube is connected with the current output terminal of described current source.
As it is highly preferred that described current source also includes the 3rd NMOS tube, the 3rd resistance and the 4th resistance；
The drain electrode of described second NMOS tube is connected with the current output terminal of described current source, particularly as follows:
The drain electrode of described second NMOS tube is connected with the source electrode of described 3rd NMOS tube；The drain electrode of described 3rd NMOS tube with
The current output terminal of described current source connects；The grid of described 3rd NMOS tube is by described 3rd resistance and described supply voltage
Connect；The grid of described 3rd NMOS tube passes through described 4th resistance eutral grounding.
As it is highly preferred that described bias voltage is equal to described control voltage.
As it is highly preferred that described switching current cells includes electron current source and switch；Institute is passed through in described electron current source
State switch and be connected to described total current node；The signal that the control end of described switch is connected to described decoder corresponding is defeated
Go out end.
As it is highly preferred that described switch is the first transistor；Described the first transistor first connection pole with described always
Current node connects, and the second connection pole of described the first transistor is connected with the outfan in described electron current source；Described first is brilliant
The signal output part controlling pole corresponding with described decoder of body pipe connects.
As it is highly preferred that described switching current cells also includes current-limiting resistance and transistor seconds；Described second is brilliant
First connection pole of body pipe by current-limiting resistance ground connection or connects power supply；Second connection pole of described transistor seconds and described son electricity
The outfan in stream source connects；The inversion signal controlling pole controlling pole and described the first transistor of described transistor seconds is even
Connect.
As it is highly preferred that described digital logic signal is N position, described current steer module includes 2N-1 described switch electricity
Flow unit, and the conducting electric current of each described switching current cells is Iu；
Then flow through electric current Io=Iu × (2 of described total current nodeN-1×bN-1+2N-2×bN-2+...+2×b1+b0)
Wherein, bN-1,bN-2...b1,b0N number of occurrence for described digital logic signal.
As it is highly preferred that described digital to analog converter also includes input register；Described input register and described decoding
The input of device connects, for the digital logic signal to be input to described decoder is latched compared to prior art,
Having the beneficial effects that of the embodiment of the present invention: the invention provides a kind of digital to analog converter, including decoder, current steer module,
Current source, the first amplifier, the first resistance；Described current steer module has several switching current cells, each switching current list
The outfan of unit is connected to the total current node of described current steer module；Described decoder has and several switching currents described
Several signal output parts that unit connects one to one, for the digital logic signal of input is converted to control signal, control
Make corresponding switching current cells on or off；The normal phase input end of described first amplifier is connected with bias voltage；Described
The outfan of one amplifier is the voltage output end of digital to analog converter, and is connected to described first amplifier by described first resistance
Negative-phase input；The current output terminal of described current source and the negative-phase input of described first amplifier are connected to described total current
Node.The present invention uses a kind of current source to produce a bias current Ib, and this bias current is injected into the negative of output amplifier
Input, flows through the first resistance R1 and produces pressure drop Ib × R1, and the difference of this pressure drop Ib × R1 and bias voltage Vp is that digital-to-analogue turns
The minima of parallel operation output voltage.When they size couplings, the output voltage minima of digital to analog converter can arrive power supply ground, from
And rail-to-rail output voltage can be realized.The present invention can eliminate the bias voltage impact on output voltage swing, reduces output
The minima of voltage so that the current steering digital-to-analog converter of Single-end output can be applied in the product of low-voltage and low-power dissipation.
Accompanying drawing explanation
Fig. 1 is the digital to analog converter based on current steer of a kind of single ended voltage output of prior art；
Fig. 2 is the structured flowchart of a kind of digital to analog converter that the embodiment of the present invention provides；
Fig. 3 is the circuit diagram of a kind of embodiment of the current source 3 in the embodiment of the present invention；
Fig. 4 is the circuit diagram of the another embodiment of the current source 3 in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
As in figure 2 it is shown, it is the structured flowchart of a kind of digital to analog converter that the embodiment of the present invention provides.
Described digital to analog converter includes decoder 1, current steer module 2, current source the 3, first amplifier A1, the first resistance R1；
Described current steer module 2 has several switching current cells, and the outfan of each switching current cells is connected to
The total current node of described current steer module 2；
Described decoder 1 has several signals output connected one to one with several switching current cells described
End, for the digital logic signal of input is converted to control signal, controls corresponding switching current cells on or off；
The normal phase input end of described first amplifier is connected with bias voltage；The outfan of described first amplifier is digital-to-analogue conversion
The voltage output end of device, and the negative-phase input of described first amplifier it is connected to by described first resistance；Described current source
The negative-phase input of current output terminal and described first amplifier is connected to described total current node.
Due to described first amplifier A1 " empty short ", the electric current Io flowing through described total current node can be obtained equal to described electricity
The output electric current Ib in stream source 3 and the feedback current Ic sum flowing through described first resistance R1, the output of the most described digital to analog converter
Voltage
Vout=(Io-Ib) × R1+Vp=Io × R1+Vp-Ib × R1 (2)
Compared with the scheme of prior art, the embodiment of the present invention introduces the current source 3 being connected with total current node, at meter
Count the output voltage Vout of weighted-voltage D/A converter time, formula (2) than formula (1) add "-Ib × R1 " this such that it is able to eliminate partially
Put the voltage Vp impact on the output voltage Vout amplitude of oscillation, reduce the minima of Vout so that the current steer type number of Single-end output
Weighted-voltage D/A converter can be applied in the product of low-voltage and low-power dissipation.
As it is highly preferred that as Vp-Ib × R1=0, the minima of Vout is 0, it is possible to achieve rail-to-rail target.
As it is highly preferred that digital to analog converter also includes input register 4；Described input register 4 and described decoder 1
Input connect, for the digital logic signal to be input to described decoder 1 is latched.
Specifically, described switching current cells includes electron current source and switch；Described switch is passed through in described electron current source
It is connected to described total current node；The end that controls of described switch is connected to the signal output part that described decoder 1 is corresponding.
In the present embodiment, described switch is the first transistor；Described the first transistor first connection pole with described always
Current node connects, and the second connection pole of described the first transistor is connected with the outfan in described electron current source；Described first is brilliant
The signal output part controlling pole corresponding with described decoder 1 of body pipe connects.
As it is highly preferred that described switching current cells also includes current-limiting resistance and transistor seconds；Described second is brilliant
First connection pole of body pipe by current-limiting resistance ground connection or connects power supply；Second connection pole of described transistor seconds and described son electricity
The outfan in stream source connects；The inversion signal controlling pole controlling pole and described the first transistor of described transistor seconds is even
Connect.Owing to the first transistor and described transistor seconds are complementary, therefore both necessarily have and only one of which is conducting so that institute
State electron current source and can be always maintained at the state of conducting, decrease the response time that described electron current source produces because of switch,
Improve the response speed of whole digital to analog converter.
In the present embodiment, described digital logic signal is N position, and described current steer module 2 includes 2N-1 described switch
Current unit, and the conducting electric current of each described switching current cells is Iu；Then flow through the electric current of described total current node
Io=Iu × (2N-1×bN-1+2N-2×bN-2+...+2×b1+b0) (3)
Wherein, bN-1,bN-2...b1,b0For N number of occurrence of described digital logic signal, come described digital logic signal
Determine that a how many current branch are conductings.
Convolution (2) and formula (3) can obtain the output voltage of digital to analog converter
Vout=Iu × (2N-1×bN-1+2N-2×bN-2+...+2×b1+b0)×R1+Vp-Ib×R1 (4)
Such as, take N=3, the most described current steer module 2 has 7 switching current cells；It is input to 3 figure places of decoder 1
Word logical signal is respectively (1,0,1) from a high position to low level, then need to control 5 switching current cells conductings.Decoder 1 receives
After the digital logic signal of (1,0,1), generate control signal for making the conducting of 5 switching current cells (0,0,1,1,1,
1,1)；Wherein, each in control signal is corresponding to a switch of described current steer module 2, when control signal is 0,
Corresponding switch OFF makes corresponding switching current cells end, and when control signal is 1, corresponding switch Guan Bi makes phase
The switching current conducting answered.It should be noted that the position that " 1 " in control signal occurs can be random, it is also possible to be excellent
First distributing from low level, having 5 " 1 " to make the scheme of 5 switching current cells conductings broadly fall into the protection of the present invention as long as meeting
In the range of.
The current steer module 2 of the present invention is not limited to above-mentioned structure, it is also possible to be to include N number of described switching current cells,
And the conducting electric current of the 1st switching current cells is Iu, the conducting electric current of i+1 switching current cells is i-th switch
The twice of the conducting electric current of current unit, then flow through electric current Io=Iu × (2 of described total current nodeN-1×bN-1+2N-2×bN-2
+...+2×b1+b0)
Wherein, bN-1,bN-2...b1,b0For N number of occurrence of described digital logic signal, come described digital logic signal
Determine which current branch is conducting.
As it is highly preferred that described current source 3 is voltage-controlled type current source.
As it is shown on figure 3, it is the circuit diagram of a kind of embodiment of current source 3 in the embodiment of the present invention.
In described a kind of embodiment, described current source 3 includes the second amplifier A2, the first NMOS tube Mn1, a PMOS
Pipe Mp1, the second PMOS Mp2 and the second resistance R2；
The normal phase input end of described second amplifier A2 is connected with controlling voltage Vc；The outfan of described second amplifier A2 and institute
The grid stating the first NMOS tube Mn1 connects；The negative-phase input of described second amplifier A2 and the source electrode of described first NMOS tube Mn1
Connect, and by described second resistance R2 ground connection；
The drain electrode of described first NMOS tube Mn1 is connected with the drain electrode of described first PMOS Mp1, and with a described PMOS
The grid of pipe Mp1, the grid of described second PMOS Mp2 connect；The source electrode of described first PMOS Mp1 and described 2nd PMOS
The source electrode of pipe Mp2 is connected to supply voltage Vdd；The drain electrode of the second PMOS Mp2 is with the current output terminal of described current source 3 even
Connect.
Wherein, described second amplifier A2, described first NMOS tube Mn1 and described second resistance R2 are used for producing electric current
Ib0, Ib0=Vc/R2.Described first PMOS Mp1 and described second PMOS Mp2 are for producing the image current of Ib0, i.e. institute
State the output electric current Ib, Ib=Ib0=Vc/R2 of current source 3.
Then convolution (4) can obtain the output voltage of digital to analog converter
Vout=Iu × (2N-1×bN-1+2N-2×bN-2+...+2×b1+b0)×R1+Vp-Vc×R1/R2 (5)
As it is highly preferred that described current source 3 also includes the 3rd PMOS Mp3, the 3rd resistance R3 and the 4th resistance R4；
The drain electrode of described second PMOS Mp2 is connected with the current output terminal of described current source 3, particularly as follows:
The drain electrode of described second PMOS Mp2 is connected with the source electrode of described 3rd PMOS Mp3；Described 3rd PMOS
The drain electrode of Mp3 is connected with the current output terminal of described current source 3；The grid of described 3rd PMOS Mp3 is by described 3rd electricity
Resistance R3 is connected with described supply voltage Vdd；The grid of described 3rd PMOS Mp3 passes through described 4th resistance R4 ground connection.
Owing to there is short channel mudulation effect, without the 3rd PMOS PMp3, the negative-phase input of the first amplifier A1
Voltage pulsation can directly affect the source-drain voltage of the second PMOS Mp2 thus affect Ib, the deviation of Ib can cause digital-to-analogue conversion
Device output voltage mistake；When there is the 3rd PMOS Mp3 part, owing to the 3rd PMOS Mp3 is cascade connected mode, the
The source-drain voltage of two PMOS Mp2 is mainly determined by Mp3 and R3, R4, so Mp3 can isolate the negative-phase input of the first amplifier A1
The voltage pulsation impact on Mp2 so that output electric current Ib is more stable.
As it is highly preferred that described control voltage Vc is equal to described bias voltage Vp.For example, it is possible to by the first amplifier A1
The normal phase input end of normal phase input end and the second amplifier A2 is simultaneously connected to same voltage source.When described bias voltage Vp is equal to institute
When stating the first DC voltage, formula (5) can deform and obtain
Vout=Iu × (2N-1×bN-1+2N-2×bN-2+...+2×b1+b0)×R1+Vp(1-R1/R2) (6)
Now by the ratio i.e. minima of scalable Vout of regulation R1 and R2, and when R1 is equal to R2, Vout's
Minima is equal to 0, reaches the maximum amplitude of oscillation, it is achieved rail-to-rail purpose.By designing the first resistance R1's and the second resistance R2
Matching ratio determines the minima size of digital to analog converter output voltage so that the minima of output voltage is to supply voltage
Vdd, the change of flow-route and temperature seem more sane.
During it should be noted that use the current source 3 of present embodiment, described current steer module 2 should be input Io's
State.
As shown in Figure 4, the circuit diagram of the another embodiment of the current source 3 during it is the embodiment of the present invention.
In described another embodiment, described current source 3 include the second amplifier A2, the first PMOS Mp1, first
NMOS tube Mn1, the second NMOS tube Mn2 and the second resistance R2；
The normal phase input end of described second amplifier A2 is connected with controlling voltage Vc；The outfan of described second amplifier A2 and institute
The grid stating the first PMOS Mp1 connects；The negative-phase input of described second amplifier A2 and the source electrode of described first PMOS Mp1
Connect, and be connected with supply voltage Vdd by described second resistance R2；
The drain electrode of described first PMOS Mp1 is connected with the drain electrode of described first NMOS tube Mn1, and with a described NMOS
The grid of pipe Mn1, the grid of described second NMOS tube Mn2 connect；The source electrode of described first NMOS tube Mn1 and described 2nd NMOS
The source ground of pipe Mn2；The drain electrode of the second NMOS tube Mn2 is connected with the current output terminal of described current source 3.
As it is highly preferred that described current source 3 also includes the 3rd NMOS tube Mn3, the 3rd resistance R3 and the 4th resistance R4；
The drain electrode of described second NMOS tube Mn2 is connected with the current output terminal of described current source 3, particularly as follows:
The drain electrode of described second NMOS tube Mn2 is connected with the source electrode of described 3rd NMOS tube Mn3；Described 3rd NMOS tube
The drain electrode of Mn3 is connected with the current output terminal of described current source 3；The grid of described 3rd NMOS tube Mn3 is by described 3rd electricity
Resistance R3 is connected with described supply voltage Vdd；The grid of described 3rd NMOS tube Mn3 passes through described 3rd resistance R3 ground connection.
As it is highly preferred that described control voltage Vc is equal to described bias voltage Vp.
During it should be noted that use the current source 3 of present embodiment, described current steer module 2 should be output Io's
State.
It should be noted that the embodiment of the embodiment of the current source 3 shown in Fig. 4 and the current source 3 shown in Fig. 3
Different and the corresponding circuit of type differing only in used metal-oxide-semiconductor connects difference, principle that both implement and having
Benefit effect is essentially identical, thus repeats no more.
Compared to prior art, having the beneficial effects that of the embodiment of the present invention: the invention provides a kind of digital to analog converter,
Including decoder, current steer module, current source, the first amplifier, the first resistance；Described current steer module has several switch electricity
Stream unit, the outfan of each switching current cells is connected to the total current node of described current steer module；Described decoding utensil
There are several signal output parts connected one to one with several switching current cells described, for the Digital Logic by input
Signal is converted to control signal, controls corresponding switching current cells on or off；The normal phase input end of described first amplifier
It is connected with bias voltage；The voltage output end that outfan is digital to analog converter of described first amplifier, and by described first electricity
Resistance is connected to the negative-phase input of described first amplifier；The current output terminal of described current source and the negative of described first amplifier
Input is connected to described total current node.The present invention uses a kind of current source to produce a bias current Ib, this biasing
Electric current is injected into the negative input end of output amplifier, flows through the first resistance R1 and produces pressure drop Ib × R1, this pressure drop Ib × R1 with inclined
The difference putting voltage Vp is the minima of digital to analog converter output voltage.When they size couplings, the output of digital to analog converter
Voltage minimum can arrive power supply ground, such that it is able to realize rail-to-rail output voltage.The present invention can eliminate bias voltage to output
The impact of voltage swing, reduces the minima of output voltage so that the current steering digital-to-analog converter of Single-end output can be applied
In the product of low-voltage and low-power dissipation.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (13)
1. a digital to analog converter, it is characterised in that include decoder, current steer module, current source, the first amplifier, the first electricity
Resistance；
Described current steer module has several switching current cells, and the outfan of each switching current cells is connected to described electricity
The total current node of stream rudder module；
Described decoder has several signal output parts connected one to one with several switching current cells described, is used for
The digital logic signal of input is converted to control signal, controls corresponding switching current cells on or off；
The normal phase input end of described first amplifier is connected with bias voltage；The outfan of described first amplifier is digital to analog converter
Voltage output end, and the negative-phase input of described first amplifier it is connected to by described first resistance；The electric current of described current source
The negative-phase input of outfan and described first amplifier is connected to described total current node.
2. the digital to analog converter as belonging to claim 1, it is characterised in that described current source is voltage-controlled type current source.
3. digital to analog converter as claimed in claim 2, it is characterised in that described current source includes the second amplifier, a NMOS
Pipe, the first PMOS, the second PMOS and the second resistance；
The normal phase input end of described second amplifier is connected with controlling voltage；The outfan of described second amplifier and a described NMOS
The grid of pipe connects；The negative-phase input of described second amplifier is connected with the source electrode of described first NMOS tube, and by described the
Two resistance eutral groundings；
The drain electrode of described first NMOS tube is connected with the drain electrode of described first PMOS, and with the grid of described first PMOS,
The grid of described second PMOS connects；The source electrode of described first PMOS is connected to power supply with the source electrode of described second PMOS
Voltage；The drain electrode of the second PMOS is connected with the current output terminal of described current source.
4. digital to analog converter as claimed in claim 3, it is characterised in that described current source also include the 3rd PMOS, the 3rd
Resistance and the 4th resistance；
The drain electrode of described second PMOS is connected with the current output terminal of described current source, particularly as follows:
The drain electrode of described second PMOS is connected with the source electrode of described 3rd PMOS；The drain electrode of described 3rd PMOS is with described
The current output terminal of current source connects；The grid of described 3rd PMOS is by described 3rd resistance with described supply voltage even
Connect；The grid of described 3rd PMOS passes through described 4th resistance eutral grounding.
5. the digital to analog converter as described in claim 3 or 4, it is characterised in that described bias voltage is equal to described control voltage.
6. digital to analog converter as claimed in claim 1, it is characterised in that described current source includes the second amplifier, a PMOS
Pipe, the first NMOS tube, the second NMOS tube and the second resistance；
The normal phase input end of described second amplifier is connected with controlling voltage；The outfan of described second amplifier and a described PMOS
The grid of pipe connects；The negative-phase input of described second amplifier is connected with the source electrode of described first PMOS, and by described the
Two resistance are connected with supply voltage；
The drain electrode of described first PMOS is connected with the drain electrode of described first NMOS tube, and with the grid of described first NMOS tube,
The grid of described second NMOS tube connects；The source electrode of described first NMOS tube and the source ground of described second NMOS tube；Second
The drain electrode of NMOS tube is connected with the current output terminal of described current source.
7. digital to analog converter as claimed in claim 6, it is characterised in that described current source also include the 3rd NMOS tube, the 3rd
Resistance and the 4th resistance；
The drain electrode of described second NMOS tube is connected with the current output terminal of described current source, particularly as follows:
The drain electrode of described second NMOS tube is connected with the source electrode of described 3rd NMOS tube；The drain electrode of described 3rd NMOS tube is with described
The current output terminal of current source connects；The grid of described 3rd NMOS tube is by described 3rd resistance with described supply voltage even
Connect；The grid of described 3rd NMOS tube passes through described 4th resistance eutral grounding.
Digital to analog converter the most as claimed in claims 6 or 7, it is characterised in that described bias voltage is equal to described control voltage.
9. digital to analog converter as claimed in claim 1, described switching current cells includes electron current source and switch；Described son
Current source is connected to described total current node by described switch；It is corresponding that the control end of described switch is connected to described decoder
A signal output part.
10. digital to analog converter as claimed in claim 9, described switch is the first transistor；The first of described the first transistor
Connecting pole to be connected with described total current node, the second connection pole of described the first transistor is with the outfan in described electron current source even
Connect；The signal output part controlling pole corresponding with described decoder of described the first transistor connects.
11. digital to analog converters as claimed in claim 10, described switching current cells also includes current-limiting resistance and the second crystalline substance
Body pipe；First connection pole of described transistor seconds by current-limiting resistance ground connection or connects supply voltage；Described transistor seconds
Second connects pole is connected with the outfan in described electron current source；Control pole and the described the first transistor of described transistor seconds
The inversion signal controlling pole connects.
12. digital to analog converters as described in claim 1 or 9, it is characterised in that described digital logic signal is N position, described electricity
Stream rudder module includes 2N-1 described switching current cells, and the conducting electric current of each described switching current cells is Iu；
Then flow through electric current Io=Iu × (2 of described total current nodeN-1×bN-1+2N-2×bN-2+...+2×b1+b0) wherein,
bN-1,bN-2...b1,b0N number of occurrence for described digital logic signal.
13. digital to analog converters as claimed in claim 1, described digital to analog converter also includes input register；Described input is posted
Storage is connected with the input of described decoder, for latching the digital logic signal to be input to described decoder.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104673A (en) * | 2017-04-01 | 2017-08-29 | 唯捷创芯(天津)电子技术股份有限公司 | A kind of low gain error current rudder-type digital-to-analog converter, chip and communication terminal |
| CN108418586A (en) * | 2017-02-10 | 2018-08-17 | 中芯国际集成电路制造(上海)有限公司 | The current steer D/A converting circuit of Single-end output |
| WO2018188501A1 (en) * | 2017-04-12 | 2018-10-18 | 华为技术有限公司 | Digital-to-analog converter |
| CN109309498A (en) * | 2018-11-08 | 2019-02-05 | 东南大学 | A kind of current steering digital-to-analog converter based on thermometer-code |
| CN112039526A (en) * | 2020-08-19 | 2020-12-04 | 北京无线电测量研究所 | Numerical control switch driving circuit applied to digital-to-analog converter |
| CN112787671A (en) * | 2019-10-23 | 2021-05-11 | 华润微集成电路(无锡)有限公司 | Current steering DAC circuit |
| CN114337664A (en) * | 2022-03-09 | 2022-04-12 | 华南理工大学 | Current steering digital-to-analog converter capable of calibrating multiple gears |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400220B1 (en) * | 2000-11-20 | 2002-06-04 | Macronix International Co., Ltd. | Autotracking feedback circuit and high speed A/D converter using same |
| CN101237238A (en) * | 2007-12-29 | 2008-08-06 | 湖南大学 | CMOS current helm DA converter based on switch current technology |
| CN103929181A (en) * | 2013-01-16 | 2014-07-16 | 飞思卡尔半导体公司 | Digital To Analog Converter With Current Steering Source For Reduced Glitch Energy Error |
| CN104811181A (en) * | 2015-04-29 | 2015-07-29 | 南京磐能电力科技股份有限公司 | Current-to-voltage conversion circuit with input bias and active power filtering effects and current-to-voltage conversion method |
-
2016
- 2016-06-30 CN CN201610512520.XA patent/CN106209098B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400220B1 (en) * | 2000-11-20 | 2002-06-04 | Macronix International Co., Ltd. | Autotracking feedback circuit and high speed A/D converter using same |
| CN101237238A (en) * | 2007-12-29 | 2008-08-06 | 湖南大学 | CMOS current helm DA converter based on switch current technology |
| CN103929181A (en) * | 2013-01-16 | 2014-07-16 | 飞思卡尔半导体公司 | Digital To Analog Converter With Current Steering Source For Reduced Glitch Energy Error |
| CN104811181A (en) * | 2015-04-29 | 2015-07-29 | 南京磐能电力科技股份有限公司 | Current-to-voltage conversion circuit with input bias and active power filtering effects and current-to-voltage conversion method |
Non-Patent Citations (1)
| Title |
|---|
| 张正旭 等: "多路V/ I 输出的高性能CMOS带隙基准源", 《微电子学》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108418586A (en) * | 2017-02-10 | 2018-08-17 | 中芯国际集成电路制造(上海)有限公司 | The current steer D/A converting circuit of Single-end output |
| CN108418586B (en) * | 2017-02-10 | 2021-09-14 | 中芯国际集成电路制造(上海)有限公司 | Single-ended output current steering digital-to-analog conversion circuit |
| CN107104673A (en) * | 2017-04-01 | 2017-08-29 | 唯捷创芯(天津)电子技术股份有限公司 | A kind of low gain error current rudder-type digital-to-analog converter, chip and communication terminal |
| WO2018188501A1 (en) * | 2017-04-12 | 2018-10-18 | 华为技术有限公司 | Digital-to-analog converter |
| US10998912B2 (en) | 2017-04-12 | 2021-05-04 | Huawei Technologies Co., Ltd. | Digital-to-analog converter to reduce noise generated by a quiescent current |
| CN109309498A (en) * | 2018-11-08 | 2019-02-05 | 东南大学 | A kind of current steering digital-to-analog converter based on thermometer-code |
| CN109309498B (en) * | 2018-11-08 | 2022-05-20 | 东南大学 | Current steering type digital-to-analog converter based on thermometer code |
| CN112787671A (en) * | 2019-10-23 | 2021-05-11 | 华润微集成电路(无锡)有限公司 | Current steering DAC circuit |
| CN112787671B (en) * | 2019-10-23 | 2024-02-06 | 华润微集成电路(无锡)有限公司 | Current steering DAC circuit |
| CN112039526A (en) * | 2020-08-19 | 2020-12-04 | 北京无线电测量研究所 | Numerical control switch driving circuit applied to digital-to-analog converter |
| CN112039526B (en) * | 2020-08-19 | 2022-07-12 | 北京无线电测量研究所 | Numerical control switch driving circuit applied to digital-to-analog converter |
| CN114337664A (en) * | 2022-03-09 | 2022-04-12 | 华南理工大学 | Current steering digital-to-analog converter capable of calibrating multiple gears |
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