CN104393845B - A kind of current-mode variable gain amplifier - Google Patents

A kind of current-mode variable gain amplifier Download PDF

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Publication number
CN104393845B
CN104393845B CN201410560866.8A CN201410560866A CN104393845B CN 104393845 B CN104393845 B CN 104393845B CN 201410560866 A CN201410560866 A CN 201410560866A CN 104393845 B CN104393845 B CN 104393845B
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pmos
drain electrode
nmos tube
current
grid
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CN104393845A (en
Inventor
徐建
周正
吴毅强
韩婷婷
马力
田密
王志功
陈建平
吉荣新
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Nanjing Taitong S & T Co Ltd
Southeast University
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Nanjing Taitong S & T Co Ltd
Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection

Abstract

The invention discloses a kind of new gain-changeable amplifier circuit under current-mode, including variable gain circuit, function digit control logic circuit and DC maladjustment calibration circuit；Variable gain circuit includes level Four electric current fully differential programmable amplifier；Function digit control logic circuit is used for after control signal is decoded into binary signal, controls variable-gain-circuit gain decibels；DC maladjustment calibration circuit feeds back to the output low frequency signal of the variable gain circuit input of variable gain circuit, forms feedback loop.In the design current-mode amplifying circuit, signal input is low-resistance, is exported as high resistant, the signal of circulation is current signal, is not influenceed by voltage swing.Current-mode variable gain amplifier uses Class AB export structure, greatly reduces the power consumption of circuit.Current amplifier is not limited by gain bandwidth product, therefore can almost be accomplished in any gain, and bandwidth is unrestricted.

Description

A kind of current-mode variable gain amplifier
Technical field
The present invention relates to a kind of gain amplifier, more particularly to a kind of current-mode variable gain amplifier.
Background technology
With the lifting of technique, metal-oxide-semiconductor bears that voltage is more and more lower, causes the reduction of supply voltage.Such as current trend 40nm low pressure tube voltages there was only 1.0V or so, and cut-in voltage Vt just has 0.4V or so.So for the amplification of two layers of pipe For circuit, only 0.2V dynamic range.From voltage signal angle, this brings huge challenge to the design of circuit.
Traditional voltage signal variable gain amplifier, realized using amplifier feedback.All it is limited to the increasing of amplifier Beneficial bandwidth product.When low gain, bandwidth ratio is wider, and when high-gain, bandwidth just narrows, and is unfavorable for the application of broadband occasion.
The content of the invention
Goal of the invention：For above-mentioned prior art, propose that a kind of variable gain that can apply to electric current input and output is put Big circuit, solves low-voltage, under the conditions of low-power consumption, bandwidth narrows when high-gain, and the amplification for being unfavorable for broadband applications is asked Topic.
Technical scheme：A kind of current-mode variable gain amplifier, including variable gain circuit, function digit control logic electricity Road and DC maladjustment calibration circuit；The variable gain circuit includes level Four electric current fully differential programmable amplifier, the first order Input of the input of electric current fully differential programmable amplifier as current-mode variable gain amplifier, fourth stage electric current are entirely poor Divide output end of the output end of programmable amplifier as current-mode variable gain amplifier；The function digit control logic electricity Road is used for the gain decibels for controlling the variable gain circuit；The DC maladjustment calibration circuit is complete by the fourth stage electric current The low frequency signal of difference programmable amplifier output feeds back to the input of first order electric current fully differential programmable amplifier, forms Feedback loop.
It is poor by two symmetrical single ended inputs as the improvement of the present invention, the single-stage electric current fully differential programmable amplifier The current follower Opposite direction connection of output is divided to form；Each current follower includes M1 to M19 metal-oxide-semiconductor, bias current sources IBIASAnd first to the 6th CDN units；Wherein, M1 to M19 is single metal-oxide-semiconductor；PMOS M1, PMOS M2, PMOS M9, PMOS M11, PMOS M13, PMOS M15, PMOS M17 and PMOS M19 source grounding, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M16, NMOS tube M18 source electrode and PMOS M8 drain electrode is all connected with outside high level VDD；PMOS M1 grid connects its drain electrode, bias current sources IBIASConnection Between PMOS M1 drain electrode and NMOS tube M5 drain electrode.NMOS tube M6 drain electrode connection PMOS M3 drain electrode, PMOS Pipe M3 source electrode connection DC level VCM；NMOS tube M7 drain electrode connection PMOS M4 drain electrode, PMOS M4 source electrode connection PMOS M2 drain electrode；PMOS M3 and PMOS M4 grid are connected and connect to NMOS tube M6 drain electrode；NMOS tube M5, NMOS tube M6, NMOS tube M7 grid are all connected to NMOS tube M5 drain electrode；PMOS M8 source electrode connection PMOS M9 leakage Pole, PMOS M9 grid connection external bias voltage source VBIAS；The first of NMOS tube M10 drain electrode the first CDN units of connection End, the input at the second end of the first CDN units connect the first end of the 2nd CDN units, the second end connection of the 2nd CDN units PMOS M11 drain electrode；The first end of NMOS tube M12 drain electrode the 3rd CDN units of connection, the second end of the 3rd CDN units Input connects the first end of the 4th CDN units, the second end connection PMOS M13 of the 4th CDN units drain electrode；NMOS tube M14 drain electrode connection PMOS M17 drain electrode, NMOS tube M16 drain electrode connection PMOS M15 drain electrode, NMOS tube M18 leakage Pole connects the first end of the 5th CDN units, and the second end of the 5th CDN units connects the first end of the 6th CDN units, the 6th CDN The second end connection PMOS M19 of unit drain electrode；PMOS M8, NMOS tube M10, NMOS tube M12, NMOS tube M14 grid Be all connected with NMOS tube M7 drain electrode, metal-oxide-semiconductor M16 and NMOS tube M18 grid is all connected with metal-oxide-semiconductor M16 drain electrode, PMOS M1 and PMOS M2 grid is all connected with PMOS M1 drain electrode, and PMOS M11, PMOS M13, PMOS M15 grid are all connected with PMOS M9 drain electrode, PMOS M17 and PMOS M19 grid are all connected with PMOS M17 drain electrode, PMOS M4 source electrode Connect the second end of the first CDN units and as the input of current follower, the company of the 3rd CDN units and the 4th CDN units The tie point of in-phase output end of the contact as current follower, the 5th CDN units and the 6th CDN units is as current follower Reversed-phase output.
As the improvement of the present invention, the DC maladjustment calibration circuit forms single order low pass feedback net with variable gain circuit Network；The DC maladjustment calibration circuit includes a fully differential electric current pecker, two active pull-ups and resistance R2；It is described complete The differential input end of difference current pecker is connected respectively connects the output end of the variable gain circuit after an active pull-up； The resistance R2 connections fully differential electric current pecker, fully differential linear transconductance is formed, is adjusted by regulation resistance R2 size DC maladjustment calibrates electronic feedbackIt is described The transmission function of feedback network is：
Wherein, ωpFor variable gain amplifier pole frequency；β0For β (s) 0 frequency value.
As the improvement of the present invention, the fully differential electric current pecker includes M1 to M26 26 metal-oxide-semiconductors and electricity Hinder R3 and resistance R4；NMOS tube M13, NMOS tube M11, NMOS tube M9, NMOS tube M7, NMOS tube M8, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M25, NMOS tube M26 source electrode are all connected with outside high level VDD, PMOS M15, PMOS M16, PMOS M17, PMOS M18, PMOS M19, PMOS M20, PMOS M21, PMOS M22 source grounding, PMOS M15-M22 grid is all connected with external bias voltage source VBIAS；NMOS tube M13 drain electrode connection PMOS M15 leakage Pole, current signal reversed-phase output Z of its tie point as fully differential electric current peckerN；NMOS tube M11 drain electrode connection PMOS Pipe M16 drain electrode, NMOS tube M9 drain electrode connection PMOS M3 drain electrode, PMOS M3 grid connection PMOS M16 leakage Pole and the inverting input X of current signal as fully differential electric current peckerN, NMOS tube M7 drain electrode connects PMOS simultaneously M4 and M1 drain electrode, PMOS M4 grid connection DC level VCM, PMOS M3 and PMOS M4 source electrode is all connected with PMOS Pipe M17 drain electrode, NMOS tube M13 and NMOS tube M11 grid are all connected with PMOS M4 drain electrode；NMOS tube M8 drain electrode is simultaneously Connect PMOS M2 and M5 drain electrode, the voltage signal inverting input of PMOS M1 grid as fully differential electric current pecker YIN, the voltage signal in-phase input end Y of PMOS M2 grid as fully differential electric current peckerIP, PMOS M1 and M2 source Pole is all connected with PMOS M18 drain electrode, PMOS M5 grid connection DC level VCM；NMOS tube M10 drain electrode connection PMOS Pipe M6 drain electrode, PMOS M5 and M6 source electrode are all connected with the grid phase of PMOS M19 drain electrode, NMOS tube M7 and NMOS tube M8 Connection, NMOS tube M9 drain and gate and NMOS tube M10 drain and gate are connected, and NMOS tube M12 drain electrode connects PMOS M20 drain electrode is connect, PMOS M6 grid connects NMOS tube M12 drain electrode and as the electricity of fully differential electric current pecker Flow the normal phase input end X of signalP；NMOS tube M14 drain electrode connection PMOS M21 drain electrode is simultaneously used as fully differential electric current pecker Current signal positive output end ZP, NMOS tube M12 and M14 grid is all connected with NMOS tube M8 drain electrode；NMOS tube M25 leakage Pole connects its grid and connects PMOS M23 drain electrode, and NMOS tube M26 drain electrode connects its grid and connects PMOS M24's Drain electrode, PMOS M23 grid connect resistance R3 and resistance R4 one end simultaneously, and the resistance R3 other end is as fully differential electric current The normal phase input end X of the current signal of peckerP, the resistance R4 other end is as the current signal of fully differential electric current pecker Inverting input XN, PMOS M24 and M23 source electrode is all connected with PMOS M22 drain electrode, and PMOS M24 grid connection is straight Flow level VCM。
As the improvement of the present invention, the active pull-up includes four metal-oxide-semiconductors；The source electrode of first metal-oxide-semiconductor connects respectively The drain electrode of two metal-oxide-semiconductors and the drain electrode of the 3rd metal-oxide-semiconductor, the drain electrode of the first metal-oxide-semiconductor connect the grid and of the first metal-oxide-semiconductor respectively The source electrode of two metal-oxide-semiconductors, the grid of the second metal-oxide-semiconductor connect the drain electrode of the second metal-oxide-semiconductor, and the drain electrode of the 3rd metal-oxide-semiconductor connects the 3rd respectively The source electrode of the grid of metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor connect the drain electrode and the 4th of the 4th metal-oxide-semiconductor respectively The grid of metal-oxide-semiconductor.
Beneficial effect：In the current-mode amplifying circuit of the present invention, signal input is low-resistance, is exported as high resistant, circulation Signal is current signal, is not influenceed by voltage swing.Current-mode variable gain amplifier uses Class-AB export structure, Greatly reduce the power consumption of circuit.Current amplifier is not limited by gain bandwidth product, therefore can almost be accomplished in any increasing In benefit, bandwidth is unrestricted.Current-mode variable gain amplifier proposed by the present invention, substantially reduces supply voltage to circuit Influence, substantially increase the input and output dynamic range of circuit, while this circuit only needs few electric current.
Brief description of the drawings
Fig. 1 is current-mode variable gain amplifier structured flowchart；
Fig. 2 is single-stage fully differential current-mode variable gain amplifier FBDPCA block diagrams；
Fig. 3 is the circuit diagram of current follower；
Fig. 4 is function digit control logic circuit schematic diagram；
Fig. 5 is the circuit diagram for the fully differential electric current pecker for being applied to DC maladjustment calibration circuit；
Fig. 6 is the active pull-up structure for being applied to DC maladjustment calibration circuit.
Embodiment
Further explanation is done to the present invention below in conjunction with the accompanying drawings.
As shown in figure 1, a kind of current-mode variable gain amplifier, including variable gain circuit, function digit control logic Circuit and DC maladjustment calibration circuit.Because single-stage current amplifier is difficult to accomplish very high gain, and output linearity degree It can change with change in gain.High-gain is realized with one-stage amplifier, stability necessarily declines, and the linearity can also be limited System is formed, it is necessary to be cascaded using casacade multi-amplifier.Series is more, and the operating current of whole circuit will increase, and increase circuit Power consumption.Weigh stability, the linearity and the aspect of power consumption three, variable gain circuit and use level Four electric current fully differential programmable amplifier (FBDPCA, Full Balanced Digital Programmable Current Amplifier) is formed；Per one step gain For Ai, then system overall current gain is A=A1A2A3A4.It is adjustable that first and second grade of current gain is designed as 0/6/12/18dB, and Tertiary current gain design is that 0/6/12dB is adjustable, and it is adjustable that fourth stage current gain is designed as 5/6/7/8/9/10dB；Whole electricity It is adjustable for 5-58dB to flow the current gain of variable gain amplifier, step-length 1dB.
Amplifier is because gain is larger, up to 58dB, about 794 times.The mismatch of input very little will cause rear class Operating point is acutely offset, therefore current-mode variable gain amplifier needs DC maladjustment to calibrate (DCOC, DC offset Canceller) circuit.The general principle of DCOC circuits be variable gain circuit output end take out low frequency signal, Ran Houjing Loop feeds back to signal the input of variable gain circuit, forms a complete feedback loop, realizes that DC maladjustment disappears The function of removing.Function digit control logic (digital control word generator) circuit mainly realizes decoder Function, after control signal is decoded into 5-58 binary signal, control variable-gain-circuit gain decibels.
As shown in Fig. 2 single-stage electric current fully differential programmable amplifier (FBDPCA) is by two symmetrical single ended input difference The current follower phase inverter (DPCA) of output connects and composes, and is mainly realized by two one-terminal current signal subtractions；Single ended input The current follower of difference output uses Class-AB export structures.The positive output end of single-stage electric current fully differential programmable amplifier Signal IOUTPWith negative output terminal signal IOUTNSize is respectively：
IOUTP=α (IINP-IINN)
IOUTN=α (IINN-IINP)
Wherein, α is gain factor, IINPFor single-stage electric current fully differential programmable amplifier positive input current signal, IINNFor Single-stage electric current fully differential programmable amplifier negative input current signal.
As shown in figure 3, electricity of the single-stage electric current fully differential programmable amplifier by two symmetrical single ended input difference outputs Follower Opposite direction connection is flowed to form；Each current follower includes M1 to M19 metal-oxide-semiconductor, bias current sources IBIASAnd first To the 6th CDN units；Wherein, M1 to M19 is single metal-oxide-semiconductor.PMOS M1, PMOS M2, PMOS M9, PMOS M11, PMOS M13, PMOS M15, PMOS M17 and PMOS M19 source grounding, NMOS tube M5, NMOS tube M6, NMOS Pipe M7, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M16, NMOS tube M18 source electrode and PMOS M8 leakage Pole is all connected with outside high level VDD；PMOS M1 grid connects its drain electrode, bias current sources IBIASIt is connected to PMOS M1's Between drain electrode and NMOS tube M5 drain electrode.NMOS tube M6 drain electrode connection PMOS M3 drain electrode, PMOS M3 source electrode connect Meet DC level VCM；NMOS tube M7 drain electrode connection PMOS M4 drain electrode, PMOS M4 source electrode connection PMOS M2 leakage Pole；PMOS M3 and PMOS M4 grid are connected and connect to NMOS tube M6 drain electrode；NMOS tube M5, NMOS tube M6, NMOS Pipe M7 grid is all connected to NMOS tube M5 drain electrode；PMOS M8 source electrode connection PMOS M9 drain electrode, PMOS M9's Grid connection external bias voltage source VBIAS；NMOS tube M10 drain electrode the first CDN units of connection, the second of the first CDN units The input at end connects the first end of the 2nd CDN units, the second end connection PMOS M11 of the 2nd CDN units drain electrode；NMOS The first end of pipe M12 drain electrode the 3rd CDN units of connection, the input at the second end of the 3rd CDN units connect the 4th CDN units First end, the second end connection PMOS M13 of the 4th CDN units drain electrode；NMOS tube M14 drain electrode connection PMOS M17 Drain electrode, NMOS tube M16 drain electrode connection PMOS M15 drain electrode, the of NMOS tube M18 drain electrode the 5th CDN units of connection One end, the second end of the 5th CDN units connect the first end of the 6th CDN units, the second end connection PMOS of the 6th CDN units M19 drain electrode；PMOS M8, NMOS tube M10, NMOS tube M12, NMOS tube M14 grid are all connected with NMOS tube M7 drain electrode, Metal-oxide-semiconductor M16 and NMOS tube M18 grid are all connected with metal-oxide-semiconductor M16 drain electrode, and PMOS M1 and PMOS M2 grid are all connected with PMOS M1 drain electrode, PMOS M11, PMOS M13, PMOS M15 grid are all connected with PMOS M9 drain electrode, PMOS M17 and PMOS M19 grid are all connected with PMOS M17 drain electrode, and PMOS M4 source electrode connects the second of the first CDN units Hold and be used as the input of current follower, the tie point of the 3rd CDN units and the 4th CDN units is as the same of current follower Reversed-phase output of the tie point of phase output terminal, the 5th CDN units and the 6th CDN units as current follower.Wherein, it is related to Metal-oxide-semiconductor M11, M13, M19, M10, M12, M18 annexation be several NMOS or PMOS in every group connection close System.
Wherein, the first N tube current mirrors are formed by metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2, second be made up of metal-oxide-semiconductor M3 and metal-oxide-semiconductor M4 N tube current mirrors, the first P tube current mirrors being made up of metal-oxide-semiconductor M5, metal-oxide-semiconductor M6 and metal-oxide-semiconductor M7, by metal-oxide-semiconductor M16 and metal-oxide-semiconductor M18 2nd P tube current mirrors of composition, the 3rd P tube current mirrors being made up of metal-oxide-semiconductor M17 and metal-oxide-semiconductor M19, include the eight of M8 to M15 Individual metal-oxide-semiconductor, bias voltage source and first form two-stage grid-common-source amplifier altogether to the 6th CDN units by metal-oxide-semiconductor M4-M10. In the current follower phase inverter (DPCA) of single ended input difference output, metal-oxide-semiconductor M6 and metal-oxide-semiconductor M7 electric current are all from metal-oxide-semiconductor M5 mirror images, while metal-oxide-semiconductor M4 and metal-oxide-semiconductor M3 are also a pair of current mirrors.Because metal-oxide-semiconductor M3 source electrodes are directly connected to direct current It is flat, equivalent to AC deposition.Therefore, the input of metal-oxide-semiconductor M4 source class, i.e. current signal is designed as low impedance points, is advantageous to electricity Flow the input of signal.Input signal is total to the amplification of grid-common-source amplifier by metal-oxide-semiconductor M4-MOS pipe M10 two-stages, and feeds back to Input, input X can be calculatedINImpedance RIN.Wherein M10, M11, M12, M13, M18, M19 are one group of a variety of chi Very little pipe, metal-oxide-semiconductor M12, metal-oxide-semiconductor M13 output current follow metal-oxide-semiconductor M10, metal-oxide-semiconductor M11, by control metal-oxide-semiconductor M12, Metal-oxide-semiconductor M13 and metal-oxide-semiconductor M10, metal-oxide-semiconductor M11 size ratio, it is possible to obtain in-phase output end ZPWith input XINIn-phase current Than；M18, M19 pipe sizing same M12, M13, because the sense of current is anti-phase by M14, M15, M16, M17, it can obtain anti-phase Output end ZNWith input XINNegative-phase sequence curent ratio.Therefore, realize that input is single-ended, the single-stage current-variable gain amplification of output difference Device.Output stage Rout is metal-oxide-semiconductor M12, the parallel connection of metal-oxide-semiconductor M13 output resistance, is high resistant.According to front stage impedance magnitude, if Count out the current amplifier for meeting input and output impedance.
Wherein, by taking a PMOS branch road as an example, current distribution network CDN units can be realized by Fig. 4, and CDN units include n PMOS, the drain electrode of n PMOS are connected and as the second end (i.e. as electric current output point) of CDN units, n PMOS First end of the source electrode as CDN units, the source electrode of each PMOS correspondingly connects the drain electrode of a metal-oxide-semiconductor in M10 groups, n The grid of individual PMOS is independent and by control word controlling switch.α1To αnFor control signal, the source current of each PMOS is controlled I1To InBreak-make.α1For high level when, switching tube disconnects, and this road electric current is obstructed；α1For low level when, switching tube close, This road electric current flows through, it is achieved thereby that electric current is programmable.Wherein, n numerical value is consistent with the number of PMOS in M10 groups. The same PMOS of NMOS branch structures, only need to be used as switch by the use of N pipes.
In Fig. 1, DC maladjustment calibration circuit forms single order low pass feedback network, the DC maladjustment school with variable gain circuit Quasi- circuit includes a fully differential electric current pecker (FBCCII), two active pull-ups and resistance R2.Fully differential electric current continues The differential input end of device is connected respectively connects the output end of variable gain circuit after an active pull-up.The transmission letter of feedback network Number is：
Wherein, β0It is β (s) in the value of 0 frequency, ωpFor variable gain amplifier pole frequency.In view of DCOC feedback nets Network, the gain of whole system are：
Due to DCOC pole frequency ωpVery low, at 0 frequency (near DC), the gain of whole system is approximately：
As long as β0Much larger than 1, it is possible to realize that DC error eliminates.When intermediate-freuqncy signal by when, now signal Frequency is much larger than ωp, feedback network is just 0 with regard to β (s), does not influence the application of working frequency.
Because the input/output signal of variable gain circuit is current signal, in order to not reduce size of current, therefore variable The output end of gain circuitry takes voltage signal, the input of feedback current to variable gain circuit, therefore needs fully differential Linear transconductance.Fully differential linear transconductance is formed using fully differential FBCCII and resistance R2 in the present invention, and mutual conductance Gm sizes are：
Electronic feedback is calibrated to variable gain circuit input letter to adjust DC maladjustment by regulation resistance R2 size Number size, i.e., control DCOC depth of feedbacks and loop gain by changing R2 size.
Fully differential electric current pecker (FBCCII) is as shown in figure 5,26 metal-oxide-semiconductors and resistance including M1 to M26 R3 and resistance R4；NMOS tube M13, NMOS tube M11, NMOS tube M9, NMOS tube M7, NMOS tube M8, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M25, NMOS tube M26 source electrode are all connected with outside high level VDD, PMOS M15, PMOS M16, PMOS M17, PMOS M18, PMOS M19, PMOS M20, PMOS M21, PMOS M22 source grounding, PMOS M15-M22 grid is all connected with external bias voltage source VBIAS；NMOS tube M13 drain electrode connection PMOS M15 leakage Pole, current signal reversed-phase output Z of its tie point as fully differential electric current peckerN；NMOS tube M11 drain electrode connection PMOS Pipe M16 drain electrode, NMOS tube M9 drain electrode connection PMOS M3 drain electrode, PMOS M3 grid connection PMOS M16 leakage Pole and the inverting input X of current signal as fully differential electric current peckerN, NMOS tube M7 drain electrode connects PMOS simultaneously M4 and M1 drain electrode, PMOS M4 grid connection DC level VCM, PMOS M3 and PMOS M4 source electrode is all connected with PMOS Pipe M17 drain electrode, NMOS tube M13 and NMOS tube M11 grid are all connected with PMOS M4 drain electrode；NMOS tube M8 drain electrode is simultaneously Connect PMOS M2 and M5 drain electrode, the voltage signal inverting input of PMOS M1 grid as fully differential electric current pecker YIN, the voltage signal in-phase input end Y of PMOS M2 grid as fully differential electric current peckerIP, PMOS M1 and M2 source Pole is all connected with PMOS M18 drain electrode, PMOS M5 grid connection DC level VCM；NMOS tube M10 drain electrode connection PMOS Pipe M6 drain electrode, PMOS M5 and M6 source electrode are all connected with the grid phase of PMOS M19 drain electrode, NMOS tube M7 and NMOS tube M8 Connection, NMOS tube M9 drain and gate and NMOS tube M10 drain and gate are connected, and NMOS tube M12 drain electrode connects PMOS M20 drain electrode is connect, PMOS M6 grid connects NMOS tube M12 drain electrode and as the electricity of fully differential electric current pecker Flow the normal phase input end X of signalP；NMOS tube M14 drain electrode connection PMOS M21 drain electrode is simultaneously used as fully differential electric current pecker Current signal positive output end ZP, NMOS tube M12 and M14 grid is all connected with NMOS tube M8 drain electrode；NMOS tube M25 leakage Pole connects its grid and connects PMOS M23 drain electrode, and NMOS tube M26 drain electrode connects its grid and connects PMOS M24's Drain electrode, PMOS M23 grid connect resistance R3 and resistance R4 one end simultaneously, and the resistance R3 other end is as fully differential electric current The normal phase input end X of the current signal of peckerP, the resistance R4 other end is as the current signal of fully differential electric current pecker Inverting input XN, PMOS M24 and M23 source electrode is all connected with PMOS M22 drain electrode, and PMOS M24 grid connection is straight Flow level VCM。
Wherein, the first P tube current mirrors are formed by metal-oxide-semiconductor M15, M16, M17, M18, M19, M20, M21, M22；By metal-oxide-semiconductor M1, M2 form the first Differential Input to pipe；Second Differential Input is formed to pipe by metal-oxide-semiconductor M3, M4；Is formed by metal-oxide-semiconductor M5, M6 Three Differential Inputs are to pipe；Commom-mode feedback circuit is formed by metal-oxide-semiconductor M23, M24, M25, M26, R3, R4, M7, M8；Metal-oxide-semiconductor M9, M10 forms the active pull-up of diode connection.Wherein the input of voltage signal inputs and current signal is low-impedance node, Current signal output end is high-impedance node.Metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 inputs for differential signal, metal-oxide-semiconductor M11 and metal-oxide-semiconductor M12 For the output stage of two stage amplifer, X is realized by feedbackP、XNLow-impedance current input, output end ZPFor metal-oxide-semiconductor M14 and MOS The parallel connection of pipe M21 channel modulation resistance, is high impedance, ZNAnd similarly.Metal-oxide-semiconductor M23, M24, M25, M26 and R3, R4 are formed Commom-mode feedback circuit, stabilizing circuit dc point.
Active pull-up R1 in Fig. 1 in DCOC can use the active pull-up design shown in Fig. 6.The active pull-up includes four Metal-oxide-semiconductor；The source electrode of first metal-oxide-semiconductor connects the drain electrode of the second metal-oxide-semiconductor and the drain electrode of the 3rd metal-oxide-semiconductor, the leakage of the first metal-oxide-semiconductor respectively Pole connects the grid of the first metal-oxide-semiconductor and the source electrode of the second metal-oxide-semiconductor respectively, and the grid of the second metal-oxide-semiconductor connects the leakage of the second metal-oxide-semiconductor Pole, the drain electrode of the 3rd metal-oxide-semiconductor connect the grid of the 3rd metal-oxide-semiconductor and the source electrode of the 4th metal-oxide-semiconductor, the source electrode of the 3rd metal-oxide-semiconductor respectively The drain electrode of the 4th metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor are connected respectively.In use, 4 metal-oxide-semiconductor are in not turning on shape State, its D.C. resistance is very big, can typically realize G Ω or so, is easier to realize relatively low DCOC pole frequencies.
In the current-mode gain-changeable amplifier circuit of the present invention, signal input is low-resistance, is exported as high resistant, circulation Signal is current signal, is not influenceed by voltage swing.Single ended input differential output current mould variable gain amplification shown in Fig. 3 Device uses Class-AB export structure, greatly reduces the power consumption of circuit.Current amplifier is not limited by gain bandwidth product System, therefore can almost accomplish in any gain, bandwidth is unrestricted.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (4)

  1. A kind of 1. current-mode variable gain amplifier, it is characterised in that：Including variable gain circuit, function digit control logic electricity Road and DC maladjustment calibration circuit；The variable gain circuit includes level Four electric current fully differential programmable amplifier, the first order Input of the input of electric current fully differential programmable amplifier as current-mode variable gain amplifier, fourth stage electric current are entirely poor Divide output end of the output end of programmable amplifier as current-mode variable gain amplifier；The function digit control logic electricity Road is used for the gain decibels for controlling the variable gain circuit；The DC maladjustment calibration circuit is complete by the fourth stage electric current The low frequency signal of difference programmable amplifier output feeds back to the input of first order electric current fully differential programmable amplifier, forms Feedback loop；Any single-stage electric current fully differential programmable amplifier is by two in the level Four electric current fully differential programmable amplifier The current follower Opposite direction connection of individual symmetrical single ended input difference output is formed；Each current follower includes M1 to M19's Metal-oxide-semiconductor, bias current sources IBIASAnd first to the 6th CDN unit, CDN units are current distribution network；Wherein, M1 to M19 For single metal-oxide-semiconductor；PMOS M1, PMOS M2, PMOS M9, PMOS M11, PMOS M13, PMOS M15, PMOS M17 and PMOS M19 source grounding, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M16, NMOS tube M18 source electrode and PMOS M8 drain electrode are all connected with outside high level VDD；PMOS Pipe M1 grid connects its drain electrode, bias current sources IBIASBe connected to PMOS M1 drain electrode and NMOS tube M5 drain electrode it Between, NMOS tube M6 drain electrode connection PMOS M3 drain electrode, PMOS M3 source electrode connection DC level VCM；NMOS tube M7 leakage Pole connection PMOS M4 drain electrode, PMOS M4 source electrode connection PMOS M2 drain electrode；PMOS M3 and PMOS M4 grid Pole is connected and connect to NMOS tube M6 drain electrode；NMOS tube M5, NMOS tube M6, NMOS tube M7 grid are all connected to NMOS tube M5 Drain electrode；PMOS M8 source electrode connection PMOS M9 drain electrode, PMOS M9 grid connection external bias voltage source VBIAS； The first end of NMOS tube M10 drain electrode the first CDN units of connection, the input at the second end of the first CDN units connect the 2nd CDN The first end of unit, the second end connection PMOS M11 of the 2nd CDN units drain electrode；NMOS tube M12 drain electrode connection the 3rd The first end of CDN units, the input at the second end of the 3rd CDN units connect the first end of the 4th CDN units, and the 4th CDN is mono- The second end connection PMOS M13 of member drain electrode；NMOS tube M14 drain electrode connection PMOS M17 drain electrode, NMOS tube M16's Drain electrode connection PMOS M15 drain electrode, the first end of NMOS tube M18 drain electrode the 5th CDN units of connection, the 5th CDN units Second end connects the first end of the 6th CDN units, the second end connection PMOS M19 of the 6th CDN units drain electrode；PMOS M8, NMOS tube M10, NMOS tube M12, NMOS tube M14 grid are all connected with NMOS tube M7 drain electrode, metal-oxide-semiconductor M16 and NMOS tube M18 grid is all connected with metal-oxide-semiconductor M16 drain electrode, and PMOS M1 and PMOS M2 grid are all connected with PMOS M1 drain electrode, PMOS M11, PMOS M13, PMOS M15 grid are all connected with PMOS M9 drain electrode, PMOS M17 and PMOS M19 Grid be all connected with PMOS M17 drain electrode, PMOS M4 source electrode connect the second end of the first CDN units and as electric current with With the input of device, the in-phase output end of the tie point of the 3rd CDN units and the 4th CDN units as current follower, the 5th Reversed-phase output of the tie point of CDN units and the 6th CDN units as current follower.
  2. A kind of 2. current-mode variable gain amplifier according to claim 1, it is characterised in that：The DC maladjustment calibration Circuit forms single order low pass feedback network with variable gain circuit；The DC maladjustment calibration circuit includes a fully differential electric current Pecker, two active pull-ups and resistance R2；The differential input end of the fully differential electric current pecker is connected one respectively to be had The output end of the variable gain circuit is connected after the resistance of source；The resistance R2 connections fully differential electric current pecker, it is complete poor to form Heterogeneous linear mutual conductance, it is defeated to the variable gain circuit that DC maladjustment calibration electronic feedback is adjusted by regulation resistance R2 size Enter the size of end signal, the mutual conductance size isThe transmission function of the feedback network is：
    <mrow> <mi>&amp;beta;</mi> <mrow> <mo>(</mo> <mi>s</mi> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <msub> <mi>&amp;beta;</mi> <mn>0</mn> </msub> <mrow> <mn>1</mn> <mo>+</mo> <mi>s</mi> <mo>/</mo> <msub> <mi>&amp;omega;</mi> <mi>p</mi> </msub> </mrow> </mfrac> </mrow>
    Wherein, ωpFor variable gain amplifier pole frequency；β0For β (s) 0 frequency value.
  3. A kind of 3. current-mode variable gain amplifier according to claim 2, it is characterised in that：The fully differential electric current connects Continuous device includes M1 to M26 26 metal-oxide-semiconductors and resistance R3 and resistance R4；NMOS tube M13, NMOS tube M11, NMOS tube M9, NMOS tube M7, NMOS tube M8, NMOS tube M10, NMOS tube M12, NMOS tube M14, NMOS tube M25, NMOS tube M26 source electrode It is all connected with outside high level VDD, PMOS M15, PMOS M16, PMOS M17, PMOS M18, PMOS M19, PMOS M20, PMOS M21, PMOS M22 source grounding, PMOS M15-M22 grid are all connected with external bias voltage source VBIAS；NMOS tube M13 drain electrode connection PMOS M15 drain electrode, its tie point are believed as the electric current of fully differential electric current pecker Number reversed-phase output ZN；NMOS tube M11 drain electrode connection PMOS M16 drain electrode, NMOS tube M9 drain electrode connection PMOS M3 Drain electrode, PMOS M3 grid connection PMOS M16 drain electrode and as fully differential electric current pecker current signal it is anti- Phase input XN, the NMOS tube M7 drain electrode for draining while connecting PMOS M4 and M1, PMOS M4 grid connection direct current Flat VCM, PMOS M3 and PMOS M4 source electrode is all connected with the grid of PMOS M17 drain electrode, NMOS tube M13 and NMOS tube M11 It is all connected with PMOS M4 drain electrode；NMOS tube M8 drain electrode connects PMOS M2 and M5 drain electrode, PMOS M1 grid simultaneously Voltage signal inverting input Y as fully differential electric current peckerIN, PMOS M2 grid is as fully differential electric current pecker Voltage signal in-phase input end YIP, PMOS M1 and M2 source electrode is all connected with PMOS M18 drain electrode, PMOS M5 grid Connect DC level VCM；NMOS tube M10 drain electrode connection PMOS M6 drain electrode, PMOS M5 and M6 source electrode are all connected with PMOS Pipe M19 drain electrode, NMOS tube M7 are connected with NMOS tube M8 grid, NMOS tube M9 drain and gate and NMOS tube M10 Drain and gate be connected, NMOS tube M12 drain electrode connection PMOS M20 drain electrode, PMOS M6 grid connection NMOS tube M12 drain electrode and the normal phase input end X of current signal as fully differential electric current peckerP；NMOS tube M14 drain electrode Connect PMOS M21 drain electrode and as the current signal positive output end Z of fully differential electric current peckerP, NMOS tube M12 and M14 grid is all connected with NMOS tube M8 drain electrode；NMOS tube M25 drain electrode connects its grid and connects PMOS M23 drain electrode, NMOS tube M26 drain electrode connects its grid and connects PMOS M24 drain electrode, and PMOS M23 grid connects resistance R3 simultaneously With resistance R4 one end, the normal phase input end X of the resistance R3 other end as the current signal of fully differential electric current peckerP, electricity Hinder inverting input X of the R4 other end as the current signal of fully differential electric current peckerN, PMOS M24 and M23 source electrode It is all connected with PMOS M22 drain electrode, PMOS M24 grid connection DC level VCM。
  4. A kind of 4. current-mode variable gain amplifier according to claim 2, it is characterised in that：The active pull-up includes Four metal-oxide-semiconductors；The source electrode of first metal-oxide-semiconductor connects the drain electrode of the second metal-oxide-semiconductor and the drain electrode of the 3rd metal-oxide-semiconductor, the first metal-oxide-semiconductor respectively Drain electrode connect the grid of the first metal-oxide-semiconductor and the source electrode of the second metal-oxide-semiconductor respectively, the grid of the second metal-oxide-semiconductor connects the second metal-oxide-semiconductor Drain electrode, the 3rd metal-oxide-semiconductor drain electrode respectively connect the 3rd metal-oxide-semiconductor grid and the 4th metal-oxide-semiconductor source electrode, the 3rd metal-oxide-semiconductor Source electrode connects the drain electrode of the 4th metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor respectively.
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