CN108634949B - Direct current offset calibration circuit of chopper instrument amplifier - Google Patents

Direct current offset calibration circuit of chopper instrument amplifier Download PDF

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CN108634949B
CN108634949B CN201810466267.8A CN201810466267A CN108634949B CN 108634949 B CN108634949 B CN 108634949B CN 201810466267 A CN201810466267 A CN 201810466267A CN 108634949 B CN108634949 B CN 108634949B
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electrically connected
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offset calibration
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calibration circuit
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CN108634949A (en
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刘帘曦
华天源
张怡
沐俊超
朱樟明
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Xidian University
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    • A61B5/316—Modalities, i.e. specific diagnostic methods
    • A61B5/318—Heart-related electrical modalities, e.g. electrocardiography [ECG]
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    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
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    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/316—Modalities, i.e. specific diagnostic methods
    • A61B5/369—Electroencephalography [EEG]
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7225—Details of analog processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation

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Abstract

The invention relates to the field of microelectronics, and discloses a direct-current offset calibration circuit of a chopper instrument amplifier. The circuit includes: the device comprises a first chopping switch, a first input coupling capacitor, a second input coupling capacitor, a preamplifier, a second chopping switch, an output level detection circuit and an offset calibration circuit; the first chopping switch is electrically connected with the preamplifier through a first input coupling capacitor and a second input coupling capacitor respectively, and the preamplifier, the second chopping switch, the output level detection circuit and the offset calibration circuit are electrically connected in sequence; the positive feedback output end of the offset calibration circuit is electrically connected to a node between the first input coupling capacitor and the preamplifier, and the negative feedback output end of the offset calibration circuit is electrically connected to a node between the second input coupling capacitor and the preamplifier. The circuit can solve the problem of preamplifier output saturation caused by electrode offset in the chopper instrument amplifier, and has better robustness and faster offset calibration speed.

Description

Direct current offset calibration circuit of chopper instrument amplifier
Technical Field
The invention relates to the microelectronic technology, in particular to a direct current offset calibration circuit of a chopper instrument amplifier.
Background
In the existing biological signal acquisition technology, a chopper instrument amplifier is usually used as a preamplifier to detect low-frequency and small-amplitude biological signals so as to meet the requirements of low-noise indexes in signal acquisition. However, the chopper technique modulates the dc offset caused by human body movement or many uncertain factors to high frequency simultaneously, so that the output of the preamplifier is saturated, which causes signal distortion.
In order to solve the problem in the chopping technology, a feedback path with an integrator structure is arranged in a chopping instrument amplifier, low-pass filtering is performed on a signal at an output end, and a direct current signal obtained after filtering is fed back to an input end to counteract direct current offset. The chopper instrumentation amplifier provided with a feedback path is shown in fig. 1, wherein a feedback loop includes a transconductance operational amplifier OTA, a pseudo resistor, a feedback capacitor, a chopper switch, and an output coupling capacitor. However, the conventional solution has the following two problems: on one hand, in order to prevent low-frequency biological signals from being filtered out, a cut-off frequency (typically 0.1Hz) lower than 1Hz needs to be designed, which may cause that interference signals with a period less than 10s cannot be filtered out, and the excessively large time constant of the design may cause a problem that the calibration speed is slow when the system encounters sudden signal change; on the other hand, in order to produce a cut-off frequency close to 0.1Hz, designers have to use large off-chip capacitors to meet design requirements, or choose to use dummy resistors in order to achieve the goal of integration on-chip (large resistors and large capacitors are difficult to integrate). However, the PVT characteristics of the pseudo resistor are poor, and the leakage current model is inaccurate, so that the deviation of the actual circuit from the design is serious, and even the circuit fails.
Therefore, a new dc offset cancellation scheme is needed to solve the problems of the existing dc offset cancellation scheme of the chopper instrumentation amplifier.
Disclosure of Invention
The invention aims to provide a direct current offset calibration circuit of a chopping instrument amplifier, which can solve the problem of preamplifier output saturation caused by electrode offset in the chopping instrument amplifier.
The application provides chopper instrumentation amplifier's direct current offset calibration circuit includes: the device comprises a first chopping switch, a first input coupling capacitor, a second input coupling capacitor, a preamplifier, a second chopping switch, an output level detection circuit and an offset calibration circuit;
the positive phase output end of the first chopping switch is electrically connected with the positive phase input end of the preamplifier through a first input coupling capacitor, and the negative phase output end of the first chopping switch is electrically connected with the negative phase input end of the preamplifier through a second input coupling capacitor;
the inverting output end of the preamplifier is electrically connected with the positive phase input end of the second chopping switch, and the positive phase output end of the preamplifier is electrically connected with the inverting input end of the second chopping switch;
the positive phase output end of the second chopping switch is electrically connected with the positive phase feedback input end of the output level detection circuit, and the negative phase output end of the second chopping switch is electrically connected with the negative phase feedback input end of the output level detection circuit;
n-bit control signal output end Y of output level detection circuit1～YNN-bit control input terminal S of offset calibration circuit1～SNElectrically connected, wherein N is more than or equal to 2 and is an integer; the clock control output end of the output level detection circuit is electrically connected with the clock control input end of the offset calibration circuit;
the positive phase feedback output end of the offset calibration circuit is electrically connected to a node between the first input coupling capacitor and the positive phase input end of the preamplifier, and the negative phase feedback output end of the offset calibration circuit is electrically connected to a node between the second input coupling capacitor and the negative phase input end of the preamplifier.
In a preferred embodiment, the output level detection circuit outputs N-bit control signal output terminals Y1～YNN-bit control input terminal S of offset calibration circuit1～SNAn electrical connection, comprising:
each output terminal of the output level detection circuit is YnInput terminals S of the offset calibration circuitnAnd an output terminal YnAnd input terminal SnAnd electrically connecting, wherein N ∈ (1-N) is an integer.
In a preferred embodiment, the output level detection circuit includes: the comparator comprises a first comparator, a second comparator, a third comparator, a fourth comparator, an N-bit adder and a control logic circuit;
the positive phase input end of the third comparator and the negative phase input end of the fourth comparator are used as the negative phase input ends of the output level detection circuit;
the positive phase input end of the first comparator is connected with a first voltage, and the output end of the first comparator is electrically connected with the first input end of the control logic circuit;
the inverting input end of the second comparator is connected with a second voltage, and the output end of the second comparator is electrically connected with the second input end of the control logic circuit;
the inverting input end of the third comparator is connected with a second voltage, and the output end of the third comparator is electrically connected with the third input end of the control logic circuit;
the positive phase input end of the fourth comparator is connected with the first voltage, and the output end of the fourth comparator is electrically connected with the fourth input end of the control logic circuit;
the positive phase output end of the control logic circuit is electrically connected with the reset end of the N-bit adder, and the negative phase output end of the control logic circuit is electrically connected with the enable end of the N-bit adder. .
In a preferred embodiment, the positive phase output terminal of the control logic circuit sends a reset signal to the reset terminal of the N-bit adder, the negative phase output terminal of the control logic circuit sends an enable signal to the enable terminal of the N-bit adder, the clock control output terminal of the output level detection circuit sends a clock control signal of the third chopper switch to the clock control input terminal of the offset calibration circuit, and the N-bit control signal output terminal Y of the output level detection circuit sends a reset signal to the reset terminal of the N-bit adder, and the clock control output terminal of the control logic circuit sends a1～YNTo N bit control input S of offset calibration circuit1～SNAnd sending an N-bit trimming control signal.
In a preferred embodiment, the offset calibration circuit comprises: the N-bit trimming low-noise band-gap reference source, the third chopping switch, the first feedback output capacitor and the second feedback output capacitor are connected in series;
multiple input ends of the N-bit trimming low-noise band-gap reference source are used as N-bit control input ends S of the offset calibration circuit1～SNThe clock control input end of the third chopping switch is used as the clock control input end of the offset calibration circuit;
the fixed reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with the positive phase input end of the third chopping switch, and the variable reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with the negative phase input end of the third chopping switch;
a first clock input end and a second clock input end of the third chopping switch receive two-phase non-overlapped chopping clocks; the positive phase output end of the third chopping switch is electrically connected with the first end of the first feedback output capacitor, and the negative phase output end of the third chopping switch is electrically connected with the first end of the second feedback output capacitor;
the second end of the first feedback output capacitor is used as a positive phase feedback output end of the offset calibration circuit, and the second end of the second feedback output capacitor is used as a negative phase feedback output end of the offset calibration circuit.
In a preferred embodiment, the offset calibration circuit further includes: a first buffer and a second buffer;
the fixed reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with the positive phase input end of the first buffer, and the variable reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with the positive phase input end of the second buffer;
the output end of the first buffer is respectively and electrically connected with the inverting end of the first buffer and the positive phase input end of the third chopping switch, and the output end of the second buffer is respectively and electrically connected with the inverting end of the second buffer and the inverting input end of the third chopping switch.
In a preferred embodiment, the output level detection circuit is used for determining whether the preamplifier needs to be calibrated, and when the output level detection circuit detects that the calibration needs to be performed, the offset calibration circuit is controlled to generate a dc voltage to offset the input dc offset.
In a preferred example, the direct-current voltage is a positive-phase direct-current voltage or a negative-phase direct-current voltage;
and the direct current offset calibration circuit stops calibration work when the preamplifier is out of a saturation state along with the increase of the direct current voltage.
In a preferred embodiment, the N-bit trimming low noise bandgap reference source comprises: the circuit comprises first to Nth transistors, first to Nth resistors, a ground resistor and a current source;
the current source is electrically connected with the source end of the first transistor, the drain end of the nth transistor is electrically connected with the source end of the (N + 1) th transistor, the nth resistor is electrically connected between the source end and the drain end of the nth transistor, wherein N belongs to (1-N-1), and N is an integer;
the first end of the grounding resistor is electrically connected with the drain end of the Nth transistor, and the second end of the grounding resistor is grounded.
In a preferred embodiment, the gate terminals of the first to nth transistors are used as the N-bit control input terminal S of the offset calibration circuit1～SN。
The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Compared with the prior art, the embodiment of the invention has at least the following differences and effects:
the direct current offset calibration circuit of the chopping instrument amplifier has the advantages that a digital circuit control feedback loop is adopted, a pseudo resistor is not needed, and the problems that an actual circuit is deviated from a design and the circuit fails are solved.
Further, the variable direct current voltage in the digital circuit control feedback loop is generated by a low noise band gap reference source (BGR) with a multi-bit trimming function, so that the digital circuit control feedback loop has better robustness.
Furthermore, the direct current offset calibration circuit of the chopper instrument amplifier adopts a digital circuit control feedback loop, and an integrator structure with a large time constant in the prior art is avoided, so that the direct current offset calibration circuit of the chopper instrument amplifier has higher response speed, and can effectively realize the acquisition of biological signals (such as ECG acquisition and EEG acquisition).
It is understood that within the scope of the present invention, the above-described technical features of the present invention and the technical features specifically described below (e.g., embodiments and examples) may be combined with each other to constitute new or preferred technical solutions. Not to be reiterated herein, but to the extent of space.
Drawings
FIG. 1 is a circuit diagram of a prior art DC offset calibration circuit for a chopper instrumentation amplifier;
FIG. 2 is a circuit diagram of a DC offset calibration circuit of a chopper instrumentation amplifier according to an embodiment of the present disclosure;
FIG. 3 is a circuit diagram of an output level detection circuit according to an embodiment of the present application;
FIG. 4 is a waveform diagram of a control signal of a control logic circuit according to an embodiment of the present application;
FIG. 5 is a circuit diagram of an offset calibration circuit according to an embodiment of the present application;
fig. 6 is a trimming circuit diagram of an N-bit trimming low noise bandgap reference source according to an embodiment of the present disclosure.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
The terms to which this application relates are interpreted:
pseudo resistance: a small circuit, formed by two diode-connected PMOS connected back-to-back, can provide a very large impedance.
Robustness: the circuit performance is not easily influenced by the process, the temperature and the power supply voltage.
DCOC circuit: a Direct Current Offset Cancellation (DCOC) circuit.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the application relates to a direct current offset calibration circuit of a chopper instrument amplifier; FIG. 2 is a circuit diagram of a DC offset calibration circuit of a chopper instrumentation amplifier according to an embodiment of the present disclosure; as shown in fig. 2, the circuit includes: a first chopping switch CH1, a first input coupling capacitor CIN1A second input coupling capacitor CIN2The circuit comprises a preamplifier AMP, a second chopping switch CH2, an output level detection circuit and an offset calibration circuit.
The non-inverting output end OUT1+ of the first chopping switch CH1 passes through a first input coupling capacitor CIN1Electrically connected to the non-inverting input terminal of the preamplifier AMP, the inverting output terminal OUT 1-of the first chopper switch CH1 is connected through a second input coupling capacitor CIN2Is electrically connected with the inverting input end of the preamplifier AMP;
the inverting output terminal of the preamplifier AMP is electrically connected with the non-inverting input terminal IN2+ of the second chopping switch CH2, and the non-inverting output terminal of the preamplifier AMP is electrically connected with the inverting input terminal IN 2-of the second chopping switch CH 2;
the positive phase output end OUT2+ of the second chopping switch CH2 is electrically connected with the positive phase feedback input end FB1+ of the output level detection circuit, and the negative phase output end OUT 2-of the second chopping switch CH2 is electrically connected with the negative phase feedback input end FB 1-of the output level detection circuit;
n-bit control signal output end Y of output level detection circuit1～YNN-bit control input end S of sequential and offset calibration circuit1～SNElectrically connected, wherein N is more than or equal to 2 and is an integer; the clock control output end CTRL1 of the output level detection circuit is electrically connected with the clock control input end CTRL2 of the offset calibration circuit;
the non-inverting feedback output terminal FB2+ of the offset calibration circuit is electrically connected to the first input coupling capacitor CIN1And front-mountedThe node between the non-inverting input terminal of the amplifier AMP and the inverting feedback output terminal FB 2-of the offset calibration circuit are electrically connected to the second input coupling capacitor CIN2And the inverting input terminal of the preamplifier AMP.
In one embodiment, an output level detection circuit is shown in fig. 3, the circuit comprising: first comparator CMP1A second comparator CMP2A third comparator CMP3The fourth comparator CMP4An N-bit adder and a control logic circuit;
first comparator CMP1And the second comparator CMP2As the non-inverting input terminal FB1+ of the output level detection circuit, and a third comparator CMP3And the positive input terminal of the fourth comparator CMP4As the inverting input terminal FB 1-of the output level detection circuit;
first comparator CMP1The positive phase input end of the transformer is connected with a first voltage VHFirst comparator CMP1Is electrically connected to a first input terminal IN3A of the control logic circuit;
second comparator CMP2The inverting input end of the first voltage source is connected with a second voltage VLSecond comparator CMP2Is electrically connected with the input terminal IN3B of the control logic circuit;
third comparator CMP3The inverting input end of the first voltage source is connected with a second voltage VLThird comparator CMP3Is electrically connected to a third input terminal IN3D of the control logic circuit;
fourth comparator CMP4The positive phase input end of the transformer is connected with a first voltage VHFourth comparator CMP4Is electrically connected to a fourth input terminal IN3C of the control logic circuit;
the positive phase output end OUT3+ of the control logic circuit is electrically connected with the reset end RST of the N-bit adder, and the negative phase output end OUT 3-of the control logic circuit is electrically connected with the enable end EN of the N-bit adder;
preferably, the first voltage is an upper limit voltage VHThe second voltage is a lower limit voltage VL(ii) a Upper limit voltage VHThe lower limit voltage V is obtained by subtracting the set voltage margin from the upper limit of the output voltage of the preamplifierLThe low limit of the output voltage of the preamplifier is obtained by subtracting the set voltage margin; the output of the current amplifier is greater than the upper limit voltage VHOr less than the lower limit voltage VLThe preamplifier output is considered to be saturated.
The positive phase output end OUT3+ of the control logic circuit sends a reset signal to the reset end RST of the N-bit adder, the negative phase output end OUT 3-of the control logic circuit sends an enable signal to the enable end EN of the N-bit adder, the clock control output end CTRL1 of the output level detection circuit sends a clock control signal of the third chopping switch CH3 to the clock control input end CTRL2 of the offset calibration circuit, and the N-bit control signal output end Y of the output level detection circuit sends a reset signal to the reset end RST of the N-bit adder, and the clock control output end CTRL 351～YNTo N bit control input S of offset calibration circuit1～SNAnd sending an N-bit trimming control signal.
In one embodiment, an offset calibration circuit is shown in fig. 5, the circuit comprising: n-bit trimming low-noise band-gap reference source BGR and first buffer BUF1A second buffer BUF2A third chopping switch CH3, a first feedback output capacitor CFB1And a second feedback output capacitor CFB2；
The input end of an N-bit trimming low-noise band-gap reference source BGR is used as an N-bit control input end S of the offset calibration circuit1～SNThe clock control input end CTRL2 of the offset calibration circuit is electrically connected with the clock control input end of the third chopping switch CH 3;
fixed reference output end V of N-bit trimming low-noise band-gap reference source BGRREDSA variable reference output end V electrically connected with the non-inverting input end of the first buffer BUF1 and used for N-bit trimming of the low noise band gap reference source BGRREFDIs electrically connected with the non-inverting input terminal of the second buffer BUF 2;
the output terminal of the first buffer BUF1 is electrically connected to the inverting terminal of the first buffer BUF1 and the non-inverting input terminal IN4+ of the third chopping switch respectively,
the output end of the second buffer BUF2 is respectively and electrically connected with the inverting end of the second buffer BUF2 and the inverting input end IN 4-of the third chopping switch;
the first clock input terminal CLK and the second clock input terminal CLKB of the third chopping switch CH3 receive two-phase non-overlapping chopping clocks;
the non-inverting output end OUT4+ of the third chopping switch CH3 and the first feedback output capacitor CFB1Is electrically connected to the inverting output terminal OUT 4-of the third chopping switch (CH3) and the second feedback output capacitor CFB2Is electrically connected with the first end of the first terminal;
first feedback output capacitor CFB1The second terminal of the first feedback capacitor is used as a positive feedback output terminal FB2+ of the offset calibration circuit, and the second feedback output capacitor CFB2As the inverting feedback output FB 2-of the offset calibration circuit.
In one embodiment, the output level detection circuit is used to determine whether the output of the preamplifier is saturated, i.e., whether calibration is required; when the output level detection circuit detects that calibration is needed, the offset calibration circuit is controlled to generate a direct-current voltage in a positive phase or a negative phase to offset input direct-current offset, and the calibration circuit stops working when the operational amplifier is separated from a saturation state along with the increase of the direct-current voltage.
Because the electrode misadjustment is up to several hundred mV (for example, the ECG electrode misadjustment is up to 300mV), the DCOC circuit is used for preventing the output of the first-stage operational amplifier from being saturated and generating signal distortion, but the direct current misadjustment is not required to be completely filtered, the misadjustment is controlled within the range of several mV, the output of the first-stage operational amplifier is not saturated, and the direct current misadjustment amplified by the first-stage operational amplifier can be filtered by the rear-stage capacitive coupling operational amplifier.
In one embodiment, the control signal waveform of a control logic circuit is as shown in fig. 4, and preferably, the logic signal thereof can be appropriately changed according to actual needs, and the signal includes a first comparator CMP1Output signal a, second comparator CMP2Output signal B, third comparator CMP3Output signal D, fourth comparator CMP4Output signal of C, N bit adder, reset signal RST of N bit adder, enable signal EN of N bit adder, and clocking of third chopping switch CH3The signal CTRL 1.
When A, B, C, D is at a high level, two signals of the preamplifier are not saturated, the amplifier works normally, at the moment, RST keeps a high potential and is not reset, EN keeps at a low level, the N-bit counter stops counting and keeps outputting, CTRL1 keeps the original state, and a third chopper CH3 keeps the previous state for chopping;
when the signal B, C changes to high potential and A, D changes to low potential, the positive phase output of the preamplifier exceeds the upper limit, the negative phase output exceeds the lower limit, the output of the preamplifier is saturated, the normal operation is changed into an abnormal state of output saturation, at the moment, RST changes to low level for a short time and then returns to high level, the N-bit counter is reset, EN changes to high level, the N-bit counter starts to count from 0, CTRL1 keeps at high level, and CH3 performs chopping under a normal clock;
when the signal A, B, C changes to high potential and D changes to low potential, the forward output of the preamplifier is normal, the inverted output exceeds the lower limit, the output of the preamplifier is saturated, at the moment, RST keeps high potential and is not reset, EN keeps high level, the N-bit counter continues counting, CTRL1 keeps high level, and CH3 performs chopping under a normal clock;
when the signal A, D changes to high potential and B, C changes to low potential, the positive phase output of the preamplifier exceeds the lower limit, the negative phase output exceeds the upper limit, the preamplifier output is saturated, the RST keeps high potential and is not reset, the EN keeps high level, the N-bit counter continues counting, CTRL1 changes to low level, and CH3 performs chopping under a reverse phase clock;
when the signal A, B, D changes to high potential and C changes to low potential, the positive phase output of the preamplifier is normal, the negative phase output exceeds the upper limit, the preamplifier output is saturated, RST keeps high potential and is not reset, EN keeps high level, the N-bit counter continues counting, CTRL1 keeps low level, and CH3 performs chopping under the reverse phase clock;
when the signal A, C, D changes to high potential and D changes to low potential, the positive phase output of the preamplifier exceeds the lower limit, the negative phase output is normal, the preamplifier output is saturated, RST keeps high potential and is not reset, EN keeps high level, the N-bit counter continues counting, CTRL1 keeps low level, and CH3 performs chopping under the reverse phase clock;
when the signal B, C, D changes to high potential and A changes to low potential, the positive phase output of the preamplifier exceeds the upper limit, the negative phase output is normal, the preamplifier output is saturated, RST keeps high potential and is not reset, EN keeps high level, the N-bit counter continues counting, CTRL1 changes to high level, and CH3 performs chopping under normal clock;
when the signal A, B, C, D changes to a high level, the preamplifier operates normally, RST is kept high and is not reset, EN changes to a low level, the N-bit counter stops counting and maintains output, CTRL1 keeps at a high level in the previous state, and CH3 keeps at the previous state and performs chopping.
In one embodiment, the control signal S is in the offset calibration circuit1～SNControl low noise band gap reference source BGR to generate variable output reference voltage VREFDAnd V isREFSA fixed reference voltage generated for a band gap reference source BGR. Because the output driving capability of the band gap reference source BGR is limited, the combination of the chopping wave and the capacitor enables the output resistance to be reduced, and in order to enhance the driving capability, a buffer is added after each of two outputs of the band gap reference source BGR; preferably, the first buffer and the second buffer may be omitted when the driving capability of the band gap reference source BGR is sufficient to drive the load. The input end of the offset calibration circuit CTRL2 is a clock phase control signal of a chopping wave CH 3; preferably, the positive and negative of the clock phase are determined according to the magnitude relation of two output signals of the preamplifier.
In one embodiment, a trimming circuit for N-bit trimming of a low noise bandgap reference source BGR is shown in FIG. 6, and comprises M1～MNResistance R1～RNAnd RS. Wherein IBGRAn output terminal V with referenceREFDConnected and electrically connected to the transistor M1Source terminal and resistor R1One terminal of (1), transistor M1Is electrically connected with the control signal S1Resistance R1Is electrically connected to the drain terminal of the transistor M1, and is electrically connected toTransistor M2Source terminal and resistor R2One terminal of (1), transistor M2Is electrically connected with the control signal S2Resistance R2Is electrically connected to the transistor M2The drain terminal of the transistor M is electrically connected to the transistor M in sequence as aboveNAnd a resistor RNTransistor MNIs electrically connected with the control signal SNTransistor MNIs electrically connected to the resistor RNOne end of (A) RNIs electrically connected to MNDrain terminal and resistor RSAnd is electrically connected to the other output V of the referenceREFS，RSAnd the other end of the same is grounded.
IBGRA branch current, V, for reference outputREFSFor a fixed reference voltage of output, VREFDFor the output variable reference voltage, by means of an N-bit control signal S1～SNThe resistance value of the access branch circuit is adjusted to adjust the output voltage value.
In one embodiment, an N-bit trimming low noise bandgap reference source comprises: the circuit comprises first to Nth transistors, first to Nth resistors, a ground resistor and a current source;
the current source is electrically connected with the source end of the first transistor, the drain end of the nth transistor is electrically connected with the source end of the (N + 1) th transistor, the nth resistor is electrically connected between the source end and the drain end of the nth transistor, N belongs to (1-N-1), and N is an integer;
the first end of the grounding resistor is electrically connected with the drain end of the Nth transistor, and the second end of the grounding resistor is grounded.
Outputting a fixed reference voltage VREFSOutputting a variable reference voltage V for the source terminal voltage of the first transistorREFDThe drain terminal voltage of the Nth transistor; the grid ends of the first transistor to the Nth transistor are used as N-bit control input ends S of the offset calibration circuit1～SNBy means of an N-bit control signal S1～SNThe resistance value of the access branch circuit is adjusted to adjust the output voltage value.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements.
All documents referred to herein are incorporated by reference into this application as if each were individually incorporated by reference. Furthermore, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the above teachings of the present invention, and such equivalents may fall within the scope of the claims of the present application.

Claims (9)

1. A direct current offset calibration circuit of a chopper instrument amplifier is characterized by comprising: the device comprises a first chopping switch, a first input coupling capacitor, a second input coupling capacitor, a preamplifier, a second chopping switch, an output level detection circuit and an offset calibration circuit;
the positive phase output end of the first chopping switch is electrically connected with the positive phase input end of the preamplifier through the first input coupling capacitor, and the negative phase output end of the first chopping switch is electrically connected with the negative phase input end of the preamplifier through the second input coupling capacitor;
the inverting output end of the preamplifier is electrically connected with the positive phase input end of the second chopping switch, and the positive phase output end of the preamplifier is electrically connected with the inverting input end of the second chopping switch;
the positive phase output end of the second chopping switch is electrically connected with the positive phase feedback input end of the output level detection circuit, and the negative phase output end of the second chopping switch is electrically connected with the negative phase feedback input end of the output level detection circuit;
n-bit control signal output end Y of the output level detection circuit1～YNAnd an N-bit control input terminal S of the offset calibration circuit1～SNElectrically connected, wherein N is more than or equal to 2 and is an integer; the clock control output end of the output level detection circuit is electrically connected with the clock control input end of the offset calibration circuit;
a positive feedback output end of the offset calibration circuit is electrically connected to a node between the first input coupling capacitor and the positive input end of the preamplifier, and an inverted feedback output end of the offset calibration circuit is electrically connected to a node between the second input coupling capacitor and the inverted input end of the preamplifier;
the offset calibration circuit comprises: the N-bit trimming low-noise band-gap reference source, the third chopping switch, the first feedback output capacitor and the second feedback output capacitor are connected in series;
a plurality of input ends of the N-bit trimming low-noise band-gap reference source are used as N-bit control input ends S of the offset calibration circuit1～SNA clock control input end of the third chopping switch is used as a clock control input end of the offset calibration circuit;
a fixed reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with a positive phase input end of the third chopping switch, and a variable reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with a negative phase input end of the third chopping switch;
a first clock input end and a second clock input end of the third chopping switch receive two-phase non-overlapped chopping clocks; a positive phase output end of the third chopping switch is electrically connected with a first end of the first feedback output capacitor, and a negative phase output end of the third chopping switch is electrically connected with a first end of the second feedback output capacitor;
the second end of the first feedback output capacitor is used as a positive phase feedback output end of the offset calibration circuit, and the second end of the second feedback output capacitor is used as a negative phase feedback output end of the offset calibration circuit.
2. The chopper instrumentation amplifier dc offset calibration circuit of claim 1, wherein the N-bit control signal output terminal Y of the output level detection circuit1～YNAnd an N-bit control input terminal S of the offset calibration circuit1～SNAn electrical connection, comprising:
each output end of the output level detection circuit is YnEach input terminal S of the offset calibration circuitnSaid output terminal YnAnd the input terminal SnAnd electrically connecting, wherein N ∈ (1-N) is an integer.
3. The chopper instrumentation amplifier dc offset calibration circuit of claim 2, wherein the output level detection circuit comprises: the comparator comprises a first comparator, a second comparator, a third comparator, a fourth comparator, an N-bit adder and a control logic circuit;
the positive phase input end of the first comparator and the positive phase input end of the second comparator are used as the positive phase input ends of the output level detection circuit, and the positive phase input end of the third comparator and the negative phase input end of the fourth comparator are used as the negative phase input ends of the output level detection circuit;
a positive phase input end of the first comparator is connected with a first voltage, and an output end of the first comparator is electrically connected with a first input end of the control logic circuit;
the inverting input end of the second comparator is connected with a second voltage, and the output end of the second comparator is electrically connected with the second input end of the control logic circuit;
the inverting input end of the third comparator is connected with the second voltage, and the output end of the third comparator is electrically connected with the third input end of the control logic circuit;
the positive phase input end of the fourth comparator is connected with the first voltage, and the output end of the fourth comparator is electrically connected with the fourth input end of the control logic circuit;
the positive phase output end of the control logic circuit is electrically connected with the reset end of the N-bit adder, and the negative phase output end of the control logic circuit is electrically connected with the enable end of the N-bit adder.
4. The DC offset calibration circuit of chopper instrumentation amplifier as defined in claim 3, wherein a positive output terminal of said control logic circuit sends a reset signal to a reset terminal of said N-bit adder, a negative output terminal of said control logic circuit sends an enable signal to an enable terminal of said N-bit adder, a clock control output terminal of said output level detection circuit sends a clock control signal of a third chopper switch to a clock control input terminal of said offset calibration circuit, and an N-bit control signal output terminal Y of said output level detection circuit1～YNTo the N-bit control input S of the offset calibration circuit1～SNAnd sending an N-bit trimming control signal.
5. The chopper instrumentation amplifier dc offset calibration circuit of claim 1, further comprising: a first buffer and a second buffer;
the fixed reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with the positive phase input end of the first buffer, and the variable reference output end of the N-bit trimming low-noise band-gap reference source is electrically connected with the positive phase input end of the second buffer;
the output end of the first buffer is electrically connected with the inverting end of the first buffer and the non-inverting input end of the third chopping switch respectively, and the output end of the second buffer is electrically connected with the inverting end of the second buffer and the inverting input end of the third chopping switch respectively.
6. The chopper instrumentation amplifier dc offset calibration circuit of claim 1, wherein the output level detection circuit is configured to determine whether the preamplifier needs to be calibrated, and when the output level detection circuit detects that the preamplifier needs to be calibrated, the offset calibration circuit is controlled to generate a dc voltage to offset an input dc offset.
7. The chopper instrumentation amplifier's DC offset calibration circuit of claim 6, wherein the DC voltage is a positive phase DC voltage or a negative phase DC voltage;
and the direct current offset calibration circuit stops calibration work when the preamplifier is out of a saturation state along with the increase of the direct current voltage.
8. The chopper instrumentation amplifier dc offset calibration circuit of claim 1, wherein the N-bit trimmed low noise bandgap reference source comprises: the circuit comprises first to Nth transistors, first to Nth resistors, a ground resistor and a current source;
the current source is electrically connected with the source end of the first transistor, the drain end of the nth transistor is electrically connected with the source end of the (N + 1) th transistor, and the nth resistor is electrically connected between the source end and the drain end of the nth transistor, wherein N belongs to (1-N-1), and N is an integer;
the N resistor is electrically connected between the source end and the drain end of the N transistor, the first end of the grounding resistor is electrically connected with the drain end of the N transistor, and the second end of the grounding resistor is grounded.
9. The chopper-regulated instrumentation amplifier DC offset calibration circuit of claim 8, wherein the gate terminals of the first through Nth transistors are used as the N-bit control input terminal S of the offset calibration circuit1～SN。
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