CN114070273A - Sequential control circuit architecture and control method of AMR sensor switch chip - Google Patents

Abstract

The invention discloses a sequential control circuit architecture of an AMR sensor switch chip.A F _ CLK output end of a fast clock circuit is connected with a CLK _1 input end of a first combinational logic operation module and a CLK input end of a second combinational logic operation module, and an EN input end of the fast clock circuit is connected with an EN output end of the first combinational logic operation module; the S _ CLK output end of the slow clock circuit is connected with the CLK _2 input end of the first combinational logic operation module; the signal output end of the first combinational logic operation module outputs a sampling signal, and the EN output end outputs a detection enabling signal; and the comparator enabling signal output end of the second combinational logic operation module outputs a comparator enabling signal, and the chopping wave output end outputs a two-phase chopping wave signal. The invention can reduce the working current of the reluctance switch chip, reduce the working energy consumption, is not easy to generate burr signals, and adopts the chopping offset cancellation technology to improve the detection precision.

Description

Sequential control circuit architecture and control method of AMR sensor switch chip

Technical Field

The invention relates to the technical field of sensor control circuits, in particular to a sequential control circuit architecture and a control method of an AMR sensor switch chip.

Background

The Anisotropic Magnetoresistance (AMR) effect is a phenomenon in which the resistivity in a ferromagnetic material changes with changes in magnetization (applied magnetic field) and direction of current flow. The magnetoresistive sensor manufactured based on this effect is widely used because of its advantages such as high sensitivity and easy integration. In a common sequential control circuit architecture, a signal output by an oscillator enters a frequency divider for processing, the frequency divider inputs the processed signal into a combinational logic operation unit, and finally outputs an AMR switch chip detection enabling clock signal and a comparator for judging and outputting a sampling clock signal, so as to control the AMR switch chip to detect the existence or nonexistence of a magnetic field. However, for applications with a large frequency division number and a long counting period, when the timing control circuit architecture is adopted to control an AMR switch chip to work, a required combinational logic operation circuit has a large scale, a large operation amount and a large power consumption, burrs are easily generated in an operation process, an AMR output signal is directly sent to a comparator, the offset of the comparator is greatly influenced by a process (an automatic zero calibration comparator cannot be used without a chopping signal), and the detection precision is low.

In view of this, the present application is specifically made.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: for the application of multiple frequency division times and long counting period, when a common sequential control circuit architecture is adopted to control an AMR switch chip to detect a magnetic field, the required combinational logic operation circuit has large scale, large operation amount and large power consumption, and burrs are easy to generate in the operation process. The aim is to provide a sequential control circuit framework and a control method of an AMR sensor switch chip, which enable analog circuits such as a magnetic resistance bridge with larger power consumption, a comparator and the like in the chip to be in a working-sleep-working state periodically through a digital control circuit, and determine the existence or nonexistence of a magnetic field through a sampling mode, thereby effectively reducing the power consumption of the chip; in addition, two-phase chopping signals are introduced to eliminate the offset voltage of the instrumentation amplifier, so that the detection precision of the reluctance switch chip is improved.

The invention is realized by the following technical scheme:

in one aspect, the present invention provides a sequential control circuit architecture of an AMR sensor switch chip, including: the clock circuit comprises a fast clock circuit, a slow clock circuit, a first combined logic operation module and a second combined logic operation module; the F _ CLK output end of the fast clock circuit is connected with the CLK _1 input end of the first combinational logic operation module and the CLK input end of the second combinational logic operation module, and the EN input end of the fast clock circuit is connected with the EN output end of the first combinational logic operation module; the S _ CLK output end of the slow clock circuit is connected with the CLK _2 input end of the first combinational logic operation module; the Sampling output end of the first combinational logic operation module outputs a Sampling signal, and the EN output end outputs a detection enabling signal; and the EN _ comp output end of the second combinational logic operation module outputs a comparator enabling signal, and the chopping output end outputs a two-phase chopping signal.

The invention firstly aims at the problems of large scale, large operation amount and large power consumption of a combinational logic operation circuit which is required by a common sequential control circuit framework when an AMR switch chip is controlled to detect a magnetic field under the conditions of multiple frequency division times and long counting period, and provides a digital circuit which is composed of a slow clock, a fast clock and a combinational logic operation module and is used for controlling analog circuits such as a magnetic resistance bridge and a comparator with large power consumption in the chip to be in a working-sleep-working state with low periodicity, and the existence or nonexistence of the magnetic field is determined by a sampling mode without real-time detection, so that the energy consumption of the chip can be effectively reduced. The working-sleeping time period of the chip is determined by the slow clock circuit, and the working time and the sampling time of the chip are obtained by the slow clock circuit, the fast clock circuit and the combinational logic operation module. The slow clock circuit is used for setting the work-sleep period of the chip, and the clock period is long and the consumed current is low; the fast clock circuit is used for generating a fast clock signal, and has short working time and low current consumption; the combinational logic operation is used for carrying out logic operation on the fast clock signal and the slow clock signal, the logic of an internal circuit is clear, the operation amount is small, and a detection enabling signal of a chip, a comparator output sampling signal and a comparator enabling signal can be generated; during the period that the chip detects that the enable signal is high-level, the comparator compares the differential output of the instrument amplifier in the duration of the sampling signal output by the comparator, the sampling signal samples the output result of the comparator, and the sampling result is sent to the output driver of the chip. Therefore, the invention adopts two sets of fast and slow clock circuits, and is matched with the combinational logic operation module, so that the chip can be controlled to complete the signal detection work within a shorter working time under a lower working current, the operation amount is small, and the power consumption of the chip can be effectively reduced. In addition, the combinational logic operation module also outputs a chopping signal to eliminate the offset voltage of the instrument amplifier, and an automatic zero calibration comparator is adopted to eliminate the offset of the comparator, so that the detection precision of the magnetic resistance switch chip is improved, and the problems that burrs are easily generated in the operation process of a common sequential control circuit framework, the AMR output signal is directly supplied to the comparator, the offset of the comparator is greatly influenced by the process, and the detection precision is low are solved.

As a further description of the present invention, the POR input end of the first combinational logic operation module receives a power-on Reset signal, the Reset output end outputs a Reset signal, and the EN output end is connected to the EN input end of the second combinational logic operation module; chopping output ends of the second combinational logic operation module comprise a chopping PH1 output end and a chopping PH2 output end.

As a further description of the present invention, the first combinational logic operation module includes: a detection enable signal generation unit, a sampling signal generation unit and a reset signal generation unit; the input end of the detection enabling signal generating unit is connected with the output end of the slow clock circuit and receives the POR signal, and the output end outputs a detection enabling signal; the input end of the sampling signal generating unit is connected with the output end of the fast clock circuit and receives the POR signal, and the output end outputs the sampling signal; the input end of the reset signal generating unit is connected with the output end of the sampling signal generating unit, and the output end of the reset signal generating unit is connected with the detection enabling signal generating unit and the sampling signal generating unit; the reset signal generating unit receives the POR signal and outputs a reset signal.

As a further description of the present invention, the detection enable signal generating unit includes: a two-input and gate a1, a flip-flop B6, and a drive buffer D1; the A1, the B6 and the D1 are connected in sequence, one input end of the A1 is connected with the S _ CLK output end of the slow clock circuit, and the other input end of the A1 receives a POR signal; the output end of the D1 outputs a detection enable signal; the sampling signal generation unit includes: a two-input and gate a2 and a counter; the A2 and the counter are connected in sequence, one input end of A2 is connected with the F _ CLK output end of the fast clock circuit, and the other input end of A2 receives POR signals; the output end of the counter outputs a sampling signal; the reset signal generation unit includes: a two-input and gate a3, delay buffers E1 and E2, and an inverter N1; the E1 and the E2 are connected in series and then connected with one input end of A3, the output end of A3 is connected with the input end of N1, and the output end of N1 outputs a reset signal; the input end of E1 is connected with the output end of the counter, the other input end of A3 receives POR signals, and the output end of N1 is connected with the Reset end of the counter and the Reset end of B6.

As a further description of the present invention, the counter includes: flip-flops B1, B2, B3, B4, and B5, and a two-input and gate a 4; the B1, B2, B3, B4 and B5 are cascaded, and the D input of each flip-flop is terminated

An output end; the CK input end of B1 terminates F _ CLK output end of the fast clock circuit (1); the Q output of B3 is connected with one input end of A4, and the Q output of B5 is connected with the other input end of A4; the reset terminals of B1, B2, B3, B4, and B5 receive a reset signal.

As a further description of the present invention, the second combinational logic operation module includes: two-input AND gates A5, A6, A7 and A8, a three-input NAND gate A9, flip-flops B6, B7, B8, B9 and B10, a delay buffer E3, an inverter N2 and a two-phase non-overlapping clock generator F; one input end of A5 receives a CLK signal, the other input end receives an EN signal, and the output end is connected with a CK input end of B6; b6, B7, B8 and B9 are cascaded, the Q output end of B6 is connected with one input end of A6, the Q output end of B7 is connected with one input end of A7, the Q output end of B9 is connected with the other input end of A6 and the other input end of A7; the output end of A7 is connected with E3 and N2 in sequence and then is connected with one input end of A8, the other input end of A8 is connected with the EN output end of the first combinational logic operation module (3), and the output end of A8 is connected with the reset ends of B6, B7, B8 and B9; the output end of A7 is connected with B The CK input end of 10, the Q output end of B10 is connected with the input end of F, and B10 receives an EN signal; the output end of the F outputs a two-phase chopping signal; the D inputs of B6, B7, B8, B9 and B10 are terminated

An output end; the output ends of A5 and A6 and the PH2 output end of F are connected with the input end of A9, and the output end of A9 outputs a comparator enable signal.

As a further description of the present invention, the two-phase non-overlapping clock generator F includes: inverters N4, N5, N6, N7, N8 and N9, two-input nand gates a10 and a11, and delay buffers E4, E5, E6 and E7;

n4 and N5 are connected in series and then connected to one input end of A10, A10, E4, E5, N6 and N7 are sequentially connected in series, the input end of N4 is connected with the Q output end of B10, and N7 outputs a chopping signal PH 1; a11, E6, E7, N8 and N9 are connected in series in sequence, one input end of A11 is connected between N4 and N5, the other input end of the A7 is connected with the output end of the N7, the output end of N9 is connected with the other input end of the A10, and N9 outputs a chopping signal PH 2.

As a further description of the present invention, the delay buffer includes: a plurality of cascaded even inverters.

As a further description of the present invention, the driving buffer includes: a plurality of cascaded odd inverters.

On the other hand, the invention provides a time sequence control method of an AMR sensor switch chip, which comprises the following steps:

The slow clock circuit sends an S _ CLK signal to the first combinational logic operation module;

the fast clock circuit sends an F _ CLK signal to the first combinational logic operation module;

the first logic operation module performs logic operation according to the S _ CLK signal and the F _ CLK signal and outputs a detection enable signal and a sampling signal;

the fast clock circuit sends an F _ CLK signal to the second combinational logic operation module;

the first combinational logic operation module sends an EN signal to the second combinational logic operation module;

the second combinational logic operation module carries out logic operation according to the F _ CLK signal and the EN signal and outputs a comparator enabling signal and a two-phase chopping signal;

and controlling the working time sequence of a chip according to the detection enabling signal, the sampling signal, the output comparator enabling signal and the two-phase chopping signal.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. the sequential control circuit architecture and the control method of the AMR sensor switch chip provided by the embodiment of the invention can reduce the working current of the reluctance switch chip and reduce the working energy consumption;

2. according to the sequential control circuit architecture and the control method of the AMR sensor switch chip, provided by the embodiment of the invention, the logic of a combinational logic control circuit is clear, the operand is small, burr signals are not easy to generate, and the detection precision is improved by adopting a chopping offset cancellation technology;

3. The sequential control circuit architecture and the control method of the AMR sensor switch chip provided by the embodiment of the invention can flexibly adjust the duty ratio of the work-sleep-work of the chip and meet different practical application requirements.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that for those skilled in the art, other related drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a common timing control circuit architecture according to embodiment 1 of the present invention;

fig. 2 is a schematic diagram of a timing control circuit architecture of an AMR sensor switch chip according to embodiment 1 of the present invention;

fig. 3 is a schematic diagram illustrating a wiring relationship of an internal circuit of a first combinational logic operation module according to embodiment 1 of the present invention;

fig. 4 is a wiring diagram of an internal circuit of a counter in a first combinational logic operation module according to embodiment 1 of the present invention;

fig. 5 is a schematic diagram illustrating a wiring relationship of an internal circuit of a second combinational logic operation module according to embodiment 1 of the present invention;

Fig. 6 is a wiring diagram of an internal circuit of a two-phase non-overlapping clock generator in a second combinational logic operation module according to embodiment 1 of the present invention;

fig. 7 is a schematic diagram of a structural logic relationship of a timing control circuit according to embodiment 2 of the present invention;

fig. 8 is a schematic diagram of an operation timing sequence of an AMR sensor switch chip according to embodiment 2 of the present invention.

Reference numbers and corresponding part names in the drawings:

the circuit comprises a 1-fast clock circuit, a 2-slow clock circuit, a 3-first combined logic operation module, a 4-second combined logic operation module, a 31-detection enabling signal generation unit, a 32-sampling signal generation unit and a 33-reset signal generation unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail so as not to obscure the present invention.

Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "one embodiment," "an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "upper", "lower", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the scope of the present invention.

Example 1

Fig. 1 shows a schematic diagram of a general sequential control circuit architecture, where a signal output by an oscillator enters a frequency divider for processing, the frequency divider inputs the processed signal into a combinational logic operation unit, and finally outputs an AMR switch chip detection enable clock signal and a comparator discriminates an output sampling clock signal for controlling the presence or absence of a detection magnetic field of the AMR switch chip. However, for applications with a large frequency division number and a long counting period, when the sequential control circuit architecture is used for controlling the operation of the AMR switch chip, the required combinational logic operation circuit has a large scale, a large operation amount and large power consumption, and burrs are easily generated in the operation process.

In view of the above-mentioned drawbacks of the conventional sequential control circuit architecture structure, the present embodiment provides a sequential control circuit architecture of an AMR sensor switch chip, as shown in fig. 2. The sequential control circuit architecture comprises: the clock circuit comprises a fast clock circuit 1, a slow clock circuit 2, a first combinational logic operation module 3 and a second combinational logic operation module 4; the F _ CLK output end of the fast clock circuit 1 is connected with the CLK _1 input end of the first combinational logic operation module 3 and the CLK input end of the second combinational logic operation module 4, and the EN input end of the fast clock circuit 1 is connected with the EN output end of the first combinational logic operation module 3; the S _ CLK output end of the slow clock circuit 2 is connected with the CLK _2 input end of the first combinational logic operation module 3; the Sampling output end of the first combinational logic operation module 3 outputs a Sampling signal, and the EN output end outputs a detection enabling signal; the EN _ comp output end of the second combinational logic operation module 4 outputs a comparator enable signal, and the chopping output end outputs a two-phase chopping signal. The POR input end of the first combinational logic operation module 3 receives a power-on Reset signal, the Reset output end outputs a Reset signal, and the EN output end is connected with the EN input end of the second combinational logic operation module 4; the chopping output end of the second combinational logic operation module 4 comprises a chopping PH1 output end and a chopping PH2 output end.

Wherein the content of the first and second substances,

the slow clock circuit 2 can be formed by adding a comparator structure based on an RC charge-discharge unit and is used for generating a slow clock signal and setting the work-sleep period of the chip, wherein the clock period is long and the consumed current is low; the period of the slow clock circuit 2 is determined by the duty-sleep-duty cycle requirements of the magnetoresistive switching chips. In this embodiment, the duty-sleep cycle of the chip is set to 1 slow clock cycle, and the duty state is 20 fast clock cycles.

The fast clock circuit 1 may be formed by an RC-based charging and discharging unit and a comparator architecture, and is used for generating a fast clock signal (compared with a slow clock signal) with a low current consumption during its operation time.

The first combined logic operation module 3 is used for performing logic operation on the fast clock signal and the slow clock signal, generating a detection enabling signal of the chip, an enabling signal of the fast clock and a sampling signal output by the comparator, so that analog circuits such as a magnetic resistance bridge and the comparator with larger power consumption in the chip are controlled to be in a working-sleep-working state periodically, the existence of a magnetic field is determined by a sampling mode, and the sampling time is set by the time of a delay unit in a time sequence control circuit framework.

And the second combined logic operation module 4 is used for carrying out logic operation on the fast clock signal, generating a two-phase chopping signal and a comparator enabling signal and controlling the comparator to work. The chopper signals are used for eliminating offset signals of the instrument amplifier, and detection precision is improved.

Under the control of the timing control circuit architecture of this embodiment, during the period when the chip detects that the enable signal is high-flat, the comparator compares the differential output of the instrumentation amplifier during the time when the comparator outputs the sampling signal, the sampling signal samples the output result of the comparator, and the sampling result is sent to the output driver of the chip. Because the embodiment adopts the fast and slow clock circuits and is matched with the combinational logic operation module, the chip can be controlled to complete the signal detection work within a short working time under a lower working current, the operation amount is small, and the power consumption of the chip can be effectively reduced. In addition, the combinational logic operation module also outputs a chopping signal to eliminate the offset voltage of the instrument amplifier, so that the detection precision of the reluctance switch chip is improved, and the problems that burrs are easily generated in the operation process and the detection precision is low in a common sequential control circuit framework are solved.

Next, the first combinational logic operation module 3 and its counter, the second combinational logic operation module 4 and its internal structure of the two-phase non-overlapping clock generator in the sequential control circuit architecture will be described in detail.

The internal circuit wiring relationship of the first combinational logic operation module 3 is shown in fig. 3, and includes: a detection enable signal generation unit 31, a sampling signal generation unit 32, and a reset signal generation unit 33; the input end of the detection enable signal generating unit 31 is connected to the output end of the slow clock circuit 2 and receives the POR signal, and the output end outputs a detection enable signal; the input end of the sampling signal generating unit 32 is connected to the output end of the fast clock circuit 1 and receives the POR signal, and the output end outputs the sampling signal; the input end of the reset signal generating unit 33 is connected to the output end of the sampling signal generating unit 32, and the output end is connected to the detection enable signal generating unit 31 and the sampling signal generating unit 32; the reset signal generation unit 33 receives the POR signal and outputs a reset signal.

Furthermore, in the first combinational logic operation module 3,

the detection enable signal generation unit 31 includes: a two-input and gate a1, a flip-flop B6, and a drive buffer D1; the A1, the B6 and the D1 are connected in sequence, one input end of the A1 is connected with the S _ CLK output end of the slow clock circuit 2, and the other input end of the A1 receives a POR signal; the output terminal of D1 outputs a detection enable signal.

The sampling signal generation unit 32 includes: a two-input and gate a2 and a counter; the A2 and the counter are connected in sequence, one input end of A2 is connected with the F _ CLK output end of the fast clock circuit 1, and the other input end receives POR signals; the output end of the counter outputs a sampling signal.

The reset signal generation unit 33 includes: a two-input and gate a3, delay buffers E1 and E2, and an inverter N1; the E1 and the E2 are connected in series and then connected with one input end of A3, the output end of A3 is connected with the input end of N1, and the output end of N1 outputs a reset signal; the input end of E1 is connected with the output end of the counter, the other input end of A3 receives POR signals, and the output end of N1 is connected with the Reset end of the counter and the Reset end of B6.

Further, in the sampling signal generating unit 32,

the counter includes: flip-flops B1, B2, B3, B4, and B5, and a two-input and gate a 4; the B1, B2, B3, B4 and B5 are cascaded, and the D input end of each flip-flop is connected with the output end; the CK input end of B1 terminates F _ CLK output end of fast clock circuit 1 (1); the Q output of B3 is connected with one input end of A4, and the Q output of B5 is connected with the other input end of A4; the reset terminals of B1, B2, B3, B4, and B5 receive a reset signal. The internal circuit wiring relationship of the counter is shown in FIG. 4.

The internal circuit wiring relationship of the second combinational logic operation module 4 is shown in fig. 5, and includes: two-input AND gates A5, A6, A7 and A8, a three-input NAND gate A9, flip-flops B6, B7, B8, B9 and B10, a delay buffer E3, an inverter N2 and a two-phase non-overlapping clock generator F; one input end of A5 receives a CLK signal, the other input end receives an EN signal, and the output end is connected with a CK input end of B6; b6, B7, B8 and B9 are cascaded, the Q output end of B6 is connected with one input end of A6, the Q output end of B7 is connected with one input end of A7, the Q output end of B9 is connected with the other input end of A6 and the other input end of A7; the output end of A7 is connected with E3 and N2 in sequence and then is connected with one input end of A8, the other input end of A8 is connected with the EN output end of the first combinational logic operation module 3(3), and the output end of A8 is connected with the reset ends of B6, B7, B8 and B9; the output end of A7 is connected with the CK input end of B10, the Q output end of B10 is connected with the input end of F, and B10 receives an EN signal; the output end of the F outputs a two-phase chopping signal; d inputs of B6, B7, B8, B9 and B10 are connected with an output end; the output ends of A5 and A6 and the PH1 output end of F are connected with the input end of A9, and the output end of A9 outputs a comparator enable signal.

Furthermore, in the second combinational logic operation module 4,

The two-phase non-overlapping clock generator F includes: inverters N4, N5, N6, N7, N8 and N9, two-input nand gates a10 and a11, and delay buffers E4, E5, E6 and E7; n4 and N5 are connected in series and then connected to one input end of A10, A10, E4, E5, N6 and N7 are sequentially connected in series, the input end of N4 is connected with the Q output end of B10, and N7 outputs a chopping signal PH 1; a11, E6, E7, N8 and N9 are connected in series in sequence, one input end of A11 is connected between N4 and N5, the other input end of the A7 is connected with the output end of the N7, the output end of N9 is connected with the other input end of the A10, and N9 outputs a chopping signal PH 2. The internal circuit connections of the two-phase non-overlapping clock generator are shown in FIG. 6.

In the first combinational logic operation module 3 and the second combinational logic operation module 4, the delay buffer includes: a plurality of cascaded even inverters. The driving buffer includes: a plurality of cascaded odd inverters.

Example 2

The present embodiment provides a timing control method for a timing control circuit architecture of an AMR sensor switch chip as described in embodiment 1, wherein a logical relationship of the timing control circuit architecture is as shown in fig. 7, and the timing control method includes the following steps:

step 1: the slow clock circuit sends an S _ CLK signal to the first combinational logic operation module;

And (3) failure 2: the fast clock circuit sends an F _ CLK signal to the first combinational logic operation module;

and step 3: the first logic operation module performs logic operation according to the S _ CLK signal and the F _ CLK signal and outputs a detection enable signal and a sampling signal;

and 4, step 4: the fast clock circuit sends an F _ CLK signal to the second combinational logic operation module;

and 5: the first combinational logic operation module sends an EN signal to the second combinational logic operation module;

step 6: the second combinational logic operation module carries out logic operation according to the F _ CLK signal and the EN signal and outputs a comparator enabling signal and a two-phase chopping signal;

and 7: and controlling the working time sequence of a chip according to the detection enabling signal, the sampling signal, the output comparator enabling signal and the two-phase chopping signal.

Please refer to fig. 8 for the timing sequence of the AMR sensor switch chip. It should be noted that various other embodiments of the clock generation circuit, the counter, the delay unit, the two-phase non-overlapping clock generator, etc. may be used in the present embodiment, and those skilled in the art may make various changes and/or modifications according to the present invention without departing from the spirit and scope of the present invention.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A sequential control circuit architecture of an AMR sensor switch chip, comprising: the clock circuit comprises a fast clock circuit (1), a slow clock circuit (2), a first combinational logic operation module (3) and a second combinational logic operation module (4); the F _ CLK output end of the fast clock circuit (1) is connected with the CLK _1 input end of the first combinational logic operation module (3) and the CLK input end of the second combinational logic operation module (4), and the EN input end of the fast clock circuit (1) is connected with the EN output end of the first combinational logic operation module (3); the S _ CLK output end of the slow clock circuit (2) is connected with the CLK _2 input end of the first combinational logic operation module (3); the Sampling output end of the first combinational logic operation module (3) outputs a Sampling signal, and the EN output end outputs a detection enabling signal; and the EN _ comp output end of the second combinational logic operation module (4) outputs a comparator enabling signal, and the chopping output end outputs a two-phase chopping signal.

2. The sequential control circuit architecture of the AMR sensor switch chip as recited in claim 1, wherein a POR input terminal of the first combinational logic operation module (3) receives a power-on Reset signal, a Reset output terminal outputs a Reset signal, and an EN output terminal is connected with an EN input terminal of the second combinational logic operation module (4); chopping output ends of the second combinational logic operation module (4) comprise a chopping PH1 output end and a chopping PH2 output end.

3. The sequential control circuit architecture of an AMR sensor switch chip according to claim 1, characterized in that said first combinational logic operation module (3) comprises: a detection enable signal generation unit (31), a sampling signal generation unit (32), and a reset signal generation unit (33); the input end of the detection enabling signal generating unit (31) is connected with the output end of the slow clock circuit (2) and receives a POR signal, and the output end outputs a detection enabling signal; the input end of the sampling signal generating unit (32) is connected with the output end of the fast clock circuit (1) and receives POR signals, and the output end outputs sampling signals; the input end of the reset signal generating unit (33) is connected with the output end of the sampling signal generating unit (32), and the output end of the reset signal generating unit is connected with the detection enabling signal generating unit (31) and the sampling signal generating unit (32); the reset signal generation unit (33) receives the POR signal and outputs a reset signal.

4. The timing control circuit architecture of an AMR sensor switch chip of claim 3,

the detection enable signal generation unit (31) includes: a two-input and gate a1, a flip-flop B6, and a drive buffer D1; the A1, the B6 and the D1 are connected in sequence, one input end of the A1 is connected with the S _ CLK output end of the slow clock circuit (2), and the other input end of the A1 receives a POR signal; the output end of the D1 outputs a detection enable signal;

the sampling signal generation unit (32) includes: a two-input and gate a2 and a counter; the A2 and the counter are sequentially connected, one input end of the A2 is connected with the F _ CLK output end of the fast clock circuit (1), and the other input end of the A2 receives a POR signal; the output end of the counter outputs a sampling signal;

the reset signal generation unit (33) includes: a two-input and gate a3, delay buffers E1 and E2, and an inverter N1; the E1 and the E2 are connected in series and then connected with one input end of A3, the output end of A3 is connected with the input end of N1, and the output end of N1 outputs a reset signal; the input end of E1 is connected with the output end of the counter, the other input end of A3 receives POR signals, and the output end of N1 is connected with the Reset end of the counter and the Reset end of B6.

5. The timing control circuit architecture of an AMR sensor switch chip of claim 4, wherein said counter comprises: flip-flops B1, B2, B3, B4, and B5, and a two-input and gate a 4; the B1, B2, B3, B4 and B5 are cascaded, and the D input end of each flip-flop is connected with the Q output end; the CK input end of B1 terminates F _ CLK output end of the fast clock circuit (1); the Q output of B3 is connected with one input end of A4, and the Q output of B5 is connected with the other input end of A4; the reset terminals of B1, B2, B3, B4, and B5 receive a reset signal.

6. The sequential control circuit architecture of an AMR sensor switch chip according to claim 1, characterized in that said second combinational logic operation module (4) comprises: two-input AND gates A5, A6, A7 and A8, a three-input NAND gate A9, flip-flops B6, B7, B8, B9 and B10, a delay buffer E3, an inverter N2 and a two-phase non-overlapping clock generator F;

one input end of A5 receives a CLK signal, the other input end receives an EN signal, and the output end is connected with a CK input end of B6;

b6, B7, B8 and B9 are cascaded, the Q output end of B6 is connected with one input end of A6, the Q output end of B7 is connected with one input end of A7, the Q output end of B9 is connected with the other input end of A6 and the other input end of A7;

the output end of A7 is connected with E3 and N2 in sequence and then is connected with one input end of A8, the other input end of A8 is connected with the EN output end of the first combinational logic operation module (3), and the output end of A8 is connected with the reset ends of B6, B7, B8 and B9;

the output end of A7 is connected with the CK input end of B10, the Q output end of B10 is connected with the input end of F, and B10 receives an EN signal; the output end of the F outputs a two-phase chopping signal;

d inputs of B6, B7, B8, B9 and B10 are connected with a Q output end;

the output ends of A5 and A6 and the PH2 output end of F are connected with the input end of A9, and the output end of A9 outputs a comparator enable signal.

7. The timing control circuit architecture of an AMR sensor switch chip of claim 6, wherein said two-phase non-overlapping clock generator F comprises: inverters N4, N5, N6, N7, N8 and N9, two-input nand gates a10 and a11, and delay buffers E4, E5, E6 and E7;

n4 and N5 are connected in series and then connected to one input end of A10, A10, E4, E5, N6 and N7 are sequentially connected in series, the input end of N4 is connected with the Q output end of B10, and N7 outputs a chopping signal PH 1;

a11, E6, E7, N8 and N9 are connected in series in sequence, one input end of A11 is connected between N4 and N5, the other input end of the A7 is connected with the output end of the N7, the output end of N9 is connected with the other input end of the A10, and N9 outputs a chopping signal PH 2.

8. The timing control circuit architecture of an AMR sensor switch chip of claim 4, wherein said delay buffer comprises: a plurality of cascaded even inverters.

9. The timing control circuit architecture of an AMR sensor switch chip of claim 4, wherein said drive buffer comprises: a plurality of cascaded odd inverters.

10. A method of controlling a timing control circuit architecture according to any of claims 1-9, comprising the steps of:

The slow clock circuit sends an S _ CLK signal to the first combinational logic operation module;

the fast clock circuit sends an F _ CLK signal to the first combinational logic operation module;

the first logic operation module performs logic operation according to the S _ CLK signal and the F _ CLK signal and outputs a detection enable signal and a sampling signal;

the fast clock circuit sends an F _ CLK signal to the second combinational logic operation module;

the first combinational logic operation module sends an EN signal to the second combinational logic operation module;

the second combinational logic operation module carries out logic operation according to the F _ CLK signal and the EN signal and outputs a comparator enabling signal and a two-phase chopping signal;

and controlling the working time sequence of a chip according to the detection enabling signal, the sampling signal, the output comparator enabling signal and the two-phase chopping signal.

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