CN109765828B - Magnetic resistance type sensor chip time sequence control circuit and control method - Google Patents
Magnetic resistance type sensor chip time sequence control circuit and control method Download PDFInfo
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Abstract
The application discloses a time sequence control circuit of a magnetic resistance type sensor chip, which detects a clock signal output by a sampling controller connected with an oscillator; the shift register and the combinational logic operation unit are both connected to the frequency divider, and the frequency divider is connected to a clock signal output by the oscillator; the shift register is connected to the combinational logic operation unit, and the combinational logic operation unit outputs a detection enable clock signal to the AMR and the comparator. The application also discloses a time sequence control method of the magnetic resistance type sensor chip. The time sequence control circuit and the control method of the magnetic resistance type sensor chip effectively realize the work-sleep control of devices with larger power consumption such as a magnetic resistance bridge, a comparator and the like, meanwhile, the time sequence control circuit has clear framework, small combined logic operation amount and difficult generation of burr signals, can flexibly adjust the duty ratio of work-sleep-work of the chip, and meets different practical application requirements.
Description
Technical Field
The application relates to the field of sensor control circuits, in particular to a magnetic resistance type sensor chip time sequence control circuit and a control method.
Background
The anisotropic magnetoresistance (Anisotropic Magneto Resistance, AMR) effect is a phenomenon in which the resistivity in ferromagnetic materials changes with changes in magnetization (applied magnetic field) and current direction. The magneto-resistance sensor manufactured based on the effect has the advantages of high sensitivity, convenience in integration and the like, and is widely applied. Since the AMR switch chip is used to detect the presence or absence of a magnetic field, real-time detection is not necessary as long as the response is sensitive. In an AMR switch chip, when devices with larger power consumption such as a magnetoresistive bridge, a comparator and the like are turned on for a long time, the power consumption of the chip is increased, and even the heat productivity of the chip is increased.
Disclosure of Invention
The application aims to solve the technical problems that in an AMR switch chip, when devices with larger power consumption such as a magnetoresistive bridge, a comparator and the like are started for a long time, the power consumption of the chip is increased, even the heat productivity of the chip is increased, and the application aims to provide a time sequence control circuit and a time sequence control method for the magnetoresistive sensor chip, which solve the problems.
The application is realized by the following technical scheme:
a time sequence control circuit of a magnetic resistance type sensor chip comprises a detection sampling controller, a frequency divider, a shift register and a combination logic operation unit; the frequency divider, the shift register and the combinational logic operation unit are all connected with the detection sampling controller, and the detection sampling controller is connected with a clock signal output by the oscillator; the shift register and the combinational logic operation unit are both connected to the frequency divider, and the frequency divider is connected to a clock signal output by the oscillator; the shift register is connected with the combinational logic operation unit, and the combinational logic operation unit outputs detection enabling clock signals to the AMR and the comparator; the combined logic operation unit also outputs a sampling clock signal to the comparator; the frequency divider divides the frequency of the input oscillator clock signal and counts the frequency; the detection sampling controller detects a sampling clock duty cycle control signal; the shift register shifts and outputs the output of the frequency divider; the combination logic operation unit generates a detection enabling signal of the chip and a sampling signal which is judged to be output by the comparator.
When the AMR reluctance switch chip is applied, the clock signal output by the oscillator is a basic clock signal, the frequency divider divides and counts the basic clock signal, and the frequency division frequency is determined together according to the frequency of work-sleep-work of the AMR reluctance switch chip and the frequency of the oscillator; the detection sampling controller detects a sampling clock duty ratio control signal, which is used for setting the working time of the switch chip, and the selection of the control signal is determined by the working time of the switch chip and the frequency of the oscillator; the shift register shifts and outputs the output of the frequency divider, and the shift is controlled by the detection sampling duty ratio selection controller and the bit number of the register; the combined logic operation unit carries out logic operation on the output of the frequency divider, the output of the shift register and the signal of the detection Sampling duty ratio selection controller, and generates a detection enable EN signal of the switch chip and a comparator discrimination output Sampling signal, and under the control of the combined logic operation unit, the time sequence working mode of the switch chip is as follows: during the period of EN being high level, the chip normally works, sampling signals sample the output result of the comparator in the chip, the Sampling result is sent to the output drive of the chip, and during the period of EN being low level, the chip enters dormancy, so that the work-sleep control of devices with larger power consumption such as a magnetoresistive bridge, the comparator and the like is effectively realized, meanwhile, the time sequence control circuit has clear framework, small combined logic operation amount and difficult generation of burr signals, the duty ratio of the work-sleep-work of the chip can be flexibly adjusted, and different practical application requirements are met.
Further, the frequency divider comprises a plurality of cascaded flip-flops; the first-stage trigger receives the clock signal output by the oscillator and is connected with the detection sampling controller; the flip-flop of the final stage is connected to a shift register.
When the application is applied, the cascade (cascades) are generally a series of identical unit devices connected end to form a new logic unit, the clock signal from the oscillator is output by the flip-flop of the final stage after passing through the flip-flop of the cascade, and the number of the cascades is determined by the requirement of frequency division.
Further, the detection sampling controller comprises a control unit A and a control unit B; the control unit A comprises an inverter I1 and an inverter I2 which are connected in series; the control unit B comprises an inverter I3 and an inverter I4 which are connected in series; the input end of the inverter I1 receives a clock signal output by the oscillator, and the output end of the inverter I2 is connected with the combinational logic operation unit; the input end of the inverter I3 is connected with a frequency divider, the output end of the inverter I3 is connected with a combinational logic operation unit, and the output end of the inverter I3 is also connected with a shift register.
Further, the combinational logic operation unit comprises a two-input nor gate N1, a three-input nor gate N2, an inverter I5 and an inverter I6; the two-input nor gate N1, the inverter I5 and the inverter I6 are connected in series, the output end of the inverter I5 is connected to the third input end of the three-input nor gate N2, the first input end and the second input end of the three-input nor gate N2 are both connected to the detection sampling controller, and the output end of the three-input nor gate N2 outputs a detection enabling clock signal to the AMR and the comparator; the input end DINB of the two-input NOR gate N1 is connected with the shift register, and the input end DINB of the two-input NOR gate N1 is connected with the frequency divider; the output end of the inverter I6 outputs a sampling clock signal to the comparator.
Further, the shift register comprises a trigger DFF0, a D port of the trigger DFF0 is connected with the frequency divider, a CK port of the trigger DFF0 is connected with the detection sampling controller, and a Qb port of the trigger DFF0 is connected with the combinational logic operation unit.
A time sequence control method of a magneto-resistance type sensor chip comprises the following steps:
constructing frequency division times according to the work-sleep cycle of the controlled equipment;
constructing a control signal and a shift register according to the working period of the controlled equipment;
obtaining the working-sleeping time sequence and the sampling working time sequence of the controlled equipment according to the frequency division times, the control signals and the shift register combination;
the controlled device performs work-sleep according to a work-sleep timing; the controlled device performs sampling according to a sampling operation timing.
In the prior art, for the application of a plurality of frequency division times and a long counting period, the common time sequence control circuit has large scale of required combinational logic operation circuits, large operation amount and easy generation of burrs in the middle process. When the application is applied, the number of signals participating in the combined logic operation in the traditional design is considered to be large, and the number of times of high-low level jump of each signal in each working-sleeping period is large, so that burr signals can be generated in the combined logic operation process.
Further, constructing the frequency division number according to the work-sleep cycle of the controlled device includes: the oscillator generates a basic clock signal; the frequency divider constructs the distribution times according to the basic clock cycle corresponding to the working-sleeping cycle of the controlled equipment.
Further, constructing the control signal and the shift register according to the duty cycle of the controlled device includes: the oscillator generates a basic clock signal; the detection sampling controller constructs a control signal according to a basic clock period corresponding to the working period of the controlled equipment; and constructing a shift register according to the basic clock cycle corresponding to the working cycle of the controlled equipment.
Further, the obtaining the working-sleeping time sequence and the sampling working time sequence of the controlled device according to the frequency division times, the control signals and the shift register combination comprises the following steps: and carrying out logic operation on the frequency division times, the control signals and the shift register signals by adopting a combined logic operation unit to obtain the work-sleep time sequence and the sampling work time sequence of the controlled equipment.
Compared with the prior art, the application has the following advantages and beneficial effects:
the application relates to a time sequence control circuit and a control method of a magnetoresistive sensor chip, wherein during the period that EN is high level, a chip normally works, sampling signals sample the output result of a comparator in the chip, the Sampling result is sent to the output drive of the chip, and during the period that EN is low level, the chip enters dormancy, so that the work-sleep control of devices with larger power consumption such as a magnetoresistive bridge, the comparator and the like is effectively realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:
FIG. 1 is a schematic diagram of a prior art circuit architecture;
FIG. 2 is a schematic diagram of a circuit architecture according to the present application;
FIG. 3 is a timing diagram of signal detection in an embodiment;
FIG. 4 is a schematic diagram of a frequency divider according to an embodiment;
FIG. 5 is a schematic diagram of the control unit A in the embodiment;
FIG. 6 is a schematic diagram of a control unit B in the embodiment;
FIG. 7 is a schematic diagram of a combinational logic operation unit according to an embodiment;
FIG. 8 is a schematic diagram of a shift register according to an embodiment;
fig. 9 is a schematic circuit architecture diagram in an embodiment.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present application, the present application will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present application and the descriptions thereof are for illustrating the present application only and are not to be construed as limiting the present application.
Example 1
As shown in fig. 2, the present application provides a magnetoresistive sensor chip timing control circuit, which includes a detection sampling controller, a frequency divider, a shift register and a combinational logic operation unit; the frequency divider, the shift register and the combinational logic operation unit are all connected with the detection sampling controller, and the detection sampling controller is connected with a clock signal output by the oscillator; the shift register and the combinational logic operation unit are both connected to the frequency divider, and the frequency divider is connected to a clock signal output by the oscillator; the shift register is connected with the combinational logic operation unit, and the combinational logic operation unit outputs detection enabling clock signals to the AMR and the comparator; the combined logic operation unit also outputs a sampling clock signal to the comparator; the frequency divider divides the frequency of the input oscillator clock signal and counts the frequency; the detection sampling controller detects a sampling clock duty cycle control signal; the shift register shifts and outputs the output of the frequency divider; the combination logic operation unit generates a detection enabling signal of the chip and a sampling signal which is judged to be output by the comparator.
Fig. 1 is a schematic diagram of a conventional timing control circuit, which is large in size and operation amount, and in which burrs are easily generated in the middle process for applications with a large frequency division number and a long counting period.
When the embodiment is implemented, the clock signal output by the oscillator is a basic clock signal, the frequency divider divides and counts the basic clock signal, and the frequency division frequency is determined together according to the frequency of the work-sleep-work of the AMR reluctance switch chip and the frequency of the oscillator; the detection sampling controller detects a sampling clock duty ratio control signal, which is used for setting the working time of the switch chip, and the selection of the control signal is determined by the working time of the switch chip and the frequency of the oscillator; the shift register shifts and outputs the output of the frequency divider, and the shift is controlled by the detection sampling duty ratio selection controller and the bit number of the register; the combined logic operation unit carries out logic operation on the output of the frequency divider, the output of the shift register and the signal of the detection Sampling duty ratio selection controller, and generates a detection enable EN signal of the switch chip and a comparator discrimination output Sampling signal, and under the control of the combined logic operation unit, the time sequence working mode of the switch chip is as follows: during the period of EN being high level, the chip normally works, sampling signals sample the output result of the comparator in the chip, the Sampling result is sent to the output drive of the chip, and during the period of EN being low level, the chip enters dormancy, so that the work-sleep control of devices with larger power consumption such as a magnetoresistive bridge, the comparator and the like is effectively realized, meanwhile, the time sequence control circuit has clear framework, small combined logic operation amount and difficult generation of burr signals, the duty ratio of the work-sleep-work of the chip can be flexibly adjusted, and different practical application requirements are met.
Example 2
In this embodiment, on the basis of embodiment 1, the frequency divider includes a plurality of cascaded flip-flops; the first-stage trigger receives the clock signal output by the oscillator and is connected with the detection sampling controller; the flip-flop of the final stage is connected to a shift register.
In this embodiment, a cascade (cascade) is generally a series of identical unit devices connected end to form a new logic unit, and after a clock signal from an oscillator passes through a cascade flip-flop, the clock signal is output by a flip-flop of a final stage, and the number of cascades is determined by the requirement of frequency division.
As shown in fig. 3, in order to clarify the operation method of the control circuit, it is assumed that the operation-sleep cycle of the chip is set to 1024 basic clock cycles, wherein the operation state is 1 basic clock cycle, the sampling cycle is half basic clock cycle, and 1023 basic clock cycles thereafter, the chip is in the sleep state; as shown in fig. 4, the frequency divider needs to divide the basic clock signal from the oscillator by 1024 according to the working-sleep period of the chip, and according to the characteristics of the DFF flip-flops, the 1024 frequency division may be formed by 10 DFF flip-flops cascaded, and in this embodiment, the DFF is designed as rising edge trigger.
The clock signal CLK_IN from the oscillator is connected with the CK terminal of the first trigger DFF1, the output Qb terminal of the first trigger DFF1 is connected with the D input terminal of the first trigger DFF1, the output Q terminal of the first trigger DFF1 is connected with the input CK terminal of the second trigger DFF2, the output Qb terminal of the second trigger DFF2 is connected with the input D terminal of the second trigger DFF2, the output Q terminal of the second trigger DFF2 is connected with the input CK terminal of the third trigger DFF3, and the connection method of the follow-up triggers is similar. The output signals of the whole frequency divider are respectively Q1, Q1b, Q2, Q2b, Q3, Q3b, Q4, Q4b, Q5, Q5b, Q6, Q6b, Q7, Q7b, Q8, Q8b, Q9, Q9b, Q10 and Q10b, wherein Qnb is the inverse of Qn, and n is an integer between 1 and 10.
Example 3
In this embodiment, on the basis of embodiment 1, the detection sampling controller includes a control unit a and a control unit B; the control unit A comprises an inverter I1 and an inverter I2 which are connected in series; the control unit B comprises an inverter I3 and an inverter I4 which are connected in series; the input end of the inverter I1 receives a clock signal output by the oscillator, and the output end of the inverter I2 is connected with the combinational logic operation unit; the input end of the inverter I3 is connected with a frequency divider, the output end of the inverter I3 is connected with a combinational logic operation unit, and the output end of the inverter I3 is also connected with a shift register.
IN the implementation of this embodiment, the detection sampling controller is formed by connecting two groups of two-stage inverters IN series, and the structure is as shown IN fig. 5 and 6, the input terminal Sin0 of the control unit a is connected with the output clk_in of the oscillator, and the output terminals of the detection sampling controller are S0 and S0b (where S0b is the inverse of S0); the input terminal Sin1 of the control unit B is connected to the output Q1 of the frequency divider unit, and the output terminals of the detection sampling controller are S1 and S1B, respectively, where S1B is the inverse direction of S1.
Example 4
In this embodiment, on the basis of embodiment 1, the combinational logic operation unit includes a two-input nor gate N1, a three-input nor gate N2, an inverter I5, and an inverter I6; the two-input nor gate N1, the inverter I5 and the inverter I6 are connected in series, the output end of the inverter I5 is connected to the third input end of the three-input nor gate N2, the first input end and the second input end of the three-input nor gate N2 are both connected to the detection sampling controller, and the output end of the three-input nor gate N2 outputs a detection enabling clock signal to the AMR and the comparator; the input end DINB of the two-input NOR gate N1 is connected with the shift register, and the input end DINB of the two-input NOR gate N1 is connected with the frequency divider; the output end of the inverter I6 outputs a sampling clock signal to the comparator.
In the implementation of this embodiment, as shown in fig. 7, the combinational logic operation unit is composed of a two-input nor gate, two inverters, and a three-input nor gate, wherein the inputs of the two-input nor gate N1 are DIN and DINb terminals respectively, the output of the two-input nor gate N1 is connected to the input end of the inverter I5, the output end of the inverter I5 is connected to the input end of the inverter I6 respectively, one input end of the three-input nor gate N24 is connected to the output terminal of the inverter I6 and the other two input terminals of the three-input nor gate N2 are S0 and S1 terminals respectively, and the output terminal of the three-input nor gate I4 is Sampling.
Example 5
In this embodiment, on the basis of embodiment 1, the shift register includes a flip-flop DFF0, a D port of the flip-flop DFF0 is connected to a frequency divider, a CK port of the flip-flop DFF0 is connected to a detection sampling controller, and a Qb port of the flip-flop DFF0 is connected to a combinational logic operation unit.
In the implementation of this embodiment, the shift register is formed by flip-flop DFFs, and the structure is shown in fig. 8, and since the operating state is one basic clock cycle, one DFF is selected as the register. The D input terminal of the DFF trigger is the data input terminal DIN of the shift register, the output Q terminal of the DFF trigger is the DOUT terminal of the shift register, and the output Qb terminal of the DFF trigger is the DOUTb terminal of the shift register.
Example 6
IN this embodiment, as shown IN fig. 9, based on embodiments 1 to 5, fig. 9 is a schematic circuit diagram, an oscillator clk_in signal is connected to a clk_in terminal of a frequency divider, the oscillator clk_in signal is connected to a Sin0 terminal of a detection sampling controller I1, an output Q1 terminal of the frequency divider is connected to a Sin1 terminal of a detection sampling controller I3, an output Q10 terminal of the frequency divider is connected to a DIN terminal of a shift register, an output Q10 terminal of the frequency divider is connected to a DIN terminal of a combinational logic unit N1, an S0b terminal of a detection sampling controller I2 is connected to an S0 terminal of a combinational logic operation unit N2, an S1 terminal of a detection sampling controller I4 is connected to an S1 terminal of a combinational logic operation unit N2, and an output DOUTb terminal of the shift register is connected to a DINb terminal of the combinational logic operation unit N1. The output EN terminal of the combination logic operation unit I6 is a detection enable EN signal of the switch chip, and the output Sampling terminal of the combination logic operation unit N2 is a Sampling signal of the switch chip.
Example 7
The application discloses a time sequence control method of a magneto-resistance type sensor chip, which comprises the following steps: constructing frequency division times according to the work-sleep cycle of the controlled equipment; constructing a control signal and a shift register according to the working period of the controlled equipment; obtaining the working-sleeping time sequence and the sampling working time sequence of the controlled equipment according to the frequency division times, the control signals and the shift register combination; the controlled device performs work-sleep according to a work-sleep timing; the controlled device performs sampling according to a sampling operation timing.
Further, constructing the control signal and the shift register according to the duty cycle of the controlled device includes: the oscillator generates a basic clock signal; the detection sampling controller constructs a control signal according to a basic clock period corresponding to the working period of the controlled equipment; and constructing a shift register according to the basic clock cycle corresponding to the working cycle of the controlled equipment.
Further, the obtaining the working-sleeping time sequence and the sampling working time sequence of the controlled device according to the frequency division times, the control signals and the shift register combination comprises the following steps: and carrying out logic operation on the frequency division times, the control signals and the shift register signals by adopting a combined logic operation unit to obtain the work-sleep time sequence and the sampling work time sequence of the controlled equipment.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the application, and is not meant to limit the scope of the application, but to limit the application to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the application are intended to be included within the scope of the application.
Claims (7)
1. The magnetic resistance type sensor chip time sequence control circuit is characterized by comprising a detection sampling controller, a frequency divider, a shift register and a combination logic operation unit; the frequency divider, the shift register and the combinational logic operation unit are all connected with the detection sampling controller, and the detection sampling controller is connected with a clock signal output by the oscillator; the shift register and the combinational logic operation unit are both connected to the frequency divider, and the frequency divider is connected to a clock signal output by the oscillator; the shift register is connected with the combinational logic operation unit, and the combinational logic operation unit outputs detection enabling clock signals to the AMR and the comparator; the combined logic operation unit also outputs a sampling clock signal to the comparator;
the frequency divider divides the frequency of the input oscillator clock signal and counts the frequency;
the detection sampling controller detects a sampling clock duty cycle control signal;
the shift register shifts and outputs the output of the frequency divider;
the combined logic operation unit generates a detection enabling signal of the chip and a sampling signal which is judged to be output by the comparator;
the combined logic operation unit comprises a two-input NOR gate N1, a three-input NOR gate N2, an inverter I5 and an inverter I6; the two-input nor gate N1, the inverter I5 and the inverter I6 are connected in series, the output end of the inverter I5 is connected to the third input end of the three-input nor gate N2, the first input end and the second input end of the three-input nor gate N2 are both connected to the detection sampling controller, and the output end of the three-input nor gate N2 outputs a detection enabling clock signal to the AMR and the comparator; the input end DINB of the two-input NOR gate N1 is connected with the shift register, and the input end DINB of the two-input NOR gate N1 is connected with the frequency divider; the output end of the inverter I6 outputs a sampling clock signal to the comparator;
the shift register comprises a trigger DFF0, a D port of the trigger DFF0 is connected with a frequency divider, a CK port of the trigger DFF0 is connected with a detection sampling controller, and a Qb port of the trigger DFF0 is connected with a combinational logic operation unit.
2. The magnetoresistive sensor chip timing control circuit of claim 1 wherein the frequency divider comprises a plurality of cascaded flip-flops; the first-stage trigger receives the clock signal output by the oscillator and is connected with the detection sampling controller; the flip-flop of the final stage is connected to a shift register.
3. The magnetoresistive sensor chip timing control circuit of claim 1 wherein the sense sample controller comprises a control unit a and a control unit B; the control unit A comprises an inverter I1 and an inverter I2 which are connected in series; the control unit B comprises an inverter I3 and an inverter I4 which are connected in series; the input end of the inverter I1 receives a clock signal output by the oscillator, and the output end of the inverter I2 is connected with the combinational logic operation unit; the input end of the inverter I3 is connected with a frequency divider, the output end of the inverter I3 is connected with a combinational logic operation unit, and the output end of the inverter I3 is also connected with a shift register.
4. A magnetoresistive sensor chip timing control method employing a magnetoresistive sensor chip timing control circuit according to any of claims 1 to 3, characterized by comprising:
constructing frequency division times according to the work-sleep cycle of the controlled equipment;
constructing a control signal and a shift register according to the working period of the controlled equipment;
obtaining the working-sleeping time sequence and the sampling working time sequence of the controlled equipment according to the frequency division times, the control signals and the shift register combination;
the controlled device performs work-sleep according to a work-sleep timing; the controlled device performs sampling according to a sampling operation timing.
5. The method of claim 4, wherein constructing the frequency division number according to the operation-sleep cycle of the controlled device comprises:
the oscillator generates a basic clock signal;
the frequency divider constructs the distribution times according to the basic clock cycle corresponding to the working-sleeping cycle of the controlled equipment.
6. The method of claim 4, wherein constructing the control signal and the shift register according to the duty cycle of the controlled device comprises:
the detection sampling controller constructs a control signal according to a basic clock period corresponding to the working period of the controlled equipment;
and constructing a shift register according to the basic clock cycle corresponding to the working cycle of the controlled equipment.
7. The method of claim 4, wherein deriving the operation-sleep and sampling operation timings of the controlled apparatus based on the frequency division times, the control signal, and the shift register combination comprises: and carrying out logic operation on the frequency division times, the control signals and the shift register signals by adopting a combined logic operation unit to obtain the work-sleep time sequence and the sampling work time sequence of the controlled equipment.
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| CN112857401B (en) * | 2021-02-15 | 2023-03-31 | 北京瑞尔天天科技有限公司 | High-precision and high-stability frequency scale circuit |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4360788A (en) * | 1980-07-14 | 1982-11-23 | John Fluke Mfg. Co., Inc. | Phase-locked loop frequency synthesizer |
| US4442513A (en) * | 1982-02-05 | 1984-04-10 | The Bendix Corporation | Sonar transceiver system and method |
| US6182237B1 (en) * | 1998-08-31 | 2001-01-30 | International Business Machines Corporation | System and method for detecting phase errors in asics with multiple clock frequencies |
| CN202309908U (en) * | 2011-06-23 | 2012-07-04 | 中国科学院西安光学精密机械研究所 | CCD control circuit based on FPGA |
| CN103063232A (en) * | 2011-10-21 | 2013-04-24 | 上海腾怡半导体有限公司 | One-chip latch type Hall sensor |
| CN104989663A (en) * | 2015-08-07 | 2015-10-21 | 成都芯进电子有限公司 | DC brushless fan driving chip with rotary speed controlled by voltage |
| CN105932998A (en) * | 2016-04-18 | 2016-09-07 | 宁波大学 | Glitch-type PUF circuit employing delay tree structure |
| CN107835021A (en) * | 2017-11-24 | 2018-03-23 | 西安交通大学 | A kind of asynchronous sequential control circuit of Variable delay and control method |
| CN108155897A (en) * | 2017-12-12 | 2018-06-12 | 上海灿瑞科技股份有限公司 | A kind of low power consumption switch Hall sensor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1244214A1 (en) * | 2001-03-23 | 2002-09-25 | STMicroelectronics Limited | Phase control digital frequency divider |
-
2019
- 2019-02-25 CN CN201910137613.2A patent/CN109765828B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4360788A (en) * | 1980-07-14 | 1982-11-23 | John Fluke Mfg. Co., Inc. | Phase-locked loop frequency synthesizer |
| US4442513A (en) * | 1982-02-05 | 1984-04-10 | The Bendix Corporation | Sonar transceiver system and method |
| US6182237B1 (en) * | 1998-08-31 | 2001-01-30 | International Business Machines Corporation | System and method for detecting phase errors in asics with multiple clock frequencies |
| CN202309908U (en) * | 2011-06-23 | 2012-07-04 | 中国科学院西安光学精密机械研究所 | CCD control circuit based on FPGA |
| CN103063232A (en) * | 2011-10-21 | 2013-04-24 | 上海腾怡半导体有限公司 | One-chip latch type Hall sensor |
| CN104989663A (en) * | 2015-08-07 | 2015-10-21 | 成都芯进电子有限公司 | DC brushless fan driving chip with rotary speed controlled by voltage |
| CN105932998A (en) * | 2016-04-18 | 2016-09-07 | 宁波大学 | Glitch-type PUF circuit employing delay tree structure |
| CN107835021A (en) * | 2017-11-24 | 2018-03-23 | 西安交通大学 | A kind of asynchronous sequential control circuit of Variable delay and control method |
| CN108155897A (en) * | 2017-12-12 | 2018-06-12 | 上海灿瑞科技股份有限公司 | A kind of low power consumption switch Hall sensor |
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