CN109698687B - Magnetic signal detection time sequence control circuit and control method - Google Patents
Magnetic signal detection time sequence control circuit and control method Download PDFInfo
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Abstract
The invention discloses a magnetic signal detection time sequence control circuit, which comprises a sequential pulse generator, a clock signal counting circuit and a magnetic signal detection circuit, wherein the sequential pulse generator is used for counting the clock signal frequency division and generating a group of sequential pulse signals; the non-overlapping clock generator generates a control signal of a Hall plate orthogonal current method and sends the control signal to the Hall plate and the logic operation unit; the logic operation unit generates a detection enable EN signal and sends the detection enable EN signal to the chopper amplifier and the comparator, and generates a selection signal EN_REF and sends the selection signal EN_REF to the chopper amplifier reference voltage; when the detection enable EN signal is at a high level, the Hall switch chip is placed in a working state; when the detection enable EN signal is at a low level, the hall switch chip is put to sleep. The invention also discloses a magnetic signal detection time sequence control method. According to the magnetic signal detection time sequence control circuit and the magnetic signal detection time sequence control method, when the magnetic switch chip detects magnetic signals, the polarities of magnetic fields are not distinguished, the installation of magnets is convenient, and the chip adopts a periodic working-sleeping mode, so that the power consumption of a system is effectively reduced.
Description
Technical Field
The invention relates to the field of sensor control circuits, in particular to a magnetic signal detection time sequence control circuit and a control method.
Background
The hall switch chip is a magnetic field sensor manufactured according to the hall effect. In 1879, when the conduction mechanism of metal is studied, it is found that when an externally applied magnetic field passes perpendicularly to the current direction of the conductor, carriers deflect, and an additional electric field is generated perpendicularly to the current and magnetic field, so that a potential difference is generated across the conductor, which is also called hall effect. Later, the hall effect of semiconductors was found to be much stronger than that of metals, and hall sensors fabricated using this phenomenon have found wide application.
Since the hall voltage obtained by the hall element in the hall switch chip is very weak, if the offset voltage of the hall element and the hall voltage are not greatly different, the whole performance of the chip can be seriously affected, and even the hall switch chip can be disabled. Therefore, eliminating offset voltage is a problem that must be considered and addressed in designing hall elements. In addition, the hall switch chip is used for detecting the existence or non-existence of a magnetic field, and real-time detection is not necessary as long as the response is sensitive.
In the prior art, the Hall switch chip usually works continuously for a long time, so that the power consumption of the whole equipment is improved, and the service life of the Hall switch chip is further shortened.
Disclosure of Invention
The invention aims to provide a magnetic signal detection time sequence control circuit and a magnetic signal detection time sequence control method, which solve the problems.
The invention is realized by the following technical scheme:
a magnetic signal detection time sequence control circuit comprises a sequential pulse generator, a non-overlapping clock generator and a logic operation unit which are connected in sequence; the sequential pulse generator is connected with the logic operation unit; the non-overlapping clock generator is connected with the Hall slice, and the logic operation unit is connected with the chopper amplifier, the reference voltage and the sampling pulse; the sequential pulse generator is connected with a clock signal output by the oscillator, counts the clock signal in a frequency dividing way and generates a group of sequential pulse signals; the non-overlapping clock generator receives the sequential pulse signals, generates control signals of a Hall plate quadrature current method and sends the control signals to the Hall plate and the logic operation unit; the logic operation unit receives the sequential pulse signals, the clock signals output by the oscillator and the control signals generated by the non-overlapping clock generator, generates a detection enable EN signal and sends the detection enable EN signal to the chopper amplifier and the comparator, and generates a selection signal EN_REF and sends the selection signal EN_REF to the chopper amplifier reference voltage; the logic operation unit also outputs a sampling pulse signal which is judged and output by the comparator; when the detection enable EN signal is at a high level, the Hall switch chip is placed in a working state; when the detection enable EN signal is at a low level, the hall switch chip is put to sleep.
When the invention is applied, the invention is mainly applied to control devices such as a Hall switch chip and a chopper amplifier, a reference voltage, a comparator and the like matched with the Hall switch chip, the oscillator generates a standard clock signal, the sequential pulse generator counts the frequency division of the standard clock signal and generates a group of sequential pulse signals, wherein the group of sequential pulse signals refer to a group of pulse signals with time sequence, and the sequential pulse signals can be used for carrying out subsequent generation of various control signals; and after receiving the sequential pulse signals, the non-overlapping clock generator performs a series of logic operations on the sequential pulse signals to generate control signals of a Hall plate orthogonal current method, wherein the two control signals generated by the orthogonal current method are mutually orthogonal, and under the action of the control signals of the Hall plate orthogonal current method, the direction of a Hall plate detection magnetic field is periodically changed.
The logic operation unit generates a detection enable EN signal, the detection enable EN signal is used for carrying out work-sleep control on the Hall switch chip and the matched device thereof, and when the detection enable EN signal is at a high level, the Hall switch chip is placed in a working state; when the detection enable EN signal is at a low level, the hall switch chip is put to sleep. And the selection signal en_ref generated by the logic operation unit is used for controlling sampling control of the chopper amplifier reference voltage. The comparator output by the logic operation unit judges and outputs a sampling pulse signal to be used for sampling the output result of the comparator, and because the control signal generated by the orthogonal current method is adopted to carry out alternating control on the Hall plate, the sampling of the two directions of the Hall plate detection magnetic field can be realized in the one-time electrifying working process, and the Hall switch chip is sleeped through the detection enable EN signal after the sampling is finished, so that the polarity of the magnetic field is not distinguished when the magnetic switch chip detects the magnetic signal, the installation of a magnet is convenient, and the chip adopts a periodic working-sleeping mode, thereby effectively reducing the power consumption of the system.
Further, the hall chip quadrature current method control signal generated by the non-overlapping clock generator is two paths of signals: CTR1 and CTR2; during the detection of the enable EN signal, the CTR1 and CTR2 are high level non-overlapping clocks; the comparator output by the logic operation unit judges that the output sampling pulse signals are three paths: SH1, SH2, and sh_out; taking five continuous periods in a clock signal output by the oscillator as a working cycle, wherein the working cycle comprises a continuous T1 period, a continuous T2 period, a continuous T3 period, a continuous T4 period and a continuous T5 period; during the periods T1 and T3, the EN signal, the EN_REF signal, the SH1 signal, the SH2 signal and the SH_OUT signal are high; in the period T2, the EN signal, the SH2 signal, and the sh_out signal are at high level, and the en_ref signal and the SH1 signal are at low level; in the period T4, the EN signal, SH1 signal and sh_out signal are at high level, and the en_ref signal and SH2 signal are at low level; in the T5 period, the SH1 signal and the SH2 signal are high, and the EN signal, the en_ref signal, and the sh_out signal are low.
When the invention is applied, CTR1 and CTR2 are high-level non-overlapping clocks, so that CTR1 and CTR2 cannot generate high level at the same time, the situation that two input ends of a Hall piece are simultaneously connected with high level is avoided, and the use safety of the Hall piece is ensured; during the working process:
In the period of T1, CTR1 is at high level, CTR2 is at low level, the detected magnetic field is in one direction, such as N/S direction, and the electric signal generated on the Hall plate is sampled for the first time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the first time;
in the period of T2, CTR1 is at low level, and part of time sequence of CTR2 is at high level, at the moment, the detected magnetic field direction is the same as the moment of T1, for example, the N/S direction, the first sampling is continuously carried out on the electric signal generated on the Hall chip, meanwhile, the EN_REF signal is at low level, and the sampling of the reference voltage is closed; sampling the result of the comparator by the rising edge of SH1, and sending the result to a first register;
in the period of T3, CTR1 is at low level, and part of the time sequence of CTR2 is at high level, because the waveform relationship of CTR2 and CTR1 changes, the detected magnetic field direction is opposite to the time of T1, for example, the S/N direction, and the electric signal generated on the Hall plate is sampled for the second time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the second time;
CTR1 is in high level and CTR2 is in low level in the period T4, the detected magnetic field direction is opposite to the moment T1, for example, the S/N direction, the electric signal generated on the Hall plate is continuously sampled for the second time, meanwhile, the EN_REF signal is in low level, and the reference voltage sampling is closed; sampling the result of the comparator by the rising edge of SH2, and sending the result to the second register;
And the EN signal is at a low level in the T5 period, the Hall switch chip is closed, the result in the second register is finally sampled by the rising edge of SH_OUT, and the output result is sent to the output driver. The end of this one working cycle, the sleep is entered until the next working cycle.
The application further realizes the detection of the magnetic fields in two directions of the Hall piece through the design of the time sequence, and the Hall piece enters sleep after the working cycle is finished, thereby reducing the power consumption.
Further, the sequential pulse generator comprises a single pulse generator and a plurality of cascaded flip-flops; the cascading mode of the plurality of cascaded triggers is that the D end of each stage of trigger is connected with the Q end of the previous stage of trigger until the first stage of trigger; the D end of the first-stage trigger is connected with the output end of the single pulse generator, and the input end of the single pulse generator and the CK ends of all the triggers are connected with clock signals output by the oscillator; the output signals of the output ends of the single pulse generator and the output signals of the Q ends of all the triggers form a group of sequential pulse signals.
In order to generate a set of sequential pulse signals, the present application is designed to generate sequential pulse signals.
Further, the sequential pulse generator generates a set of sequential pulse signals Q1, Q2, Q3, Q4; the non-overlapping clock generator comprises an inverter I1, a buffer I2, a NAND gate I3, an inverter I4, a buffer I5, a NOR gate I6, an inverter I7, an inverter I8, a buffer I9, a NAND gate I10, an inverter I11, a buffer I12, a NOR gate I13 and an inverter I14 which are sequentially connected, wherein the output end of the inverter I14 is connected with the input end of the inverter I1; the output end of the buffer I2 is connected with one input end of the NAND gate I3, the other input end of the NAND gate I3 is connected with the pulse signal Q2, and the output end of the NAND gate I3 is connected with the input end of the inverter I4; the output end of the buffer I5 is connected with one input end of the NOR gate I6, the other input end of the NOR gate I6 is connected with the pulse signal Q3, and the output end of the NOR gate I6 is connected with the input end of the inverter I7; the output end of the buffer I9 is connected with one input end of the NAND gate I10, the other input end of the NAND gate I10 is connected with the pulse signal Q4, and the output end of the NAND gate I10 is connected with the input end of the inverter I11; the output end of the buffer I12 is connected with one input end of the NOR gate I13, the other input end of the NOR gate I13 is connected with the pulse signal Q1, and the output end of the NOR gate I13 is connected with the input end of the inverter I14; the input end of the inverter I7 outputs a CTR1 signal, and the input end of the inverter I14 outputs a CTR2 signal.
When the invention is applied, in order to realize the CTR1 and CTR2 signals which are of orthogonal current method and are of high level and not overlapped with each other, the invention makes the structural design, and creatively introduces a plurality of groups of structures formed by serially connecting inverters and buffers into the structure, thereby finally achieving the purpose of the required CTR1 and CTR2 signals.
Further, the sequential pulse generator generates a set of sequential pulse signals Q0, Q1, Q2, Q3, Q4, Q5; the logic operation unit comprises a four-input NOR gate L1, an inverter L2, an inverting buffer L3, a NOR gate L4, an inverter L5, a trigger L6, a NOR gate L7 and an inverter L8 which are sequentially connected; the four input ends of the four-input NOR gate L1 are respectively connected with a Q0 signal, a Q1 signal, a Q2 signal and a Q3 signal, and the output end of the four-input NOR gate L1 is connected with the input end of the inverter L2; one input end of the nor gate L4 is connected with the output end of the inverter L2, the other input end of the nor gate L4 is connected with the output end of the inverting buffer L3, the output end of the inverter L2 is connected with the input end of the inverting buffer L3, the output end of the nor gate L4 is connected with the D end of the trigger L6, and the CK end of the trigger L6 is connected with the clock signal output by the oscillator; the Q end of the trigger L6 is connected with one input end of the NOR gate L7, the other input end of the NOR gate L7 is connected with a CTR2 signal, the output end of the NOR gate L7 is connected with the input end of the inverter L8, and the output end of the inverter L8 outputs a detection enable EN signal; the logic operation unit further comprises a NOR gate L9, an inverter L10, an inverter L11, an inverter L12 and an inverter L13; one input end of the NOR gate L9 is connected with a Q1 signal, and the other input end of the NOR gate L9 is connected with a Q3 signal; the output end of the NOR gate L9 is connected with the input end of the inverter L10, and the output end of the inverter L10 outputs a selection signal EN_REF; the input end of the inverter L11 is connected with a Q2 signal, and the output end of the inverter L11 outputs an SH1 signal; the input end of the inverter L12 is connected with a Q4 signal, and the output end of the inverter L12 outputs an SH2 signal; the input end of the inverter L13 is connected with the Q5 signal, and the output end of the inverter L13 outputs the SH_OUT signal.
When the invention is applied, the design of the logic operation unit is an important component of the invention, and the output signal of the logic operation unit is not only controlled by a chip, but also needs to output sampling pulse, so the invention makes the above digital circuit structural design, and can achieve the required effect by carrying out multiple logic operations on the pulse signal.
A magnetic signal detection time sequence control method comprises the following steps: generating a group of sequential pulse signals according to the standard clock signal; generating control signals CTR1 and CTR2 of a Hall plate orthogonal current method according to the sequential pulse signals, wherein the CTR1 and CTR2 are used as two-phase orthogonal switch signals for controlling the Hall element; taking a plurality of continuous periods in a clock signal output by the oscillator as a working cycle, wherein CTR1 is high level at least twice in the working cycle; in one working cycle, the electric signal generated on the Hall plate is sampled at least twice, and each sampling at least comprises a high level of CTR1 once; the hall switch chip is put to sleep for one or more cycles at the end of one duty cycle until the next duty cycle.
When the invention is applied, the invention is mainly applied to control the Hall switch chip and devices such as chopper amplifier, reference voltage, comparator and the like matched with the Hall switch chip. In the invention, a control signal generated by an orthogonal current method is adopted to carry out alternating control on the Hall plate, and CTR1 has high level at least twice in one working cycle; in a duty cycle, carry out at least twice to the signal of telecommunication that produces on the hall piece, and at least once the high level of CTR1 is included in the sampling each time, just so just can realize in the sampling that just can all sample the two directions of hall piece detection magnetic field in a circular telegram working process, through detecting enabling EN signal with hall switch chip sleep after accomplishing the sampling, thereby the polarity of magnetic field is not distinguished when magnetic switch chip detects the magnetic signal, the installation of magnet is convenient, and the chip adopts periodic work-sleep mode, effectively reduce the consumption of system.
Further, the period of the sequential pulse signal is obtained according to the number of basic clock periods contained in the working-sleeping period of the Hall switch chip; the width of the sequential pulse signal is obtained according to the number of basic clock cycles contained in the sampling time of the Hall switch chip.
Further, five continuous periods in the clock signal output by the oscillator are taken as one working cycle, and the working cycle comprises a continuous period T1, a continuous period T2, a continuous period T3, a continuous period T4 and a continuous period T5; the electric signal and the reference voltage signal generated on the Hall plate in the T1 period are sampled for the first time respectively; sampling an electric signal generated on the Hall plate in a T2 period, closing sampling of a reference voltage, sampling a result of the comparator in the T2 period, and sending the result to a first register; respectively sampling the electric signal and the reference voltage signal generated on the Hall plate for the second time in the period of T3; sampling an electric signal generated on the Hall plate in a T4 period, closing sampling of a reference voltage, sampling a result of the comparator, and sending the result to the second register; and finally sampling the result in the second register in the period T5, and outputting the result to an output driver.
When the invention is applied, in the working process:
in the period of T1, CTR1 is at high level, CTR2 is at low level, the detected magnetic field is in one direction, such as N/S direction, and the electric signal generated on the Hall plate is sampled for the first time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the first time;
in the period of T2, CTR1 is at low level, and part of time sequence of CTR2 is at high level, at the moment, the detected magnetic field direction is the same as the moment of T1, for example, the N/S direction, the first sampling is continuously carried out on the electric signal generated on the Hall chip, meanwhile, the EN_REF signal is at low level, and the sampling of the reference voltage is closed; sampling the result of the comparator by the rising edge of SH1, and sending the result to a first register;
in the period of T3, CTR1 is at low level, and part of the time sequence of CTR2 is at high level, because the waveform relationship of CTR2 and CTR1 changes, the detected magnetic field direction is opposite to the time of T1, for example, the S/N direction, and the electric signal generated on the Hall plate is sampled for the second time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the second time;
CTR1 is in high level and CTR2 is in low level in the period T4, the detected magnetic field direction is opposite to the moment T1, for example, the S/N direction, the electric signal generated on the Hall plate is continuously sampled for the second time, meanwhile, the EN_REF signal is in low level, and the reference voltage sampling is closed; sampling the result of the comparator by the rising edge of SH2, and sending the result to the second register;
And the EN signal is at a low level in the T5 period, the Hall switch chip is closed, the result in the second register is finally sampled by the rising edge of SH_OUT, and the output result is sent to the output driver. The end of this one working cycle, the sleep is entered until the next working cycle.
Further, the detection enabling signal of the Hall switch chip is an EN signal, and the EN signal is obtained according to the sequential pulse signals; when the EN signal is high, the Hall switch chip is in a working state; when the EN signal is high, the hall switch chip is put to sleep.
Further, the clocks are not overlapped when CTR1 and CTR2 are high during the EN signal high level.
When the invention is applied, CTR1 and CTR2 are high-level non-overlapping clocks, so that CTR1 and CTR2 cannot be high-level at the same time, the situation that two input ends of a Hall piece are simultaneously connected with high level is avoided, and the use safety of the Hall piece and the accuracy of magnetic field detection are ensured.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the magnetic signal detection time sequence control circuit and the control method, the two directions of the Hall piece detection magnetic field can be sampled in the process of one-time electrifying operation, and the Hall switch chip is sleepy through detecting the enable EN signal after the sampling is completed, so that the polarity of the magnetic field is not distinguished when the magnetic switch chip detects the magnetic signal, the installation of a magnet is facilitated, and the chip adopts a periodic working-sleeping mode, so that the power consumption of a system is effectively reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:
FIG. 1 is a schematic diagram of the present application applied to a Hall switch chip;
FIG. 2 is a schematic diagram of a chip timing control circuit according to the present application;
FIG. 3 is a schematic diagram of the structure of the present application;
FIG. 4 is a schematic diagram of a sequential pulse generator according to the present application;
FIG. 5 is a schematic diagram of a non-overlapping clock generator according to the present application;
FIG. 6 is a schematic diagram of a logic unit according to the present application;
FIG. 7 is a waveform diagram of the operation timing of the chip of the present application;
FIG. 8 is a waveform diagram of a sequential pulse sequence in accordance with the present application;
FIG. 9 is a diagram of non-overlapping clock waveforms in accordance with the present application.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present application, the present application will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present application and the descriptions thereof are for illustrating the present application only and are not to be construed as limiting the present application.
Example 1
As shown in fig. 1 to 3, the magnetic signal detection timing control circuit of the present application includes a sequential pulse generator, a non-overlapping clock generator and a logic operation unit which are sequentially connected; the sequential pulse generator is connected with the logic operation unit; the non-overlapping clock generator is connected with the Hall slice, and the logic operation unit is connected with the chopper amplifier, the reference voltage and the sampling pulse; the sequential pulse generator is connected with a clock signal output by the oscillator, counts the clock signal in a frequency dividing way and generates a group of sequential pulse signals; the non-overlapping clock generator receives the sequential pulse signals, generates control signals of a Hall plate quadrature current method and sends the control signals to the Hall plate and the logic operation unit; the logic operation unit receives the sequential pulse signals, the clock signals output by the oscillator and the control signals generated by the non-overlapping clock generator, generates a detection enable EN signal and sends the detection enable EN signal to the chopper amplifier and the comparator, and generates a selection signal EN_REF and sends the selection signal EN_REF to the chopper amplifier reference voltage; the logic operation unit also outputs a sampling pulse signal which is judged and output by the comparator; when the detection enable EN signal is at a high level, the Hall switch chip is placed in a working state; when the detection enable EN signal is at a low level, the hall switch chip is put to sleep.
When the embodiment is implemented, the invention is mainly applied to control devices such as a Hall switch chip and a chopper amplifier, a reference voltage, a comparator and the like matched with the Hall switch chip, the oscillator generates a standard clock signal, the sequential pulse generator counts the frequency division of the standard clock signal and generates a group of sequential pulse signals, wherein the group of sequential pulse signals refer to a group of pulse signals with time sequence, and the sequential pulse signals can be used for carrying out subsequent generation of various control signals; and after receiving the sequential pulse signals, the non-overlapping clock generator performs a series of logic operations on the sequential pulse signals to generate control signals of a Hall plate orthogonal current method, wherein the two control signals generated by the orthogonal current method are mutually orthogonal, and under the action of the control signals of the Hall plate orthogonal current method, the direction of a Hall plate detection magnetic field is periodically changed.
The logic operation unit generates a detection enable EN signal, the detection enable EN signal is used for carrying out work-sleep control on the Hall switch chip and the matched device thereof, and when the detection enable EN signal is at a high level, the Hall switch chip is placed in a working state; when the detection enable EN signal is at a low level, the hall switch chip is put to sleep. And the selection signal en_ref generated by the logic operation unit is used for controlling sampling control of the chopper amplifier reference voltage. The comparator output by the logic operation unit judges and outputs a sampling pulse signal to be used for sampling the output result of the comparator, and because the control signal generated by the orthogonal current method is adopted to carry out alternating control on the Hall plate, the sampling of the two directions of the Hall plate detection magnetic field can be realized in the one-time electrifying working process, and the Hall switch chip is sleeped through the detection enable EN signal after the sampling is finished, so that the polarity of the magnetic field is not distinguished when the magnetic switch chip detects the magnetic signal, the installation of a magnet is convenient, and the chip adopts a periodic working-sleeping mode, thereby effectively reducing the power consumption of the system.
Example 2
As shown in fig. 7 to 9, in this embodiment, based on embodiment 1, the hall chip quadrature current method control signal generated by the non-overlapping clock generator is two signals: CTR1 and CTR2; during the detection of the enable EN signal, the CTR1 and CTR2 are high level non-overlapping clocks; the comparator output by the logic operation unit judges that the output sampling pulse signals are three paths: SH1, SH2, and sh_out; taking five continuous periods in a clock signal output by the oscillator as a working cycle, wherein the working cycle comprises a continuous T1 period, a continuous T2 period, a continuous T3 period, a continuous T4 period and a continuous T5 period; during the periods T1 and T3, the EN signal, the EN_REF signal, the SH1 signal, the SH2 signal and the SH_OUT signal are high; in the period T2, the EN signal, the SH2 signal, and the sh_out signal are at high level, and the en_ref signal and the SH1 signal are at low level; in the period T4, the EN signal, SH1 signal and sh_out signal are at high level, and the en_ref signal and SH2 signal are at low level; in the T5 period, the SH1 signal and the SH2 signal are high, and the EN signal, the en_ref signal, and the sh_out signal are low.
When the embodiment is implemented, CTR1 and CTR2 are high-level non-overlapping clocks, so that CTR1 and CTR2 cannot be high-level at the same time, the situation that two input ends of a Hall piece are simultaneously connected with high-level is avoided, and the use safety of the Hall piece is ensured; during the working process:
In the period of T1, CTR1 is at high level, CTR2 is at low level, the detected magnetic field is in one direction, such as N/S direction, and the electric signal generated on the Hall plate is sampled for the first time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the first time;
in the period of T2, CTR1 is at low level, and part of time sequence of CTR2 is at high level, at the moment, the detected magnetic field direction is the same as the moment of T1, for example, the N/S direction, the first sampling is continuously carried out on the electric signal generated on the Hall chip, meanwhile, the EN_REF signal is at low level, and the sampling of the reference voltage is closed; sampling the result of the comparator by the rising edge of SH1, and sending the result to a first register;
in the period of T3, CTR1 is at low level, and part of the time sequence of CTR2 is at high level, because the waveform relationship of CTR2 and CTR1 changes, the detected magnetic field direction is opposite to the time of T1, for example, the S/N direction, and the electric signal generated on the Hall plate is sampled for the second time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the second time;
CTR1 is in high level and CTR2 is in low level in the period T4, the detected magnetic field direction is opposite to the moment T1, for example, the S/N direction, the electric signal generated on the Hall plate is continuously sampled for the second time, meanwhile, the EN_REF signal is in low level, and the reference voltage sampling is closed; sampling the result of the comparator by the rising edge of SH2, and sending the result to the second register;
And the EN signal is at a low level in the T5 period, the Hall switch chip is closed, the result in the second register is finally sampled by the rising edge of SH_OUT, and the output result is sent to the output driver. The end of this one working cycle, the sleep is entered until the next working cycle.
The application further realizes the detection of the magnetic fields in two directions of the Hall piece through the design of the time sequence, and the Hall piece enters sleep after the working cycle is finished, thereby reducing the power consumption.
Example 3
As shown in fig. 4, the present embodiment is based on embodiment 2, wherein the sequential pulse generator includes a single pulse generator and a plurality of flip-flops in cascade; the cascading mode of the plurality of cascaded triggers is that the D end of each stage of trigger is connected with the Q end of the previous stage of trigger until the first stage of trigger; the D end of the first-stage trigger is connected with the output end of the single pulse generator, and the input end of the single pulse generator and the CK ends of all the triggers are connected with clock signals output by the oscillator; the output signals of the output ends of the single pulse generator and the output signals of the Q ends of all the triggers form a group of sequential pulse signals.
In order to generate a set of sequential pulse signals, the present application implements such a digital circuit architecture designed to generate sequential pulse signals.
Example 4
As shown in fig. 5, the present embodiment is based on embodiment 2, in which the sequential pulse generator generates a set of sequential pulse signals Q1, Q2, Q3, Q4; the non-overlapping clock generator comprises an inverter I1, a buffer I2, a NAND gate I3, an inverter I4, a buffer I5, a NOR gate I6, an inverter I7, an inverter I8, a buffer I9, a NAND gate I10, an inverter I11, a buffer I12, a NOR gate I13 and an inverter I14 which are sequentially connected, wherein the output end of the inverter I14 is connected with the input end of the inverter I1; the output end of the buffer I2 is connected with one input end of the NAND gate I3, the other input end of the NAND gate I3 is connected with the pulse signal Q2, and the output end of the NAND gate I3 is connected with the input end of the inverter I4; the output end of the buffer I5 is connected with one input end of the NOR gate I6, the other input end of the NOR gate I6 is connected with the pulse signal Q3, and the output end of the NOR gate I6 is connected with the input end of the inverter I7; the output end of the buffer I9 is connected with one input end of the NAND gate I10, the other input end of the NAND gate I10 is connected with the pulse signal Q4, and the output end of the NAND gate I10 is connected with the input end of the inverter I11; the output end of the buffer I12 is connected with one input end of the NOR gate I13, the other input end of the NOR gate I13 is connected with the pulse signal Q1, and the output end of the NOR gate I13 is connected with the input end of the inverter I14; the input end of the inverter I7 outputs a CTR1 signal, and the input end of the inverter I14 outputs a CTR2 signal.
In order to realize the CTR1 and CTR2 signals which are orthogonal current method and have high level and do not overlap clocks, the invention makes the structural design, creatively introduces a plurality of groups of structures formed by serially connecting inverters and buffers into the structure, and finally achieves the purpose of the required CTR1 and CTR2 signals.
Example 5
As shown in fig. 6, the present embodiment is based on embodiment 2, in which the sequential pulse generator generates a set of sequential pulse signals Q0, Q1, Q2, Q3, Q4, Q5; the logic operation unit comprises a four-input NOR gate L1, an inverter L2, an inverting buffer L3, a NOR gate L4, an inverter L5, a trigger L6, a NOR gate L7 and an inverter L8 which are sequentially connected; the four input ends of the four-input NOR gate L1 are respectively connected with a Q0 signal, a Q1 signal, a Q2 signal and a Q3 signal, and the output end of the four-input NOR gate L1 is connected with the input end of the inverter L2; one input end of the nor gate L4 is connected with the output end of the inverter L2, the other input end of the nor gate L4 is connected with the output end of the inverting buffer L3, the output end of the inverter L2 is connected with the input end of the inverting buffer L3, the output end of the nor gate L4 is connected with the D end of the trigger L6, and the CK end of the trigger L6 is connected with the clock signal output by the oscillator; the Q end of the trigger L6 is connected with one input end of the NOR gate L7, the other input end of the NOR gate L7 is connected with a CTR2 signal, the output end of the NOR gate L7 is connected with the input end of the inverter L8, and the output end of the inverter L8 outputs a detection enable EN signal; the logic operation unit further comprises a NOR gate L9, an inverter L10, an inverter L11, an inverter L12 and an inverter L13; one input end of the NOR gate L9 is connected with a Q1 signal, and the other input end of the NOR gate L9 is connected with a Q3 signal; the output end of the NOR gate L9 is connected with the input end of the inverter L10, and the output end of the inverter L10 outputs a selection signal EN_REF; the input end of the inverter L11 is connected with a Q2 signal, and the output end of the inverter L11 outputs an SH1 signal; the input end of the inverter L12 is connected with a Q4 signal, and the output end of the inverter L12 outputs an SH2 signal; the input end of the inverter L13 is connected with the Q5 signal, and the output end of the inverter L13 outputs the SH_OUT signal.
When the embodiment is implemented, the design of the logic operation unit is an important component of the invention, and the output signal of the logic operation unit is not only controlled by a chip, but also needs to output sampling pulses.
Example 6
As shown in fig. 7 to 9, the magnetic signal detection timing control method of the present invention includes the steps of: generating a group of sequential pulse signals according to the standard clock signal; generating control signals CTR1 and CTR2 of a Hall plate orthogonal current method according to the sequential pulse signals, wherein the CTR1 and CTR2 are used as two-phase orthogonal switch signals for controlling the Hall element; taking a plurality of continuous periods in a clock signal output by the oscillator as a working cycle, wherein CTR1 is high level at least twice in the working cycle; in one working cycle, the electric signal generated on the Hall plate is sampled at least twice, and each sampling at least comprises a high level of CTR1 once; the hall switch chip is put to sleep for one or more cycles at the end of one duty cycle until the next duty cycle.
When the invention is applied, the invention is mainly applied to control the Hall switch chip and devices such as chopper amplifier, reference voltage, comparator and the like matched with the Hall switch chip. In the invention, a control signal generated by an orthogonal current method is adopted to carry out alternating control on the Hall plate, and CTR1 has high level at least twice in one working cycle; in a duty cycle, carry out at least twice to the signal of telecommunication that produces on the hall piece, and at least once the high level of CTR1 is included in the sampling each time, just so just can realize in the sampling that just can all sample the two directions of hall piece detection magnetic field in a circular telegram working process, through detecting enabling EN signal with hall switch chip sleep after accomplishing the sampling, thereby the polarity of magnetic field is not distinguished when magnetic switch chip detects the magnetic signal, the installation of magnet is convenient, and the chip adopts periodic work-sleep mode, effectively reduce the consumption of system.
Example 7
In this embodiment, on the basis of embodiment 6, five consecutive periods in the clock signal output by the oscillator are taken as one working cycle, where the working cycle includes consecutive periods T1, T2, T3, T4 and T5; the electric signal and the reference voltage signal generated on the Hall plate in the T1 period are sampled for the first time respectively; sampling an electric signal generated on the Hall plate in a T2 period, closing sampling of a reference voltage, sampling a result of the comparator in the T2 period, and sending the result to a first register; respectively sampling the electric signal and the reference voltage signal generated on the Hall plate for the second time in the period of T3; sampling an electric signal generated on the Hall plate in a T4 period, closing sampling of a reference voltage, sampling a result of the comparator, and sending the result to the second register; and finally sampling the result in the second register in the period T5, and outputting the result to an output driver.
When the embodiment is implemented, in the working process:
in the period of T1, CTR1 is at high level, CTR2 is at low level, the detected magnetic field is in one direction, such as N/S direction, and the electric signal generated on the Hall plate is sampled for the first time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the first time;
In the period of T2, CTR1 is at low level, and part of time sequence of CTR2 is at high level, at the moment, the detected magnetic field direction is the same as the moment of T1, for example, the N/S direction, the first sampling is continuously carried out on the electric signal generated on the Hall chip, meanwhile, the EN_REF signal is at low level, and the sampling of the reference voltage is closed; sampling the result of the comparator by the rising edge of SH1, and sending the result to a first register;
in the period of T3, CTR1 is at low level, and part of the time sequence of CTR2 is at high level, because the waveform relationship of CTR2 and CTR1 changes, the detected magnetic field direction is opposite to the time of T1, for example, the S/N direction, and the electric signal generated on the Hall plate is sampled for the second time, and meanwhile, the EN_REF signal is at high level, so that the reference voltage signal is sampled for the second time;
CTR1 is in high level and CTR2 is in low level in the period T4, the detected magnetic field direction is opposite to the moment T1, for example, the S/N direction, the electric signal generated on the Hall plate is continuously sampled for the second time, meanwhile, the EN_REF signal is in low level, and the reference voltage sampling is closed; sampling the result of the comparator by the rising edge of SH2, and sending the result to the second register;
and the EN signal is at a low level in the T5 period, the Hall switch chip is closed, the result in the second register is finally sampled by the rising edge of SH_OUT, and the output result is sent to the output driver. The end of this one working cycle, the sleep is entered until the next working cycle.
Example 7
In this embodiment, based on embodiment 6, the detection enable signal of the hall switch chip is an EN signal, and the EN signal is obtained according to a sequential pulse signal; when the EN signal is high, the Hall switch chip is in a working state; when the EN signal is high, the hall switch chip is put to sleep. The clocks do not overlap when CTR1 and CTR2 are high during the EN signal high.
When the embodiment is implemented, the CTR1 and the CTR2 are mutually high-level non-overlapping clocks, so that the CTR1 and the CTR2 cannot simultaneously generate high levels, the situation that two input ends of a Hall piece are simultaneously connected with the high levels is avoided, and therefore the use safety of the Hall piece and the accuracy of magnetic field detection are ensured.
Example 8
In this embodiment, as shown in fig. 7, in order to clarify the operation method of the control circuit, it is assumed that the operation-sleep cycle of the chip is set to 1024 basic clock cycles, wherein the operation enable EN signal is 4 basic clock cycles, and the chip is in the sleep state for the following 1020 basic clock cycles.
As shown in fig. 8, the sequential pulse generator performs 1024 division counting on the basic clock signal from the oscillator according to the operation-sleep period of the chip as 1024 basic clock periods, and generates 6 groups of sequential pulse sequences Q0, Q1, Q2, Q3, Q4, Q5 with a pulse width of one basic clock period and a period of 1024 basic periods according to the sampling time, and the circuit embodiment thereof is shown in fig. 4.
As shown in fig. 9, the non-overlapping clock generator generates two-phase quadrature switching signals for controlling the hall element, the input signals Q1, Q2, Q3, Q4 of the non-overlapping clock unit are respectively connected to the outputs Q1, Q2, Q3, Q4 of the sequential pulse generator, the output signals of the non-overlapping clocks are CTR1, CTR2, and during the period when EN is high, CTR1, CTR2 are mutually high-level non-overlapping clocks, where Tnon is non-overlapping time, and the specific implementation of the circuit is shown in fig. 5, which is adjusted by the internal delay unit of the non-overlapping clock unit.
As shown IN fig. 6, the logic operation unit performs logic operation on the generated output signals Q0, Q1, Q2, Q3, Q4, Q5 of the sequential pulse generator, the output signals CTR1, CTR2 of the non-overlapping clock generator, and the oscillator output signal clk_in to obtain respective control signals EN, CTR1, CTR2, en_ref, SH1, SH2, sh_out of the switching chip.
When EN is at high level, each module of the chip is placed in a working state, electric signals generated on the Hall plate and reference voltage signals are respectively sampled for the first time in a T1 period of a time sequence waveform diagram, the electric signals generated on the Hall plate are sampled in a T2 period of the time sequence waveform diagram, the sampling of the reference voltage is closed, and meanwhile, the result of the comparator is sampled by the rising edge of SH1 in the T2 period, and the result is sent to the first register. And respectively carrying out second sampling on the electric signal and the reference voltage signal generated on the Hall plate in the T3 period of the time sequence waveform diagram, sampling the electric signal generated on the Hall plate in the T4 period of the time sequence waveform diagram, closing the sampling of the reference voltage, and simultaneously sampling the result of the comparator by the rising edge of SH2 in the T4 period, and outputting the result to a second register. The result in the second register is finally sampled by the rising edge of SH_OUT in the T5 period of the time sequence waveform diagram, and the output result is sent to the output driver. As shown in fig. 7, the magnetic field detection is completed twice in one working cycle, and the working-sleeping time period can be flexibly adjusted, so that the expandability and the practicability are high.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. A magnetic signal detection time sequence control circuit is characterized by comprising a sequential pulse generator, a non-overlapping clock generator and a logic operation unit which are connected in sequence; the sequential pulse generator is connected with the logic operation unit; the non-overlapping clock generator is connected with the Hall slice, and the logic operation unit is connected with the chopper amplifier, the reference voltage and the sampling pulse;
the sequential pulse generator is connected with a clock signal output by the oscillator, counts the clock signal in a frequency dividing way and generates a group of sequential pulse signals; wherein the sequential pulse generator generates a group of sequential pulse signals Q1, Q2, Q3, Q4; the non-overlapping clock generator comprises an inverter I1, a buffer I2, a NAND gate I3, an inverter I4, a buffer I5, a NOR gate I6, an inverter I7, an inverter I8, a buffer I9, a NAND gate I10, an inverter I11, a buffer I12, a NOR gate I13 and an inverter I14 which are sequentially connected, wherein the output end of the inverter I14 is connected with the input end of the inverter I1; the output end of the buffer I2 is connected with one input end of the NAND gate I3, the other input end of the NAND gate I3 is connected with the pulse signal Q2, and the output end of the NAND gate I3 is connected with the input end of the inverter I4; the output end of the buffer I5 is connected with one input end of the NOR gate I6, the other input end of the NOR gate I6 is connected with the pulse signal Q3, and the output end of the NOR gate I6 is connected with the input end of the inverter I7; the output end of the buffer I9 is connected with one input end of the NAND gate I10, the other input end of the NAND gate I10 is connected with the pulse signal Q4, and the output end of the NAND gate I10 is connected with the input end of the inverter I11; the output end of the buffer I12 is connected with one input end of the NOR gate I13, the other input end of the NOR gate I13 is connected with the pulse signal Q1, and the output end of the NOR gate I13 is connected with the input end of the inverter I14; the input end of the inverter I7 outputs a CTR1 signal, and the input end of the inverter I14 outputs a CTR2 signal; the sequential pulse generator generates a group of sequential pulse signals Q0, Q1, Q2, Q3, Q4 and Q5; the logic operation unit comprises a four-input NOR gate L1, an inverter L2, an inverting buffer L3, a NOR gate L4, an inverter L5, a trigger L6, a NOR gate L7 and an inverter L8 which are sequentially connected; the four input ends of the four-input NOR gate L1 are respectively connected with a Q0 signal, a Q1 signal, a Q2 signal and a Q3 signal, and the output end of the four-input NOR gate L1 is connected with the input end of the inverter L2; one input end of the nor gate L4 is connected with the output end of the inverter L2, the other input end of the nor gate L4 is connected with the output end of the inverting buffer L3, the output end of the inverter L2 is connected with the input end of the inverting buffer L3, the output end of the nor gate L4 is connected with the D end of the trigger L6, and the CK end of the trigger L6 is connected with the clock signal output by the oscillator; the Q end of the trigger L6 is connected with one input end of the NOR gate L7, the other input end of the NOR gate L7 is connected with a CTR2 signal, the output end of the NOR gate L7 is connected with the input end of the inverter L8, and the output end of the inverter L8 outputs a detection enable EN signal; the logic operation unit further comprises a NOR gate L9, an inverter L10, an inverter L11, an inverter L12 and an inverter L13; one input end of the NOR gate L9 is connected with a Q1 signal, and the other input end of the NOR gate L9 is connected with a Q3 signal; the output end of the NOR gate L9 is connected with the input end of the inverter L10, and the output end of the inverter L10 outputs a selection signal EN_REF; the input end of the inverter L11 is connected with a Q2 signal, and the output end of the inverter L11 outputs an SH1 signal; the input end of the inverter L12 is connected with a Q4 signal, and the output end of the inverter L12 outputs an SH2 signal; the input end of the inverter L13 is connected with a Q5 signal, and the output end of the inverter L13 outputs an SH_OUT signal;
The non-overlapping clock generator receives the sequential pulse signals, generates control signals of a Hall plate quadrature current method and sends the control signals to the Hall plate and the logic operation unit;
the logic operation unit receives the sequential pulse signals, the clock signals output by the oscillator and the control signals generated by the non-overlapping clock generator, generates a detection enable EN signal and sends the detection enable EN signal to the chopper amplifier and the comparator, and generates a selection signal EN_REF and sends the selection signal EN_REF to the chopper amplifier reference voltage; the logic operation unit also outputs a sampling pulse signal which is judged and output by the comparator; when the detection enable EN signal is at a high level, the Hall switch chip is placed in a working state; when the detection enable EN signal is at a low level, the hall switch chip is put to sleep.
2. The magnetic signal detection timing control circuit according to claim 1, wherein the hall chip quadrature current method control signal generated by the non-overlapping clock generator is two signals: CTR1 and CTR2; during the detection of the enable EN signal, the CTR1 and CTR2 are high level non-overlapping clocks;
the comparator output by the logic operation unit judges that the output sampling pulse signals are three paths: SH1, SH2, and sh_out; taking five continuous periods in a clock signal output by the oscillator as a working cycle, wherein the working cycle comprises a continuous T1 period, a continuous T2 period, a continuous T3 period, a continuous T4 period and a continuous T5 period;
During the periods T1 and T3, the EN signal, the EN_REF signal, the SH1 signal, the SH2 signal and the SH_OUT signal are high;
in the period T2, the EN signal, the SH2 signal, and the sh_out signal are at high level, and the en_ref signal and the SH1 signal are at low level;
in the period T4, the EN signal, SH1 signal and sh_out signal are at high level, and the en_ref signal and SH2 signal are at low level;
in the T5 period, the SH1 signal and the SH2 signal are high, and the EN signal, the en_ref signal, and the sh_out signal are low.
3. The magnetic signal detection timing control circuit according to claim 2, wherein the sequential pulse generator comprises a single pulse generator and a plurality of flip-flops in cascade; the cascading mode of the plurality of cascaded triggers is that the D end of each stage of trigger is connected with the Q end of the previous stage of trigger until the first stage of trigger; the D end of the first-stage trigger is connected with the output end of the single pulse generator, and the input end of the single pulse generator and the CK ends of all the triggers are connected with clock signals output by the oscillator; the output signals of the output ends of the single pulse generator and the output signals of the Q ends of all the triggers form a group of sequential pulse signals.
4. A magnetic signal detection timing control method using the circuit of any one of claims 1 to 3, characterized by comprising the steps of:
Generating a group of sequential pulse signals according to the standard clock signal;
generating control signals CTR1 and CTR2 of a Hall plate orthogonal current method according to the sequential pulse signals, wherein the CTR1 and CTR2 are used as two-phase orthogonal switch signals for controlling the Hall element; taking a plurality of continuous periods in a clock signal output by the oscillator as a working cycle, wherein CTR1 is high level at least twice in the working cycle;
in one working cycle, the electric signal generated on the Hall plate is sampled at least twice, and each sampling at least comprises a high level of CTR1 once; the hall switch chip is put to sleep for one or more cycles at the end of one duty cycle until the next duty cycle.
5. The method according to claim 4, wherein the period of the sequential pulse signal is derived from the number of basic clock cycles included in the duty-sleep cycle of the hall switch chip; the width of the sequential pulse signal is obtained according to the number of basic clock cycles contained in the sampling time of the Hall switch chip.
6. The method according to claim 4, wherein five consecutive periods of the clock signal output from the oscillator are used as one duty cycle, and the duty cycle includes consecutive T1 period, T2 period, T3 period, T4 period, and T5 period;
The electric signal and the reference voltage signal generated on the Hall plate in the T1 period are sampled for the first time respectively;
sampling an electric signal generated on the Hall plate in a T2 period, closing sampling of a reference voltage, sampling a result of the comparator in the T2 period, and sending the result to a first register;
respectively sampling the electric signal and the reference voltage signal generated on the Hall plate for the second time in the period of T3;
sampling an electric signal generated on the Hall plate in a T4 period, closing sampling of a reference voltage, sampling a result of the comparator, and sending the result to the second register;
and finally sampling the result in the second register in the period T5, and outputting the result to an output driver.
7. The method of claim 4, wherein the enable signal of the hall switch chip is EN signal, and the EN signal is derived from the sequential pulse signal;
when the EN signal is high, the Hall switch chip is in a working state; when the EN signal is high, the hall switch chip is put to sleep.
8. The method of claim 7, wherein CTR1 and CTR2 are not overlapped clocks at high level when EN signal is high.
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| CN113567761A (en) * | 2021-07-27 | 2021-10-29 | 成都通量科技有限公司 | CMOS full-integrated electromagnetic detection radio frequency front-end sensor |
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