CN105958953B - A kind of data sink - Google Patents
A kind of data sink Download PDFInfo
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- CN105958953B CN105958953B CN201610237069.5A CN201610237069A CN105958953B CN 105958953 B CN105958953 B CN 105958953B CN 201610237069 A CN201610237069 A CN 201610237069A CN 105958953 B CN105958953 B CN 105958953B
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- amplifier
- load circuit
- data sink
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
- H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
- H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
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Abstract
The invention discloses a kind of data sink, which includes: first order amplifier；Second level amplifier；For connecting the first load circuit of the negative output end of the first order amplifier and the normal phase input end of the second level amplifier；For connecting the second load circuit of the positive output end of the first order amplifier and the negative-phase input of second level amplifier；Wherein, first load circuit is identical as the equivalent resistance of second load circuit；First load circuit and second load circuit are used to increase the communication zero point of the first order amplifier.Data sink provided by the invention communicates zero point for increasing with the second load circuit by the first load circuit, and then the bandwidth of data amplifier pre-amplifier can be improved.
Description
Technical field
The present invention relates to communication device technology fields, more specifically, being related to a kind of data sink.
Background technique
Current mobile device is to be developed towards longer using the direction of time, i.e., under identical electricity, needs to move
Dynamic equipment work longest, this also proposed challenge other than requiring to battery technology, to the power consumption of each functional module.Faster
Data transmission bauds, lower power consumption, the cost more saved are as newly developed requirement.
As the nucleus module of D-PHY artificial circuit part, the rate of data sink is the main of decision D-PHY performance
Index.Data sink is made of casacade multi-amplifier, and the bandwidth of amplifier directly determines the speed of data transmission.Data receiver
The main function of device is accurately to receive and be amplified to CMOS grades of digital signal for the small signal of serial differential, is resent to subsequent
Module carries out the processing such as unstring.Wherein, D-PHY be formulated by MIPI alliance, and designed and used by mobile device manufacturer it is logical
Letter specification.Alphabetical " D " is derived from " 500 " in Roman number, be due to the specification is based on single channel 500Mbps at the beginning of formulation
The typical rate of (Million bits per second) is formulated, and as the progress of technique and technology develop, single channel speed
Rate is being continuously improved.
Data sink problem encountered is gain and the compromise of bandwidth, and the amplifier of level-one is difficult to realize, so one
As use the cascade structure of casacade multi-amplifier, lifting step by step gain under the premise of guaranteeing bandwidth.With gradually rising for gain,
Signal swing constantly increases, and the emphasis of design is not quite similar.The input signal amplitude of oscillation is smaller higher to bandwidth requirement, so data
In receiver, the structure of pre-amplifier more focuses on bandwidth.Therefore, the bandwidth of data amplifier pre-amplifier how is improved,
It is a communication device technology field problem urgently to be resolved.
Summary of the invention
To solve the above problems, the data sink passes through the first load the present invention provides a kind of data sink
Circuit communicates zero point for increasing with the second load circuit, and then can increase bandwidth.
To achieve the goals above, the invention provides the following technical scheme:
A kind of data sink, the data sink include:
First order amplifier；
Second level amplifier；
For connecting the negative output end of the first order amplifier and the normal phase input end of the second level amplifier
The first load circuit；
For connecting the of the positive output end of the first order amplifier and the negative-phase input of second level amplifier
Two load circuits；
Wherein, first load circuit is identical as the equivalent resistance of second load circuit；The first load electricity
Road and second load circuit are used to increase the communication zero point of the data sink.
Preferably, in above-mentioned data sink, first load circuit include: first switch tube, second switch,
Third switching tube, the first current source and the second current source；
The control terminal of the third switching tube inputs the first biasing voltage signal, and the first pole and second level amplifier are just
The connection of phase input terminal, the second pole are connect with the negative output end of the first order amplifier, and its second pole passes through the second electricity
Stream source ground connection；
The control terminal of the second switch by the first current source be grounded, the first pole connect power supply, the second pole with
First pole of the third switching tube connects；
The control terminal of the first switch tube is connect with the second pole of the second switch, and the first pole connects the electricity
Source, the second pole are grounded by first current source.
Preferably, in above-mentioned data sink, the first switch tube is NMOS, and the second switch is PMOS.
Preferably, in above-mentioned data sink, second load circuit include: the 4th switching tube, the 5th switching tube,
6th switching tube, third current source and the 4th current source；
The control terminal of 6th switching tube inputs first biasing voltage signal, the first pole and second level amplifier
Negative-phase input connection, the second pole connect with the positive output end of the first order amplifier, and its second pole passes through the
Four current sources ground connection；
The control terminal of 5th switching tube is grounded by third current source, the first pole connection power supply, and second
Pole is connect with the first pole of the 6th switching tube；
The control terminal of 4th switching tube is connect with the second pole of the 5th switching tube, and the first pole connects the electricity
Source, the second pole are grounded by the third current source.
Preferably, in above-mentioned data sink, first current source is the 7th switching tube；7th switching tube
First pole connects the second pole of the first switch tube, the second pole ground connection, and control terminal inputs the second biasing voltage signal；
Second current source is the 8th switching tube；The of first pole of the 8th switching tube and the third switching tube
The connection of two poles, the second pole ground connection, control terminal input second biasing voltage signal.
Preferably, in above-mentioned data sink, the third current source is the 9th switching tube；9th switching tube
First pole connects the second pole of the 4th switching tube, and the second pole ground connection controls the letter of the second bias voltage described in single input
Number；
4th current source is the tenth switching tube；First pole of the tenth switching tube connects the 6th switching tube
Second pole, the second pole ground connection, control terminal input second biasing voltage signal.
Preferably, in above-mentioned data sink, the first order amplifier includes: the 11st switching tube, the 12nd opens
Close pipe and the 13rd switching tube；
The control terminal of 11st switching tube is the normal phase input end of the first order amplifier, defeated for inputting first
Enter signal, the first pole connects the second pole of the 13rd switching tube, and the second pole connects the second of the third switching tube
Pole；
The control terminal of 12nd switching tube is the negative-phase input of the first order amplifier, defeated for inputting second
Enter signal, the first pole connects the second pole of the 13rd switching tube, and the second pole connects the second of the 6th switching tube
Pole；The control terminal of 13rd switching tube is for inputting third biasing voltage signal, and the first pole is for connecting the power supply.
Preferably, in above-mentioned data sink, the 4th switching tube is NMOS, and the 5th switching tube is PMOS.
Preferably, in above-mentioned data sink, the second level amplifier includes: the operation transconductance amplification of symmetric form
Device；
The second level amplifier has the Miller negative capacitance for reducing the first order amplifier output capacitance.
Preferably, in above-mentioned data sink, first load circuit includes load switch pipe, the load switch
The equivalent output impedance of pipe is equal to the inverse of the mutual conductance of the load switch pipe.As can be seen from the above description, provided by the invention
Data sink includes: first order amplifier；Second level amplifier；For connecting the negative output end of the first order amplifier
And the first load circuit of the normal phase input end of the second level amplifier；For connecting the positive of the first order amplifier
Second load circuit of the negative-phase input of output end and second level amplifier；Wherein, first load circuit with it is described
The equivalent resistance of second load circuit is identical；First load circuit and second load circuit are for increasing described first
The communication zero point of grade amplifier.Data sink provided by the invention is by the first load circuit with the second load circuit for increasing
Add communication zero point, and then the bandwidth of data amplifier pre-amplifier can be improved.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of data sink provided in an embodiment of the present invention；
Fig. 2 is the circuit diagram of another data sink provided in an embodiment of the present invention；
Fig. 3 is a kind of Computing Principle schematic diagram of the equivalent resistance of first load circuit provided in an embodiment of the present invention；
Fig. 4 is the circuit diagram of another data sink provided in an embodiment of the present invention；
Fig. 5 is a kind of bandwidth simulation result schematic diagram provided in an embodiment of the present invention；
Fig. 6 is a kind of structural schematic diagram of second level amplifier provided in an embodiment of the present invention；
Fig. 7 is another bandwidth simulation result schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As the nucleus module of D-PHY artificial circuit part, the rate of data sink is the main of decision D-PHY performance
Index.Generally as shown in FIG. 1, FIG. 1 is a kind of knots of data sink provided in an embodiment of the present invention for the structure of data sink
Structure schematic diagram, the data sink include: first order amplifier 1, second level amplifier 2, third level amplifier 3 and buffer
4.Wherein, third level amplifier is double amplifiers for turning singly to export.
For data sink mainly by Differential OPAMP structure composition, the bandwidth of amplifier directly determines the speed of data transmission
Degree.The main function of high-speed receiver be the small signal of serial differential is accurately received and is amplified to CMOS grades of digital signal, then
It is sent to subsequent module and carries out the processing such as unstring.Receiver problem encountered is gain and the compromise of bandwidth, and level-one is put
Big device is difficult to realize, so general using multistage structure, lifting step by step gain under the premise of guaranteeing bandwidth.With gain
It gradually rises, signal swing constantly increases, and the emphasis of design is not quite similar.The input signal amplitude of oscillation is smaller to get over bandwidth requirement
Height, so the structure of prime more focuses on bandwidth.Pre-amplifier is the first order amplifier of data sink.
For available data amplifier in order to increase the bandwidth of pre-amplifier, a kind of mode is by connecting on load resistance
One inductance makes circuit become a zero point and a pair of of conjugation complex pole from single real pole, to reach the mesh of broadened bandwidth
, passive inductance device occupies chip and crosses large area, while power consumption is larger, needs to consume more multi-power source voltage nargin, this is low
It is difficult to be applicable under supply voltage.Another way be solve area for cutting by active inductance, but with a kind of upper embodiment party
Formula is the same, needs to consume more multi-power source voltage nargin, this is difficult to be applicable at low supply voltages.To solve the above-mentioned problems, originally
Inventive embodiments provide a kind of data sink, which includes:
First order amplifier；
Second level amplifier；
First for connecting the negative output end of first order amplifier and the normal phase input end of second level amplifier is negative
Carry circuit；
For connecting the second load electricity of first order amplifier positive output end and second level amplifier negative-phase input
Road；
Wherein, the first load circuit is identical as the equivalent resistance of the second load circuit；First load circuit and the second load
Circuit is used to increase the communication zero point of first order amplifier.
Trsanscondutance amplifier in data sink is for the first order amplifier as data sink, second level amplifier
For the second pole amplifier as data sink.The negative output end of first order amplifier passes through the first load circuit and the
The positive output end of two-stage amplifier connects, and the positive output end of first order amplifier is put by the second load circuit with the second level
The negative output end connection of big device, the feedback electricity by the first load circuit and the second load circuit as first order amplifier
Road increases the communication zero point of data sink, realizes higher bandwidth.
Data sink provided in an embodiment of the present invention, which can be realized, is amplified to rail-to-rail for the small signal of high-speed-differential is undistorted
Digital signal.First load circuit and the second load circuit are made of active device completely, for realizing the function for increasing bandwidth
Can, the first load circuit and the second load circuit do not use passive device, thereby save most of area and power consumption, effectively
The function of realizing active inductance.
In order to make the technical scheme provided by the embodiment of the invention clearer, above scheme is carried out with reference to the accompanying drawing detailed
Thin description.
With reference to Fig. 2, Fig. 2 is the circuit diagram of another data sink provided in an embodiment of the present invention, the data sink
It include: first order amplifier 11；Second level amplifier 12；For connecting the negative output end and second of first order amplifier 11
First load circuit 13 of the normal phase input end of grade amplifier 12；For connect first order amplifier 11 positive output end and
Second load circuit 14 of the negative-phase input of second level amplifier 12.
Wherein, the first load circuit 13 is identical as the equivalent resistance of the second load circuit 14；First load circuit 13 and
Two load circuits 14 are used to increase the communication zero point of first order amplifier.
In data sink of the embodiment of the present invention, by the first load circuit 13 and the second load circuit 14 as the
The feed circuit of first stage amplifier 11 increases the communication zero point of first order amplifier 11, realizes higher bandwidth.
As shown in Fig. 2, the first load circuit 13 include: first switch tube M1, second switch M2, third switching tube M3,
First current source ISS1And the second current source ISS2.The control terminal of third switching tube M3 inputs the first biasing voltage signal Bias1,
Its first pole is connect with the normal phase input end of second level amplifier 12, the negative output end of the second pole and first order amplifier 11
Connection, and its second pole passes through the second current source ISS2Ground connection；The control terminal of second switch M2 passes through the first current source ISS1It connects
Ground, the first pole connect power vd D, and the second pole is connect with the first pole of third switching tube M3；The control of first switch tube M1
End is connect with the second pole of second switch M2, and the first pole connects power vd D, and the second pole passes through the first current source ISS1It connects
Ground.First switch tube M1 is NMOS, second switch PMOSM2.
Second load circuit 14 includes: the 4th switching tube M4, the 5th switching tube M5, the 6th switching tube M6, third current source
ISS3And the 4th current source ISS4.The control terminal of 6th switching tube M6 inputs the first biasing voltage signal Bias1, the first pole with
The negative-phase input of second level amplifier 12 connects, and the second pole is connect with the positive output end of first order amplifier 11, and its
Second pole passes through the 4th current source ISS4Ground connection；The control terminal of 5th switching tube M5 passes through third current source ISS3Ground connection, first
Pole connects power vd D, and the second pole is connect with the first pole of the 6th switching tube M6；The control terminal of 4th switching tube M4 is opened with the 5th
The second pole connection of pipe M5 is closed, the first pole connects power vd D, and the second pole passes through third current source ISS3Ground connection.
In the embodiment of the present invention, the first load circuit 13 is identical as 14 structure of the second load circuit, in first order amplifier
11 two output ends form symmetrical feedback circuit structure.
It should be noted that the present invention is intended to provide can be improved the preceding dual-stage amplifier of data sink bandwidth, Fig. 2 institute
Show the amplifier of two-stage before data sink illustrates only.The structure of follow up amplifier (third level amplifier and buffer) can
With identical as the amplifier architecture in tradition.
In data sink shown in Fig. 2, the first load circuit 13 is identical as 14 structure of the second load circuit.The two is
Intersect biasing circuit by what NMOS and PMOS was constituted.Therefore the first load circuit 13 and the second load circuit 14 can reduce voltage
The consumption of nargin is driven only with a voltage source VDD.
First load circuit 13 and second load circuit 14 all have load switch pipe.First load
The equivalent output impedance of circuit 13 and second load circuit 14 is equal to the inverse of the mutual conductance of the load switch pipe.The
In one load circuit 13, second switch M2 is load switch pipe.In second load circuit 14, the 5th switching tube M5 is that load is opened
Guan Guan.
In the load circuit for making respective place by the source follower that first switch tube M1 and the 4th switching tube M4 are separately constituted
Load switch pipe be similar to diode connection, so the output resistance of load switch pipe maintains a lesser 1/gm, gm
For the mutual conductance of load switch pipe.In data sink shown in Fig. 2, two load switch pipes are PMOS.
Since first order amplifier 11 amplifies input signal with certain gain, gain is first order amplifier 11
The ratio between mutual conductance Gm and the mutual conductance of load PMOS, the compromise between the gain and bandwidth of the adjustment amplifier that can be convenient in this way, can
While to increase dominant pole frequency, the static gain of amplifier ensure that.It is negative in combination with Miller in second level amplifier 12
The application of capacitor, effectively reduces the output capacitance of first order amplifier 11, and first order amplifier 11 is realized in overall structure cooperation
High bandwidth.
With reference to Fig. 3, Fig. 3 is that a kind of Computing Principle of the equivalent resistance of first load circuit provided in an embodiment of the present invention shows
It is intended to.Fig. 3 individually analyzes the first load circuit, and the second load circuit is identical as the analysis of the first load circuit, herein
It repeats no more.
By one voltage source V of position equivalence replacement of the second current sourceX, from the figure 3, it may be seen that the equivalent electricity of the first load circuit
Hinder Rout are as follows:
Wherein, CGS2For the parasitic capacitance between the first pole of second switch M2 and control terminal.S is Complex frequency, to draw
The corresponding relationship of the transformation of cloth Lars and Fourier transformation.S=j* ω, j are complex unit, and ω is phase.gM1For first switch
The mutual conductance of pipe, gM2For the mutual conductance of second switch.It is known that the structural load circuit has by the calculation formula of above-mentioned Rout
Have characteristic: the inductive effect under high frequency, this characteristic can generate a zero point under certain frequency, with compensation due to
High-frequency signal amplitude caused by the limitation of bandwidth declines in transmission line.The position of zero point and M1, M2 mutual conductance is directly related, can be with
The position of zero point is adjusted by adjusting its channel width-over-length ratio and electric current source size, so adjust the bandwidth of first order amplifier with
And gain.
Have above-mentioned it is found that data sink shown in Fig. 2 can increased by the first load circuit and the second load circuit
While adding dominant pole frequency, guarantee the static gain of first order amplifier, the convenient gain for adjusting amplifier and bandwidth it
Between compromise.
The implementation of each current source and first order amplifier in data sink shown in Fig. 2 is as shown in figure 4, figure
4 be the circuit diagram of another data sink provided in an embodiment of the present invention.In data sink shown in Fig. 4, illustrate only
First order amplifier, the first load circuit and the second load circuit.
As shown in figure 4, the first current source is the 7th switching tube M7, the first pole of the 7th switching tube M7 connects first switch tube
The second pole of M1, the second pole ground connection, control terminal input the second biasing voltage signal Bias2；Second current source is opened for the 8th
Pipe M8 is closed, the first pole of the 8th switching tube M8 is connect with the second pole of third switching tube M3, the second pole ground connection, and control terminal is defeated
Enter the second biasing voltage signal.
It should be noted that in the embodiment of the present invention ground voltage can be provided by power supply VSS, it is grounded.
As shown in figure 4, third current source is the 9th switching tube M9, the first pole of the 9th switching tube M9 connects the 4th switching tube
The second pole of M4, the second pole ground connection, controls the second biasing voltage signal of single input Bias2；4th current source is opened for the tenth
Pipe M10 is closed, the first pole of the tenth switching tube M10 connects the second pole of the 6th switching tube M6, and the second pole ground connection, control terminal is defeated
Enter the second biasing voltage signal Bias2.
As shown in figure 4, first order amplifier includes: the 11st switching tube M11, the 12nd switching tube M12 and the 13rd
Switching tube M13.The control terminal of 11st switching tube M11 is the normal phase input end of first order amplifier, for inputting the first input
Signal Vinp, the first pole connect the second pole of the 13rd switching tube M13, and the second pole connects the second of third switching tube M3
Pole.The control terminal of 12nd switching tube M12 is the negative-phase input of first order amplifier, for inputting the second input signal
Vinn, the first pole connect the second pole of the 13rd switching tube M13, and the second pole connects the second pole of the 6th switching tube M6；The
The control terminal of 13 switching tube M13 is for inputting third biasing voltage signal Bias3, and the first pole is for connecting power vd D.The
Four switching tubes are NMOS, and the 5th switching tube is PMOS.
It should be noted that in the embodiment of the present invention each biasing voltage signal can be provided by a biasing circuit.
The first order amplifier of the core amplifier of data sink, the circuit structure of first order amplifier are as shown in Figure 4.
First order amplifier is to fold amplifier, and the mutual conductance of first order amplifier is determined by M11, M12.First load circuit and second negative
The output end of circuit is carried by M3, M6 and M8, the cascaded structure of M10 provides a stable electric current, while raising output common mode
Voltage can effectively improve bandwidth under the premise of gain is certain.
Using the first order amplifier of load circuit described in the embodiment of the present invention and using the first of traditional pure resistor load
Grade amplifier carries out bandwidth Experimental Comparison, and simulation result such as Fig. 5, Fig. 5 are a kind of bandwidth emulation knot provided in an embodiment of the present invention
Fruit schematic diagram.
In Fig. 5, horizontal axis indicates that frequency f, unit Hz, the longitudinal axis indicate gain, unit dB.Wherein, block curve is this
The simulation curve of first order amplifier described in inventive embodiments, dashed region are the simulation curve of traditional first order amplifier.By
It is found that under identical gain, bandwidth is improved by 1.05GHz to 2GHz Fig. 5 curve, it can be seen that due to the effect of high frequency zero,
Bandwidth has further promotion.
In data sink shown in Fig. 2, the structure of second level amplifier can using as shown in fig. 6, Fig. 6 as the embodiment of the present invention
A kind of structural schematic diagram of the second level amplifier provided.Second level amplifier shown in Fig. 6 includes: that the operation transconductance of symmetric form is put
Big device；Second level amplifier has the Miller negative capacitance for reducing first order amplifier output capacitance.It puts the second level shown in Fig. 6
Big device include: the 25th switching tube M25 of the 14th switching tube M14-, the first Miller negative capacitance C1, the second Miller negative capacitance C2,
First filter capacitor C3 and the second filter capacitor C4.
Wherein, it is second that sixteenmo, which closes the second pole of pipe M16 and the common node of the first pole of the 19th switching tube M19,
The positive output end outn2 of grade amplifier.The second pole of 24th switching tube M24 and the first pole of the 14th switching tube M14
Common node be second level amplifier negative sense output end outp2.
The ratio of the channel width-over-length ratio of M16, M17, M18 is B:B:1.The ratio of the channel width-over-length ratio of M23, M24, M25 is 1:B:
B.The ratio of the channel width-over-length ratio of M21, M14 is 1:1.The ratio of the channel width-over-length ratio of M19, M15 is 1:1.Wherein, B is just greater than 1
Integer.
Second level amplifier with the OTA of symmetric form (OperationalTransconductanceAplifier: operation across
Lead amplifier) based on design, the differential signal that two-way is amplified can be obtained.The setting of Miller negative capacitance C1, C2 can have
Effect reduces the output capacitance of first order amplifier.Due to flying capcitor (flying capcitor be Fig. 6 in Miller negative capacitance C1,
C2 positive feedback effect) equally can generate another communication zero point in first order amplifier, can be further compensate for gain, should
The position of communication zero point is decided by flying capcitor (C1, C2 in Fig. 6) size, with first order amplifiers using can significantly mention
Rise the bandwidth of first order amplifier.
C1=C2=C is setC, the position of zero point is with CCThe simulation result of variation is as shown in Figure 7.Fig. 7 is the embodiment of the present invention
Another bandwidth simulation result schematic diagram of offer.C is shown in Fig. 7CWhen for 25fF, 15fF and 5fF corresponding three it is imitative
True curve.In Fig. 7, horizontal axis indicates that frequency f, unit Hz, the longitudinal axis indicate gain, unit dB.As shown in Figure 7, work as capacitance
CCWhen different, bandwidth and gain are different.
The present invention is different from general active inductance structure and consumes a large amount of voltage margin, but passes through the tune to circuit structure
It is whole, i.e., the external structure of load is biased, thus reduces the consumption of voltage margin.The overall structure quiescent point of load circuit
Foundation only need three overdrive voltages, can be easier to be applicable in the structure that low supply voltage works.Wherein, it crosses and drives
Dynamic voltage is the smallest Vds voltage for keeping metal-oxide-semiconductor in a saturated state, Vds=Vgs-Vth.Vds indicates the drain-source electricity of metal-oxide-semiconductor
Pressure, Vgs indicate that the gate source voltage of metal-oxide-semiconductor, Vth indicate the threshold voltage of metal-oxide-semiconductor.As shown in figure 4, being with the first load circuit
Example, symmetrical structure for the first load circuit need three overdrive voltages in six metal-oxide-semiconductors, as M2, M3, M8 need
It is respectively connected to an overdrive voltage.
It can be realized the gain compensation under high frequency by generating high frequency zero simultaneously, realize the effect of balanced device, fill
Divide the positive feedback property using Miller negative capacitance, further strengthens gain compensation effect, and be achieved in the expansion of bandwidth.
To sum up shown in, in the embodiment of the present invention, the symmetrical load circuit of two of first order amplifier using NMOS with
The structure that PMOS intersects biasing is used for first order amplifier load, to promote bandwidth.The minimum list of the voltage margin of load consumption
A metal-oxide-semiconductor overdrive voltage, therefore, the data sink can be more convenient to be applied to low-voltage driving.It is loaded in load circuit
The equivalent output impedance of switching tube is 1/gm, can be convenient bandwidth and gain size that compromise adjusts amplifier.It is applied to simultaneously
The inductive effect of the load circuit of this structure in high frequency realizes Equalizer (to generate high frequency zero compensating gain
Weighing apparatus) effect.
Use first order amplifier to fold amplifier structure, the collocation design with the symmetric form OTA of second level amplifier, the
The design distinguished of Miller negative capacitance applied by two-stage amplifier only offsets the input capacitance of second level amplifier (i.e. in tradition
Reduce second level load capacitance), while reducing the load capacitance of second level amplifier, first order amplifier can also be reduced
Output capacitance.Simultaneously by with the first load circuit and the second load circuit, its positive feedback property is made full use of, first
Grade generates high frequency zero with the decaying of compensating gain, further enhances the effect of Equalizer.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (9)
1. a kind of data sink characterized by comprising
First order amplifier；
Second level amplifier；
For connecting the of the negative output end of the first order amplifier and the normal phase input end of the second level amplifier
One load circuit；
Second for connecting the positive output end of the first order amplifier and the negative-phase input of second level amplifier is negative
Carry circuit；
Wherein, first load circuit is identical as the equivalent resistance of second load circuit；First load circuit with
Second load circuit is used to increase the communication zero point of the data sink, to improve bandwidth；
First load circuit includes: first switch tube, second switch, third switching tube, the first current source and second
Current source；The control terminal of the third switching tube inputs the first biasing voltage signal, and the first pole and second level amplifier are just
The connection of phase input terminal, the second pole are connect with the negative output end of the first order amplifier, and its second pole passes through the second electricity
Stream source ground connection；The control terminal of the second switch by the first current source be grounded, the first pole connect power supply, the second pole with
First pole of the third switching tube connects；Second pole of the control terminal of the first switch tube and the second switch connects
It connects, the first pole connects the power supply, and the second pole is grounded by first current source；First load circuit with it is described
Second load circuit structure is identical, forms symmetrical feedback circuit structure in two output ends of the first order amplifier.
2. data sink according to claim 1, which is characterized in that the first switch tube be NMOS, described second
Switching tube is PMOS.
3. data sink according to claim 1, which is characterized in that second load circuit includes: the 4th switch
Pipe, the 5th switching tube, the 6th switching tube, third current source and the 4th current source；
The control terminal of 6th switching tube inputs first biasing voltage signal, and the first pole is negative with second level amplifier
The connection of phase input terminal, the second pole are connect with the positive output end of the first order amplifier, and its second pole passes through the 4th electricity
Stream source ground connection；
The control terminal of 5th switching tube is grounded by third current source, and the first pole connects the power supply, the second pole with
First pole of the 6th switching tube connects；
The control terminal of 4th switching tube is connect with the second pole of the 5th switching tube, and the first pole connects the power supply,
Its second pole is grounded by the third current source.
4. data sink according to claim 3, which is characterized in that first current source is the 7th switching tube；Institute
The first pole for stating the 7th switching tube connects the second pole of the first switch tube, the second pole ground connection, control terminal input second
Biasing voltage signal；
Second current source is the 8th switching tube；First pole of the 8th switching tube and the second pole of the third switching tube
Connection, the second pole ground connection, control terminal input second biasing voltage signal.
5. data sink according to claim 4, which is characterized in that the third current source is the 9th switching tube；Institute
The first pole for stating the 9th switching tube connects the second pole of the 4th switching tube, and the second pole ground connection controls described in single input
Second biasing voltage signal；
4th current source is the tenth switching tube；First pole of the tenth switching tube connects the second of the 6th switching tube
Pole, the second pole ground connection, control terminal input second biasing voltage signal.
6. data sink according to claim 3, which is characterized in that the first order amplifier includes: the 11st to open
Guan Guan, the 12nd switching tube and the 13rd switching tube；
The control terminal of 11st switching tube is the normal phase input end of the first order amplifier, for inputting the first input letter
Number, the first pole connects the second pole of the 13rd switching tube, and the second pole connects the second pole of the third switching tube；
The control terminal of 12nd switching tube is the negative-phase input of the first order amplifier, for inputting the second input letter
Number, the first pole connects the second pole of the 13rd switching tube, and the second pole connects the second pole of the 6th switching tube；Institute
The control terminal of the 13rd switching tube is stated for inputting third biasing voltage signal, the first pole is for connecting the power supply.
7. data sink according to claim 3, which is characterized in that the 4th switching tube be NMOS, the described 5th
Switching tube is PMOS.
8. data sink according to claim 1, which is characterized in that the second level amplifier includes: symmetric form
Operation transconductance amplifier；
The second level amplifier has the Miller negative capacitance for reducing the first order amplifier output capacitance.
9. data sink according to claim 1, which is characterized in that first load circuit includes load switch
Pipe, the equivalent output impedance of the load switch pipe are equal to the inverse of the mutual conductance of the load switch pipe.
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| CN201610237069.5A CN105958953B (en) | 2016-04-15 | 2016-04-15 | A kind of data sink |
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| CN201610237069.5A CN105958953B (en) | 2016-04-15 | 2016-04-15 | A kind of data sink |
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| CN105958953B true CN105958953B (en) | 2019-05-31 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI599165B (en) * | 2016-10-13 | 2017-09-11 | 智原科技股份有限公司 | Amplifier with adjustable gain |
| CN113551770B (en) * | 2021-07-23 | 2023-12-29 | 中国科学院半导体研究所 | Terahertz wave amplitude and phase reading device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677230A (en) * | 2008-09-15 | 2010-03-24 | 联发科技（新加坡）私人有限公司 | three-stage frequency-compensated operational amplifier |
| CN102386859A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | Wide band amplifier with frequency compensation |
| CN103595356A (en) * | 2013-11-12 | 2014-02-19 | 四川和芯微电子股份有限公司 | High-frequency bandwidth amplifying circuit |
| CN105099171A (en) * | 2014-05-16 | 2015-11-25 | 深圳市中兴微电子技术有限公司 | Compensation network, switching power supply circuit and circuit compensation method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201243533A (en) * | 2011-04-19 | 2012-11-01 | Hon Hai Prec Ind Co Ltd | Power source equipment |
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2016
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677230A (en) * | 2008-09-15 | 2010-03-24 | 联发科技（新加坡）私人有限公司 | three-stage frequency-compensated operational amplifier |
| CN102386859A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | Wide band amplifier with frequency compensation |
| CN103595356A (en) * | 2013-11-12 | 2014-02-19 | 四川和芯微电子股份有限公司 | High-frequency bandwidth amplifying circuit |
| CN105099171A (en) * | 2014-05-16 | 2015-11-25 | 深圳市中兴微电子技术有限公司 | Compensation network, switching power supply circuit and circuit compensation method |
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