CN112039526B - Numerical control switch driving circuit applied to digital-to-analog converter - Google Patents
Numerical control switch driving circuit applied to digital-to-analog converter Download PDFInfo
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- H03—ELECTRONIC CIRCUITRY
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- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Abstract
One embodiment of the present invention discloses a digital control switch driving circuit applied to a digital-to-analog converter, which includes: the device comprises a signal input/output unit and a swing amplitude numerical control unit, wherein the signal input/output unit is used for adjusting the waveform of an input signal; the swing numerical control unit adjusts the output swing of the output signal adjusted by the input and output unit through digital control. According to the technical scheme, the signal input and output unit adjusts the waveform of an input signal and the swing numerical control unit adjusts the reduction degree of the output swing of the output signal by the input and output unit through digital control, and finally the purpose of adjusting and improving the dynamic performance of the DAC is achieved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a numerical control switch driving circuit applied to a digital-to-analog converter.
Background
In a digital-to-analog converter (DAC) of, for example, a current-steering architecture, a control signal generated by an encoding circuit drives a current source switch to output a differential current provided by a current source array, and a circuit driving the current source switch is referred to as a switch driving circuit. The switch driving circuit is used for buffering the control signal and providing the best possible driving signal for the current switch, and the driving signal has great influence on the transient response and the dynamic performance of the DAC output.
The influence of the current switch driving circuit on the dynamic performance of the high-speed DAC has three main aspects: firstly, the switch driving signals are asynchronous, secondly, the switch driving signals have the charge feed-through effect, and thirdly, the current switches are simultaneously turned off. For the asynchronous current switch driving signals, a synchronous latch controlled by a clock signal can be added in front of the switch driving circuit to ensure the synchronization of the driving signals. For the problems of feed-through effect of switch driving signal charges and simultaneous turn-off of current switches, optimization and solution are needed through a switch driving circuit.
Disclosure of Invention
The invention provides a numerical control switch driving circuit applied to a digital-to-analog converter aiming at the problems of feed-through effect of switch driving signal charges and simultaneous turn-off of a current switch, and the dynamic performance of a DAC (digital-to-analog converter) can be adjusted and improved.
In order to achieve the purpose, the invention adopts the following technical scheme:
one aspect of the present invention provides a digitally controlled switch driver circuit for use in a digital to analog converter, the circuit comprising: a signal input and output unit and a swing numerical control unit,
wherein the content of the first and second substances,
the signal input and output unit is used for adjusting the waveform of an input signal;
the swing numerical control unit adjusts the output swing of the output signal of the input and output unit through digital control.
In a specific embodiment, the signal input and output unit comprises a first MOS tube of a first conduction type, a second MOS tube of the first conduction type, a third MOS tube of the first conduction type, a fourth MOS tube of the first conduction type, a first MOS tube of a second conduction type, a second MOS tube of the second conduction type, a third MOS tube of the second conduction type and a fourth MOS tube of the second conduction type;
wherein the content of the first and second substances,
the grid electrode of the first MOS tube of the first conduction type and the grid electrode of the first MOS tube of the second conduction type receive a first input signal;
the grid electrode of the third MOS tube of the first conduction type and the grid electrode of the fourth MOS tube of the second conduction type receive a second input signal;
the source electrode of the first MOS tube of the first conduction type and the source electrode of the third MOS tube of the first conduction type are both connected to the ground;
the source electrode of the first MOS tube of the second conduction type and the source electrode of the fourth MOS tube of the second conduction type receive power supply voltage;
the grid electrode and the drain electrode of the second MOS tube of the first conduction type are in short circuit connection;
the grid electrode and the drain electrode of the fourth MOS tube of the first conduction type are in short circuit connection;
the source electrode of the second MOS tube of the first conduction type is connected with the drain electrode of the first MOS tube of the first conduction type, and the drain electrode of the second MOS tube of the first conduction type is connected with the drain electrode of the first MOS tube of the second conduction type;
the source electrode of the fourth MOS tube of the first conduction type is connected with the drain electrode of the third MOS tube of the first conduction type, and the drain electrode of the fourth MOS tube of the first conduction type is connected with the drain electrode of the fourth MOS tube of the second conduction type;
the source electrode of the second MOS tube of the second conduction type and the source electrode of the third MOS tube of the second conduction type receive power supply voltage, and the drain electrode of the second MOS tube of the second conduction type is connected with the drain electrode of the first MOS tube of the second conduction type;
the drain electrode of the third MOS tube of the second conduction type is connected with the drain electrode of the fourth MOS tube of the second conduction type;
the grid electrode of the second MOS tube of the second conductivity type and the grid electrode of the third MOS tube of the second conductivity type are mutually connected and are connected to the swing numerical control unit;
the first output signal is output by the drain electrode of the fourth MOS transistor of the first conductivity type, and the output signal of the second signal output end is output by the drain electrode of the second MOS transistor of the first conductivity type.
In a specific embodiment, the swing numerical control unit includes: the first current source, a fifth MOS tube of the first conduction type, a fifth MOS tube of the second conduction type and the digital control signal unit are connected;
wherein the content of the first and second substances,
the grid electrode and the drain electrode of the fifth MOS tube of the first conductivity type are in short circuit connection and are connected to the output end of the first current source, and the source electrode of the fifth MOS tube of the first conductivity type is grounded;
the input end of the first current source is connected with the power voltage;
the grid electrode of the fifth MOS tube of the first conductivity type is connected with the first end of the digital control signal unit;
the second end of the digital control signal unit is connected to the drain electrode of the fifth MOS tube of the second conduction type, the source electrode of the fifth MOS tube of the second conduction type is connected with power voltage, and the grid electrode of the fifth MOS tube of the second conduction type is in short circuit connection with the drain electrode and is connected with the grid electrode of the third MOS tube of the second conduction type.
In one embodiment, the digital control signal unit includes:
the first control element group comprises N MOS tubes of the first conductivity type;
the second control element group comprises M MOS tubes of the first conductivity type, wherein M is equal to or more than 1;
wherein the content of the first and second substances,
the drains of all the MOS transistors of the N first conductivity type MOS transistors are connected to the second end, and the gates of all the MOS transistors of the N first conductivity type MOS transistors receive respective control signals respectively, so as to adjust the voltage value of the second end, and further control the swing amplitudes of the first output signal and the second output signal;
the source electrodes of all the M MOS tubes of the first conductivity type are connected to the ground, and the grid electrodes of all the M MOS tubes of the first conductivity type are connected to the first end;
the source electrode of the nth MOS tube in the N MOS tubes of the first conduction type is connected with the drain electrode of the mth MOS tube in the M MOS tubes of the first conduction type, wherein N is more than or equal to 1 and M is more than or equal to N.
In a specific embodiment, the MOS transistors of the first conductivity type and the MOS transistors of the second conductivity type are:
NMOS transistor and PMOS transistor; or alternatively
PMOS pipe and NMOS pipe.
The invention has the following beneficial effects:
according to the technical scheme, the signal input and output unit adjusts the waveform of an input signal and the swing numerical control unit adjusts the reduction degree of the output swing of the output signal by the input and output unit through multi-bit digital control, and finally the purpose of adjusting and improving the dynamic performance of the DAC is achieved. In the signal input/output unit, the second MOS transistor of the first conductivity type and the fourth MOS transistor of the first conductivity type function to increase the low level value of the output signal, so as to raise the low voltage rail of the output swing and achieve the purpose of reducing the swing of the output signal. The second MOS tube of the second conductivity type and the third MOS tube of the second conductivity type are used for accelerating the rising of the output signal, so that the rising time of the output signal is shorter than the falling time, the output signal with a proper high overlapping point can be obtained by adjusting the size of each tube, the output signal is used as a switch control signal of a DAC current source, and the switch control signal with a low swing amplitude and a high overlapping point is beneficial to the optimization of the dynamic performance of the DAC.
The digital control signal unit in the swing numerical control unit can control the opening and closing of the corresponding branch by controlling the input values of the M digital control signal ends, and adjust the voltage value of the short-circuit point, namely the gate voltage values of the second MOS tube of the second conductivity type and the third MOS tube of the second conductivity type in the signal input and output unit, so that the purpose of controlling the swing of the output signal is achieved, and convenience is provided for the subsequent optimization of the dynamic performance of the DAC.
Drawings
In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are one embodiment of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a circuit diagram embodiment of a digitally controlled swing switch driver circuit according to an embodiment of the present invention.
Fig. 2 shows waveforms of output driving signals with high crossover points and digitally controlled swings, according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples. Variations and modifications may be made by those skilled in the art without departing from the principles of the invention and should be considered within the scope of the invention.
As shown in fig. 1, it is a circuit diagram of a digitally controlled switch driver circuit applied to a DAC according to an embodiment of the present invention. The circuit comprises: signal input/output unit 1, swing numerical control unit 2 and digital signal control unit 20.
The signal input and output unit 1 completes adjustment of input signal waveforms to optimize transient characteristics of current source switch currents of subsequent DACs. The first method of waveform adjustment is to reduce the output swing of the output signal to reduce the feedthrough effect of the switch signal, and the second method is directed to the DAC current source (in this embodiment, an NMOS switch current source) to make the output signal have a high overlap point, so as to prevent the differential switch from being turned off at the same time.
The swing numerical control unit 2 adjusts the reduction degree of the output swing of the output signal by the input and output unit 1 through digital control, so as to facilitate the subsequent optimization work of the DAC spurious-free dynamic range index.
Specifically, the signal input/output unit 1 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP 4.
An input signal VP of a pair of differential input signals VP and VN is input to a gate of the first NMOS transistor MN1 and a gate of the first PMOS transistor MP 1;
the input signal VN is input to the gate of the third NMOS transistor MN3 and the gate of the fourth PMOS transistor MP 4;
the source electrode of the first NMOS transistor MN1 and the source electrode of the third NMOS transistor MN3 are both connected to the ground GND;
the source electrode of the first PMOS pipe MP1 and the source electrode of the fourth PMOS pipe MP4 receive a power supply voltage VDD;
the second NMOS tube MN2 and the fourth NMOS tube MN4 both adopt a diode connection mode, namely the grid electrode of the second NMOS tube MN2 is in short circuit connection with the drain electrode thereof, and the grid electrode of the fourth NMOS tube MN4 is in short circuit connection with the drain electrode thereof;
the source electrode of the second NMOS transistor MN2 is connected with the drain electrode of the first NMOS transistor MN1, and the drain electrode is connected with the drain electrode of the first PMOS transistor MP 1;
the source electrode of the fourth NMOS tube MN4 is connected with the drain electrode of the third NMOS tube MN3, and the drain electrode of the fourth NMOS tube MP 4;
the source electrode of the second PMOS transistor MP2 and the source electrode of the third PMOS transistor MP3 receive a power supply voltage VDD;
the drain electrode of the second PMOS transistor MP2 is connected to the drain electrode of the first PMOS transistor MP1, the drain electrode of the third PMOS transistor MP3 is connected to the drain electrode of the fourth PMOS transistor MP4, and the gate electrode of the second PMOS transistor MP2 and the gate electrode of the third PMOS transistor MP3 are connected to each other and to the swing numerical control unit 2;
the output signal VOUTP is output by the drains of the fourth NMOS transistor MN4, the third PMOS transistor MP3 and the fourth PMOS transistor MP4, and the output signal VOUTN is output by the drains of the second NMOS transistor MN2, the first PMOS transistor MP1 and the second PMOS transistor MP 2.
The second NMOS transistor MN2 and the fourth NMOS transistor MN4 are used to increase the low level values of the output signals VOUTP and VOUTN, so as to raise the low voltage rail of the output swing and reduce the swing of the output signals. The second PMOS transistor MP2 and the third PMOS transistor MP3 are used to accelerate the rise of the output signal, so that the rise time of the output signal VOUTP, VOUTN is shorter than the fall time, and the output signal VOUTP, VOUTN with a proper high overlap point can be obtained by adjusting the size of each transistor.
Subsequently, the output signals VOUTP, VOUTN will be used as switch control signals for the DAC current sources, and the switch control signals with low swing and high overlap points are beneficial to optimizing the dynamic performance of the DAC.
In a specific embodiment, the swing numerical control unit 2 includes a first current source I1, a fifth NMOS transistor MN5, a fifth PMOS transistor MP5, and a digital control signal unit 20.
The first current source I1 and the fifth NMOS transistor MN5 generate bias voltages;
the grid electrode and the drain electrode of the fifth NMOS transistor MN5 are in short circuit and are connected to the output end of the first current source I1, and the source electrode is grounded;
the input end of the first current source I1 is connected with a power voltage VDD, and the gate of the fifth NMOS transistor MN5 outputs the bias voltage;
the gate of the fifth NMOS transistor MN5 is connected to the first end of the digital control signal unit 20;
the second end of the digital control signal unit is connected to the drain of the fifth PMOS transistor MP5, the source of the fifth PMOS transistor MP5 is connected to the supply voltage, and the gate and the drain of the fifth PMOS transistor MP5 are connected to a short circuit at a short-circuit point a in the figure and to the gate of the third PMOS transistor MP 3.
The voltage value of the point a, namely the gate voltage values of the second PMOS transistor MP2 and the third PMOS transistor MP3 in the signal input/output unit 1, is adjusted by controlling the input value of the digital control signal unit, so as to control the swing of the output signals VOUTP and VOUTN, and provide convenience for the subsequent optimization of the dynamic performance of the DAC.
In one embodiment, as shown in fig. 1, the digital control signal unit 20 includes sixth to eleventh NMOS transistors: MN6-MN 11;
the sources of the sixth NMOS transistor MN6, the eighth NMOS transistor MN8 and the tenth NMOS transistor MN10 are all connected to the GND, the gates are all connected with the bias voltage output by the gate of the fifth NMOS transistor MN5, and the current mirror structure is formed by the gate of the sixth NMOS transistor MN6, the eighth NMOS transistor MN8 and the fifth NMOS transistor MN 5;
the drain electrode of the sixth NMOS transistor MN6 is connected to the source electrode of the seventh NMOS transistor MN7, the drain electrode of the eighth NMOS transistor MN8 is connected to the source electrode of the ninth NMOS transistor MN9, and the drain electrode of the tenth NMOS transistor MN10 is connected to the source electrode of the eleventh NMOS transistor MN 11;
the gate of the seventh NMOS transistor MN7 is connected to the first digital control signal terminal C1 of the digital control signal unit, the gate of the ninth NMOS transistor MN9 is connected to the second digital control signal terminal C2, and the gate of the eleventh NMOS transistor MN11 is connected to the third digital control signal terminal C3;
the drain electrode of the seventh NMOS transistor MN7, the drain electrode of the ninth NMOS transistor MN9, and the drain electrode of the eleventh NMOS transistor MN11 are all connected to the drain electrode of the fifth PMOS transistor MP 5;
the source electrode of the fifth PMOS pipe MP5 is connected with the power supply voltage VDD;
the gate and the drain of the fifth PMOS transistor MP5 are connected in a short circuit, the short-circuit point a is connected to the gates of the second PMOS transistor MP2 and the third PMOS transistor MP3 in the signal input/output unit 1, and the second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror structure.
The on/off of the corresponding branch can be controlled by controlling the input values of the first digital control signal terminal C1, the second digital control signal terminal C2 and the third digital control signal terminal C3, and the voltage value of the point a, that is, the gate voltage values of the second PMOS transistor MP2 and the third PMOS transistor MP3 in the signal input/output unit 1, is adjusted, so as to control the swing of the output signals VOUTP and VOUTN, and provide convenience for the subsequent optimization of the dynamic performance of the DAC.
It should be noted that only three-bit digital control signal terminals C1, C2, and C3 and their connection circuits are provided in this embodiment, and optionally, in practical applications, a multi-bit digital control signal terminal may be provided according to practical situations to adjust the swing range of the output signal.
For example, the digital control signal unit 20 includes:
the first control element group comprises N MOS tubes of the first conductivity type;
the second control element group comprises M MOS tubes of the first conductivity type, wherein N is equal to or more than 1;
wherein, the first and the second end of the pipe are connected with each other,
the drains of all the MOS transistors of the N first conductivity type MOS transistors are connected to the second end, and the gates of all the MOS transistors of the N first conductivity type MOS transistors receive respective control signals respectively, so as to adjust the voltage value of the second end, and further control the swing amplitudes of the first output signal and the second output signal;
the source electrodes of all the M MOS tubes of the first conductivity type are connected to the ground, and the grid electrodes of all the M MOS tubes of the first conductivity type are connected to the first end;
the source electrode of the nth MOS tube of the N MOS tubes of the first conduction type is connected with the drain electrode of the mth MOS tube of the M MOS tubes of the first conduction type, wherein N is greater than or equal to 1 and is less than or equal to N.
Fig. 2 is a waveform diagram of an output drive signal with a high crossover point and a digitally controlled swing obtained by a circuit according to an embodiment of the present invention. Wherein 1 corresponds to the waveform diagram of the output driving signal obtained by the C1 on-time circuit; 2 corresponds to the waveform diagram of the output driving signal obtained by the circuit when the C1 and the C2 are simultaneously opened; and 3 corresponds to the waveform diagram of the output driving signal obtained by the circuit when C1, C2 and C3 are simultaneously turned on.
Wherein, the symbol GP is VOUTP and GN is VOUTN.
In addition, as can be understood by those skilled in the art, under the teaching of the present invention, as the NMOS transistor and the PMOS transistor in the embodiment in fig. 1 are interchanged, and the corresponding DAC current source is changed into a circuit obtained by a PMOS switching current source, and then the parameters of each device are specifically adjusted, so as to achieve the purpose of the present invention.
It should be understood that the above-described embodiments of the present invention are examples for clearly illustrating the invention, and are not to be construed as limiting the embodiments of the present invention, and it will be obvious to those skilled in the art that various changes and modifications can be made on the basis of the above description, and it is not intended to exhaust all embodiments, and obvious changes and modifications can be made on the basis of the technical solutions of the present invention.
Claims (4)
1. A digitally controlled switch driver circuit for use in a digital to analog converter, the circuit comprising: a signal input and output unit (1) and a swing amplitude numerical control unit (2),
wherein the content of the first and second substances,
the signal input and output unit is used for adjusting the waveform of an input signal and comprises a first MOS tube (MN1) of a first conduction type, a second MOS tube (MN2) of the first conduction type, a third MOS tube (MN3) of the first conduction type, a fourth MOS tube (MN4) of the first conduction type, a first MOS tube (MP1) of a second conduction type, a second MOS tube (MP2) of the second conduction type, a third MOS tube (MP3) of the second conduction type and a fourth MOS tube (MP4) of the second conduction type;
wherein, the first and the second end of the pipe are connected with each other,
the gate of the first MOS transistor (MN1) of the first conductivity type and the gate of the first MOS transistor (MP1) of the second conductivity type receive the first input signal (VP);
the gate of the third MOS transistor (MN3) of the first conductivity type and the gate of the fourth MOS transistor (MP4) of the second conductivity type receive the second input signal (VN);
the source electrode of the first MOS tube (MN1) of the first conduction type and the source electrode of the third MOS tube (MN3) of the first conduction type are both connected to the ground;
the source electrode of the first MOS transistor (MP1) of the second conduction type and the source electrode of the fourth MOS transistor (MP4) of the second conduction type receive a power supply voltage;
the grid electrode and the drain electrode of the second MOS tube (MN2) of the first conduction type are in short circuit connection;
the grid electrode and the drain electrode of a fourth MOS tube (MN4) of the first conduction type are in short circuit connection;
the source electrode of the second MOS tube (MN2) of the first conduction type is connected with the drain electrode of the first MOS tube (MN1) of the first conduction type, and the drain electrode of the second MOS tube (MN2) of the first conduction type is connected with the drain electrode of the first MOS tube (MP1) of the second conduction type;
the source electrode of the fourth MOS tube (MN4) of the first conduction type is connected with the drain electrode of the third MOS tube (MN3) of the first conduction type, and the drain electrode of the fourth MOS tube (MN4) of the first conduction type is connected with the drain electrode of the fourth MOS tube (MP4) of the second conduction type;
the source electrode of the second MOS tube (MP2) of the second conduction type and the source electrode of the third MOS tube (MP3) of the second conduction type receive a power supply voltage, and the drain electrode of the second MOS tube (MP2) of the second conduction type is connected with the drain electrode of the first MOS tube (MP1) of the second conduction type;
the drain electrode of the third MOS tube (MP3) of the second conduction type is connected with the drain electrode of the fourth MOS tube (MP4) of the second conduction type;
the grid electrode of the second MOS tube (MP2) of the second conduction type and the grid electrode of the third MOS tube (MP3) of the second conduction type are mutually connected and are connected to the swing numerical control unit;
the first output signal (VOUTP) is output by the drain electrode of the fourth MOS transistor (MN4) of the first conductivity type, and the output signal (VOUTN) of the second signal output end is output by the drain electrode of the second MOS transistor (MN2) of the first conductivity type;
the swing numerical control unit adjusts the output swing of the output signal of the input and output unit through digital control.
2. The circuit of claim 1, wherein the swing numerical control unit comprises: a first current source (I1), a fifth MOS transistor (MN5) of the first conductivity type, a fifth MOS transistor (MP5) of the second conductivity type and a digital control signal unit (20);
wherein the content of the first and second substances,
the gate and the drain of the fifth MOS transistor (MN5) of the first conductivity type are in short circuit connection and are connected to the output end of the first current source (I1), and the source is grounded;
the input end of the first current source (I1) is connected with the power voltage;
the grid electrode of a fifth MOS tube (MN5) of the first conduction type is connected with the first end of the digital control signal unit;
the second end of the digital control signal unit is connected to the drain of the fifth MOS transistor (MP5) of the second conductivity type, the source of the fifth MOS transistor (MP5) of the second conductivity type is connected to a power supply voltage, and the gate and the drain of the fifth MOS transistor (MP5) of the second conductivity type are connected to a short circuit and to the gate of the third MOS transistor (MP3) of the second conductivity type.
3. The circuit according to claim 2, wherein the digital control signal unit (20) comprises:
the first control element group comprises N MOS tubes of the first conductivity type;
the second control element group comprises M MOS tubes of the first conductivity type, wherein N is equal to or more than 1;
wherein, the first and the second end of the pipe are connected with each other,
the drains of all the MOS transistors of the N first conductivity type MOS transistors are connected to the second end, and the gates of all the MOS transistors of the N first conductivity type MOS transistors receive respective control signals respectively, so as to adjust the voltage value of the second end, and further control the swing amplitudes of the first output signal and the second output signal;
the source electrodes of all the MOS tubes in the M MOS tubes of the first conduction type are connected to the ground, and the grid electrodes of all the MOS tubes of the M MOS tubes of the first conduction type are connected to the first end;
the source electrode of the nth MOS tube in the N MOS tubes of the first conduction type is connected with the drain electrode of the mth MOS tube in the M MOS tubes of the first conduction type, wherein N is more than or equal to 1 and M is more than or equal to N.
4. The circuit according to any one of claims 1-3, wherein the MOS transistors of the first conductivity type and the MOS transistors of the second conductivity type are:
an NMOS tube and a PMOS tube; or
PMOS pipe and NMOS pipe.
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| US10931249B2 (en) * | 2018-06-12 | 2021-02-23 | Kandou Labs, S.A. | Amplifier with adjustable high-frequency gain using varactor diodes |
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| EP1653623A1 (en) * | 2004-10-29 | 2006-05-03 | Broadcom Corporation | Method and system for a glitch-free differential current steering switch circuit for high speed, high resolution digital-to-analog conversion |
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