CN104079246A - Low power consumption high slew rate high gain bandwidth product fully differential operational amplifier - Google Patents
Low power consumption high slew rate high gain bandwidth product fully differential operational amplifier Download PDFInfo
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Abstract
The invention discloses a low power consumption high slew rate high gain bandwidth product fully differential operational amplifier. An operational amplifier circuit adopts an input stage current extraction structure and partially extracts currents inside a load pipe through an active current mirror to reduce the effective resistance of the operational amplifier; slew rate enhancing circuits are in parallel connection with bilateral sides of a main operational amplifier to enhance the slew rate of output signals; an output stage applies a Class-AB output structure. According to the low power consumption high slew rate high gain bandwidth product fully differential operational amplifier, the current mirror is connected to an input end load pipe in a parallel mode, the effect of transconductance reduction is achieved due to adjustment of the breadth length ratio of the current mirror, and accordingly the integral circuit keeps the gain bandwidth product and satisfies the integral modulator required level under the condition that the power consumption is reduced and a feedforward structure is connected to the operational amplifier in a parallel mode to inject compensating current for the load to increase the slew rate of the output signals when the operational amplifier is in a working state and transient state power consumption is not consumed excessively.
Description
Technical field
The invention belongs to analog integrated circuit technical field, be specifically related to the long-pending Full differential operational amplifier of the high Slew Rate high gain-bandwidth of a kind of low-power consumption.
Background technology
Present portable electric appts of all kinds is just moving towards huge numbers of families and each industrial application.Data converter is as the interface between analog signal and digital signal, and demand is increasing.Delta-sigma modulator can be realized exclusive high accuracy, applies very extensive.In delta-sigma modulator, in integrator the design of amplifier most important, the amplifier of prime especially, the noise of its generation is maximum to the contribution of modulator output overall noise.
Amplifier is applied in delta-sigma modulator, as first order integrator, works.In integrator, the limited DC gain of amplifier causes static receiver error, limited GBW (gain bandwidth product) and SR (slew rate) cause dynamic error, these errors all refer to the value of integrator time-domain response after stable and the deviation between ideal value, can be integrated into noise, these noises all result from the output of integrator.
As can be seen from Figure 1, the static dynamic noise of first order integrator is to the noise transfer function of modulator output close to straight-through 1, and more to rear class, static dynamic noise is shaped more severely.Therefore, be also that the noise of first order integrator has the greatest impact to modulator output performance, corresponding design parameter also can be the harshest.From some integrator non-ideal factor the calculated results, can analyze and draw, amplifier Slew Rate and gain bandwidth product index request in first order integrator are very high, and this is also the main challenge in the modulator design of the very fast clock frequency of high voltage.
Conventional operational amplifier has two classes at present: single stage operational amplifier (as shown in Figure 2) and the miller-compensated operational amplifier of two-stage (as shown in Figure 3).Single stage operational amplifier structure is the simplest, but will realize high-gain and high Slew Rate must have very large tail current, and high-gain and high Slew Rate can not be provided in the situation of low-power consumption, so few people use.The miller-compensated operational amplifier of two-stage is comparatively conventional, designs simplyr, and gain is very high, and phase margin is also abundant, however larger tail current and the output stage electric current of its stability requirement, and this will increase power consumption; Once exigent output Slew Rate, the electric current needing so only can be larger.Do not meet in this requirement of delta-sigma modulator.
Summary of the invention
For the existing above-mentioned technical problem of prior art, the invention provides the long-pending Full differential operational amplifier of the high Slew Rate high gain-bandwidth of a kind of low-power consumption, by current draw technology, improved gain bandwidth product, reduced power consumption simultaneously, and utilize slew rate enhancing circuit to increase Slew Rate, and make the big upgrade of delta-sigma modulator performance, effectively reduce system power dissipation.
The long-pending Full differential operational amplifier of the high Slew Rate high gain-bandwidth of low-power consumption, comprising:
Main operation amplifier unit;
Slew Rate enhancement unit, for improving the Slew Rate of main operational amplifier output difference sub-signal;
Common mode feedback unit, averages amplification for the output difference sub-signal to described, so that two-way common-mode voltage feedback signal cmfb1～cmfb2 to be provided to main operational amplifier;
Described main operational amplifier is according to two-way common-mode voltage feedback signal cmfb1～cmfb2, and applied current extraction technique to the input differential signal amplification that gains, obtains described output difference sub-signal under the environment of low-power consumption.
Described main operation amplifier unit comprises 21 metal-oxide-semiconductor M1～M21, four resistance R 1～R4 and two capacitor C 1～C2, wherein, the source electrode of the source electrode of metal-oxide-semiconductor M18 and metal-oxide-semiconductor M13, the source electrode of metal-oxide-semiconductor M3, the source electrode of metal-oxide-semiconductor M5, the source electrode of metal-oxide-semiconductor M6, the source electrode of metal-oxide-semiconductor M4, the source electrode of metal-oxide-semiconductor M14, the source electrode of metal-oxide-semiconductor M19, the drain electrode of the drain electrode of metal-oxide-semiconductor M7 and metal-oxide-semiconductor M8 connects altogether and connects supply voltage, and the grid of metal-oxide-semiconductor M18 is connected with the grid of metal-oxide-semiconductor M19 and receives common-mode voltage feedback signal cmfb1, the drain electrode of the drain electrode of metal-oxide-semiconductor M18 and metal-oxide-semiconductor M13, the drain electrode of metal-oxide-semiconductor M15, one end of the drain electrode of metal-oxide-semiconductor M20 and capacitor C 1 is connected and produces anodal output difference sub-signal, one end of the grid of metal-oxide-semiconductor M13 and resistance R 1, the drain electrode of metal-oxide-semiconductor M3, the drain electrode of metal-oxide-semiconductor M5, the drain electrode of metal-oxide-semiconductor M1 is connected with the grid of metal-oxide-semiconductor M8, and the other end of resistance R 1 is connected with the grid of metal-oxide-semiconductor M3, and the grid of metal-oxide-semiconductor M5 is connected with the grid of metal-oxide-semiconductor M6 and receives given bias voltage Vbp, the drain electrode of the drain electrode of metal-oxide-semiconductor M6 and metal-oxide-semiconductor M4, one end of resistance R 2, the grid of metal-oxide-semiconductor M14, the grid of metal-oxide-semiconductor M7 is connected with the drain electrode of metal-oxide-semiconductor M2, and the other end of resistance R 2 is connected with the grid of metal-oxide-semiconductor M4, the drain electrode of the drain electrode of metal-oxide-semiconductor M14 and metal-oxide-semiconductor M19, one end of capacitor C 2, the drain electrode of the drain electrode of metal-oxide-semiconductor M16 and metal-oxide-semiconductor M21 is connected and produces negative pole output difference sub-signal, the drain electrode of the source electrode of metal-oxide-semiconductor M7 and metal-oxide-semiconductor M9, the drain electrode of metal-oxide-semiconductor M11, the grid of metal-oxide-semiconductor M15 is connected with one end of resistance R 3, the other end of resistance R 3 is connected with the grid of metal-oxide-semiconductor M9, the grid of metal-oxide-semiconductor M11 is connected with the grid of metal-oxide-semiconductor M17 and the grid of metal-oxide-semiconductor M12 and receives given bias voltage Vbn, the drain electrode of metal-oxide-semiconductor M17 is connected with the source electrode of metal-oxide-semiconductor M2 with the source electrode of metal-oxide-semiconductor M1, the grid of metal-oxide-semiconductor M1 receives anodal input differential signal, the grid of metal-oxide-semiconductor M2 receives negative pole input differential signal, the drain electrode of the source electrode of metal-oxide-semiconductor M8 and metal-oxide-semiconductor M12, the drain electrode of metal-oxide-semiconductor M10, the grid of metal-oxide-semiconductor M16 is connected with one end of resistance R 4, the other end of resistance R 4 is connected with the grid of metal-oxide-semiconductor M10, the grid of metal-oxide-semiconductor M20 is connected with the grid of metal-oxide-semiconductor M21 and receives common-mode voltage feedback signal cmfb2, the other end of the source electrode of metal-oxide-semiconductor M20 and capacitor C 1, the source electrode of metal-oxide-semiconductor M15, the source electrode of metal-oxide-semiconductor M9, the source electrode of metal-oxide-semiconductor M11, the source electrode of metal-oxide-semiconductor M17, the source electrode of metal-oxide-semiconductor M12, the source electrode of metal-oxide-semiconductor M10, the source electrode of metal-oxide-semiconductor M16, the other end of the source electrode of metal-oxide-semiconductor M21 and capacitor C 2 connects and ground connection altogether, metal-oxide-semiconductor M18, M13, M3, M5, M6, M4, M14 and M19 adopt PMOS pipe, and metal-oxide-semiconductor M7, M8, M1, M2, M20, M15, M9, M11, M17, M12, M10, M16 and M21 adopt NMOS pipe.
Described Slew Rate enhancement unit comprises two slew rate enhancing circuits, and described slew rate enhancing circuit comprises nine metal-oxide-semiconductor N1～N9, wherein, the source electrode of the source electrode of metal-oxide-semiconductor N7 and metal-oxide-semiconductor N5, the source electrode of metal-oxide-semiconductor N3, the source electrode of metal-oxide-semiconductor N4, the source electrode of the source electrode of metal-oxide-semiconductor N6 and metal-oxide-semiconductor N8 connects altogether and connects supply voltage, the grid of the grid of metal-oxide-semiconductor N7 and metal-oxide-semiconductor N5, the drain electrode of metal-oxide-semiconductor N5, the drain electrode of metal-oxide-semiconductor N3 is connected with the drain electrode of metal-oxide-semiconductor N1, the drain electrode of metal-oxide-semiconductor N7 connects the cathode output end of main operation amplifier unit, the grid of metal-oxide-semiconductor N1 receives anodal input differential signal, the source electrode of metal-oxide-semiconductor N1 is connected with the source electrode of metal-oxide-semiconductor N9 with the source electrode of metal-oxide-semiconductor N2, the grid of metal-oxide-semiconductor N3 is connected and receives given reference voltage V REF1 with the grid of metal-oxide-semiconductor N4, the grid of metal-oxide-semiconductor N9 receives given reference voltage V REF2, the source ground of metal-oxide-semiconductor N9, the grid of the grid of metal-oxide-semiconductor N8 and metal-oxide-semiconductor N6, the drain electrode of metal-oxide-semiconductor N6, the drain electrode of metal-oxide-semiconductor N4 is connected with the drain electrode of metal-oxide-semiconductor N2, the drain electrode of metal-oxide-semiconductor N8 connects the cathode output end of main operation amplifier unit, the grid of metal-oxide-semiconductor N2 receives negative pole input differential signal, metal-oxide-semiconductor N3～N8 adopts PMOS pipe, and metal-oxide-semiconductor N1, N2 and N9 adopt NMOS pipe.
Described common mode feedback unit comprises nine metal-oxide-semiconductor Q1～Q9 and two capacitor C 3～C4, wherein, the source electrode of the source electrode of metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q2, the source electrode of the source electrode of metal-oxide-semiconductor Q3 and metal-oxide-semiconductor Q4 connects altogether and connects supply voltage, the drain electrode of the grid of metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q1, the drain electrode of the drain electrode of metal-oxide-semiconductor Q2 and metal-oxide-semiconductor Q5 is connected and produces common-mode voltage feedback signal cmfb1, the grid of metal-oxide-semiconductor Q2 receives given bias voltage Vbp, the grid of the grid of metal-oxide-semiconductor Q3 and metal-oxide-semiconductor Q4, the drain electrode of metal-oxide-semiconductor Q3 is connected with the drain electrode of metal-oxide-semiconductor Q6, the drain electrode of the drain electrode of metal-oxide-semiconductor Q4 and metal-oxide-semiconductor Q7, the grid of the drain electrode of metal-oxide-semiconductor Q8 and metal-oxide-semiconductor Q7 is connected and produces common-mode voltage feedback signal cmfb2, the source electrode of metal-oxide-semiconductor Q5 is connected with the drain electrode of metal-oxide-semiconductor Q9 with the source electrode of metal-oxide-semiconductor Q6, the grid of metal-oxide-semiconductor Q5 receives given common-mode voltage vcmo, the grid of metal-oxide-semiconductor Q6 is connected with one end of capacitor C 4 with one end of capacitor C 3, the cathode output end of the main operation amplifier of another termination unit of capacitor C 3, the cathode output end of the main operation amplifier of another termination unit of capacitor C 4, the grid of metal-oxide-semiconductor Q9 is connected with the grid of metal-oxide-semiconductor Q8 and receives given bias voltage Vbn, the source electrode of the source electrode of the source electrode of metal-oxide-semiconductor Q9 and metal-oxide-semiconductor Q7 and metal-oxide-semiconductor Q8 connects and ground connection altogether, metal-oxide-semiconductor Q1～Q4 adopts PMOS pipe, and metal-oxide-semiconductor Q5～Q9 adopts NMOS pipe.
Discharge circuit of the present invention adopts input stage current draw structure, utilizes active electric current mirror partly to extract the electric current in load pipe, to reduce its effective resistance; At main amplifier both sides parallel connection slew rate enhancing circuit, be used for strengthening the Slew Rate of output signal simultaneously, and output stage application Class-AB export structure.The present invention is parallel-current mirror on the input load pipe of operational amplifier first, and calculate the size of current draw, regulate as required the breadth length ratio of current mirror, make the electric current flowing through in the metal-oxide-semiconductor of diode connection reduce respective value, and then reaching the effect that reduces mutual conductance, this structure has also been applied in output stage simultaneously.Integrated circuit has kept gain bandwidth product to meet the level that whole modulator requires under the condition of power-dissipation-reduced like this; Moreover, consider that main circuit is difficult to meet the whole requirement of system in Slew Rate.But require can not roll up again output stage electric current and input pipe tail current under the pressure of power consumption, therefore feed forward architecture in parallel on operational amplifier, when amplifier is in running order, be that load injecting compensating electric current is used the Slew Rate of signal to increase, and can not consume too much transient power consumption.
Compared with prior art, the present invention has the following advantages and technique effect:
(1) power consumption is extremely low.Owing to having used current draw structure, in the situation that tail current remains unchanged, by output resistance being brought up to 1/ original (1-k), improve DC gain, and equivalent transconductance Gm does not change; In output stage, owing to extracting the effect of electric current, keeping can suitably increasing current mirror image ratio under the condition that output stage electric current is constant, thereby increasing Gm, gain and GBW are also improved.In main amplifier, four compensating resistance R1～R4 are mainly used in isolating the parasitic capacitance of respective diode connection pipe, are equivalent to introduce zero point on frequency domain, push away time limit far away, increase the stability of amplifier in the environment of low-power consumption.
(2) Slew Rate of main amplifier is greatly improved.By the lifting of slew rate enhancing circuit, main amplifier Slew Rate is promoted to original twice, and does not consume too much extra power consumption, therefore can meet the requirement of delta-sigma ADC, while making it be operated in audio signal, can not produce distortion, greatly reduce power consumption meeting under the prerequisite of design objective.Under the signal input that it is-4.35dB that emulation shows in amplitude, signal to noise ratio has reached 106.4dB, and power consumption and quality factor are only 3.86mW and 565.75fJ/Conversion-step respectively.
Accompanying drawing explanation
Fig. 1 is that static state and dynamic noise are to the noise transfer function schematic diagram of modulator output.
Fig. 2 is the structural representation of single stage operational amplifier.
Fig. 3 is the structural representation of the miller-compensated operational amplifier of two-stage.
Fig. 4 is the structural representation of Full differential operational amplifier of the present invention.
Fig. 5 is the structural representation of main operation amplifier unit.
Fig. 6 is the structural representation of slew rate enhancing circuit.
Fig. 7 is the structural representation of common mode feedback unit.
Fig. 8 is that first order amplifier is about the AC response characteristic Simulation oscillogram of phase place and gain.
Fig. 9 is that first order amplifier is about the common mode loop response characteristic simulation waveform figure of phase place and gain.
Embodiment
In order more specifically to describe the present invention, below in conjunction with the drawings and the specific embodiments, technical scheme of the present invention is elaborated.
As shown in Figure 4, the long-pending Full differential operational amplifier of the high Slew Rate high gain-bandwidth of a kind of low-power consumption, comprising: main amplifier unit, two slew rate enhancing circuits and common mode feedback unit.
Due to the large input and output amplitude of oscillation and fast clock frequency, the gain bandwidth product that amplifier is required and Slew Rate are all very high, and design difficulty is large.After the comparison of amplifier structure and literature survey, amplifier finally adopts one-level current-mirror structure and Class-AB output, and has introduced current draw technology, resnstance transformer and Slew Rate enhancing technology, saves to greatest extent power consumption under the requirement that meets design objective.
Therefore present embodiment adopts main amplifier cellular construction as shown in Figure 5, one-level current-mirror structure, Class-AB output stage guarantees identical positive and negative Slew Rate.Pipe M5 and M6 are as current source, from inputting the drain current I to pipe M1 and M2
1in extracted one part of current kI
1(0<k<1), greatly improved the DC gain of one-level current-mirror structure amplifier, its expression formula is shown below:
Wherein: g
m, I
1, V
gs, V
th, λ is respectively the long index of modulation of mutual conductance, transient current, gate source voltage, threshold voltage and ditch of respective tubes, B
1and B
2be respectively corresponding current mirror image ratio.From above formula, can obtain the equivalent transconductance G of amplifier
mwith output resistance R
out:
In addition, by Fig. 5, can be obtained:
I
13,15＝B
1(1-k)I
1
Therefore, current draw technology improves DC gain by output resistance being brought up to 1/ original (1-k), and equivalent transconductance G
mdo not change.Now the gain bandwidth product gain bandwidth product expression formula of amplifier is as follows:
Gain bandwidth product is also constant as can be seen here.Yet, owing to extracting the effect of electric current, keeping can suitably increasing B under the condition that output stage electric current is constant
1and B
2, increase G
m, gain and gain bandwidth product are also improved accordingly.
In this amplifier structure, dominant pole is positioned at output, and two limits lay respectively at the drain node of M3 and M9.In design physical circuit, make on the one hand the electric current that flows through M13, M14 and M15, M16 equate as far as possible, guarantee that working point is correct; On the other hand primary and secondary pole location and output stage electric current to be rationally set, meet the requirement of DC gain and phase margin simultaneously.Four compensating resistance R1～R4 are mainly used in isolating the parasitic capacitance of respective diode connection pipe, are equivalent to introduce zero point on frequency domain, push away time limit far away, increase the stability of amplifier.
As shown in Figure 7, two electric capacity are obtained actual output common mode level to the circuit structure of common mode feedback unit, through error amplifier, feed back to amplifier output.In the idle half period of amplifier, half supply voltage (common-mode voltage) is all received at electric capacity two ends, refreshes.Error amplifier adopts one-level current-mirror structure, and good stability, does not need miller compensation and speed fast.By being connected in parallel on two pipes of amplifier output upper and lower, feed back, further improved the speed of common-mode feedback.In addition, in common mode feedback circuit, introduce current draw technology, under the prerequisite that does not consume too much power consumption, improved gain and the gain bandwidth product of common mode loop.In general, the gain bandwidth product of common mode loop at least will reach 1/3 of main amplifier.
For the main amplifier structure of Fig. 5, if more than Slew Rate is brought up to 15V/ μ s, the power consumption of consumption will be very large.In order to address this problem, many Slew Rate enhancing technology are suggested.Its basic thought is to increase dynamic bias circuit on the basis of quiescent biasing.When input amplitude is smaller, the tail current of amplifier self provides all pipes required quiescent current, and now dynamic bias circuit is not worked; When input amplitude surpasses after the treatable threshold value of Slew Rate, dynamic bias circuit is started working, and for amplifier provides extra electric current, amplifier output can be responded.Simple directly method is exactly directly the tail current of amplifier to be carried out to a dynamic compensation when large-signal is inputted, but when increasing tail current, has also increased the electric current of other all pipes, cannot reduce power consumption, also can make pipe bear excessive electric current.
For fear of the problems referred to above, to output loading dynamic compensation, be directly a better selection.Present embodiment adopts as the slew rate enhancing circuit of Fig. 6 structure, is divided into upper and lower two parts, and this figure is the first half.Same road current offset for tail pipe N9 and current draw pipe N3, N4 etc., arranges half that quiescent current that its breadth length ratio makes N3, N4 is slightly smaller than N9.When small-signal is inputted like this, N3, N4 are in linear zone, and N7 and N5 are off state.When large-signal is inputted, such as Vin+ is far longer than Vin-, right current draw pipe N4 is still in linear zone, and N2 enters saturation region, its drain terminal voltage drop, and N3 and N4 conducting, to Vout+ load injecting compensating electric current.Meanwhile, the right circuit of the latter half is started working equally, to Vout-load injecting compensating electric current; On the contrary, if Vin-is far longer than Vin+, the right circuit of the first half and the left side circuit of the latter half are started working, compensation output load current.By such mode, Slew Rate is increased, and does not consume too much transient power consumption.
It is very general that this Slew Rate strengthens technology, is suitable for the circuit that great majority need to strengthen Slew Rate.One that in design, should be noted that is the cut-in voltage of slew rate enhancing circuit, within the scope of the input amplitude of oscillation, compromise and choose, and too low there is no need, also can increase dynamic power consumption, the too high effect that do not have.Another Slew Rate that it should be noted that main amplifier self can not be too little, otherwise easily cause unstable.In addition, the current mirror of responsible charging stream is as the rationally setting of the image ratio of N3 and N4, and ratio is too little, and compensation effect is not obvious; Ratio is too high, easily causes overshoot.Meanwhile, the area of four efferent ducts such as N7, N8 can design a little bit smallerly, to suppress overshoot phenomenon.
Table 1 is the simulation result of first order amplifier, and emulation load capacitance value used can be exported by calculating termination all capacitances when amplifier is worked obtain.DC current gain, gain bandwidth product and the Slew Rate that can see first order amplifier all meet design requirement, and the gain bandwidth product of common mode loop has also reached 1/3 of amplifier.The AC response of amplifier, common mode loop respond as shown in Figure 8 and Figure 9.
By the time-domain response of amplifier, can be seen within the scope of the input amplitude of oscillation (interval 0.1V), better more stably response is got up.Curve chart is not still very smooth, is mainly that compensating resistance causes.The Slew Rate of main amplifier itself is thus lifted to original twice.Make the large lifting of precision of whole system.
Table 1
Total transient current of amplifier consumption is 206.93uA.Simulation result is all higher than design objective as can be seen from Table 1, and this is that partial results is shown in table 2 for the consideration in process corner.Because the dominant pole of amplifier is positioned at output node, so the process corner of electric capacity is very large to amplifier performance impact, needs enough design capacities.Under different process corner, this amplifier can be stablized normal work as can be seen from Table 2
Table 2
| Corner (process corner) | PM (phase margin) | GBW/MHz |
| tt1 | 57.0533 | 54.3022 |
| tt10 | 54.2742 | 77.4528 |
| tt11 | 65.8185 | 56.2049 |
| tt12 | 60.9571 | 66.828 |
| tt13 | 43.7157 | 100.021 |
| tt14 | 59.5422 | 74.6592 |
| tt15 | 50.3297 | 88.5995 |
| tt16 | 49.34 | 87.7744 |
| tt17 | 64.8443 | 65.4561 |
| tt18 | 57.7117 | 75.6282 |
| tt19 | 57.0655 | 46.2625 |
| tt2 | 65.5327 | 41.991 |
| tt20 | 64.3028 | 34.5032 |
| tt21 | 61.0402 | 39.28 |
| tt22 | 58.9564 | 51.2213 |
| tt23 | 68.3688 | 36.9098 |
| tt24 | 64.3986 | 44.0652 |
| tt25 | 58.4969 | 48.5575 |
| tt26 | 66.4667 | 35.4585 |
| tt27 | 63.0686 | 41.4956 |
| tt3 | 61.9406 | 48.1462 |
| tt4 | 56.2162 | 66.9297 |
| tt5 | 68.2637 | 48.4338 |
| tt6 | 62.8386 | 54.9295 |
| tt7 | 57.7156 | 60.142 |
| tt8 | 67.5125 | 44.9072 |
| tt9 | 63.1986 | 51.2154 |
Claims (4)
1. the long-pending Full differential operational amplifier of the high Slew Rate high gain-bandwidth of low-power consumption, is characterized in that, comprising:
Main operation amplifier unit;
Slew Rate enhancement unit, for improving the Slew Rate of main operational amplifier output difference sub-signal;
Common mode feedback unit, averages amplification for the output difference sub-signal to described, so that two-way common-mode voltage feedback signal cmfb1～cmfb2 to be provided to main operational amplifier;
Described main operational amplifier is according to two-way common-mode voltage feedback signal cmfb1～cmfb2, and applied current extraction technique to the input differential signal amplification that gains, obtains described output difference sub-signal under the environment of low-power consumption.
2. Full differential operational amplifier according to claim 1, is characterized in that: described main operation amplifier unit comprises 21 metal-oxide-semiconductor M1～M21, four resistance R 1～R4 and two capacitor C 1～C2, wherein, the source electrode of the source electrode of metal-oxide-semiconductor M18 and metal-oxide-semiconductor M13, the source electrode of metal-oxide-semiconductor M3, the source electrode of metal-oxide-semiconductor M5, the source electrode of metal-oxide-semiconductor M6, the source electrode of metal-oxide-semiconductor M4, the source electrode of metal-oxide-semiconductor M14, the source electrode of metal-oxide-semiconductor M19, the drain electrode of the drain electrode of metal-oxide-semiconductor M7 and metal-oxide-semiconductor M8 connects altogether and connects supply voltage, and the grid of metal-oxide-semiconductor M18 is connected with the grid of metal-oxide-semiconductor M19 and receives common-mode voltage feedback signal cmfb1, the drain electrode of the drain electrode of metal-oxide-semiconductor M18 and metal-oxide-semiconductor M13, the drain electrode of metal-oxide-semiconductor M15, one end of the drain electrode of metal-oxide-semiconductor M20 and capacitor C 1 is connected and produces anodal output difference sub-signal, one end of the grid of metal-oxide-semiconductor M13 and resistance R 1, the drain electrode of metal-oxide-semiconductor M3, the drain electrode of metal-oxide-semiconductor M5, the drain electrode of metal-oxide-semiconductor M1 is connected with the grid of metal-oxide-semiconductor M8, and the other end of resistance R 1 is connected with the grid of metal-oxide-semiconductor M3, and the grid of metal-oxide-semiconductor M5 is connected with the grid of metal-oxide-semiconductor M6 and receives given bias voltage Vbp, the drain electrode of the drain electrode of metal-oxide-semiconductor M6 and metal-oxide-semiconductor M4, one end of resistance R 2, the grid of metal-oxide-semiconductor M14, the grid of metal-oxide-semiconductor M7 is connected with the drain electrode of metal-oxide-semiconductor M2, and the other end of resistance R 2 is connected with the grid of metal-oxide-semiconductor M4, the drain electrode of the drain electrode of metal-oxide-semiconductor M14 and metal-oxide-semiconductor M19, one end of capacitor C 2, the drain electrode of the drain electrode of metal-oxide-semiconductor M16 and metal-oxide-semiconductor M21 is connected and produces negative pole output difference sub-signal, the drain electrode of the source electrode of metal-oxide-semiconductor M7 and metal-oxide-semiconductor M9, the drain electrode of metal-oxide-semiconductor M11, the grid of metal-oxide-semiconductor M15 is connected with one end of resistance R 3, the other end of resistance R 3 is connected with the grid of metal-oxide-semiconductor M9, the grid of metal-oxide-semiconductor M11 is connected with the grid of metal-oxide-semiconductor M17 and the grid of metal-oxide-semiconductor M12 and receives given bias voltage Vbn, the drain electrode of metal-oxide-semiconductor M17 is connected with the source electrode of metal-oxide-semiconductor M2 with the source electrode of metal-oxide-semiconductor M1, the grid of metal-oxide-semiconductor M1 receives anodal input differential signal, the grid of metal-oxide-semiconductor M2 receives negative pole input differential signal, the drain electrode of the source electrode of metal-oxide-semiconductor M8 and metal-oxide-semiconductor M12, the drain electrode of metal-oxide-semiconductor M10, the grid of metal-oxide-semiconductor M16 is connected with one end of resistance R 4, the other end of resistance R 4 is connected with the grid of metal-oxide-semiconductor M10, the grid of metal-oxide-semiconductor M20 is connected with the grid of metal-oxide-semiconductor M21 and receives common-mode voltage feedback signal cmfb2, the other end of the source electrode of metal-oxide-semiconductor M20 and capacitor C 1, the source electrode of metal-oxide-semiconductor M15, the source electrode of metal-oxide-semiconductor M9, the source electrode of metal-oxide-semiconductor M11, the source electrode of metal-oxide-semiconductor M17, the source electrode of metal-oxide-semiconductor M12, the source electrode of metal-oxide-semiconductor M10, the source electrode of metal-oxide-semiconductor M16, the other end of the source electrode of metal-oxide-semiconductor M21 and capacitor C 2 connects and ground connection altogether, metal-oxide-semiconductor M18, M13, M3, M5, M6, M4, M14 and M19 adopt PMOS pipe, and metal-oxide-semiconductor M7, M8, M1, M2, M20, M15, M9, M11, M17, M12, M10, M16 and M21 adopt NMOS pipe.
3. Full differential operational amplifier according to claim 1, is characterized in that: described Slew Rate enhancement unit comprises two slew rate enhancing circuits, and described slew rate enhancing circuit comprises nine metal-oxide-semiconductor N1～N9, wherein, the source electrode of the source electrode of metal-oxide-semiconductor N7 and metal-oxide-semiconductor N5, the source electrode of metal-oxide-semiconductor N3, the source electrode of metal-oxide-semiconductor N4, the source electrode of the source electrode of metal-oxide-semiconductor N6 and metal-oxide-semiconductor N8 connects altogether and connects supply voltage, the grid of the grid of metal-oxide-semiconductor N7 and metal-oxide-semiconductor N5, the drain electrode of metal-oxide-semiconductor N5, the drain electrode of metal-oxide-semiconductor N3 is connected with the drain electrode of metal-oxide-semiconductor N1, the drain electrode of metal-oxide-semiconductor N7 connects the cathode output end of main operation amplifier unit, the grid of metal-oxide-semiconductor N1 receives anodal input differential signal, the source electrode of metal-oxide-semiconductor N1 is connected with the source electrode of metal-oxide-semiconductor N9 with the source electrode of metal-oxide-semiconductor N2, the grid of metal-oxide-semiconductor N3 is connected and receives given reference voltage V REF1 with the grid of metal-oxide-semiconductor N4, the grid of metal-oxide-semiconductor N9 receives given reference voltage V REF2, the source ground of metal-oxide-semiconductor N9, the grid of the grid of metal-oxide-semiconductor N8 and metal-oxide-semiconductor N6, the drain electrode of metal-oxide-semiconductor N6, the drain electrode of metal-oxide-semiconductor N4 is connected with the drain electrode of metal-oxide-semiconductor N2, the drain electrode of metal-oxide-semiconductor N8 connects the cathode output end of main operation amplifier unit, the grid of metal-oxide-semiconductor N2 receives negative pole input differential signal, metal-oxide-semiconductor N3～N8 adopts PMOS pipe, and metal-oxide-semiconductor N1, N2 and N9 adopt NMOS pipe.
4. Full differential operational amplifier according to claim 1, is characterized in that: described common mode feedback unit comprises nine metal-oxide-semiconductor Q1～Q9 and two capacitor C 3～C4, wherein, the source electrode of the source electrode of metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q2, the source electrode of the source electrode of metal-oxide-semiconductor Q3 and metal-oxide-semiconductor Q4 connects altogether and connects supply voltage, the drain electrode of the grid of metal-oxide-semiconductor Q1 and metal-oxide-semiconductor Q1, the drain electrode of the drain electrode of metal-oxide-semiconductor Q2 and metal-oxide-semiconductor Q5 is connected and produces common-mode voltage feedback signal cmfb1, the grid of metal-oxide-semiconductor Q2 receives given bias voltage Vbp, the grid of the grid of metal-oxide-semiconductor Q3 and metal-oxide-semiconductor Q4, the drain electrode of metal-oxide-semiconductor Q3 is connected with the drain electrode of metal-oxide-semiconductor Q6, the drain electrode of the drain electrode of metal-oxide-semiconductor Q4 and metal-oxide-semiconductor Q7, the grid of the drain electrode of metal-oxide-semiconductor Q8 and metal-oxide-semiconductor Q7 is connected and produces common-mode voltage feedback signal cmfb2, the source electrode of metal-oxide-semiconductor Q5 is connected with the drain electrode of metal-oxide-semiconductor Q9 with the source electrode of metal-oxide-semiconductor Q6, the grid of metal-oxide-semiconductor Q5 receives given common-mode voltage, the grid of metal-oxide-semiconductor Q6 is connected with one end of capacitor C 4 with one end of capacitor C 3, the cathode output end of the main operation amplifier of another termination unit of capacitor C 3, the cathode output end of the main operation amplifier of another termination unit of capacitor C 4, the grid of metal-oxide-semiconductor Q9 is connected with the grid of metal-oxide-semiconductor Q8 and receives given bias voltage Vbn, the source electrode of the source electrode of the source electrode of metal-oxide-semiconductor Q9 and metal-oxide-semiconductor Q7 and metal-oxide-semiconductor Q8 connects and ground connection altogether, metal-oxide-semiconductor Q1～Q4 adopts PMOS pipe, and metal-oxide-semiconductor Q5～Q9 adopts NMOS pipe.
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