CN104836541A - Fully differential operational amplifier with adjustable GBW (Gain Bandwidth Product) for ADC (Analog to Digital Converter) - Google Patents
Fully differential operational amplifier with adjustable GBW (Gain Bandwidth Product) for ADC (Analog to Digital Converter) Download PDFInfo
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Abstract
The invention provides a fully differential operational amplifier with an adjustable GBW (Gain Bandwidth Product) for an ADC (Analog to Digital Converter). The fully differential operational amplifier comprises a two-phase non-overlapping clock generator, a switched capacitor current source, a biasing circuit and a main operational amplifier circuit, wherein the two-phase non-overlapping clock generator provides a non-overlapping clock signal to the switched capacitor current source and the main operational amplifier circuit; the switched capacitor current source produces a reference current source related to sampling frequency and provides the reference current source to the biasing circuit; and the biasing circuit provides the required bias voltage for a main operational amplifier module. According to the fully differential operational amplifier, the gain bandwidth product can be automatically adjusted under the control of the sampling rate of the ADC, so that the power consumption consumed by the ADC changes along with the sampling rate, and the efficiency of the ADC under the different sampling rates is improved.
Description
Technical field
The present invention relates to Design of Amplifiers technical field, be specifically related to a kind of Full differential operational amplifier adjustable for the GBW of ADC.
Background technology
Along with the fast development of radio communication, derive the communication protocol being applied to different field.In order to meet the requirement of many standard communication protocols, the ADC in system needs to be operated in different sampling rates, provides sufficiently high precision and efficiency simultaneously.In order to address these problems, many power consumptions cuttable ADC structures is carried out.General when the sample frequency of ADC is higher, amplifier must have larger unity gain bandwidth to meet the requirement of settling time, and this just needs to consume larger electric current; And when sample frequency reduces, the requirement of settling time is reduced, have the amplifier of larger unity gain bandwidth will waste a lot of power consumption, reduce ADC be operated in low sampling rate under efficiency.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of Full differential operational amplifier adjustable for the GBW of ADC, the unity gain bandwidth of this operational amplifier regulates automatically by the control of ADC sampling rate, optimize the power consumption that pipeline ADC consumes under different sampling rate, improve the efficiency of ADC.
The present invention is achieved by the following technical programs.
A kind of Full differential operational amplifier adjustable for the GBW of ADC provided by the invention, comprises two-phase non-overlapping clock generator, switched-capacitor currents source, biasing circuit and amplifier main circuit; Described two-phase non-overlapping clock generator provides non-overlapping clock signal to switched-capacitor currents source and amplifier main circuit; Switched-capacitor currents source produces the reference current source relevant to sample frequency to biasing circuit; Biasing circuit provides required bias voltage to main amplifier module.
Described two-phase non-overlapping clock generator is formed by two branch circuit parallel connections, and described two branch roads are in series by multiple inverter with door respectively; Also interconnection between described two branch roads, described two branch roads are all by amplifier clock signal.
Described switched-capacitor currents source comprises switching tube MP1 ~ MP2, switching tube MN1 ~ MN4, amplifier A3, electric capacity C0 ~ C3 and resistance R0, the output that the grid of described switching tube MN1 ~ MN4 is corresponding with two-phase non-overlapping clock generator respectively connects, the source electrode of described switching tube MN1 is connected with the drain electrode of switching tube MN3, the source electrode of described switching tube MN2 is connected with the drain electrode of switching tube MN4, described switching tube MN3, the source electrode ground connection respectively of MN4, electric capacity C1 is in series with between the source electrode of described switching tube MN3 and drain electrode, electric capacity C2 is in series with between the source electrode of described switching tube MN4 and drain electrode.
The drain electrode of described switching tube MN1, MN2 is connected rear by electric capacity C3 ground connection, and the drain electrode of described switching tube MN1 is also connected with the drain electrode of switching tube MP1, the in-phase input end of amplifier A3 respectively.
The inverting input of described amplifier A3 and reference voltage V
refend connects, and output is connected with the grid of switching tube MP1; The grid of described switching tube MP1 is connected with the grid of switching tube MP2 by resistance R0, the grid of described switching tube MP2 is also connected with power supply by electric capacity C0, the source electrode of described switching tube MP1, MP2 is all connected with power supply, and the drain electrode output current of described switching tube MP2 is to biasing circuit.
Described biasing circuit comprises switching tube MP3 ~ MP7, switching tube MN5 ~ MN15 and input current Iref1 ~ Iref3, described switching tube MN6, MN7 are connected with power supply with Iref3 respectively by input current Iref1, Iref2 with the drain electrode of MN9, be connected with the drain electrode of switching tube MN5 after the source electrode of described switching tube MN6 is connected with the source electrode of switching tube MN7, the grid of described switching tube MN5, MN6 is all connected with the drain electrode of switching tube MN6.
The grid of described switching tube MN7 is connected with the grid of switching tube MN9 after being connected with drain electrode, after the drain electrode of described switching tube MN9 is also connected with the grid of switching tube MN8, MN10, MN12 and MN14 respectively again with V
bn1end connects; The drain electrode of described switching tube MN8 is connected with the source electrode of switching tube MN9.
After the grid of described switching tube MN9 is also connected with the grid of switching tube MN11, MN13 and MN15 respectively again with V
bn2end connects; Described switching tube MN11, MN13 are connected with the source electrode of MN15 is corresponding with the drain electrode of switching tube MN10, MN12 and MN14 respectively, drain corresponding with the drain electrode of switching tube MP4, MP5 and MP6 respectively connection; The source grounding of described switching tube MN5, MN8, MN10, MN12 and MN14.
Be connected with the drain electrode of switching tube MP3 after the source electrode of described switching tube MP4, MP5 is connected, the grid of described switching tube MP3 is connected with the grid of MP4 and drain respectively, the grid of described switching tube MP5 with drain respectively with V
bp2end connect be connected after be connected with the grid of switching tube MP6 again, the source electrode of described switching tube MP6 is connected with the drain electrode of switching tube MP7, the grid of described switching tube MP7 and the drain electrode of switching tube MP6 also respectively with V
bp1end connects; The source electrode of described switching tube MP3 with MP7 is connected with power supply respectively.
Described input current Iref1 ~ Iref3 meets relational expression: 4Iref1=Iref2=Iref3.
Described amplifier main circuit is formed by main amplifier module, auxiliary OP AMP modules A 1 ~ A2, the connection in series-parallel of switch common-mode feedback module, described main amplifier module comprises switching tube MP8 ~ MP15, switching tube MN16 ~ MN19, described switching tube MP10, MP14 are all connected with power supply with the source electrode of MP15, the drain electrode of described switching tube MP10 is connected with the source electrode of switching tube MP11, the drain electrode of described switching tube MP11 is connected with the source electrode of switching tube MP8 and MP9 respectively, the grid of described switching tube MP8, MP9, MP10 and MP11 respectively with V
ipend, V
inend, V
pb1end and V
pb2end is corresponding to be connected.
The drain electrode of described MP8 is connected with the drain electrode of switching tube MN18, the source electrode of switching tube MN16 respectively and is connected with the input of auxiliary OP AMP modules A 2 afterwards; The drain electrode of described MP9 is connected with the drain electrode of switching tube MN19, the source electrode of switching tube MN17 respectively and is connected with the input of auxiliary OP AMP modules A 2 afterwards; The grid of described switching tube MN18 with MN19 is connected afterwards and V
cmfbend connects, source ground; The grid of described switching tube MN16 with MN17 is corresponding with the output of auxiliary OP AMP modules A 2 to be connected.
The drain electrode of described switching tube MN16 is connected with the drain electrode of switching tube MP12 afterwards and V
onend connects, and the drain electrode of described switching tube MN17 is connected with the drain electrode of switching tube MP13 afterwards and V
opend connects; The output that the grid of described switching tube MP12, MP13 is corresponding with auxiliary OP AMP modules A 1 respectively connects, the source electrode of described switching tube MP12 is connected with the drain electrode of switching tube MP14 and is connected with the input of auxiliary OP AMP modules A 1 afterwards, the source electrode of described switching tube MP13 is connected with the drain electrode of switching tube MP15 and is connected with the input of auxiliary OP AMP modules A 1 afterwards, and the grid of described switching tube MP14 with MP15 is connected afterwards and V
bp1end connects.
Described switch common-mode feedback module comprises electric capacity C1-1 ~ C1-4, electric capacity C2-1 ~ C2-2, switch CLK1-1 ~ CLK1-6 and switch CLK2-1 ~ CLK2-6, described switch CLK1-1 ~ CLK1-6 is controlled by clock signal clk 1, and described switch CLK2-1 ~ CLK2-6 is controlled by clock signal clk 2; One end of described electric capacity C1-1 is respectively by switch CLK2-1, CLK1-1 and V
cmend, V
onend is corresponding to be connected, the other end respectively with V
bn1end, V
cmfbend is connected with electric capacity C1-2, described electric capacity C1-1 and V
bn1the branch road that end connects also is in series with switch CLK2-3, described electric capacity C1-1 and V
cmfbthe branch road that end connects also is in series with switch CLK1-3, the other end of described electric capacity C1-2 by switch CLK2-5, CLK1-5 respectively with V
cmend, V
opend is corresponding to be connected.
Described V
onend and V
cmfbelectric capacity C2-1 is also in series with, described Vcmfb end and V between end
opelectric capacity C2-2 is also in series with between end.
One end of described electric capacity C1-3 is respectively by switch CLK1-2, CLK2-2 and V
cmend, V
onend is corresponding to be connected, the other end respectively with V
bn1end, V
cmfbend is connected with electric capacity C1-4, described electric capacity C1-3 and V
bn1the branch road that end connects also is in series with switch CLK1-4, described electric capacity C1-3 and V
cmfbthe branch road that end connects also is in series with switch CLK2-4, the other end of described electric capacity C1-4 by switch CLK1-6, CLK2-6 respectively with V
cmend, V
opend is corresponding to be connected.
Described auxiliary OP AMP modules A 1 comprises switching tube MN20 ~ MN30, switching tube MP16 ~ MP24, and described switching tube MP16, MP18, MP20 are all connected with power supply with the source electrode of MP23, the connected rear and V of grid of described switching tube MP16, MP18
bp1end connects, and the drain electrode of described switching tube MP16 is connected with the drain electrode of switching tube MN20, the source electrode of MP17 respectively, and the drain electrode of described MP18 is connected with the drain electrode of switching tube MN21, the source electrode of MP19 respectively; Described switching tube MN20, MN21 common source, and the grid of switching tube MN20 and V
ipend connects, the grid of switching tube MN21 and V
inend connects; The drain electrode of described switching tube MN22 is connected with the source electrode of switching tube MN20, and source electrode is connected with the drain electrode of switching tube MN23, the grid of described switching tube MN22 and MN23 respectively with V
bn2end, V
bn1end is corresponding to be connected.
The grid of described switching tube MP17 with MP19 is connected and and V
bp2end connects, the drain electrode of described switching tube MP17 respectively with V
onthe drain electrode of end, switching tube MN25 connects, and the source electrode of described switching tube MN25 is connected with the drain electrode of switching tube MN24, the drain electrode of described switching tube MP19 respectively with V
opthe drain electrode of end, switching tube MN27 connects, and the source electrode of described switching tube MN27 is connected with the drain electrode of switching tube MN26, and the grid of described switching tube MN25 with MN27 is connected and and V
bn2end connects, and the grid of described switching tube MN24 with MN26 is connected and and V
cmfbend connects.
The grid of described switching tube MP20 with MP23 is connected and and V
bp1end connects, and the drain electrode of described switching tube MP20 is connected with the drain electrode of switching tube MN29, the source electrode of switching tube MP21 respectively, the grid of described switching tube MN29 and V
onend connects, and source electrode is connected with the drain electrode of the grid of switching tube MN28 and drain electrode, switching tube MP24 respectively; The grid of described switching tube MP21 with MP22 is connected and and V
bp2end connects, and the drain electrode of described switching tube MP21 is connected with the drain electrode of MP22, the grid of switching tube MN30 and draining respectively, the grid of described switching tube MN30 also with V
cmfbend connects; The source electrode of described switching tube MP22 with MP24 is all connected with the drain electrode of switching tube MP23, the grid of described switching tube MP24 and V
opend connects.
The source grounding of described switching tube MN23, MN24, MN26, MN28 and MN30.
Beneficial effect of the present invention is: the unity gain bandwidth of this amplifier regulates automatically by the control of ADC sampling rate, thus the power consumption that ADC is consumed becomes with sampling rate, improves the efficiency of ADC under different sampling rate; When load capacitance is 500fF, clock frequency changes to 10MHz by 100MHz, the pipe of this amplifier is all operated in saturation region, unity gain bandwidth is reduced to 117.6MHz by 495.9MHz, gain is all greater than 98dB, phase margin is all greater than 74 °, meets the requirement of 10bit pipeline ADC to high-performance op-amp.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present invention;
Fig. 2 is the circuit diagram of two-phase non-overlapping clock generator in Fig. 1;
Fig. 3 is the circuit diagram of Fig. 1 breaker in middle current source capacitance;
Fig. 4 is the circuit diagram of biasing circuit in Fig. 1;
Fig. 5 is the circuit diagram of the main amplifier module of amplifier main circuit in Fig. 1;
Fig. 6 is the circuit diagram of Fig. 1 breaker in middle common-mode feedback module;
Fig. 7 is the circuit diagram of auxiliary OP AMP module in Fig. 5;
Fig. 8 is the analogous diagram of Fig. 3 breaker in middle current source capacitance output current;
Fig. 9 is the relation schematic diagram of Fig. 3 breaker in middle current source capacitance output current and sample frequency;
Figure 10 is the relation schematic diagram of unity gain bandwidth of the present invention and sample frequency.
Embodiment
Further describe technical scheme of the present invention below, but described in claimed scope is not limited to.
A kind of Full differential operational amplifier adjustable for the GBW of ADC as shown in Fig. 1 ~ Fig. 7, comprises two-phase non-overlapping clock generator, switched-capacitor currents source, biasing circuit and amplifier main circuit; Described two-phase non-overlapping clock generator provides non-overlapping clock signal to switched-capacitor currents source and amplifier main circuit; Switched-capacitor currents source produces the reference current source relevant to sample frequency to biasing circuit; Biasing circuit provides required bias voltage to main amplifier module.
Described two-phase non-overlapping clock generator is formed by two branch circuit parallel connections, and described two branch roads are in series by multiple inverter with door respectively; Also interconnection between described two branch roads, described two branch roads are all by amplifier clock signal.Two-phase non-overlapping clock generator produces two non-overlapping clock signal clks 1, CLK2, for the switched-capacitor CMFB in control switch current source capacitance and amplifier main circuit.
Described switched-capacitor currents source comprises switching tube MP1 ~ MP2, switching tube MN1 ~ MN4, amplifier A3, electric capacity C0 ~ C3 and resistance R0, the output that the grid of described switching tube MN1 ~ MN4 is corresponding with two-phase non-overlapping clock generator respectively connects, the source electrode of described switching tube MN1 is connected with the drain electrode of switching tube MN3, the source electrode of described switching tube MN2 is connected with the drain electrode of switching tube MN4, described switching tube MN3, the source electrode ground connection respectively of MN4, electric capacity C1 is in series with between the source electrode of described switching tube MN3 and drain electrode, electric capacity C2 is in series with between the source electrode of described switching tube MN4 and drain electrode, the drain electrode of described switching tube MN1, MN2 is connected rear by electric capacity C3 ground connection, and the drain electrode of described switching tube MN1 is also connected with the drain electrode of switching tube MP1, the in-phase input end of amplifier A3 respectively, the inverting input of described amplifier A3 and reference voltage V
refend connects, and output is connected with the grid of switching tube MP1, the grid of described switching tube MP1 is connected with the grid of switching tube MP2 by resistance R0, the grid of described switching tube MP2 is also connected with power supply by electric capacity C0, the source electrode of described switching tube MP1, MP2 is all connected with power supply, and the drain electrode output current of described switching tube MP2 is to biasing circuit.
MN1-MN4 is four nmos switch pipes, is controlled by clock signal clk 1 and CLK2.Electric capacity C1, C2 equal and opposite in direction, forms switched-capacitor resistor together with switching tube.When CLK1 is high level, switching tube MN1 and MN4 conducting, electric capacity C1 is charged to V
ref, electric capacity C2 two ends are discharged into ground; When CLK2 is high level, switching tube MN2 and MN3 conducting, electric capacity C2 is charged to V
ref, electric capacity C1 two ends are discharged into ground.Switching tube MP1 and MP2 forms current mirror, and size is equal, therefore exports reference current source I
refequal the electric current I flowing through switching tube MP1
mP1.Due to the effect of switching tube, at nodes X and Y place, very large ripple can be produced, thus make to export reference current fluctuation.Electric capacity C3 can be used for reducing the ripple at nodes X place, and capacitance is larger, and the ripple at nodes X place is less, but the time that output current reaches needed for stable state is also longer.At node Y place, the resistance R0 of increase and electric capacity C0 forms a low-pass first order filter, is used for the ripple of the grid voltage reducing switching tube MP2, thus reduces the fluctuation of output current source.In addition compared with resistance, electric capacity is less with the change of technological parameter and temperature, thus exports reference current source more stable.
Described biasing circuit comprises switching tube MP3 ~ MP7, switching tube MN5 ~ MN15 and input current Iref1 ~ Iref3, described switching tube MN6, MN7 are connected with power supply with Iref3 respectively by input current Iref1, Iref2 with the drain electrode of MN9, be connected with the drain electrode of switching tube MN5 after the source electrode of described switching tube MN6 is connected with the source electrode of switching tube MN7, the grid of described switching tube MN5, MN6 is all connected with the drain electrode of switching tube MN6.The grid of described switching tube MN7 is connected with the grid of switching tube MN9 after being connected with drain electrode, after the drain electrode of described switching tube MN9 is also connected with the grid of switching tube MN8, MN10, MN12 and MN14 respectively again with V
bn1end connects; The drain electrode of described switching tube MN8 is connected with the source electrode of switching tube MN9.After the grid of described switching tube MN9 is also connected with the grid of switching tube MN11, MN13 and MN15 respectively again with V
bn2end connects; Described switching tube MN11, MN13 are connected with the source electrode of MN15 is corresponding with the drain electrode of switching tube MN10, MN12 and MN14 respectively, drain corresponding with the drain electrode of switching tube MP4, MP5 and MP6 respectively connection; The source grounding of described switching tube MN5, MN8, MN10, MN12 and MN14.Be connected with the drain electrode of switching tube MP3 after the source electrode of described switching tube MP4, MP5 is connected, the grid of described switching tube MP3 is connected with the grid of MP4 and drain respectively, the grid of described switching tube MP5 with drain respectively with V
bp2end connect be connected after be connected with the grid of switching tube MP6 again, the source electrode of described switching tube MP6 is connected with the drain electrode of switching tube MP7, the grid of described switching tube MP7 and the drain electrode of switching tube MP6 also respectively with V
bp1end connects; The source electrode of described switching tube MP3 with MP7 is connected with power supply respectively.
Necessary bias voltage when biasing circuit provides amplifier to work, because the bias current in the present invention is relevant with sample rate, excursion is very large, in order to ensure that operational amplifier is operated in saturation region always, switching tube MN7, MN12, MN13 and MP5 are set in biasing circuit, make this biasing circuit except providing the wide amplitude of oscillation, saturation region can also be operated in when input current alters a great deal always.Input current I
ref1, I
ref2, I
ref3thered is provided by switched-capacitor currents source; Described input current Iref1 ~ Iref3 meets relational expression: 4Iref1=Iref2=Iref3.
Described amplifier main circuit is formed by main amplifier module, auxiliary OP AMP modules A 1 ~ A2, the connection in series-parallel of switch common-mode feedback module, described main amplifier module comprises switching tube MP8 ~ MP15, switching tube MN16 ~ MN19, described switching tube MP10, MP14 are all connected with power supply with the source electrode of MP15, the drain electrode of described switching tube MP10 is connected with the source electrode of switching tube MP11, the drain electrode of described switching tube MP11 is connected with the source electrode of switching tube MP8 and MP9 respectively, the grid of described switching tube MP8, MP9, MP10 and MP11 respectively with V
ipend, V
inend, V
pb1end and V
pb2end is corresponding to be connected; The drain electrode of described MP8 is connected with the drain electrode of switching tube MN18, the source electrode of switching tube MN16 respectively and is connected with the input of auxiliary OP AMP modules A 2 afterwards; The drain electrode of described MP9 is connected with the drain electrode of switching tube MN19, the source electrode of switching tube MN17 respectively and is connected with the input of auxiliary OP AMP modules A 2 afterwards; The grid of described switching tube MN18 with MN19 is connected afterwards and V
cmfbend connects, source ground; The grid of described switching tube MN16 with MN17 is corresponding with the output of auxiliary OP AMP modules A 2 to be connected; The drain electrode of described switching tube MN16 is connected with the drain electrode of switching tube MP12 afterwards and V
onend connects, and the drain electrode of described switching tube MN17 is connected with the drain electrode of switching tube MP13 afterwards and V
opend connects; The output that the grid of described switching tube MP12, MP13 is corresponding with auxiliary OP AMP modules A 1 respectively connects, the source electrode of described switching tube MP12 is connected with the drain electrode of switching tube MP14 and is connected with the input of auxiliary OP AMP modules A 1 afterwards, the source electrode of described switching tube MP13 is connected with the drain electrode of switching tube MP15 and is connected with the input of auxiliary OP AMP modules A 1 afterwards, and the grid of described switching tube MP14 with MP15 is connected afterwards and V
bp1end connects.
By improving the mutual conductance of input pipe, the output impedance of cascade and the gain of auxiliary OP AMP, can improve the gain of main amplifier module.The use of gain lift technique can affect frequency characteristic and the time domain specification of main amplifier module.In order to ensure the stability of system, the unit gain frequency of General Requirements auxiliary OP AMP module is less than second limit of main amplifier module, be greater than the unit gain frequency of closed-loop system simultaneously, gain lift technique also can produce extra zero pole point pair, and the right appearance of zero pole point can increase the settling time of main amplifier module significantly.
Described switch common-mode feedback module comprises electric capacity C1-1 ~ C1-4, electric capacity C2-1 ~ C2-2, switch CLK1-1 ~ CLK1-6 and switch CLK2-1 ~ CLK2-6, described switch CLK1-1 ~ CLK1-6 is controlled by clock signal clk 1, and described switch CLK2-1 ~ CLK2-6 is controlled by clock signal clk 2; One end of described electric capacity C1-1 is respectively by switch CLK2-1, CLK1-1 and V
cmend, V
onend is corresponding to be connected, the other end respectively with V
bn1end, V
cmfbend is connected with electric capacity C1-2, described electric capacity C1-1 and V
bn1the branch road that end connects also is in series with switch CLK2-3, described electric capacity C1-1 and V
cmfbthe branch road that end connects also is in series with switch CLK1-3, the other end of described electric capacity C1-2 by switch CLK2-5, CLK1-5 respectively with V
cmend, V
opend is corresponding to be connected; Described V
onend and V
cmfbelectric capacity C2-1 is also in series with, described V between end
cmfbend and V
opelectric capacity C2-2 is also in series with between end; One end of described electric capacity C1-3 is respectively by switch CLK1-2, CLK2-2 and V
cmend, V
onend is corresponding to be connected, the other end respectively with V
bn1end, V
cmfbend is connected with electric capacity C1-4, described electric capacity C1-3 and V
bn1the branch road that end connects also is in series with switch CLK1-4, described electric capacity C1-3 and V
cmfbthe branch road that end connects also is in series with switch CLK2-4, the other end of described electric capacity C1-4 by switch CLK1-6, CLK2-6 respectively with V
cmend, V
opend is corresponding to be connected.
Clock signal clk 1 in switch common-mode feedback module and CLK2 are provided by two-phase non-overlapping clock generator.Compared with traditional switch electric capacity common mode feedback circuit, newly increase one group of electric capacity C
1and switch, circuit structure is more symmetrical, operating rate is faster than traditional structure about one times, the error that charge injection causes also reduces; But be the increase in load capacitance and the chip area of amplifier.
Described auxiliary OP AMP modules A 1 comprises switching tube MN20 ~ MN30, switching tube MP16 ~ MP24, and described switching tube MP16, MP18, MP20 are all connected with power supply with the source electrode of MP23, the connected rear and V of grid of described switching tube MP16, MP18
bp1end connects, and the drain electrode of described switching tube MP16 is connected with the drain electrode of switching tube MN20, the source electrode of MP17 respectively, and the drain electrode of described MP18 is connected with the drain electrode of switching tube MN21, the source electrode of MP19 respectively; Described switching tube MN20, MN21 common source, and the grid of switching tube MN20 and V
ipend connects, the grid of switching tube MN21 and V
inend connects; The drain electrode of described switching tube MN22 is connected with the source electrode of switching tube MN20, and source electrode is connected with the drain electrode of switching tube MN23, the grid of described switching tube MN22 and MN23 respectively with V
bn2end, V
bn1end is corresponding to be connected; The grid of described switching tube MP17 with MP19 is connected and and V
bp2end connects, the drain electrode of described switching tube MP17 respectively with V
onthe drain electrode of end, switching tube MN25 connects, and the source electrode of described switching tube MN25 is connected with the drain electrode of switching tube MN24, the drain electrode of described switching tube MP19 respectively with V
opthe drain electrode of end, switching tube MN27 connects, and the source electrode of described switching tube MN27 is connected with the drain electrode of switching tube MN26, and the grid of described switching tube MN25 with MN27 is connected and and V
bn2end connects, and the grid of described switching tube MN24 with MN26 is connected and and V
cmfbend connects; The grid of described switching tube MP20 with MP23 is connected and and V
bp1end connects, and the drain electrode of described switching tube MP20 is connected with the drain electrode of switching tube MN29, the source electrode of switching tube MP21 respectively, the grid of described switching tube MN29 and V
onend connects, and source electrode is connected with the drain electrode of the grid of switching tube MN28 and drain electrode, switching tube MP24 respectively; The grid of described switching tube MP21 with MP22 is connected and and V
bp2end connects, and the drain electrode of described switching tube MP21 is connected with the drain electrode of MP22, the grid of switching tube MN30 and draining respectively, the grid of described switching tube MN30 also with V
cmfbend connects; The source electrode of described switching tube MP22 with MP24 is all connected with the drain electrode of switching tube MP23, the grid of described switching tube MP24 and V
opend connects; The source grounding of described switching tube MN23, MN24, MN26, MN28 and MN30.Adopt the folded cascode configuration of PMOS input, structure and the auxiliary OP AMP modules A 1 of auxiliary OP AMP modules A 2 are similar.Because the load capacitance of auxiliary OP AMP is smaller, adopt switch common-mode feedback can affect the precision of circuit, require that the common mode feedback circuit operating rate of auxiliary OP AMP wants fast simultaneously, therefore adopt common-mode feedback continuous time.
Wherein, V
cmfbfor common mode feedback voltage, V
bn1, V
bn2, V
bp2, V
bp1for the bias voltage that biasing circuit produces, V
cmfor common-mode voltage, V
opfor forward output voltage, V
onfor reverse output voltage, V
infor reverse input voltage, V
ipforward input voltage.
Under different clock frequencies, carry out Transient to switch current source capacitance output current, as shown in Figure 8, as can be seen from the figure, output current needs about 10 μ s times to reach final stationary value to analogous diagram.Table 1 illustrates the impact of temperature on switch current source capacitance output current, and when temperature changes to 80 DEG C from-40 DEG C, under different clock frequencies, the change of output current is all less than 1.5%, and temperature characterisitic is better than the biasing circuit based on resistance far away.Fig. 9 is the graph of a relation of output current and clock frequency, can find out, output current becomes good linear relationship with clock frequency.The graph of a relation of Figure 10 is load capacitance when being 500fF amplifier unity gain bandwidth and clock frequency, when clock frequency drops to 10MHz by 100MHz, unity gain bandwidth is reduced to 117.6MHz by 495.9MHz, the electric current that amplifier main circuit (comprising biasing circuit) consumes is reduced to 170 μ A from 1.6mA, significantly reduce the power consumption of amplifier, thus improve the efficiency of ADC under different sampling rate.Table 2 gives corresponding gain and phase margin, and along with the raising of clock frequency, the DC current gain of amplifier slightly declines, but overall higher than 98dB; Phase margin change greatly, is reduced to 74.1 ° by 78 °.
The output current in switched-capacitor currents source under table 1 different temperatures
Gain under table 2 different clock frequencies and phase margin
Claims (8)
1. one kind for the adjustable Full differential operational amplifier of the GBW of ADC, comprise two-phase non-overlapping clock generator, switched-capacitor currents source, biasing circuit and amplifier main circuit, it is characterized in that: described two-phase non-overlapping clock generator provides non-overlapping clock signal to switched-capacitor currents source and amplifier main circuit; Switched-capacitor currents source produces the reference current source relevant to sample frequency to biasing circuit; Biasing circuit provides required bias voltage to main amplifier module.
2. as claimed in claim 1 for the Full differential operational amplifier that the GBW of ADC is adjustable, it is characterized in that: described two-phase non-overlapping clock generator is formed by two branch circuit parallel connections, described two branch roads are in series by multiple inverter with door respectively; Also interconnection between described two branch roads, described two branch roads are all by amplifier clock signal.
3. the Full differential operational amplifier adjustable for the GBW of ADC as claimed in claim 1, it is characterized in that: described switched-capacitor currents source comprises switching tube MP1 ~ MP2, switching tube MN1 ~ MN4, amplifier A3, electric capacity C0 ~ C3 and resistance R0, the output that the grid of described switching tube MN1 ~ MN4 is corresponding with two-phase non-overlapping clock generator respectively connects, the source electrode of described switching tube MN1 is connected with the drain electrode of switching tube MN3, the source electrode of described switching tube MN2 is connected with the drain electrode of switching tube MN4, described switching tube MN3, the source electrode ground connection respectively of MN4, electric capacity C1 is in series with between the source electrode of described switching tube MN3 and drain electrode, electric capacity C2 is in series with between the source electrode of described switching tube MN4 and drain electrode,
The drain electrode of described switching tube MN1, MN2 is connected rear by electric capacity C3 ground connection, and the drain electrode of described switching tube MN1 is also connected with the drain electrode of switching tube MP1, the in-phase input end of amplifier A3 respectively;
The inverting input of described amplifier A3 is connected with reference voltage Vref end, and output is connected with the grid of switching tube MP1; The grid of described switching tube MP1 is connected with the grid of switching tube MP2 by resistance R0, the grid of described switching tube MP2 is also connected with power supply by electric capacity C0, the source electrode of described switching tube MP1, MP2 is all connected with power supply, and the drain electrode output current of described switching tube MP2 is to biasing circuit.
4., as claimed in claim 1 for the Full differential operational amplifier that the GBW of ADC is adjustable, it is characterized in that: described biasing circuit comprises switching tube MP3 ~ MP7, switching tube MN5 ~ MN15 and input current I
ref1~ I
ref3, the drain electrode of described switching tube MN6, MN7 and MN9 is respectively by input current I
ref1, I
ref2and I
ref3be connected with power supply, be connected with the drain electrode of switching tube MN5 after the source electrode of described switching tube MN6 is connected with the source electrode of switching tube MN7, the grid of described switching tube MN5, MN6 is all connected with the drain electrode of switching tube MN6;
The grid of described switching tube MN7 is connected with the grid of switching tube MN9 after being connected with drain electrode, after the drain electrode of described switching tube MN9 is also connected with the grid of switching tube MN8, MN10, MN12 and MN14 respectively again with V
bn1end connects; The drain electrode of described switching tube MN8 is connected with the source electrode of switching tube MN9;
After the grid of described switching tube MN9 is also connected with the grid of switching tube MN11, MN13 and MN15 respectively again with V
bn2end connects; Described switching tube MN11, MN13 are connected with the source electrode of MN15 is corresponding with the drain electrode of switching tube MN10, MN12 and MN14 respectively, drain corresponding with the drain electrode of switching tube MP4, MP5 and MP6 respectively connection; The source grounding of described switching tube MN5, MN8, MN10, MN12 and MN14;
Be connected with the drain electrode of switching tube MP3 after the source electrode of described switching tube MP4, MP5 is connected, the grid of described switching tube MP3 is connected with the grid of MP4 and drain respectively, the grid of described switching tube MP5 with drain respectively with V
bp2end connect be connected after be connected with the grid of switching tube MP6 again, the source electrode of described switching tube MP6 is connected with the drain electrode of switching tube MP7, the grid of described switching tube MP7 and the drain electrode of switching tube MP6 also respectively with V
bp1end connects; The source electrode of described switching tube MP3 with MP7 is connected with power supply respectively.
5., as claimed in claim 4 for the Full differential operational amplifier that the GBW of ADC is adjustable, it is characterized in that: described input current I
ref1~ I
ref3meet relational expression: 4I
ref1=I
ref2=I
ref3.
6. the Full differential operational amplifier adjustable for the GBW of ADC as claimed in claim 1, it is characterized in that: described amplifier main circuit is by main amplifier module, auxiliary OP AMP modules A 1 ~ A2, the connection in series-parallel of switch common-mode feedback module forms, described main amplifier module comprises switching tube MP8 ~ MP15, switching tube MN16 ~ MN19, described switching tube MP10, the source electrode of MP14 with MP15 is all connected with power supply, the drain electrode of described switching tube MP10 is connected with the source electrode of switching tube MP11, the drain electrode of described switching tube MP11 is connected with the source electrode of switching tube MP8 and MP9 respectively, described switching tube MP8, MP9, the grid of MP10 and MP11 respectively with V
ipend, V
inend, V
pb1end and V
pb2end is corresponding to be connected,
The drain electrode of described MP8 is connected with the drain electrode of switching tube MN18, the source electrode of switching tube MN16 respectively and is connected with the input of auxiliary OP AMP modules A 2 afterwards; The drain electrode of described MP9 is connected with the drain electrode of switching tube MN19, the source electrode of switching tube MN17 respectively and is connected with the input of auxiliary OP AMP modules A 2 afterwards; The grid of described switching tube MN18 with MN19 is connected afterwards and V
cmfbend connects, source ground; The grid of described switching tube MN16 with MN17 is corresponding with the output of auxiliary OP AMP modules A 2 to be connected;
The drain electrode of described switching tube MN16 is connected with the drain electrode of switching tube MP12 afterwards and V
onend connects, and the drain electrode of described switching tube MN17 is connected with the drain electrode of switching tube MP13 afterwards and V
opend connects; The output that the grid of described switching tube MP12, MP13 is corresponding with auxiliary OP AMP modules A 1 respectively connects, the source electrode of described switching tube MP12 is connected with the drain electrode of switching tube MP14 and is connected with the input of auxiliary OP AMP modules A 1 afterwards, the source electrode of described switching tube MP13 is connected with the drain electrode of switching tube MP15 and is connected with the input of auxiliary OP AMP modules A 1 afterwards, and the grid of described switching tube MP14 with MP15 is connected afterwards and V
bp1end connects.
7., as claimed in claim 6 for the Full differential operational amplifier that the GBW of ADC is adjustable, it is characterized in that: described switch common-mode feedback module comprises electric capacity C
1-1~ C
1-4, electric capacity C
2-1~ C
2-2, switch CLK1-1 ~ CLK1-6 and switch CLK2-1 ~ CLK2-6, described switch CLK1-1 ~ CLK1-6 is controlled by clock signal clk 1, and described switch CLK2-1 ~ CLK2-6 is controlled by clock signal clk 2; Described electric capacity C
1-1one end respectively by switch CLK2-1, CLK1-1 and V
cmend, V
onend is corresponding to be connected, the other end respectively with V
bn1end, V
cmfbend and electric capacity C
1-2connect, described electric capacity C
1-1with V
bn1the branch road that end connects also is in series with switch CLK2-3, described electric capacity C
1-1with V
cmfbthe branch road that end connects also is in series with switch CLK1-3, described electric capacity C
1-2the other end by switch CLK2-5, CLK1-5 respectively with V
cmend, V
opend is corresponding to be connected;
Described V
onend and V
cmfbelectric capacity C is also in series with between end
2-1, described V
cmfbend and V
opelectric capacity C is also in series with between end
2-2;
Described electric capacity C
1-3one end respectively by switch CLK1-2, CLK2-2 and V
cmend, V
onend is corresponding to be connected, the other end respectively with V
bn1end, V
cmfbend and electric capacity C
1-4connect, described electric capacity C
1-3with V
bn1the branch road that end connects also is in series with switch CLK1-4, described electric capacity C
1-3with V
cmfbthe branch road that end connects also is in series with switch CLK2-4, described electric capacity C
1-4the other end by switch CLK1-6, CLK2-6 respectively with V
cmend, V
opend is corresponding to be connected.
8. the Full differential operational amplifier adjustable for the GBW of ADC as claimed in claim 6, it is characterized in that: described auxiliary OP AMP modules A 1 comprises switching tube MN20 ~ MN30, switching tube MP16 ~ MP24, described switching tube MP16, MP18, MP20 are all connected with power supply with the source electrode of MP23, the connected rear and V of grid of described switching tube MP16, MP18
bp1end connects, and the drain electrode of described switching tube MP16 is connected with the drain electrode of switching tube MN20, the source electrode of MP17 respectively, and the drain electrode of described MP18 is connected with the drain electrode of switching tube MN21, the source electrode of MP19 respectively; Described switching tube MN20, MN21 common source, and the grid of switching tube MN20 and V
ipend connects, the grid of switching tube MN21 and V
inend connects; The drain electrode of described switching tube MN22 is connected with the source electrode of switching tube MN20, and source electrode is connected with the drain electrode of switching tube MN23, the grid of described switching tube MN22 and MN23 respectively with V
bn2end, V
bn1end is corresponding to be connected;
The grid of described switching tube MP17 with MP19 is connected and and V
bp2end connects, the drain electrode of described switching tube MP17 respectively with
vonthe drain electrode of end, switching tube MN25 connects, and the source electrode of described switching tube MN25 is connected with the drain electrode of switching tube MN24, the drain electrode of described switching tube MP19 respectively with
vopthe drain electrode of end, switching tube MN27 connects, and the source electrode of described switching tube MN27 is connected with the drain electrode of switching tube MN26, and the grid of described switching tube MN25 with MN27 is connected and and V
bn2end connects, and the grid of described switching tube MN24 with MN26 is connected and and V
cmfbend connects;
The grid of described switching tube MP20 with MP23 is connected and and V
bp1end connects, and the drain electrode of described switching tube MP20 is connected with the drain electrode of switching tube MN29, the source electrode of switching tube MP21 respectively, the grid of described switching tube MN29 and V
onend connects, and source electrode is connected with the drain electrode of the grid of switching tube MN28 and drain electrode, switching tube MP24 respectively; The grid of described switching tube MP21 with MP22 is connected and and V
bp2end connects, and the drain electrode of described switching tube MP21 is connected with the drain electrode of MP22, the grid of switching tube MN30 and draining respectively, the grid of described switching tube MN30 also with V
cmfbend connects; The source electrode of described switching tube MP22 with MP24 is all connected with the drain electrode of switching tube MP23, the grid of described switching tube MP24 and V
opend connects;
The source grounding of described switching tube MN23, MN24, MN26, MN28 and MN30.
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| CN104836541B (en) | 2018-01-09 |
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