CN113746483B - Sigma-Delta ADC applied to temperature sensor - Google Patents
Sigma-Delta ADC applied to temperature sensor Download PDFInfo
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- CN113746483B CN113746483B CN202111043077.3A CN202111043077A CN113746483B CN 113746483 B CN113746483 B CN 113746483B CN 202111043077 A CN202111043077 A CN 202111043077A CN 113746483 B CN113746483 B CN 113746483B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/352—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M3/354—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
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Abstract
The invention is a Sigma-Delta ADC applied to a temperature sensor, comprising: the temperature sensor comprises a selection switch circuit, a switch capacitance integrating circuit, a dynamic comparator, a time sequence generating circuit, a biasing circuit and a switch point circuit, wherein the input end of the selection switch circuit is connected with a front-end circuit of the temperature sensor, the output end of the selection switch circuit is connected with the switch capacitance integrating circuit, and the output end of the switch capacitance integrating capacitor is connected with the input end of the dynamic comparator. The invention has the advantages that: the T-shaped switch with the switch circuit adopting the complementary structure formed by the MOS tubes can offset the channel charge injection effect and the leakage current influence under low-frequency input, and improves the accuracy and resolution of analog-to-digital conversion; the switched capacitor integrating circuit uses an auto-zero technology and a fully differential structure to reduce the offset voltage of the integrator and adjust the period number of the sampling stage for amplifying the voltage, and increases the feedforward path to reduce the average output of the first-stage integrator so as to improve the stability of the whole circuit.
Description
Technical Field
The invention relates to the technical field of analog-to-digital converter circuits, in particular to a Sigma-Delta ADC applied to a temperature sensor.
Background
After the 5G indoor base station is deployed in a large scale, the Internet of things becomes an epoch-making rise after the Internet, and the Internet of things is possible to interconnect and communicate with each other. For wireless sensor nodes of the internet of things, the acquisition of the temperature information of the die is very important, and the die can be used for reducing the sensitivity to the temperature, so that the wireless sensor nodes are a very important part of the temperature sensor.
The ADC is a key module in the temperature sensor, and is used for digitizing the voltage proportion generated by a front-end circuit in the temperature sensor, so as to provide usable temperature information for the temperature compensation module, namely, the higher the accuracy of digital signals output by the ADC is, the higher the accuracy of the temperature detected by the temperature sensor is.
Disclosure of Invention
The invention mainly provides the Sigma-Delta ADC which is used for converting the output of the front-end circuit into a high-resolution and high-precision digital signal and is applied to the temperature sensor on the premise of meeting the low power consumption of the temperature sensor based on the requirement of the temperature sensor on the ADC precision.
The technical scheme adopted by the invention for solving the technical problems is that the Sigma-Delta ADC applied to the temperature sensor is characterized in that: comprising the following steps:
a selection switch circuit for switching the input voltage of the Sigma-Delta ADC;
the switch capacitance integrating circuit is used for sampling and holding the input voltage and integrating the input voltage;
a dynamic comparator for converting the integrated input voltage into a pulse width modulated signal BS containing temperature information;
the time sequence generating circuit provides driving signals for the selection switch circuit, the dynamic comparator and the switch capacitance integrating circuit;
the bias circuit provides bias voltage for the switched capacitor integrating circuit and the dynamic comparator;
the switching circuit is arranged in the time sequence generating circuit, the selecting switching circuit and the switch capacitance integrating circuit and is controlled by a control signal formed by one or two signals of a pulse width modulation signal BS and a driving signal, and is used for counteracting the channel charge injection effect and the leakage current influence under low-frequency input.
As a preferred solution of the foregoing solution, the switch circuit is a T-type switch with a complementary structure, and includes a MOS transistor MNA, MNB, MNC, MPA, MPB and an MPC, where the drain of the MOS transistor MNA is electrically connected to the source of the MOS transistor MNB, the drain of the MOS transistor MPA is electrically connected to the source of the MOS transistor MPB, the source of the MOS transistor MNA is electrically connected to the source of the MOS transistor MPA as an input terminal of the switch circuit, the drain of the MOS transistor MNB and the drain of the MOS transistor MPB are electrically connected to an output terminal of the switch circuit, the source of the MOS transistor MPC is connected to a voltage VDD, the drain of the MOS transistor MPC is electrically connected to the drain of the MOS transistor MNA, the drain of the MOS transistor MNC is connected to a voltage VSS, the source of the MOS transistor MNC is electrically connected to the drain of the MOS transistor MPA, the MOS transistors MNA, MNB and MPC are controlled by the same control signal, and the MOS transistors MNA, MNB and MPC are controlled by control signals opposite to the control MOS transistors MNA, MNB and MPC.
As a preferable mode of the above-described aspect, the timing generation circuit includes an input terminal for inputting clock signals CLK1 and CLK2 having a duty ratio of 0.5 and an output terminal for outputting signals Q1, Q2, EVAL, QF1D, QF, QF2D and QF2, the frequency of the clock signal CLK2 is twice that of the clock signal CLK1, the signal Q1 is a signal delayed from the signal CLK1 when the pulse width modulation signal BS is a first level, the signal Q1 is a signal delayed from the signal CLK2 when the pulse width modulation signal BS is a second level, the first level is one of a high level and a low level, the second level is opposite to the first level, the signal Q2 is opposite to the signal Q1, the signal EVAL is a pulse signal having the same period as the signal CLK1, the signal QF1 is a clock signal having the same period as the signal CLK1 and a duty ratio of 0.75, the signal Q1 is a signal delayed from the signal QF1 when the pulse width modulation signal BS is a second level, the signal Q1 is one of a signal delayed from the signal QF2, and the signal Q2 is opposite to the signal QF 1.
As a preferred solution of the foregoing solution, the selection switch circuit includes a first input end, a second input end, a first output end, and a second output end, where the first input end is electrically connected to the first end of the first switch circuit, the first end of the second switch circuit, the first end of the third switch circuit, and the first end of the fourth switch circuit, the second input end is electrically connected to the first end of the fifth switch circuit and the first end of the sixth switch circuit, the first output end is electrically connected to the second end of the first switch circuit, the second end of the second switch circuit, the second end of the fifth switch circuit, and the second end of the seventh switch circuit, and the second output end is electrically connected to the second end of the third switch circuit, the second end of the fourth switch circuit, the second end of the second switch circuit, and the second end of the eighth switch circuit, and the seventh switch second end are all grounded.
As a preferable scheme of the scheme, the switched capacitor integration circuit uses an automatic zero setting technology and comprises a first-stage fully-differential switched capacitor integrator and a second-stage fully-differential switched capacitor integrator, wherein the forward output end and the reverse output end of the first-stage fully-differential switched capacitor integrator are correspondingly connected with the forward input end and the reverse input end of the second-stage fully-differential switched capacitor integrator, the forward output end of the second-stage fully-differential switched capacitor integrator is connected with the forward input end of the dynamic comparator, and the reverse output end of the second-stage fully-differential switched capacitor integrator is connected with the reverse input end of the dynamic comparator.
As a preferable mode of the above-mentioned mode, a feedforward circuit is provided in the switched capacitor integrating circuit.
As a preferable scheme of the scheme, the first operational amplifier and the second operational amplifier are both common-source common-gate full-differential operational amplifiers with two-stage structures, the common-source common-gate full-differential operational amplifiers comprise MOS tubes MP1-MP12, MN1-MN8, resistors R1-R2 and capacitors C1-C4, the MOS tubes MN7-MN8, the MOS tubes MP8-MP12, the resistors R1-R2 and the capacitors C3-C4 form a common-mode feedback circuit, the MOS tubes MP1-MP5 and the MN1-MN4 form a first-stage amplifying circuit, and the MOS tubes MP6-MP7 and the MN5-MN6 form a second-stage amplifying circuit.
As a preferable mode of the above, the first-stage amplifying circuit has a gain of
The gain of the second-stage amplifying circuit is
The integral operational amplifier of the cascode fully differential operational amplifier has the gain of
Wherein the method comprises the steps ofIs the transconductance of the MOS tube,in order to output the resistance of the resistor,in order to output the electrical conductance,。
as a preferable scheme of the scheme, the dynamic comparator comprises a pre-amplification stage, a comparison stage and a latch stage, wherein the dynamic comparator sequentially comprises the pre-amplification stage, the comparison stage and the latch stage, the pre-amplification stage comprises MOS tubes MN9-MN11 and MP13-MP19, the comparison stage comprises MOS tubes MN12-MN19 and MP17-MP22, the latch stage comprises MOS tubes MN20-MN23 and MP23-MP26, the grid electrode of the MOS tube MN9 and the grid electrode of the MN10 are respectively a reverse input end and a forward input end of the dynamic comparator, the drain electrode of the MOS tube MN25 is positioned at the reverse output end of the dynamic comparator, and the drain electrode of the MOS tube MN26 is positioned at the forward output end of the dynamic comparator.
As a preferable mode of the above-mentioned scheme, in the pre-amplification stage, the MN9 drain electrode and the MN10 drain electrode are positive and negative output terminals of the pre-amplification stage; in the comparison stage, a gate electrode of MN18 and a gate electrode of MN19 are positive and negative input ends of the comparison stage, MN16, MN17, MP19 and MP20 form a positive feedback latch structure, MP18 and MP21 are reset tubes, and a drain electrode of MP22 and a drain electrode of MP17 are positive and negative output ends of the comparison stage; in the latch stage, the MP23 gate and the MN20 gate form a negative input end of the latch stage together, and the MP24 gate and the MN23 gate form a positive input end of the latch stage together.
The invention has the advantages that: the T-shaped switch with the switch circuit adopting the complementary structure formed by the MOS tubes can offset the channel charge injection effect and the leakage current influence under low-frequency input, and improves the accuracy and resolution of analog-to-digital conversion; the switched capacitor integrating circuit uses an auto-zero technology and a fully differential structure to reduce the offset voltage of the integrator and adjust the period number of the sampling stage for amplifying the voltage, and increases the feedforward path to reduce the average output of the first-stage integrator so as to improve the stability of the whole circuit.
Drawings
Fig. 1 is a schematic circuit diagram of a switching circuit in an embodiment.
Fig. 2 is a schematic circuit diagram of a timing generation circuit in an embodiment.
FIG. 3 is a schematic circuit diagram of a Sigma-Delta ADC in an embodiment.
Fig. 4 is a schematic circuit diagram of a cascode fully differential operational amplifier in an embodiment.
Fig. 5 is a schematic circuit diagram of a dynamic comparator in an embodiment.
Fig. 6 is a schematic circuit diagram of a bias circuit in an embodiment.
Detailed Description
The technical scheme of the invention is further described below through examples and with reference to the accompanying drawings.
Examples:
the Sigma-Delta ADC applied to the temperature sensor comprises a selection switch circuit, a switch capacitance integrating circuit, a dynamic comparator, a time sequence generating circuit, a bias circuit and a switch point circuit, wherein the input end of the selection switch circuit is connected with the front-end circuit of the temperature sensor, the output end of the selection switch circuit is connected with the switch capacitance integrating circuit, and the output end of the switch capacitance integrating capacitor is connected with the input end of the dynamic comparator.
In this embodiment, the selection switch circuit is used to switch the input voltage of the Sigma-Delta ADC; the switch capacitance integrating circuit is used for sampling and holding the input voltage and performing integration processing on the input voltage; the dynamic comparator is used for converting the integrated input voltage into a pulse width modulation signal BS containing temperature information; the time sequence generating circuit provides driving signals for the selection switch circuit, the dynamic comparator and the switch capacitance integrating circuit; the bias circuit provides bias voltage for the switched capacitor integrating circuit and the dynamic comparator; the switching circuit is arranged in the time sequence generating circuit, the selecting switching circuit and the switched capacitor integrating circuit and is controlled by a control signal formed by one or two signals of a pulse width modulation signal BS and a driving signal, and is used for counteracting the channel charge injection effect and the leakage current influence under low-frequency input.
As shown in fig. 1, the switch circuit is a T-type switch with a complementary structure, and includes a MOS transistor MNA, MNB, MNC, MPA, MPB and an MPC, the drain of the MOS transistor MNA is electrically connected to the source of the MOS transistor MNB, the drain of the MOS transistor MPA is electrically connected to the source of the MOS transistor MPB, the source of the MOS transistor MNA is electrically connected to the source of the MOS transistor MPA as an input end of the switch circuit, the drain of the MOS transistor MNB is electrically connected to the drain of the MOS transistor MPB as an output end of the switch circuit, the source of the MOS transistor MPC is connected to the voltage VDD, the drain of the MOS transistor MPC is electrically connected to the drain of the MOS transistor MNA, the drain of the MOS transistor MNC is connected to the voltage VSS, the source of the MOS transistor MNA is electrically connected to the drain of the MOS transistor MPA, the MOS transistors MNA, MNB and MPC are controlled by the same control signal CLK, and the MOS transistors MPA, MNB and MNC are controlled by a control signal CLKB opposite to the control MOS transistors MNA, MNB and MPC. The control signal is a non-overlapping clock signal swinging between the voltage VSS and the voltage VDD, when the control signal CLK is at the VDD, the grids of the MOS tubes MNA and MNB are biased to the VDD, the grids of the MOS tubes MPA and MPB are biased to the VSS, the drain voltage of the MOS tube MPC is at the VDD, the drain voltage of the MOS tube MNC is at the VSS, VGS of the MOS tubes MNB and MPB are reverse biased, no matter whether leakage current exists in the MOS tubes MNA and MNB, the MOS tubes MNB and MPB are in a deep cut-off region, and the channel charge injection effect and the leakage current influence under low-frequency input can be counteracted.
The timing generation circuit comprises an input end for inputting clock signals CLK1 and CLK2 with a duty ratio of 0.5 and an output end for outputting signals Q1, Q2, EVAL, QF1D, QF1, QF2D and QF2, wherein the frequency of the clock signal CLK2 is twice as high as that of the clock signal CLK1, the signal Q1 is a signal delayed from the signal CLK1 when the pulse width modulation signal BS is at a first level, the signal Q1 is a signal delayed from the signal CLK2 when the pulse width modulation signal BS is at a second level, the first level is one of a high level and a low level, the second level is opposite to the first level, the signal Q2 is opposite to the signal Q1, the signal EVAL is a pulse signal with the same period as that of the signal CLK1, the signal QF1 is a clock signal with the same period as that of the signal CLK1 and a duty ratio of 0.75, the signal QF1D is a signal delayed from the signal QF1, and the signal QF2 is opposite to the signal QF1 and the signal QF2D is opposite to the signal QF 1.
The timing generation circuit, as shown in fig. 2, comprises a timing circuit with the same three-way structure, which is respectively marked as a first timing circuit, a second timing circuit and a third timing circuit, the timing circuit comprises a first branch and a second branch, the first branch comprises a first NOT gate, a first NAND gate, a first delay unit and a second NOT gate, the second branch comprises a second NAND gate, a second delay unit and a third NOT gate, the output end of the first NOT gate is connected with the first input end of the first NAND gate, the output end of the first NAND gate is connected with the input end of the first delay unit, the output end of the first NAND gate is connected with the first input end of the second NOT gate and the first input end of the second NAND gate, the output end of the second NAND gate is connected with the second output end of the BSN1, the output end of the second NAND gate is connected with the second BSN1, the output end of the BSN1 is connected with the output end of the second clock circuit, the output end of the BSN1 is connected with the output end of the BSN1, the output end of the second branch of the first time sequence circuit is electrically connected with the first end of the switch circuit BSN2, the second end of the switch circuit BSN2 is electrically connected with the second end of the switch circuit BS2, the first end of the switch circuit BS2 is electrically connected with the output end of the second branch of the second time sequence circuit, the junction of the switch circuit BS2 and the switch circuit BSN2 is used for outputting a signal Q1 externally, the input end of the third time sequence circuit is electrically connected with the output end of the first NOR gate, two inputs of the first NOR gate are respectively clock signals CLK1 and CLK2, the output end of the first branch of the third time sequence circuit outputs a signal QF1D, the output end of the second branch of the third time sequence circuit outputs a signal QF2D externally, and the output end of the fourth buffer gate in the first delay unit of the third time sequence circuit is led out with a lead to output QF1 externally. The output end of the first branch of the second time sequence circuit is connected to the first input end of the second NOR gate after passing through two serially connected buffer gates, the output end of the sixth buffer gate of the second time delay unit of the second time sequence circuit is connected to the second input end of the second NOR gate after passing through one NOR gate, the signal QF1D is connected to the third input end of the second NOR gate, and the second NOR gate outputs a signal EVAL outwards.
In the time sequence circuit, the switch circuits BS1 and BS2 are the switch circuits shown in fig. 1, the on-off of the switch circuits BS1, BS2, BSN1 and BSN2 are controlled by the pwm signal BS output by the dynamic comparator, when BS is at high level, the switch circuits BS1 and BS2 are turned on, and the switch circuits BSN1 and BSN2 are turned off.
As shown in fig. 3, the selection switch circuit includes a first input end, a second input end, a first output end and a second output end, where the first input end is electrically connected with the first end of the switch circuit K1, the first end of the switch circuit K2, the first end of the switch circuit K3 and the first end of the switch circuit K4, the second input end is electrically connected with the first end of the switch circuit K5 and the first end of the switch circuit K6, the first output end is electrically connected with the second end of the switch circuit K1, the second end of the switch circuit K2, the second end of the switch circuit K5 and the second end of the switch circuit K7, and the second output end is electrically connected with the second end of the switch circuit K3, the second end of the switch circuit K4, the second end of the switch circuit K2 and the second end of the switch circuit K8, and the second end of the switch circuit K7 and the second end of the switch circuit K8 are all grounded. The control signals of the switch circuits K1 and K6 are Q1BSN, the control signals of the switch circuits K2 and K8 are Q2BS, the control signals of the switch circuits K3 and K5 are Q2BSN, the control signals of the switch circuits K4 and K7 are Q1BS, and the signal BSN is opposite to the signal BS.
The switched capacitor integrator circuit uses an automatic zero setting technology to reduce the influence of offset voltage and 1/f noise of the amplifier, and comprises a first-stage fully-differential switched capacitor integrator, a second-stage fully-differential switched capacitor integrator and a feedforward circuit, wherein the forward output end and the reverse output end of the first-stage fully-differential switched capacitor integrator are correspondingly connected with the forward input end and the reverse input end of the second-stage fully-differential switched capacitor integrator, the forward output end of the second-stage fully-differential switched capacitor integrator is connected with the forward input end of the dynamic comparator, the reverse output end of the second-stage fully-differential switched capacitor integrator is connected with the reverse input end of the dynamic comparator, and the forward input end and the reverse input end of the first-stage fully-differential switched capacitor integrator are correspondingly connected with the first output end of the selector switch circuit and the second output end of the selector switch circuit. In this embodiment, the gain factor of the first-stage fully differential switched capacitor integrator is 1/4, the gain factor of the second-stage fully differential switched capacitor integrator is 2/3, and the feedback coefficient of the switched capacitor integrating circuit is 1/2.
The positive input end of the first-stage full-differential switched capacitor integrator is respectively and electrically connected with the first end of the switch circuit K14 and the first end of the capacitor Cs2, the second end of the switch circuit K14 is electrically connected with the first end of the capacitor unit C2, the second end of the capacitor unit C2 is respectively and electrically connected with the first end of the switch circuit K12, the first end of the switch circuit K15, the second end of the capacitor Cs2, the first operational amplifier positive input end, the second end of the switch circuit K15, the first end of the capacitor CINT1 and the first end of the switch circuit K13, the second end of the switch circuit K12, the second end of the switch circuit K13 and the second end of the capacitor CINT1, and the first operational amplifier reverse output end is the reverse output end of the first-stage full-differential switched capacitor integrator. The circuit from the reverse input end of the first-stage fully-differential switched-capacitor integrator to the forward output end of the first-stage fully-differential switched-capacitor integrator is the same as the circuit from the forward input end of the first-stage fully-differential switched-capacitor integrator to the reverse output end of the first-stage fully-differential switched-capacitor integrator. The switching circuit K14 is controlled by the signal BSN, the switching circuit K15 is controlled by the signal Q2, the switching circuit K12 is controlled by the signal Q1, and the switching circuit K13 resets the switch. In the first-stage fully differential switched capacitor integrator, a switched capacitor circuit formed by a switch circuit K14, a capacitor unit C2, a switch circuit K15 and a capacitor Cs2 is a sampling circuit, and a capacitor CINT1 is an integrating capacitor. When the Q1 bit is high, the first-stage fully-differential switched capacitor integrator is in a sampling stage, when the Q1 bit is low, the first-stage fully-differential switched capacitor integrator is in an integrating stage, in the sampling stage, the first operational amplifier is switched to unit gain for reducing offset voltage of the operational amplifier, t1 is the end time of the sampling stage, and at the time of t1, the input voltage Vin is sampled on the capacitor unit C2 relative to the virtual ground Vx of the operational amplifier, so that voltages Vin (t 1) -Vx (t 1) are stored on the capacitor unit C2. In the integration phase, the integration capacitor CINT1 switches in the feedback path of the operational amplifier, and C2 discharges to Vx. Thus, the charge will be integrated: assuming that the sampling switch is ideal, the op-amp is noise free and has infinite open loop gain, the sum will be equal to the offset voltage and the integrator offset is eliminated. In this embodiment, the capacitor unit C2 is formed by connecting eleven capacitors Cs2 in parallel, and the amplification factor α of VBE is related to the number of capacitors connected in parallel in the capacitor unit C2, and can be adjusted accordingly according to the number of conversion periods.
The positive input end of the second-stage fully differential switched capacitor integrator is electrically connected with the first end of a switch circuit K16, the second end of the switch circuit K16 is electrically connected with the first end of a switch circuit K19 and the first end of a capacitor C01 respectively, the second end of the capacitor C01 is electrically connected with the first end of a switch K17 and the first end of a switch circuit K20 respectively, the second section of the switch circuit K19 and the second end of the switch circuit K20 are grounded in an alternating current manner, the second end of the switch circuit K17 is electrically connected with the first end of a switch circuit K18, the first end of a capacitor CINT3 and the positive input end of a second operational amplifier respectively, and the reverse output end of the second operational amplifier is electrically connected with the second end of the capacitor CINT3 and the second end of the switch circuit K18 respectively. The circuit between the reverse input end of the second-stage fully-differential switched-capacitor integrator and the forward output end of the second-stage fully-differential switched-capacitor integrator is the same as the circuit between the forward input end of the second-stage fully-differential switched-capacitor integrator and the reverse output end of the second-stage fully-differential switched-capacitor integrator. In the second-stage fully differential switched capacitor integrator, the switching circuit K16 is controlled by the signal QF2D, the switching circuit K17 is controlled by the signal QF1, the switching circuit K19 is controlled by the signal QF1D, the switching circuit K20 is controlled by the signal QF2, the switching circuit K18 is a bit reset switch, the capacitor C01 is a sampling capacitor, and the capacitor CINT3 is an integrating capacitor.
The feedforward circuit is the same with the sampling circuit of the first-stage full-differential switched capacitor integrator, and is composed of a switch circuit K9, a capacitor Cs1, a capacitor unit C1, a switch circuit K10 and a switch circuit K11, wherein the first end of the capacitor Cs1 and the first end of the switch circuit K9 are electrically connected with the input end of the first-stage full-differential switched capacitor integrator, the second end of the capacitor Cs1 is electrically connected with the second end of the capacitor unit C1, the first end of the switch circuit K11 and the first end of the switch circuit K10 respectively, the first end of the capacitor unit C1 is electrically connected with the second end of the switch circuit K9, the second end of the switch circuit K11 is connected with AC ground, and the second end of the switch circuit K10 is electrically connected with the second operational amplifier forward input end. The switching circuit K9 is controlled by the signal BSN, the switching circuit K11 is controlled by the signal Q1, the switching circuit K10 is controlled by the signal Q2, the capacitor unit C1 and the capacitor unit C2 are identical in structure, and the feedforward circuit enables the average output of the first-stage fully-differential switched capacitor integrator to be kept zero, so that the output swing of the first-stage fully-differential switched capacitor integrator can be effectively eliminated, and the noise transfer function of the Sigma-Delta ADC is not changed.
The first operational amplifier and the second operational amplifier are two-stage structure common-source common-gate full-differential operational amplifiers, as shown in fig. 4, and comprise MOS tubes MP1-MP12, MN1-MN8, resistors R1-R2 and capacitors C1-C4, wherein the MOS tubes MN7-MN8, the MOS tubes MP8-MP12, the resistors R1-R2 and the capacitors C3-C4 form a common-mode feedback circuit, the MP8 source electrode is connected with VDD, the MP8 grid electrode is electrically connected with the output Vb1 of the bias circuit, the MP8 drain electrode is electrically connected with the MP9 source electrode, the MP10 source electrode and the MP11 source electrode respectively, the MP10 grid electrode is electrically connected with the MP11 grid electrode, the MP9 grid electrode is electrically connected with the first end of the capacitor C3, the first end of the capacitor C4, the first end of the resistor R1 and the first end of the resistor R2 respectively, the MP9 drain electrode is electrically connected with the MP12 source electrode, the MP12 drain electrode is electrically connected with the MN7 drain electrode and the MN8 grid electrode respectively, the MN7 source electrode is electrically connected with the MN8 drain electrode, the MN8 source electrode is connected with GND, and the MP7 grid electrode and MP12 grid electrode is electrically connected with the output Vb3 and the output Vb2 of the bias circuit respectively.
The MOS transistors MP1-MP5 and MN1-MN4 form a first stage amplifying circuit, a MP1 source electrode is connected with VDD, a MP1 grid electrode is electrically connected with an output Vb1 of the biasing circuit, a MP1 drain electrode is electrically connected with a MP2 source electrode and a MP3 source electrode respectively, a MP2 grid electrode and a MP3 grid electrode are respectively a positive input end and a negative input end of the common-source common-grid full-differential operational amplifier, a MP2 drain electrode is electrically connected with a MP10 drain electrode and a MP4 source electrode respectively, a MP4 drain electrode is electrically connected with a MN1 drain electrode, a MN1 source electrode is electrically connected with a MN3 drain electrode, a MN3 source electrode is grounded GND, a MP3 drain electrode is electrically connected with a MP11 drain electrode and a MP5 source electrode respectively, a MP5 drain electrode is electrically connected with a MN2 drain electrode, a MN4 source electrode is grounded GND, a MP4 grid electrode and a MP5 grid electrode are electrically connected with an output Vb2 of the biasing circuit respectively, a MN1 grid electrode and a MN2 grid electrode are electrically connected with an output Vb3 of the biasing circuit, and a MN3 grid electrode and a MN4 grid electrode are electrically connected with a MN8 grid electrode respectively.
The MOS transistors MP6-MP7 and MN5-MN6 form a second-stage amplifying circuit. MP6 source and MP7 source all connect VDD, MP6 grid and MP7 grid all are connected with bias circuit's output Vb1 electricity, MP6 drain electrode is connected with resistance R1 second end, electric capacity C3 second end, MN5 source and electric capacity C2 first end electricity respectively, electric capacity C2 is connected with MN5 grid and MP4 drain electrode electricity respectively, MN5 drain electrode ground GND, MP7 drain electrode is connected with resistance R2 second end respectively, electric capacity C4 second end, MN6 source and electric capacity C1 first end electricity, electric capacity C1 is connected with MN6 grid and MP5 drain electrode electricity respectively, MN6 drain electrode ground GND, MN5 source is the positive output of common-source common-gate common-differential operational amplifier, MN6 source is the reverse output of common-source common-gate common-differential operational amplifier.
In this embodiment, the gain of the first stage amplifying circuit is
The gain of the second-stage amplifying circuit is
The gain of the operational amplifier of the integral cascode fully differential operational amplifier is
Wherein the method comprises the steps ofIs the transconductance of the MOS tube,in order to output the resistance of the resistor,in order to output the electrical conductance,。
the dynamic comparator is shown in fig. 5, and comprises a pre-amplification stage, a comparison stage and a latch stage, wherein the pre-amplification stage comprises MOS tubes MN9-MN11 and MP13-MP19, the grid electrode of the MOS tube MN9 is the reverse input end of the dynamic comparator, the grid electrode of the MOS tube MN10 is the forward input end of the dynamic comparator, the source electrode of the MN9 is respectively and electrically connected with the source electrode of the MN10 and the source electrode of the MN11, the grid electrode of the MN11 is connected with a bias circuit, the drain electrode of the MN11 is grounded GND, the drain electrode of the MN9 is respectively and electrically connected with the drain electrode of the MP13, the grid electrode of the MP13, the drain electrode of the MP14 and the drain electrode of the MP15, the drain electrode of the MP10 is respectively and electrically connected with the drain electrode of the MP16, the grid electrode of the MP16, the source electrode of the MP14, the source electrode of the MP15 and the source electrode of the MP16 are all connected with VDD. The MN9 drain electrode and the MN10 drain electrode are the positive and negative output ends of the pre-amplification stage, and the positive and negative output ends of the pre-amplification stage are electrically connected with the positive and negative input ends of the comparison stage.
The comparison stage adopts a latch structure, forms positive feedback through two inverters connected end to end, comprises MOS transistors MN12-MN19 and MP17-MP22, an MN18 grid electrode is a positive input end of the comparison stage, an MN19 grid electrode is a negative input end of the comparison stage, an MN18 source electrode and an MN19 source electrode are both grounded GND, an MN18 drain electrode is electrically connected with an MN16 source electrode, an MN16 drain electrode is electrically connected with an MN13 source electrode, an MN13 grid electrode is connected with a signal CLK, an MN13 source electrode is respectively electrically connected with an MP17 grid electrode, an MP12 grid electrode, an MP18 drain electrode, an MP19 drain electrode, an MP20 grid electrode and an MN17 grid electrode, an MN19 drain electrode is electrically connected with an MN17 source electrode, an MN17 drain electrode is electrically connected with an MN14 source electrode, the MN14 grid is connected with the signal CLK, the MN14 source is electrically connected with the MP122 grid, the MP15 grid, the MP121 drain, the MP20 drain, the MP19 grid and the MN16 grid respectively, the MP17 source, the MP18 source, the MP19 source, the MP20 source and the MP21 source are all connected with the VDD, the MP18 grid and the MP21 grid are all connected with the signal CLK, the MP17 drain is electrically connected with the MN12 drain, the MN12 source is grounded GND, the MP22 drain is electrically connected with the MN15 drain, the MN15 source is grounded GND, the MP22 drain and the MP17 drain are respectively positive and negative output ends of the comparison stage, and the positive and negative output ends of the comparison stage are electrically connected with the positive and negative input ends of the latch stage. In the comparison stage, the MOS transistors MN16, MN17, MP19, and MP20 form a positive feedback latch structure, the MOS transistors MP18 and MP21 are reset transistors, and the signal CLK is a signal EVAL output by the timing generation circuit.
The latch stage comprises MOS tubes MN20-MN23 and MP23-MP26, wherein the MP23 grid electrode and the MN20 grid electrode jointly form a negative input end of the latch stage, the MP24 grid electrode and the MN23 grid electrode jointly form a positive input end of the latch stage, the MP23 source electrode and the MP24 source electrode are both connected with VDD, the MP23 drain electrode is electrically connected with the MP25 source electrode, the MP25 drain electrode is electrically connected with the MP26 grid electrode, the MN22 grid electrode, the MN21 drain electrode and the MN20 drain electrode respectively, the MP26 drain electrode is electrically connected with the MP25 grid electrode, the MN21 grid electrode, the MN22 drain electrode and the MN23 drain electrode respectively, the MN20 source electrode, the MN22 source electrode and the MN23 source electrode are grounded, and the MP26 drain electrode and the MP25 drain electrode are respectively positive and negative output ends of the latch stage, namely a positive output end and a negative output end of the dynamic comparator.
During normal comparison, the MOS transistors MN18 and MN19 work in a linear region, the signal EVAL is high level, the MOS transistors MN13 and MN14 are turned on, and the MOS transistors MP18 and MP21 are turned off. When the comparator is reset, the signal EVAL is low level, the MOS transistors MN13 and MN15 are disconnected, the MOS transistors MP18 and MP21 are conducted, and the output is low level. Because no current passes through the comparison stage, no power consumption is generated, and the power consumption of the Sigma-Delta ADC as a whole can be reduced.
The bias circuit is shown in FIG. 6, and comprises MOS transistors MP27-MP35, MOS transistors MN24-MN34 and a resistor Rb, wherein the MP27 source electrode is connected with VDD, the MP27 drain electrode is respectively connected with MP27 gate electrode and MN24 drain electrode, the MN24 source electrode is connected with MN26 source electrode, the MN26 source electrode is connected with the first end of the resistor Rb, the second end of the resistor Rb is grounded GND, the MP28 source electrode is connected with VDD, the MP28 gate electrode is electrically connected with MP27 gate electrode, the MP28 drain electrode is electrically connected with MN25 drain electrode, the MN25 gate electrode is respectively connected with MN24 gate electrode and MN25 drain electrode, the MN25 source electrode is electrically connected with MN27 drain electrode, the MN27 gate electrode is respectively connected with MN26 gate electrode and MN27 drain electrode, the MN27 source electrode is grounded GND, the MP29 source electrode is electrically connected with VDD, the MP29 drain electrode is electrically connected with MN28 drain electrode, the MN28 gate electrode is electrically connected with MN27 drain electrode, MN28 source electrode is grounded GND, MP31 source electrode is grounded VDD, MP31 drain electrode is electrically connected with MP32 source electrode, MP32 drain electrode is electrically connected with MP33 source electrode, MP33 drain electrode is electrically connected with MP34 source electrode, MP34 drain electrode is electrically connected with MP35 source electrode, MP35 drain electrode is respectively electrically connected with MP31-MP5 gate electrode and MN29 drain electrode, MN29 gate electrode is electrically connected with MN27 drain electrode, MN29 source electrode is grounded GND, MP30 source electrode is grounded VDD, MP30 gate electrode is electrically connected with MP29 gate electrode, MP30 drain electrode is respectively electrically connected with MN34 drain electrode and MN34-MN30 gate electrode, MN34 source electrode is electrically connected with MN33 drain electrode, MN33 source electrode is electrically connected with MN32 drain electrode, MN32 source electrode is electrically connected with MN31 drain electrode, MN31 source electrode is electrically connected with MN30 drain electrode, MN30 source electrode is grounded GND.
The source electrode of MN25 outputs bias voltage Vb to the outside, the gate electrode of MP30 outputs bias voltage Vb1 to the outside, the drain electrode of MP35 outputs bias voltage Vb2 to the outside, the drain electrode of MP30 outputs bias voltage Vb3 to the outside, bias voltage Vb1 is connected to the gates of MOS transistors MP8, MP1, MP6 and MP7 of the cascode fully differential operational amplifier, bias voltage Vb2 is connected to the gates of MOS transistors MP12, MP4 and MP5 of the cascode fully differential operational amplifier, bias voltage Vb3 is connected to the gates of MOS transistors MN7, MN1 and MN2 of the cascode fully differential operational amplifier, and bias voltage Vb is connected to the gate of MOS transistor MN11 of the dynamic comparator.
In this embodiment, the reference voltage is internally fitted so that the Sigma-Delta ADC does not need to acquire the reference voltage from the temperature sensor.
The specific embodiments described herein are offered by way of example only to illustrate the spirit of the invention. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Claims (6)
1. A Sigma-Delta ADC for a temperature sensor, characterized by: comprising the following steps:
a selection switch circuit for switching the input voltage of the Sigma-Delta ADC;
the switch capacitance integrating circuit is used for sampling and holding the input voltage and integrating the input voltage;
a dynamic comparator for converting the integrated input voltage into a pulse width modulated signal BS containing temperature information;
the time sequence generating circuit provides driving signals for the selection switch circuit, the dynamic comparator and the switch capacitance integrating circuit;
the bias circuit provides bias voltage for the switched capacitor integrating circuit and the dynamic comparator;
the switching circuit is arranged in the time sequence generating circuit, the selecting switching circuit and the switched capacitor integrating circuit, is controlled by a control signal formed by one or two signals of a pulse width modulation signal BS and a driving signal and is used for counteracting the channel charge injection effect and the leakage current influence under low-frequency input;
the switching circuit is a T-shaped switch with a complementary structure and comprises an MOS tube MNA, an MOS tube MNB, an MOS tube MNC, an MOS tube MPA, an MOS tube MPB and an MOS tube MPC, wherein the drain electrode of the MOS tube MNA is electrically connected with the source electrode of the MOS tube MNB, the drain electrode of the MOS tube MPA is electrically connected with the source electrode of the MOS tube MPB, the source electrode of the MOS tube MNA is electrically connected with the source electrode of the MOS tube MPA as the input end of the switching circuit, the drain electrode of the MOS tube MNB is electrically connected with the drain electrode of the MOS tube MPB as the output end of the switching circuit, the source electrode of the MOS tube MPC is connected with a voltage VDD, the source electrode of the MOS tube MPC is electrically connected with the drain electrode of the MOS tube MPA, the MOS tube MNA, the MOS tube MNB and the MOS tube MNC are controlled by the same control signal, and the MOS tube MPA, the MOS tube MPB and the MOS tube MPC are controlled by the control signal opposite to the control signal of the MOS tube MNA, the MOS tube MPB and the MOS tube MPC;
the switch capacitance integrating circuit uses an automatic zero setting technology and comprises a first-stage fully-differential switch capacitance integrator and a second-stage fully-differential switch capacitance integrator, wherein the forward output end and the reverse output end of the first-stage fully-differential switch capacitance integrator are correspondingly connected with the forward input end and the reverse input end of the second-stage fully-differential switch capacitance integrator, the forward output end of the second-stage fully-differential switch capacitance integrator is connected with the forward input end of the dynamic comparator, and the reverse output end of the second-stage fully-differential switch capacitance integrator is connected with the reverse input end of the dynamic comparator;
the first operational amplifier and the second operational amplifier are both a common-source common-gate full-differential operational amplifier with a two-stage structure, the common-source common-gate full-differential operational amplifier comprises MOS tubes MP1-MP12, MN1-MN8, resistors R1-R2 and capacitors C1-C4, the MOS tubes MN7-MN8, the MOS tubes MP8-MP12, the resistors R1-R2 and the capacitors C3-C4 form a common-mode feedback circuit, the MOS tubes MP1-MP5 and MN1-MN4 form a first-stage amplifying circuit, and the MOS tubes MP6-MP7 and MN5-MN6 form a second-stage amplifying circuit;
the gain of the first-stage amplifying circuit is
The gain of the second-stage amplifying circuit is
The integral operational amplifier of the cascode fully differential operational amplifier has the gain of
Wherein the method comprises the steps ofTransconductance of MOS tube->For outputting resistance +.>In order to output the electrical conductance,
。
2. a Sigma-Delta ADC for temperature sensors according to claim 1, characterized in that: the timing generation circuit includes an input terminal for inputting clock signals CLK1 and CLK2 having a duty ratio of 0.5 and an output terminal for outputting signals Q1, Q2, EVAL, QF1D, QF, QF2D and QF2, the frequency of the clock signal CLK2 being twice that of the clock signal CLK1, the signal Q1 being a signal delayed from the signal CLK1 when the pulse width modulation signal BS is at a first level, the signal Q1 being a signal delayed from the signal CLK2 when the pulse width modulation signal BS is at a second level, the first level being one of a high level and a low level, the second level being opposite to the first level, the signal Q2 being opposite to the signal Q1, the signal EVAL being a pulse signal having the same period as the signal CLK1, the signal QF1 being a clock signal having the same period as the signal CLK1 and a duty ratio of 0.75, the signal QF1D being a signal delayed from the signal QF1, the signal QF2 being opposite to the signal QF 1D.
3. A Sigma-Delta ADC for temperature sensors according to claim 1, characterized in that: the selection switch circuit comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is respectively and electrically connected with a first end of the switch circuit K1, a first end of the switch circuit K2, a first end of the switch circuit K3 and a first end of the switch circuit K4, the second input end is respectively and electrically connected with a first end of the switch circuit K5 and a first end of the switch circuit K6, the first output end is respectively and electrically connected with a second end of the switch circuit K1, a second end of the switch circuit K2, a second end of the switch circuit K5 and a second end of the switch circuit K7, and the second output end is respectively and electrically connected with a second end of the switch circuit K3, a second end of the switch circuit K4, a second end of the switch circuit K2 and a second end of the switch circuit K8, and the second end of the switch circuit K7 and the second end of the switch circuit K8 are both grounded.
4. A Sigma-Delta ADC for temperature sensors according to claim 1, characterized in that: and a feedforward circuit is arranged in the switched capacitor integration circuit.
5. A Sigma-Delta ADC for temperature sensors according to claim 1, characterized in that: the dynamic comparator is sequentially connected and comprises a pre-amplification stage, a comparison stage and a latch stage, wherein the pre-amplification stage comprises MOS tubes MN9-MN11 and MP13-MP19, the comparison stage comprises MOS tubes MN12-MN19 and MP17-MP22, the latch stage comprises MOS tubes MN20-MN23 and MP23-MP26, the grid electrode of the MOS tube MN9 and the grid electrode of the MN10 are respectively the reverse input end and the forward input end of the dynamic comparator, the drain electrode of the MOS tube MN25 is positioned at the reverse output end of the dynamic comparator, and the drain electrode of the MOS tube MN26 is positioned at the forward output end of the dynamic comparator.
6. A Sigma-Delta ADC for temperature sensors according to claim 5, characterized in that: in the pre-amplification stage, an MN9 drain electrode and an MN10 drain electrode are positive and negative output ends of the pre-amplification stage; in the comparison stage, a gate electrode of MN18 and a gate electrode of MN19 are positive and negative input ends of the comparison stage, MN16, MN17, MP19 and MP20 form a positive feedback latch structure, MP18 and MP21 are reset tubes, and a drain electrode of MP22 and a drain electrode of MP17 are positive and negative output ends of the comparison stage; in the latch stage, the MP23 gate and the MN20 gate form a negative input end of the latch stage together, and the MP24 gate and the MN23 gate form a positive input end of the latch stage together.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6697006B1 (en) * | 2001-10-03 | 2004-02-24 | Analog Devices, Inc. | Conditioning circuit for selectively buffering an input signal to a signal processing circuit, and a signal processing circuit incorporating the conditioning circuit |
| US6847319B1 (en) * | 2003-07-22 | 2005-01-25 | Standard Microsystems Corporation | Temperature-to-digital converter |
| CN104836541A (en) * | 2015-03-10 | 2015-08-12 | 遵义师范学院 | Fully differential operational amplifier with adjustable GBW (Gain Bandwidth Product) for ADC (Analog to Digital Converter) |
| US9705525B1 (en) * | 2016-06-09 | 2017-07-11 | Sandisk Technologies Llc | Multiple resolution temperature sensor |
| WO2020211515A1 (en) * | 2018-05-21 | 2020-10-22 | 珠海晶通科技有限公司 | High-accuracy temperature sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5684599B2 (en) * | 2011-02-18 | 2015-03-11 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
| US10461771B2 (en) * | 2018-03-20 | 2019-10-29 | Texas Instruments Incorporated | Sigma-delta analog-to-digital converter with multiple counters |
-
2021
- 2021-09-07 CN CN202111043077.3A patent/CN113746483B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6697006B1 (en) * | 2001-10-03 | 2004-02-24 | Analog Devices, Inc. | Conditioning circuit for selectively buffering an input signal to a signal processing circuit, and a signal processing circuit incorporating the conditioning circuit |
| US6847319B1 (en) * | 2003-07-22 | 2005-01-25 | Standard Microsystems Corporation | Temperature-to-digital converter |
| CN104836541A (en) * | 2015-03-10 | 2015-08-12 | 遵义师范学院 | Fully differential operational amplifier with adjustable GBW (Gain Bandwidth Product) for ADC (Analog to Digital Converter) |
| US9705525B1 (en) * | 2016-06-09 | 2017-07-11 | Sandisk Technologies Llc | Multiple resolution temperature sensor |
| WO2020211515A1 (en) * | 2018-05-21 | 2020-10-22 | 珠海晶通科技有限公司 | High-accuracy temperature sensor |
Non-Patent Citations (2)
| Title |
|---|
| Yong Wang,Yan Hong,Wang Ling Goh,Kevin C. T. Chai.A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization.2017 IEEE International Symposium on Circuits and Systems (ISCAS).2017,1-4. * |
| 一种高精度CMOS温度传感器的设计;黄继伟，张祥;福州大学学报(自然科学版);第48卷(第5期);585-590 * |
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