CN111865315B - Comparator circuit suitable for assembly line flash ADC - Google Patents
Comparator circuit suitable for assembly line flash ADC Download PDFInfo
- Publication number
- CN111865315B CN111865315B CN202010670791.4A CN202010670791A CN111865315B CN 111865315 B CN111865315 B CN 111865315B CN 202010670791 A CN202010670791 A CN 202010670791A CN 111865315 B CN111865315 B CN 111865315B
- Authority
- CN
- China
- Prior art keywords
- transistor
- comparator
- differential
- input pair
- differential input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Abstract
The invention provides a comparator circuit suitable for a pipeline flash ADC, which comprises: the device comprises a pre-amplification module, a first-stage comparison module and a second-stage comparison module; the pre-amplifying module comprises a pre-amplifier, and the first-stage comparing module and the second-stage comparing module both comprise comparators; by setting two stages of different comparators and adopting a pipeline type clock signal to sequentially trigger the preamplifier and the two stages of comparators, the regeneration time of the comparators is equivalently prolonged, the conversion speed of the flash ADC is improved, the generation probability of a metastable state when the pipeline flash ADC is compared in the two stages of comparators is effectively reduced, and the sampling efficiency of the flash ADC circuit is effectively improved.
Description
Technical Field
The invention belongs to the technical field of analog-to-digital conversion, and relates to a comparator circuit suitable for a pipeline flash ADC.
Background
flash ADCs (ultra-high-speed Analog-to-Digital converters) are widely used in many technical fields such as modern communication field, data acquisition and optical communication field. As data processing speeds increase, the requirements on the analog to digital conversion rate in data acquisition and storage systems also increase. At present, a flash ADC is limited by a traditional structure, namely when the precision of an analog-to-digital converter is N, the number of correspondingly required comparators is 2N-1, and the number of divider resistors is 2N; when the precision is improved, the number of the comparators and the divider resistors is increased sharply, which affects the analog-to-digital conversion speed of the flash ADC and restricts the analog-to-digital conversion speed of the flash ADC.
In order to improve the structural defect, a commonly used solution at present is mainly to use a comparator with a folded interpolation structure, and although the number of required comparators can be reduced to a certain extent, the folded interpolation structure has the problems of reduced precision at a folded point, easy occurrence of metastable state and the like, that is, when input levels of two input ends of the comparator are very close, the output of the comparator is uncertain for a long time, and the efficiency of analog-to-digital conversion is reduced to a certain extent.
Therefore, how to improve the overall analog-to-digital conversion speed and stability while ensuring the conversion accuracy of the flash ADC has become a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a comparator circuit suitable for a pipelined flash ADC, the comparator circuit comprising: the pre-amplification module comprises n pre-amplifiers and is used for amplifying input differential signals and reference differential signals input into each pre-amplifier to obtain different first differential signals; a first-stage comparison module comprising n first comparators and n-1 first interpolation comparators; wherein n is an integer greater than 1; each first comparator corresponds to each preamplifier one by one; the input end of the first comparator is connected with the output end of the corresponding preamplifier and used for comparing the first differential signal output by the preamplifier to obtain a compared second differential signal; each first interpolation comparator is arranged between two adjacent preamplifiers, a first input end of each first interpolation comparator is connected with an output end of one preamplifier of the two corresponding adjacent preamplifiers, and a second input end of each first interpolation comparator is connected with an output end of the other preamplifier of the two corresponding adjacent preamplifiers, and is used for comparing first differential signals respectively output by the two adjacent preamplifiers to obtain a third differential signal; a second stage comparison module comprising 2n-2 second interpolation comparators; each second interpolation comparator is arranged between the adjacent first comparator and the first interpolation comparator, the first input end of the second interpolation comparator is connected with the output end of the corresponding first interpolation comparator in the adjacent first comparator and the first interpolation comparator, and the second input end of the second interpolation comparator is connected with the output end of the corresponding first comparator in the adjacent first comparator and the first interpolation comparator, and is used for comparing the second differential signal output by the first comparator with the third differential signal output by the first interpolation comparator to obtain a second interpolation comparison result; each second interpolation comparison result forms a final output result of the comparator circuit; the pre-amplification module, the first-stage comparison module and the second-stage comparison module are respectively connected with a clock signal module and respectively connected with a first clock signal, a second clock signal and a third clock signal, so that the pre-amplification module switches respective working states according to the first clock signal, the first-stage comparison module according to the second clock signal and the second-stage comparison module according to the third clock signal, and comparison operation of the comparator circuit is achieved.
In an embodiment of the invention, the first clock signal, the second clock signal, and the third clock signal are pipelined clock signals, and have a delay interval in sequence.
In an embodiment of the present invention, the preamplifier includes a first differential input pair transistor, a second differential input pair transistor, a first switch transistor and a first tail pipe; the first differential input pair of transistors and the second differential input pair of transistors each comprise a first transistor and a second transistor; a first transistor of the first differential input pair tube and a first transistor of the second differential input pair tube are connected to the input differential signal, and a second transistor of the first differential input pair tube and a second transistor of the second differential input pair tube are connected to the reference differential signal; the first differential input pair tube and the second differential input pair tube are both connected with the first tail tube; the output end of the first differential input pair transistor is the first output end of the preamplifier and is connected with the first input end of the first switch transistor; the output end of the second differential input pair transistor is the second output end of the preamplifier and is connected with the second input end of the first switch transistor; the control end of the first switch tube is connected to the first clock signal, so that the preamplifier compares the input differential signal with the reference differential signal according to the first clock signal to obtain the first differential signal.
In an embodiment of the present invention, the first interpolating comparator includes a third differential input pair tube, a fourth differential input pair tube, a second switch tube and a first reproducible latch; the third differential input pair transistor and the fourth differential input pair transistor each comprise a first transistor and a second transistor; the first transistor of the third differential input pair transistor and the first transistor of the fourth differential input pair transistor are correspondingly connected with the first output end and the second output end of one preamplifier of two adjacent preamplifiers, and the second transistor of the third differential input pair transistor and the second transistor of the fourth differential input pair transistor are correspondingly connected with the first output end and the second output end of the other preamplifier of the two adjacent preamplifiers; the output end of the third differential input pair transistor is connected with the first input end of the first reproducible latch and the first input end of the second switch transistor; the output end of the fourth differential input pair transistor is connected with the second input end of the first reproducible latch and the second input end of the second switching tube; the two output ends of the first reproducible latch are the two output ends of the first interpolating comparator; and the control end of the second switch tube is connected with a second clock signal, so that the first interpolation comparator compares the two input groups of first differential signals according to the second clock signal to obtain a third differential signal.
In an embodiment of the present invention, the transistors in the first differential input pair transistor and the second differential input pair transistor are both PMOS transistors.
In an embodiment of the present invention, the first comparator includes a fifth differential input pair transistor, a sixth differential input pair transistor, a third switch transistor, and a second regenerative latch; the fifth differential input pair transistor and the sixth differential input pair transistor each comprise a first transistor and a second transistor; the first transistor of the fifth differential input pair transistor and the first transistor of the sixth differential input pair transistor are connected with the corresponding first output end of the preamplifier, and the second transistor of the fifth differential input pair transistor and the second transistor of the sixth differential input pair transistor are connected with the corresponding second output end of the preamplifier; the output end of the fifth differential input pair transistor is connected with the first input end of the second reproducible latch and the first input end of the third switching transistor; the output end of the sixth differential input pair transistor is connected with the second input end of the second reproducible latch and the second input end of the third switching transistor; two output ends of the second reproducible latch are two output ends of the first comparator; the control end of the third switch tube is connected to the second clock signal, so that the first comparator compares the connected first differential signal according to the second clock signal to obtain the second differential signal.
In an embodiment of the present invention, the second interpolation comparator includes a seventh differential input pair transistor, an eighth differential input pair transistor, a fourth switch transistor, a third regenerative latch, and a second tail pipe; the seventh differential input pair tube and the eighth differential input pair tube are connected with the second tail tube, and both the seventh differential input pair tube and the eighth differential input pair tube comprise a first transistor and a second transistor; the first transistor of the seventh differential input pair tube and the first transistor of the eighth differential input pair tube are correspondingly connected with two output ends of the first interpolation comparator in the adjacent first comparator and first interpolation comparator, and the second transistor of the seventh differential input pair tube and the second transistor of the eighth differential input pair tube are correspondingly connected with two output ends of the first comparator in the adjacent first comparator and first interpolation comparator; the output end of the seventh differential input pair transistor is connected with the first input end of the third regenerative latch and the first input end of the fourth switching tube; the output end of the eighth differential input pair transistor is connected with the second input end of the third regenerative latch and the second input end of the fourth switching transistor; the two outputs of the third reproducible latch are the two outputs of the second interpolative comparator; and the control end of the fourth switching tube is connected to the third clock signal, so that the second interpolation comparator compares the input second differential signal with the third differential signal according to the third clock signal to obtain a second interpolation comparison result.
In an embodiment of the present invention, transistors in the seventh differential input pair transistor and the eighth differential input pair transistor are both NMOS transistors.
In an embodiment of the invention, a first delay time is provided between the second clock signal and the third clock signal, and the first delay time is adapted to the regeneration time of the first comparator and the first interpolation comparator.
In an embodiment of the invention, the first clock signal and the second clock signal have opposite phases, and the second clock signal and the third clock signal have opposite phases.
In an embodiment of the present invention, the pipeline flash ADC includes a voltage dividing resistor network; the pre-amplification module is connected with the voltage-dividing resistor network, so that reference differential voltage is converted into different reference differential signals through the voltage-dividing resistor network and is input into the pre-amplifiers in the pre-amplification module.
As described above, the comparator circuit suitable for the pipeline flash ADC provided by the present invention has the following technical effects by setting up the preamplifier and two stages of different comparators, and sequentially triggering the preamplifier and the two stages of comparators by using the pipeline clock signal:
1) by adopting the structure, when the clock signal is not inverted, the next-stage comparator cannot be triggered to work, so that the probability of metastable state of the comparator is reduced.
2) By adopting the pipelined clock to trigger each stage of comparison module, the comparison time of each stage of comparison module can be greatly shortened, and the overall conversion rate of the flash ADC system is improved.
Drawings
FIG. 1 is a schematic diagram of a comparator circuit for a pipelined flash ADC according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a single preamplifier according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a single first interpolation comparator in one embodiment of the present invention;
FIG. 4 is a schematic diagram of a single first comparator according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a single second interpolation comparator in one embodiment of the present invention;
FIG. 6 is a timing diagram illustrating the clock signals of each stage according to an embodiment of the present invention;
fig. 7 is a schematic diagram showing a circuit structure for implementing the timing sequence of the clock signals of each stage according to the present invention.
Description of the element reference
110 pre-amplifying module
111 preamplifier
120 first stage comparison module
121 first comparator
122 first interpolation comparator
130 second stage comparison module
131 second interpolation comparator
210 first differential input pair transistor
211 first differential input pair transistor
212 second transistor of the first differential input pair
220 second differential input pair transistor
221 first transistor of second differential input pair
222 second transistor of a second differential input pair of transistors
230 first switch tube
240 first tail pipe
251 first signal input terminal
252 second signal input terminal
253 third signal input terminal
254 fourth signal input terminal
261 first signal output terminal
262 second signal output terminal
310 third differential input pair transistor
311 first transistor of third differential input pair
312 second transistor of third differential input pair transistor
320 fourth differential input pair tube
321 first transistor of fourth differential input pair transistor
322 second transistor of fourth differential input pair
330 second switch tube
340 first reproducible latch
351 third signal output terminal
352 fourth signal output terminal
410 fifth differential input pair transistor
411 first transistor of fifth differential input pair transistor
412 fifth differential input pair transistor
420 sixth differential input pair transistor
421 first transistor of sixth differential input pair
422 second transistor of sixth differential input pair transistor
430 third switch tube
440 second reproducible latch
451 fifth signal output terminal
452 sixth signal output terminal
510 seventh differential input pair transistor
511 first transistor of seventh differential input pair transistor
512 second transistor of seventh differential input pair transistor
520 eighth differential input pair transistor
521 first transistor of eighth differential input pair transistor
522 second transistor of eighth differential input pair transistor
530 fourth switching tube
540 third reproducible latch
550 second tail pipe
561 seventh signal output terminal
562 eighth signal output terminal
Mn 1-Mn 18 first-eighteenth NMOS tubes
Mp 1-Mp 14 first PMOS tube-fourteenth PMOS tube
Sixth NMOS transistor to eleventh NMOS transistor of first interpolation comparator Mn6 to Mn11
Sixth NMOS tube to eleventh NMOS tube of Mn6 '-Mn 11' first comparator
Third PMOS tube to eighth PMOS tube of Mp 3-Mp 8 first interpolation comparator
Third PMOS tube to eighth PMOS tube of Mp3 'Mp 8' first comparator
Clk _1 to Clk _3 first to third clock signals
Vin-Vip input differential signal
Vref _ nk-Vref _ pk reference differential signal
Vin1_ i-Vip1_ i ith first differential signal
Vin2_ i-Vip2_ i ith second differential signal
Vin3_ i-Vip3_ i ith third differential signal
Vref _ nk1-Vref _ pk1 first to nth reference differential signals
Vref_nkn-Vref_pkn
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The technical principle of the comparator circuit applicable to the pipeline flash ADC is as follows: by setting two different stages of comparators and adopting a pipelined clock signal to sequentially trigger the preamplifier and the two stages of comparators, the regeneration time of the comparators is equivalently prolonged, so that the probability of metastable state occurrence when the flash ADC adopting an interpolation structure is compared in the two stages of comparators after pre-amplification treatment is effectively reduced, and the sampling efficiency of the flash ADC circuit is effectively improved.
In this embodiment, a comparator circuit suitable for a pipelined flash ADC is provided, the circuit including: the device comprises a pre-amplification module, a first-stage comparison module and a second-stage comparison module. The first-stage comparison module is a P-type MOS comparator array; the second-stage comparison module is an N-type MOS comparator array. The pre-amplification module, the first comparison module and the second comparison module are sequentially connected step by step.
The pre-amplification module, the first-stage comparison module and the second-stage comparison module are respectively connected with an external clock signal module and are used for respectively accessing a first clock signal, a second clock signal and a third clock signal, so that the pre-amplification module switches respective working states according to the first clock signal, the first-stage comparison module according to the second clock signal and the second-stage comparison module according to the third clock signal, and comparison operation of the comparator circuit is realized.
Furthermore, the clock signal module is a pipelined clock generator, and the first clock signal, the second clock signal and the third clock signal are pipelined clock signals and have delay intervals in sequence; different pipelined clock signals are adopted to trigger each stage of circuit to start working respectively, the final output result of the comparator circuit is obtained, namely, the thermometer code is obtained, and the thermometer code is transmitted to a non-binary coding circuit of the flash ADC for conversion.
In this embodiment, the pre-amplification module, the first comparison module, and the second comparison module in the comparator circuit are all connected to an external power source through a first power input terminal and a second power input terminal, and power supply to the pre-amplification module, the first comparison module, and the second comparison module is realized through the external power source.
The pre-amplification module comprises n pre-amplifiers, namely a first pre-amplifier to an nth pre-amplifier; wherein n is an integer greater than 1. The preamplifier has the same structure and is used for amplifying the input differential signal Vin-Vip input to the preamplifier and different reference differential signals to obtain different first differential signals.
Further, the pre-amplification module is connected with a voltage-dividing resistor network in the pipeline flash ADC, so that the reference differential voltage Vref _ nk-Vref _ pk is converted into different reference differential signals through the voltage-dividing resistor network, namely Vref _ nk1-Vref _ pk1, Vref _ nk2-Vref _ pk2 … … Vref _ nkn-Vref _ pkn, and each reference differential signal is input into each pre-amplifier in the pre-amplification module.
The first-stage comparison module is of an interpolation structure and comprises n first comparators and n-1 first interpolation comparators; the first comparators are in one-to-one correspondence with the preamplifiers, and the input ends of the first comparators are connected with the output ends of the corresponding preamplifiers, that is, the ith preamplifier is correspondingly connected with the ith first comparator (i is smaller than n), and the first comparators are used for comparing the first differential signals output by the ith preamplifier to obtain second differential signals after comparison.
Each first interpolation comparator is arranged between two adjacent preamplifiers, a first input end of each first interpolation comparator is connected with an output end of one corresponding preamplifier in two adjacent preamplifiers, and a second input end of each first interpolation comparator is connected with an output end of the other corresponding preamplifier in two adjacent preamplifiers, so that first differential signals respectively output by two adjacent preamplifiers are compared to obtain a third differential signal; the first input end of the ith first interpolation comparator is connected with the output end of the ith preamplifier, and the second input end of the ith first interpolation comparator is connected with the jth preamplifier, so that a first differential signal output by the ith preamplifier and the first differential signal output by the jth preamplifier are compared to obtain a third differential signal; wherein, the ith preamplifier and the jth preamplifier are adjacent preamplifiers.
The second-stage comparison module is of an interpolation structure and comprises 2n-2 second interpolation comparators; each second interpolation comparator is arranged between the adjacent first comparator and first interpolation comparator, and the first input end of the second interpolation comparator is connected with the output end of the corresponding first interpolation comparator in the adjacent first comparator and first interpolation comparator; a second input end of the second interpolation comparator is connected to the output end of the corresponding adjacent first comparator and the output end of the first comparator in the first interpolation comparators, and is used for comparing a second differential signal output by the first comparator with a third differential signal output by the first interpolation comparator to obtain a second interpolation comparison result; each of the second interpolation comparison results constitutes a final output result of the comparator circuit.
Please refer to fig. 2, which shows a schematic structural diagram of a single preamplifier in this embodiment. As shown in fig. 2, a single one of the preamplifiers includes: the differential input device comprises a first signal input end, a second signal input end, a first signal output end, a second signal output end, a first differential input pair tube, a second differential input pair tube, a first switch tube and a first tail tube.
The first signal input end and the fourth signal input end are used for accessing the input differential signal Vin-Vip, and the second signal input end and the third signal input end are used for accessing the reference differential signal Vref _ nk-Vref _ pk. It should be noted that the reference differential signals Vref _ nk-Vref _ pk accessed in each of the preamplifiers are different.
The first switching tube comprises a first PMOS tube Mp1 and a second PMOS tube Mp2, the drains of the first switching tube and the second switching tube are connected with the first power supply input end, and the gates of the first switching tube and the second switching tube are connected with a first clock signal Clk _ 1; the source electrode of the first PMOS tube Mp1 is connected with the first signal output end; and the source electrode of the second PMOS pipe Mp2 is connected with the second signal output end.
The first differential input pair transistor comprises a first NMOS transistor Mn1 and a third MOS transistor Mn3, the drains of the first NMOS transistor Mn1 and the third MOS transistor Mn3 are connected with the first signal output end, the grid electrode of the first NMOS transistor Mn1 is connected with the first signal input end, and the grid electrode of the third MOS transistor Mn3 is connected with the third signal input end.
The second differential input pair transistor comprises a second NMOS transistor Mn2 and a fourth MOS transistor Mn4, the drains of the second NMOS transistor Mn2 and the fourth MOS transistor Mn4 are connected with the second signal output end, the grid electrode of the second NMOS transistor Mn2 is connected with the third signal input end, and the grid electrode of the fourth MOS transistor Mn4 is connected with the fourth signal input end.
The first tail tube is a fifth MOS tube Mn5, the drain electrode is connected with the source electrodes of the first NMOS tube Mn1 to the fourth NMOS tube Mn4, the grid electrode is connected with a first clock signal Clk _1, and the source electrode is connected with the second power supply input end.
The pre-amplification module controls the on-off of the first switch tube and the first tail tube through the first clock signal, and controls the pre-amplifier to switch the working state, so that the differential signals input by the signal input ends are amplified.
Specifically, when the first clock signal Clk _1 is at a low level, the pre-amplification module is in a reset state, and both the first signal output end and the second signal output end are at a high level; when the first clock signal Clk _1 is changed from a low level to a high level, the pre-amplification module starts to operate, the fifth NMOS transistor Mn5 is turned on, the drain voltage value of the fifth NMOS transistor Mn5 becomes a low level, the first to fourth differential input pair transistors are all in an unsaturated region, the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are in an off state, and voltage signals output by the first signal output terminal and the second signal output terminal gradually decrease from the high level along with the turn-on of each input pair transistor; however, because a certain difference exists between the input differential signals, the falling amplitudes of the first output voltage output by the first signal output terminal and the second output voltage signal output by the second signal output terminal are different, that is, the difference exists between the falling amplitudes of the first output voltage and the second output voltage.
Please refer to fig. 3, which is a schematic diagram illustrating a structure of the first interpolation comparator in the present embodiment. As shown in fig. 3, a single one of the first interpolative comparators comprises: the first regenerative latch comprises a third signal output end, a fourth signal output end, a third differential input pair tube, a fourth differential input pair tube, a second switch tube and a first regenerative latch.
Wherein the third differential input pair of transistors and the fourth differential input pair of transistors each comprise a first transistor and a second transistor; the first transistor of the third differential input pair transistor and the first transistor of the fourth differential input pair transistor are correspondingly connected with the first signal output end and the second signal output end of one preamplifier in two adjacent preamplifiers; the second transistor of the third differential input pair transistor and the second transistor of the fourth differential input pair transistor are correspondingly connected with the first signal output end and the second signal output end of the other preamplifier of the two adjacent preamplifiers, and are used for being respectively connected with two groups of first differential signals output by the two adjacent preamplifiers of the previous stage.
In a specific implementation manner, for the ith first interpolating comparator, the first transistor of the third differential input pair transistor and the first transistor of the fourth differential input pair transistor are correspondingly connected to the first signal output terminal and the second signal output terminal of the ith preamplifier of the previous stage, and are used for accessing the ith first differential signals Vin1_ i and Vip1_ i output by the ith preamplifier; the second transistor of the third differential input pair transistor and the second transistor of the fourth differential input pair transistor are correspondingly connected with the first signal output end and the second signal output end of the jth preamplifier, and are used for accessing jth first differential signals Vin1_ j and Vip1_ j output by the jth preamplifier; wherein the jth preamplifier and the ith preamplifier are adjacent preamplifiers.
The output end of the third differential input pair transistor is connected with the first input end of the first reproducible latch and the first input end of the second switch transistor; and the output end of the fourth differential input pair transistor is connected with the second input end of the first reproducible latch and the second input end of the second switching tube.
The two output ends of the first reproducible latch are the two output ends of the first interpolating comparator; the control end of the second switch tube is connected to the second clock signal; a first output end of a second switch tube is connected with the output end of the third differential input pair tube and the third signal output end, and a second output end of the second switch tube is connected with the output end of the fourth differential input pair tube and the fourth signal output end; the second switch tube controls the on and off of the second switch tube according to the second clock signal accessed by the control end, so that the first interpolation comparator is controlled to compare two groups of input first differential signals according to the second clock signal, and the third differential signal is obtained.
In this embodiment, the second switch tube includes the sixth NMOS tube Mn6, the seventh NMOS tube Mn7, the tenth NMOS tube Mn10 and the eleventh NMOS tube Mn11, and the sources thereof are all connected to the second power input end; the gates of the sixth NMOS transistor Mn6 and the seventh NMOS transistor Mn7 are connected to receive the second clock signal Clk _ 2; the drain of the sixth NMOS transistor Mn6 is connected to the output of the third differential input pair transistor, and the drain of the seventh NMOS transistor Mn7 is connected to the third signal output terminal; the gates of the tenth NMOS transistor Mn10 and the eleventh NMOS transistor Mn11 are connected to the second clock signal Clk _ 2; the drain of the eleventh NMOS transistor Mn11 is connected to the output of the fourth differential input pair transistor, and the drain of the tenth NMOS transistor Mn10 is connected to the fourth signal output terminal, so that when the second clock signal Clk _2 is at a high level, the second switch transistor keeps the first interpolating comparator in an inactive state, that is, the first interpolating comparator circuit does not operate, and the third differential input pair transistor, the output of the fourth differential input pair transistor, and the third signal output terminal and the fourth signal output terminal are all set to a low level.
In this embodiment, the third differential input pair transistor includes the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4, sources of the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4 are connected to the first power input terminal, drains of the third PMOS transistor Mp4 and the fourth PMOS transistor Mp are connected to serve as output terminals of the third differential input pair transistor, and a drain of the sixth NMOS transistor Mn6 and a first input terminal of the first regenerative latch are connected to each other; and the differential input signal accessed by the third differential input pair tube is converted into a corresponding current value and is input into the first reproducible latch.
The fourth differential input pair transistor comprises a fifth PMOS transistor Mp5 and a sixth PMOS transistor Mp6, sources of the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 are both connected with the first power supply input end, drains of the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 are connected to serve as output ends of the fourth differential input pair transistor, and a drain of an eleventh NMOS transistor Mn11 and a second input end of the first reproducible latch are connected; and the differential input signals accessed by the fourth differential input pair tube and the fifth differential input pair tube are converted into corresponding current values and input into the first reproducible latch.
The first reproducible latch comprises a seventh PMOS tube Mp7, an eighth PMOS tube Mp8, an eighth NMOS tube Mn8 and a ninth NMOS tube Mn 9; a source electrode of the seventh PMOS transistor Mp7 is used as a first input end of the first regenerative latch, and is connected to the drain electrode of the sixth NMOS transistor Mn6 and the output end of the third differential input pair transistor, a gate electrode of the seventh PMOS transistor Mp7 is connected to the gate electrode of the eighth NMOS transistor Mn8, the drain electrode of the ninth NMOS transistor Mn9, the drain electrode of the eighth PMOS transistor Mp8, and the fourth signal output end, and a drain electrode of the seventh PMOS transistor Mp7 is connected to the drain electrodes of the seventh NMOS transistor Mn7 and the eighth NMOS transistor Mn8, the gate electrode of the ninth NMOS transistor Mn9, the gate electrode of the eighth PMOS transistor Mp8, and the third signal output end; the source of the eighth PMOS transistor Mp8 is used as the second input end of the first regenerative latch, and is connected to the drain of the eleventh NMOS transistor Mn11 and the output end of the fourth differential input pair transistor, the gate of the eighth PMOS transistor Mp8 is connected to the gate of the ninth NMOS transistor Mn9, the drain of the eighth NMOS transistor Mn8, the drain of the seventh PMOS transistor Mp7, and the third signal output end, and the drain of the eighth PMOS transistor Mp8 is connected to the drains of the ninth NMOS transistor Mn9 and the tenth NMOS transistor Mn10, the gate of the eighth NMOS transistor Mn8, the gate of the seventh PMOS transistor Mp7, and the fourth signal output end. The seventh PMOS transistor Mn7 and the eighth PMOS transistor Mn8 form a parallel positive feedback path of the first reproducible latch, and are configured to adjust the output levels of the third signal output end and the fourth signal output end according to the magnitudes of the input signals connected to the first input end and the second input end of the first reproducible latch; in a specific embodiment, when the input signal inputted to the first input terminal of the first reproducible latch is greater than the input signal inputted to the second input terminal of the first reproducible latch, the output level of the third signal output terminal is set to be a high level, and the output level of the fourth signal output terminal is set to be a low level; and vice versa, namely when the input signal accessed by the first signal input end of the first reproducible latch is smaller than the input signal accessed by the second signal input end of the first reproducible latch, the output level of the third signal output end is set to be low level, and the output level of the fourth signal output end is set to be high level.
Please refer to fig. 4, which is a schematic structural diagram of a single first comparator in the present embodiment. As shown in fig. 4, the single first comparator and the first interpolation comparator are similar in structure, including: the first differential input pair transistor comprises a first signal output end, a first differential input pair transistor, a first switch transistor and a first reproducible latch.
The circuit structure of the first comparator and the first interpolation comparator are substantially the same, wherein the circuit structure of the second reproducible latch and the circuit structure of the first reproducible latch are the same; the circuit structures of the third switching tube and the second switching tube are the same; and the circuit connection relation between the third switch tube and the second reproducible latch is the same as the circuit connection relation between the second switch tube and the first reproducible latch in the first interpolation comparator, that is, the output end of the fifth differential input pair tube is connected with the first input end of the second reproducible latch and the first input end of the third switch tube; the output end of the sixth differential input pair transistor is connected with the second input end of the second reproducible latch and the second input end of the third switching transistor; two output ends of the second reproducible latch are two output ends of the first comparator; and the control end of the third switching tube is connected to the second clock signal.
The circuit configurations of the first comparator and the first interpolative comparator are different in that the configurations of the two differential input pair transistors in the first comparator and the two differential input pair transistors in the first interpolative comparator are different.
Wherein the fifth and sixth differential input pair of transistors each comprise a first transistor and a second transistor; the first transistor of the fifth differential input pair transistor and the first transistor of the sixth differential input pair transistor are connected with the corresponding first signal output end of the preamplifier; and the second transistor of the fifth differential input pair transistor and the second transistor of the sixth differential input pair transistor are connected with the second signal output end of the corresponding preamplifier, and are used for accessing the first differential signal output by the corresponding preamplifier.
Please refer to fig. 5, which is a schematic structural diagram of a single second interpolation comparator in the present embodiment. As shown in fig. 5, a single said second interpolative comparator, comprising: the system comprises a seventh signal output end, an eighth signal output end, a seventh differential input pair tube, an eighth differential input pair tube, a fourth switch tube, a third regenerative latch and a second tail tube.
Wherein the seventh differential input pair of transistors and the eighth differential input pair of transistors each comprise a first transistor and a second transistor; the first transistor of the seventh differential input pair and the first transistor of the eighth differential input pair are connected to the third signal output terminal and the fourth signal output terminal of the corresponding first interpolating comparator; a second transistor of the seventh differential input pair transistor and a second transistor of the eighth differential input pair transistor are connected to the corresponding fifth signal output terminal and the sixth signal output terminal of the first comparator, and are configured to access the third differential signal output by the first interpolation comparator and the second differential signal output by the first comparator; the first interpolation comparator and the first comparator correspondingly connected with the second interpolation comparator are adjacent comparators in the first-stage comparison module.
In a specific implementation manner, for the ith second interpolation comparator, the first transistor of the seventh differential input pair transistor and the first transistor of the eighth differential input pair transistor are correspondingly connected to the third signal output terminal and the fourth signal output terminal of the ith first interpolation comparator of the previous stage, so as to access the ith third differential signal Vin3_ i and vip3_ i output by the ith first interpolation comparator; the second transistor of the seventh differential input pair transistor and the second transistor of the eighth differential input pair transistor are correspondingly connected to the fifth signal output terminal and the sixth signal output terminal of the ith first comparator of the previous stage, and are used for accessing the ith second differential signal Vin2_ i and Vip2_ i output by the ith first comparator.
The output end of the seventh differential input pair transistor is connected with the first input end of the third reproducible latch, and the output end of the eighth differential input pair transistor is connected with the second input end of the third reproducible latch; the public alternating point of the seventh differential input pair tube and the eighth differential input pair tube is connected with the second tail tube
The control end of the fourth switching tube is connected to the third clock control signal; a first output end of the fourth switching tube is connected with an output end of the seventh differential input pair tube, a first input end of the third regenerative latch and the seventh signal output end; a second output end of the fourth switching tube is connected with an output end of the eighth differential input pair tube, a second input end of the third reproducible latch and the eighth signal output end; and the fourth switching tube controls the conduction and the disconnection of the third switching tube according to a third clock signal input by the control end, so that the second interpolation comparator is controlled to compare the input second differential signal with the third differential signal according to the third clock signal, and a second interpolation comparison result is obtained.
In this embodiment, the fourth switching tube includes a ninth PMOS tube Mp9, a tenth PMOS tube Mp10, an eleventh PMOS tube Mp11 and a twelfth PMOS tube Mp12, and a source of each PMOS tube is connected to the first power input end; the grid electrode of each PMOS tube is connected to the third clock signal; the drain of the ninth PMOS transistor Mp9 is connected to the output end of the seventh differential input pair transistor; the drain of the twelfth PMOS tube Mp12 is connected to the output end of the eighth differential input pair tube; the drain electrode of the tenth PMOS transistor Mp10 is connected to the seventh signal output terminal; the drain electrode of the eleventh PMOS tube Mp11 is connected with the eighth signal output end; and when the third clock signal Clk _3 is at a low level and the fourth switching transistor enables the second interpolative comparator circuit to be in an inactive state, the output terminals of the seventh differential input pair transistor, the eighth differential input pair transistor, and the first output terminal and the second output terminal of the third regenerative latch are set to a high level.
The second tail tube is a sixteenth NMOS tube Mn16, the gate of the second tail tube is connected to the third clock signal Clk _3, the source of the second tail tube is connected to the second power input terminal, and the drain of the second tail tube is connected to the common ac ground of the seventh differential input pair tube and the eighth differential input pair tube, so as to provide current for the second interpolating comparator circuit; when the third clock signal Clk _3 is low, there is no current in the third regenerative latch even in the reset mode, so that the power consumption of the second interpolative comparator can be reduced.
The seventh differential input pair transistor comprises a twelfth NMOS transistor Mn12 and a thirteenth NMOS transistor Mn13, sources of the twelfth NMOS transistor and the thirteenth NMOS transistor are connected with a drain of the sixteenth NMOS transistor Mn16, drains of the twelfth NMOS transistor and the thirteenth NMOS transistor are connected and then serve as an output end of the seventh differential input pair transistor and a first input end of the third reproducible latch; and the differential input signal accessed by the seventh differential input pair tube is converted into a corresponding current value and is input into the third reproducible latch.
The eighth differential input pair transistor comprises a fourteenth NMOS transistor Mn14 and a fifteenth NMOS transistor Mn15, sources of the fourteenth NMOS transistor Mn14 and the fifteenth NMOS transistor Mn15 are connected with a drain of the sixteenth NMOS transistor Mn16, drains of the fourteenth NMOS transistor Mn15 and the fifteenth NMOS transistor Mn16 are connected and then serve as an output end of the eighth differential input pair transistor, and are connected with a second input end of the third reproducible latch; and the differential input signals accessed by the eighth differential input pair tube are converted into corresponding current values and input into the third reproducible latch.
The third reproducible latch comprises a thirteenth PMOS tube Mp13, a fourteenth PMOS tube Mp14, a seventeenth NMOS tube Mn17 and an eighteenth NMOS tube Mn 18; the gate of the thirteenth PMOS transistor Mp13 is connected to the gate of the seventeenth NMOS transistor Mn17, the drain of the fourteenth PMOS transistor Mp14, the drain of the eighteenth NMOS transistor Mn18, the drain of the eleventh PMOS transistor Mp11, and the eighth signal output terminal; the gate of the fourteenth PMOS transistor Mp14 is connected to the gate of the eighteenth NMOS transistor Mn18, the drain of the thirteenth PMOS transistor Mp13, the drain of the seventeenth NMOS transistor Mn17, the drain of the tenth PMOS transistor Mp10, and the seventh signal output terminal. The source electrode of a seventeenth NMOS transistor Mn17 is used as a first input end in the third reproducible latch and is connected with the drain electrode of a ninth PMOS transistor Mp9 and the output end of the seventh differential input pair transistor; the drain of a seventeenth NMOS transistor Mn17 is connected to the drain of a tenth PMOS transistor Mp10, the drain of a thirteenth PMOS transistor Mp13, the gate of a fourteenth PMOS transistor Mp14, the gate of an eighteenth NMOS transistor Mn18, and the seventh signal output terminal; the grid electrode of a seventeenth NMOS tube Mn17 is connected with the grid electrode of a thirteenth PMOS tube Mp13, the drain electrode of an eleventh PMOS tube Mp14, the drain electrode of a fourteenth PMOS tube Mp14, the drain electrode of an eighteenth NMOS tube Mn18 and the eighth signal output end; the source electrode of an eighteenth NMOS transistor Mn18 is used as a second input end in the third reproducible latch, and is connected with the drain electrode of a twelfth PMOS transistor Mp12 and the output end of the eighth differential input pair transistor; the drain of the eighteenth NMOS transistor Mn18 is connected to the drain of the eleventh PMOS transistor Mp11, the drain of the fourteenth PMOS transistor Mp14, the gate of the thirteenth PMOS transistor Mp13, the gate of the seventeenth NMOS transistor Mn17, and the eighth signal output terminal; the gate of the eighteenth NMOS transistor Mn18 is connected to the drain of the tenth PMOS transistor Mp10, the drain of the thirteenth PMOS transistor Mp13, the gate of the fourteenth PMOS transistor Mp14, the drain of the seventeenth NMOS transistor Mn17, and the seventh signal output terminal.
A seventeenth NMOS transistor Mn17 and an eighteenth NMOS transistor Mn18 form a parallel positive feedback path of the third regenerative latch, and output levels of the seventh signal output terminal and the eighth signal output terminal are adjusted by using the positive feedback path and according to magnitudes of input signals accessed by the first input terminal and the second input terminal of the third regenerative latch. The manner of adjusting the output levels of the seventh signal output end and the eighth signal output end by the third reproducible latch is the same as the manner of adjusting the output levels of the third signal output end and the fourth signal output end by the first reproducible latch, and details are not repeated herein.
Please refer to fig. 6 and fig. 7, which are schematic diagrams of a trigger timing diagram of the clock signals of each stage in the present embodiment and a timing implementation circuit of the clock signals of each stage, respectively. As shown in fig. 6, each stage of clock signal has a certain delay time than the previous stage of clock signal; the phase of the first-stage clock signal is opposite to that of the second-stage clock signal, and the phase of the second-stage clock signal is opposite to that of the third-stage clock signal; that is, when the first-stage clock signal is triggered at a high level and the second-stage clock signal is triggered at a low level, the third-stage clock signal is triggered at a high level. As shown in fig. 7, Clk _ T is an external clock signal, the Clk _ T clock signal is processed by a delay circuit to be a trigger clock Clk _1 of the comparator module of the first stage, and the delay circuit of the clock of the subsequent two-stage circuit is similar to that of the first stage, and generates a second-stage clock signal Clk _2 and a third-stage clock signal Clk _3, respectively. Under the connection mode, not only the time delay function can be realized, but also the time sequence of the clock can be triggered reversely.
Furthermore, the delay time between the second clock signal and the third clock signal is adapted to the regeneration time of the first comparator and the first interpolation comparator. In other words, the delay circuit is used for realizing the triggering logic of the second clock signal and the third clock, the time for realizing the delay of the delay circuit and the consistency of triggering the comparator of the current stage need to be considered in a specific circuit, and the comparison time of the comparator of each stage can be shortest only when the clock triggers near the peak value of the input difference value of the comparator, so that the maximum conversion efficiency of the flash ADC is achieved.
And the first comparator sequentially performs comparison operation under the control of the second clock signal and the third clock signal to obtain a second interpolation comparison result as a final output result of the comparator circuit.
Specifically, the second clock signal Clk _2 and the third clock signal Clk _3 are clock control signals with a certain delay and inverted phases; when the second clock signal Clk _2 is low, the first interpolating comparator and the first comparator start to operate. For the first interpolation comparator, if each NMOS transistor in the second switch transistor is turned off, the third differential input pair transistor and the fourth differential input pair transistor are turned on, and are connected to two groups of first differential signals output by two adjacent preamplifiers of a previous stage; the output voltages of the third signal output end and the fourth signal output end in the first interpolation comparator start to be raised in a low level state; meanwhile, two groups of differential input pair transistors work in a non-saturation region, the first differential signals which are respectively accessed are converted into corresponding currents and input into the first reproducible latch, the first reproducible latch continuously raises the output voltage of the signal output end corresponding to the input pair transistor with relatively large input current to a high level and lowers the output voltage of the other signal output end to a low level based on the positive feedback loop according to the magnitude of the input current, and therefore the third differential result which is compared by the first interpolation comparator is obtained. Similarly, for the first comparator, when the second clock signal Clk _2 is at a low level, each NMOS transistor in the third switching transistor is turned off, and then the fifth differential input pair transistor and the sixth differential input pair transistor are turned on to access the first differential signal output by the preamplifier corresponding to the previous stage; the output voltages of the fifth output end and the sixth output end in the first comparator start to be raised in a low level state; meanwhile, the four input pair transistors of the first comparator are connected in pairs to form a group of input pair transistors (the structure is mainly used for being consistent with the structure of the first interpolation comparator and achieving symmetry of the whole circuit), the two groups of transistors work in a non-saturation region, the level of the first signal output end connected to each transistor is converted into corresponding current and input into the second reproducible latch, and similarly, the second reproducible latch continuously raises the output voltage of the signal output end corresponding to the input pair transistor with relatively large input current to a high level and lowers the output voltage of the other signal output end to a low level according to the magnitude of the input current based on the positive feedback loop, so that the comparison result of the first comparator is obtained. For the second interpolating comparator, when the second clock signal Clk _2 is at a low level, the third clock signal Clk _3 is at a high level, and the second interpolating comparator is in a set state.
When the second clock signal Clk _2 is at a high level, the third clock signal Clk _3 is at a low level, and the second switch in the first interpolative comparator is turned on, so that the levels of the two corresponding input terminals of the first regenerative latch are both set at the low level, the first interpolative comparator is enabled to be in an off state, and the low level is output from the two output terminals of the first interpolative comparator. Similarly, the first comparator is also in a non-operating state, and two output ends of the first comparator output low levels. Meanwhile, the fourth switching tubes in the second interpolation comparator are all in a disconnected state, the second interpolation comparator does not work, and is in a set state, so that output signals of output ends of the second interpolation comparator are all in a high level. After a period of time delay, when the second clock signal Clk _2 is changed to a low level, the third clock signal Clk _3 is changed to a high level, the first comparator and the first interpolation comparator are changed to a set state and both output a high level, and the second interpolation comparator is changed to a working state, and the input second differential signal and the input third differential signal are compared to generate a second interpolation comparison result; the first comparator, the first interpolation comparator, and the second interpolation comparator repeat the above-described process according to the change of each clock signal.
Even if the third clock signal Clk _3 is not triggered at the peak of the difference of the input signals, the second-stage interpolation comparator can operate only when the input level is greater than the minimum threshold voltage because the input pair transistors are N-type MOS transistors. And the output signals of the first comparator and the first interpolating comparator (and the input signal of the second interpolating comparator) change from low level, even if the triggering timing of the third clock signal Clk _3 is too early, because the output signals of the first comparator and the first interpolating comparator have not risen to the lowest threshold voltage of the second interpolating comparator, the second comparator will not be started due to the early triggering of the third clock signal Clk _3, so as to effectively reduce the probability of the comparator circuit generating metastable state.
In this embodiment, the N-bit ADC circuit only needs 2 bits by adopting a pre-amplifying structure, starting interpolation in the second stage circuit and adopting a two-stage interpolation comparator structure N-2 +1 pre-amplifiers, reducing the number of amplifiers 3/4. The area and the power consumption of the ADC are further optimized.
In summary, compared with the conventional comparator circuit of the flash ADC, the comparator circuit applicable to the pipelined flash ADC of the present invention employs the pipelined clock to trigger each stage of comparator module, so that the trigger times of the results output by each stage of comparator are different, thereby increasing the conversion rate of the flash ADC system; meanwhile, the connection mode of input geminate transistors of different stages of comparators is changed, P-type MOS transistors are adopted as the input geminate transistors of the first stage of comparators, and N-type MOS transistors are adopted as the input geminate transistors of the second stage of comparators. By adopting the circuit structure, under the streamline type clock triggering mode, when the clock does not invert, the next-stage comparator cannot be triggered to work, so that the probability of metastable state generation by comparison of the comparator is reduced, and the effect of improving the sampling rate of the flash ADC is achieved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
1. A comparator circuit adapted for use in a pipelined flash ADC, the comparator circuit comprising:
the pre-amplification module comprises n pre-amplifiers and is used for amplifying the input differential signals and the reference differential signals input into each pre-amplifier to obtain different first differential signals;
a first stage comparison module comprising n first comparators and n-1 first interpolation comparators; wherein n is an integer greater than 1; each first comparator corresponds to each preamplifier one by one; the input end of the first comparator is connected with the output end of the corresponding preamplifier and is used for comparing the first differential signal output by the preamplifier to obtain a compared second differential signal; each first interpolation comparator is arranged between two adjacent preamplifiers, a first input end of each first interpolation comparator is connected with an output end of one corresponding preamplifier in the two adjacent preamplifiers, and a second input end of each first interpolation comparator is connected with an output end of the other corresponding preamplifier in the two adjacent preamplifiers, and the first interpolation comparators are used for comparing first differential signals respectively output by the two adjacent preamplifiers to obtain a third differential signal; the differential input pair transistors of each comparator in the first-stage comparison module are P-type MOS transistors;
a second stage comparison module comprising 2n-2 second interpolation comparators; each second interpolation comparator is arranged between the adjacent first comparator and the first interpolation comparator, the first input end of the second interpolation comparator is connected with the output end of the corresponding first interpolation comparator in the adjacent first comparator and the first interpolation comparator, and the second input end of the second interpolation comparator is connected with the output end of the corresponding first comparator in the adjacent first comparator and the first interpolation comparator, and is used for comparing the second differential signal output by the first comparator with the third differential signal output by the first interpolation comparator to obtain a second interpolation comparison result; each second interpolation comparison result forms a final output result of the comparator circuit; the differential input pair transistors of each comparator in the second-stage comparison module are N-type MOS transistors;
the pre-amplification module, the first-stage comparison module and the second-stage comparison module are respectively connected with a clock signal module and respectively connected with a first clock signal, a second clock signal and a third clock signal, wherein the first clock signal, the second clock signal and the third clock are pipelined clock signals and sequentially have time-delay intervals, so that the pre-amplification module switches respective working states according to the first clock signal, the first-stage comparison module according to the second clock signal and the second-stage comparison module according to the third clock signal to realize comparison operation of the comparator circuit.
2. The comparator circuit suitable for the pipelined flash ADC of claim 1, wherein the preamplifier includes a first differential input pair, a second differential input pair, a first switch tube and a first footer; the first differential input pair of transistors and the second differential input pair of transistors each comprise a first transistor and a second transistor; a first transistor of the first differential input pair transistor and a first transistor of the second differential input pair transistor are connected to the input differential signal, and a second transistor of the first differential input pair transistor and a second transistor of the second differential input pair transistor are connected to the reference differential signal; the first differential input pair tube and the second differential input pair tube are both connected with the first tail tube; the output end of the first differential input pair transistor is the first output end of the preamplifier and is connected with the first input end of the first switch transistor; the output end of the second differential input pair transistor is the second output end of the preamplifier and is connected with the second input end of the first switch transistor; the control end of the first switch tube is connected to the first clock signal, so that the preamplifier compares the input differential signal with the reference differential signal according to the first clock signal to obtain the first differential signal.
3. The comparator circuit adapted for a pipelined flash ADC of claim 1, wherein the first interpolative comparator comprises a third differential input pair of transistors, a fourth differential input pair of transistors, a second switching transistor, and a first regenerative latch; the third differential input pair transistor and the fourth differential input pair transistor each comprise a first transistor and a second transistor; the first transistor of the third differential input pair transistor and the first transistor of the fourth differential input pair transistor are correspondingly connected with the first output end and the second output end of one preamplifier in two adjacent preamplifiers, and the second transistor of the third differential input pair transistor and the second transistor of the fourth differential input pair transistor are correspondingly connected with the first output end and the second output end of the other preamplifier in two adjacent preamplifiers; the output end of the third differential input pair transistor is connected with the first input end of the first reproducible latch and the first input end of the second switch transistor; the output end of the fourth differential input pair transistor is connected with the second input end of the first reproducible latch and the second input end of the second switching tube; the two output ends of the first reproducible latch are the two output ends of the first interpolating comparator; and the control end of the second switch tube is connected with a second clock signal, so that the first interpolation comparator compares the two input groups of first differential signals according to the second clock signal to obtain a third differential signal.
4. The comparator circuit suitable for use in a pipelined flash ADC of claim 2, wherein the transistors in the first and second differential input pair of transistors are PMOS transistors.
5. The comparator circuit suitable for use in a pipelined flash ADC of claim 1, wherein the first comparator includes a fifth differential input pair of transistors, a sixth differential input pair of transistors, a third switch transistor, and a second regenerative latch; the fifth differential input pair transistor and the sixth differential input pair transistor each comprise a first transistor and a second transistor; the first transistor of the fifth differential input pair transistor and the first transistor of the sixth differential input pair transistor are connected with the corresponding first output end of the preamplifier, and the second transistor of the fifth differential input pair transistor and the second transistor of the sixth differential input pair transistor are connected with the corresponding second output end of the preamplifier; the output end of the fifth differential input pair transistor is connected with the first input end of the second reproducible latch and the first input end of the third switching transistor; the output end of the sixth differential input pair transistor is connected with the second input end of the second reproducible latch and the second input end of the third switching transistor; two output ends of the second reproducible latch are two output ends of the first comparator; the control end of the third switching tube is connected to the second clock signal, so that the first comparator compares the connected first differential signal according to the second clock signal to obtain the second differential signal.
6. The comparator circuit suitable for a pipelined flash ADC of any one of claims 1 to 5, wherein the second interpolative comparator comprises a seventh differential input pair of transistors, an eighth differential input pair of transistors, a fourth switch transistor, a third regenerative latch, and a second footer; the seventh differential input pair transistor and the eighth differential input pair transistor are connected with the second tail pipe, and both the seventh differential input pair transistor and the eighth differential input pair transistor comprise a first transistor and a second transistor; the first transistor of the seventh differential input pair tube and the first transistor of the eighth differential input pair tube are correspondingly connected with two output ends of the first interpolation comparator in the adjacent first comparator and the first interpolation comparator, and the second transistor of the seventh differential input pair tube and the second transistor of the eighth differential input pair tube are correspondingly connected with two output ends of the first comparator in the adjacent first comparator and the first interpolation comparator; the output end of the seventh differential input pair transistor is connected with the first input end of the third reproducible latch and the first input end of the fourth switching tube; the output end of the eighth differential input pair transistor is connected with the second input end of the third reproducible latch and the second input end of the fourth switching transistor; the two output ends of the third reproducible latch are the two output ends of the second interpolating comparator; and the control end of the fourth switching tube is connected to the third clock signal, so that the second interpolation comparator compares the input second differential signal with the input third differential signal according to the third clock signal to obtain a second interpolation comparison result.
7. The comparator circuit suitable for use in a pipelined flash ADC of claim 6, wherein transistors in said seventh and eighth differential input pair of transistors are NMOS transistors.
8. The comparator circuit for a pipelined flash ADC of claim 1, wherein the second clock signal and the third clock signal have a first delay time therebetween, the first delay time being adapted to a regeneration time of the first comparator and the first interpolation comparator.
9. The comparator circuit adapted for a pipelined flash ADC of claim 8, wherein the first clock signal and the second clock signal are in opposite phase and the second clock signal and the third clock signal are in opposite phase.
10. The comparator circuit adapted for a pipelined flash ADC of claim 1, wherein the pipelined flash ADC comprises a voltage divider resistor network; the pre-amplification module is connected with the divider resistor network, so that the reference differential voltage is converted into different reference differential signals through the divider resistor network and is input into each pre-amplifier in the pre-amplification module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010670791.4A CN111865315B (en) | 2020-07-13 | 2020-07-13 | Comparator circuit suitable for assembly line flash ADC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010670791.4A CN111865315B (en) | 2020-07-13 | 2020-07-13 | Comparator circuit suitable for assembly line flash ADC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111865315A CN111865315A (en) | 2020-10-30 |
| CN111865315B true CN111865315B (en) | 2022-07-26 |
Family
ID=72982962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010670791.4A Active CN111865315B (en) | 2020-07-13 | 2020-07-13 | Comparator circuit suitable for assembly line flash ADC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111865315B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112583387A (en) * | 2020-12-14 | 2021-03-30 | 重庆百瑞互联电子技术有限公司 | Strong arm latch voltage comparator based on parallel path |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4349445B2 (en) * | 2007-07-10 | 2009-10-21 | ソニー株式会社 | Flash AD converter |
| US7710305B2 (en) * | 2008-09-22 | 2010-05-04 | National Semiconductor Corporation | Unified architecture for folding ADC |
| EP2280486A1 (en) * | 2009-07-10 | 2011-02-02 | Interuniversitair Micro-Elektronica Centrum | Interleaved pipelined binary search A/D converter |
| TWI382669B (en) * | 2009-07-16 | 2013-01-11 | Ralink Technology Corp | Comparator for a pipelined analog to digital converter and related signal sampling method |
| US7978116B2 (en) * | 2009-10-13 | 2011-07-12 | Analog Devices, Inc. | Apparatus and method for pipelined analog to digital conversion |
| KR101199574B1 (en) * | 2010-11-02 | 2012-11-12 | 한국과학기술원 | Analog to digital converter |
| US20140062545A1 (en) * | 2012-09-03 | 2014-03-06 | Tensorcom, Inc. | Method and Apparatus for Reducing the Clock Kick-Back of ADC Comparators While Maintaining Transistor Matching Behavior |
| US9467160B2 (en) * | 2014-11-11 | 2016-10-11 | Mediatek Inc. | Flash ADC with interpolators |
| KR101644999B1 (en) * | 2015-01-22 | 2016-08-03 | 한국과학기술원 | Low-Power Analog Digital Converter By Using Time-Domain Multi-Stage Interpolation |
| CN105141313B (en) * | 2015-09-28 | 2018-07-06 | 成都领芯微电子科技有限公司 | A kind of SAR ADC and its application method using low resolution DAC capacitor arrays |
| US10284188B1 (en) * | 2017-12-29 | 2019-05-07 | Texas Instruments Incorporated | Delay based comparator |
| EP3594950A1 (en) * | 2018-07-11 | 2020-01-15 | Stichting IMEC Nederland | Latched comparator and analog-to-digital converter making use thereof |
-
2020
- 2020-07-13 CN CN202010670791.4A patent/CN111865315B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111865315A (en) | 2020-10-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108574489B (en) | Comparator and successive approximation type analog-digital converter | |
| CN107425852B (en) | Successive approximation type analog-to-digital converter based on binary weighted charge redistribution | |
| CN106817131B (en) | High-speed assembly line-successive approximation type ADC based on dynamic ringing operational amplifier | |
| JP2875922B2 (en) | A / D converter | |
| WO2017091928A1 (en) | High-speed pipelined successive approximation adc based on dynamic ringing-based operational amplifier | |
| CN104242937B (en) | For the analog references level buffer device of flow-line modulus converter | |
| CN110401447B (en) | MDAC type time domain ADC structure without operational amplifier | |
| CN102045044B (en) | Comparator and A/D converter | |
| CN111865315B (en) | Comparator circuit suitable for assembly line flash ADC | |
| CN106612119B (en) | Comparator and analog-to-digital converter | |
| US10461763B2 (en) | Double data rate time interpolating quantizer with reduced kickback noise | |
| CN111245413A (en) | High-speed high-linearity grid voltage bootstrap switch circuit | |
| TWI492547B (en) | Successive approximation analog-to-digital converter | |
| CN111313871B (en) | Dynamic pre-amplification circuit and dynamic comparator | |
| CN115412077A (en) | High-speed low-power consumption prepositive latch comparator | |
| Wang et al. | A 1.2 V 1.0-GS/s 8-bit voltage-buffer-free folding and interpolating ADC | |
| US20230163777A1 (en) | Comparator and analog to digital converter | |
| CN112398476B (en) | Low-power consumption comparator with low delay distortion characteristic | |
| CN111669130B (en) | Automatic eliminating circuit for input offset voltage of operational amplifier | |
| Yasser et al. | A comparative analysis of optimized low-power comparators for biomedical-adcs | |
| CN114679161A (en) | Three-stage comparator system suitable for medium-low precision high-speed low-power consumption ADC | |
| CN112910447A (en) | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude | |
| CN113014264A (en) | Analog-digital converter with multi-mode selection | |
| Chen et al. | A low-kickback-noise latched comparator for high-speed flash analog-to-digital converters | |
| Jiang et al. | A 16-channel 12-bit rail-to-rail successive approxmation register ADC for AFEs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |