CN106656161B - A kind of rail-to-rail adaptive quick response buffer circuits - Google Patents
A kind of rail-to-rail adaptive quick response buffer circuits Download PDFInfo
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- CN106656161B CN106656161B CN201611125879.8A CN201611125879A CN106656161B CN 106656161 B CN106656161 B CN 106656161B CN 201611125879 A CN201611125879 A CN 201611125879A CN 106656161 B CN106656161 B CN 106656161B
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- pmos tube
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Abstract
The present invention relates to a kind of rail-to-rail adaptive quick response buffer circuits.The present invention is in order to solve the problems, such as that the power consumption of traditional buffer, response speed are difficult to compromise, propose a kind of novel circuit structure: by using NMOS differential input to and PMOS Differential Input to mode in parallel, realize rail-to-rail input, and a feedback control loop is introduced at the load of NMOS differential input pair, so that the response speed of input stage and the amplitude of input signal be made to be in adaptive change: the amplitude of input signal is bigger, and NMOS differential input pipe response speed is bigger；Output stage uses push-pull structure, so that the electric current of output port is neatly flowed out or is flowed into, in the case where guaranteeing power-efficient, further improves the response speed of buffer.
Description
Technical field
The present invention relates to a kind of rail-to-rail adaptive quick response buffer circuits, belong to technical field of integrated circuits.
Background technique
In all electronic equipments and product, it all be unable to do without power management chip.Low pressure difference linear voltage regulator (LDO) is just
One of the important module of power management chip, it can generate and maintain one it is precise and stable not with input voltage, negative
The output voltage for carrying environment and operation conditions change is usually used in meeting various types of processors and specific integrated circuit (ASIC) power supply
Demand.However as the continuous upgrading of semiconductor process technique, the integrated level of chip is higher and higher, and the function of device is more, transports
Scanning frequency degree faster, operating current variation it is more violent, many functions and clock have simultaneity in especially SOC, will lead to very
Very acutely (electric current changes to A grades by mA grades), driving LDO is capable of providing bigger power supply to device operation current in the short time
Electric current, more high response speed, tightened up Voltage Feedback precision and higher efficiency performance.
LDO must be sufficiently large to provide higher load electric current, output power pipe, can provide the electric current of ampere grade
In LDO, the often area of output power pipe is more than 50% or more, causes its grid that very big parasitic capacitance can be presented, when negative
When carrying acute variation, buffer carries out output power pipe to the rapid charge and discharge of the grid of output power pipe, by grid voltage
Adjustment, to realize that pressure stabilizing exports.Fig. 1 (a) and Fig. 1 (b) show the buffer structure that traditional source follows, using PMOS tube or
NMOS tube carries out buffering charge or discharge by grid of the source electrode to output power pipe.This circuit structure has some disadvantages:
(1) PMOS tube or NMOS tube are used, input range cannot achieve rail-to-rail；(2) buffer belongs to A class working condition, electric current
Source must the sufficiently large response speed for being just able to satisfy LDO, increase the power consumption of circuit.
For the disadvantage (1) in Fig. 1, the prior art proposes a kind of difference for being mixed with PMOS tube and NMOS tube as shown in Figure 2
Divide input pair, to extend input range, realizes rail-to-rail input；But it for disadvantage (2), still can not solve.
Summary of the invention
The present invention is in order to solve the disadvantage that traditional buffer circuits input range is small, response speed is slow, power consumption is high, this hair
It is bright that a kind of rail-to-rail adaptive quick response buffer circuits are provided.
The technical solution adopted in the present invention is as follows: the rail-to-rail adaptive quick response buffer circuits of one kind include defeated
Enter grade, output stage；Wherein input stage using NMOS differential input to and PMOS Differential Input pair, to realize rail-to-rail input；
Output stage realizes long arc output using the push-pull structure for working in AB class working condition under higher power-efficient.
Wherein input stage include: NMOS differential input to and PMOS Differential Input to parallel connection, the NMOS differential input pair
It is correspondingly connected with including source electrode and connects the heavy I of electric currentSS1NMOS tube MN1 and NMOS tube MN2；The PMOS Differential Input is to including
Source electrode is correspondingly connected with and connects current source ISS2PMOS tube MP1 and PMOS tube MP2；NMOS tube MN1 grid and PMOS tube MP2 grid
Extremely it is connected and connects anode input Vi_p, NMOS tube MN2 grid is connected with PMOS tube MP1 grid and connects negative terminal input Vi_n；
The drain electrode of NMOS tube MN1 and drain electrode, the operational transconductance amplifier G of PMOS tube MP9m1Anode input connection；The grid of PMOS tube MP9
Pole and operational transconductance amplifier Gm1Output end, PMOS tube MP3 grid connection；The drain electrode of PMOS tube MP3 is with PMOS tube MP5's
Source electrode connection；The drain electrode of PMOS tube MP5 and the grid of the drain electrode of PMOS tube MP1, the source electrode of PMOS tube MP7, NMOS tube MN4 connect
It connects；The drain electrode of PMOS tube MP7 is connected to ground；The grid of PMOS tube MP7 is by series with a resistor, final connection ground；NMOS tube MN2
Drain electrode and the drain electrode of PMOS tube MP10, operational transconductance amplifier Gm2Anode input connection；The grid of PMOS tube MP10 with across
Lead operational amplifier Gm2Output end, PMOS tube MP4 grid connection；The drain electrode of PMOS tube MP4 and the source electrode of PMOS tube MP6 connect
It connects；The drain electrode of PMOS tube MP6 is connect with the grid of the drain electrode of PMOS tube MP2, the source electrode of PMOS tube MP8, NMOS tube MN3；PMOS
The drain electrode of pipe MP8 is connected to ground；The grid of PMOS tube MP8 is by series with a resistor, final connection ground；The output stage is two-stage
Push-pull structure, comprising: source electrode is correspondingly connected with and connects the heavy I of electric currentSS3NMOS tube MN3 and NMOS tube MN4 constitute differential pair
Structure；The grid of the drain drain electrode for connecting PMOS tube MP11, grid and the PMOS tube MP12 of NMOS tube MN3；NMOS tube MN4's
Drain electrode connects the grid connection of the drain electrode of PMOS tube MP13, grid and PMOS tube MP14；The drain electrode of PMOS tube MP12 and NMOS
The drain electrode of pipe MN5, grid are connected with the grid of NMOS tube MN6；The drain electrode of PMOS tube MP14 connect work with the drain electrode of NMOS tube MN6
For the output port Vout of buffer；Input stage realizes rail-to-rail input, and output stage uses and works in AB class working condition
Push-pull structure realizes long arc output under higher power-efficient；Wherein PMOS tube MP3 source level, the source PMOS tube MP4
Grade, PMOS tube MP9 source level, PMOS tube MP10 source level, PMOS tube MP11 source level, PMOS tube MP12 source level, PMOS tube MP13 source level,
PMOS tube MP14 source level connects high level, and NMOS tube MN5 source level, NMOS tube MN6 source level are grounded.
Further, the operational transconductance amplifier Gm1With PMOS tube MP9, operational transconductance amplifier Gm2And PMOS tube
MP10 is a controlled current source load respectively, and operational transconductance amplifier can be according to the amplitude self adaptive control of input signal
PMOS electric current.
Further, the operational transconductance amplifier Gm1The loop of a feedback, mutual conductance fortune are constituted with PMOS tube MP9 electric current
Calculate amplifier Gm2The loop of a feedback is constituted with PMOS tube MP10 electric current, it is desirable that the loop gain of the feedback control loop of composition is less than
1, determine that loop is stable.
The beneficial effects of the present invention are: make input stage by introducing feed circuit at the load that NMOS differential inputs, it is special
Be not NMOS differential input load at PMOS tail current can according to the size adaptation of the amplitude of input signal adjust tail
The size of electric current, to guarantee that input stage is enable to respond quickly the variation of input signal；Output stage uses push-pull structure, makes
The electric current of output port neatly can be flowed out or be flowed into, and in the case where guaranteeing power-efficient, further improve buffer
Response speed.
Detailed description of the invention
(a) and (b) of Fig. 1 is the buffer circuit configuration that traditional source follows structure.
Fig. 2 is the circuit structure of traditional rail-to-rail input difference input.
Fig. 3 is rail-to-rail adaptive quick response buffer circuits schematic diagram of the invention.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.These attached drawings are simplified schematic diagram, only with
Illustration illustrates basic structure of the invention, therefore it only shows the composition relevant to the invention.
The present invention is anti-by introducing one at the load of Differential Input first on the basis of traditional rail-to-rail structure
Current feed circuit realizes a kind of rail-to-rail adaptive quick response buffer circuits as shown in the dotted line frame in Fig. 3.
As shown in figure 3, a kind of rail-to-rail adaptive quick response buffer circuits include input stage, output stage.
Input stage include: NMOS differential input to and PMOS Differential Input to parallel connection, the NMOS differential input is to including
Source electrode is correspondingly connected with and connects the heavy I of electric currentSS1NMOS tube MN1 and NMOS tube MN2；The PMOS Differential Input is to including source electrode
It is correspondingly connected with and connects current source ISS2PMOS tube MP1 and PMOS tube MP2；NMOS tube MN1 grid and PMOS tube MP2 grid phase
Connect and connect anode input Vi_p, NMOS tube MN2 grid is connected with PMOS tube MP1 grid and connects negative terminal input Vi_n；NMOS
The drain electrode of pipe MN1 and drain electrode, the operational transconductance amplifier G of PMOS tube MP9m1Anode input connection；The grid of PMOS tube MP9 with
Operational transconductance amplifier Gm1Output end, PMOS tube MP3 grid connection；The drain electrode of PMOS tube MP3 and the source electrode of PMOS tube MP5
Connection；The drain electrode of PMOS tube MP5 is connect with the grid of the drain electrode of PMOS tube MP1, the source electrode of PMOS tube MP7, NMOS tube MN4；
The drain electrode of PMOS tube MP7 is connected to ground；The grid of PMOS tube MP7 is by series with a resistor, final connection ground；NMOS tube MN2's
Drain electrode and the drain electrode of PMOS tube MP10, operational transconductance amplifier Gm2Anode input connection；The grid of PMOS tube MP10 and mutual conductance
Operational amplifier Gm2Output end, PMOS tube MP4 grid connection；The drain electrode of PMOS tube MP4 and the source electrode of PMOS tube MP6 connect
It connects；The drain electrode of PMOS tube MP6 is connect with the grid of the drain electrode of PMOS tube MP2, the source electrode of PMOS tube MP8, NMOS tube MN3；PMOS
The drain electrode of pipe MP8 is connected to ground；The grid of PMOS tube MP8 is by series with a resistor, final connection ground.
The output stage is the push-pull structure of two-stage, comprising: source electrode is correspondingly connected with and connects the heavy I of electric currentSS3NMOS tube
MN3 and NMOS tube MN4 constitutes differential pair structure；Drain electrode, grid and the PMOS of the drain electrode connection PMOS tube MP11 of NMOS tube MN3
The grid of pipe MP12；The drain electrode of NMOS tube MN4 connects the grid company of the drain electrode of PMOS tube MP13, grid and PMOS tube MP14
It connects；The drain electrode of PMOS tube MP12 is connect with the grid of the drain electrode of NMOS tube MN5, grid and NMOS tube MN6；The leakage of PMOS tube MP14
The drain electrode of pole and NMOS tube MN6 are connected to the output port Vout of buffer
Input stage is inputted to (MN1 and MN2) and PMOS Differential Input using NMOS differential to (MP1 and MP2), to realize rail
To the input of rail；The load of input stage NMOS differential input pair is the circuit structure as shown in Fig. 3 dotted line frame, is one by mutual conductance
The PMOS electric current of operational amplifier control, then by PMOS tube MP3, MP4, with PMOS Differential Input to signal together with, by negative
Carry the NMOS tube for diode connection structure, the input signal as output stage.Output stage is the push-pull knot an of two-stage
Structure recommends the second level (MP14 and MN6) output by the diode structure (MP11 and MP13) of Differential Input (MN3 and MN4).
The specific working principle is as follows for circuit of the present invention:
Input stage is differential input structure, and by taking anode inputs Vi_p as an example, when Vi_p increases, NMOS differential is inputted
Pipe, A point current potential reduce, while A point is inputted as the anode of spaning waveguide operational amplifier, keeps PMOS grid B point smaller, control PMOS load electricity
MP9 leakage current increase in stream source forms feedback and reduces A point current potential reduction amplitude, same to be transmitted to output stage by the common-source stage of MP3,
Improve the response speed of buffer；For PMOS Differential Input pipe, when Vi_p increases, F point voltage is smaller；F point is as output
The input terminal of grade, passes through two-stage push-pull configuration drive output mouth.It, can be with wherein for NMOS differential input pipe response speed
The variation of the amplitude of input signal and be in adaptive change: the amplitude of input signal is bigger, NMOS differential input pipe response speed
It is bigger.
Similarly, when being analyzed with negative terminal input Vi_n, each node voltage variation of buffer and input signal
Amplitude and NMOS differential input pipe response speed relationship, have the function of similar.
Operational transconductance amplifier Gm1The loop of a feedback, operational transconductance amplifier G are constituted with PMOS tube MP9 electric currentm2With
PMOS tube MP10 electric current constitutes the loop of a feedback, it is desirable that the loop gain of the feedback control loop of composition determines that loop is less than 1
Stable.
Pass through above-mentioned analysis, it has been found that a kind of rail-to-rail adaptive quick response buffer circuits of the present invention are by adopting
With NMOS differential input to and PMOS Differential Input rail-to-rail input is realized to mode in parallel, and inputted in NMOS differential
Pair load at introduce one feedback, to make the amplitude adaptive change of the response speed and input signal of input stage: input
The amplitude of signal is bigger, and NMOS differential input pipe response speed is bigger；Output stage uses push-pull structure, makes output port
Electric current neatly can be flowed out or be flowed into, and in the case where guaranteeing power-efficient, further improve the response speed of buffer.
Taking the above-mentioned ideal embodiment according to the present invention as inspiration, through the above description, relevant staff is complete
Various changes and amendments can be carried out without departing from the scope of the technological thought of the present invention' entirely.The technology of this invention
Property range is not limited to the contents of the specification, it is necessary to which the technical scope thereof is determined according to the scope of the claim.
Claims (3)
1. a kind of rail-to-rail adaptive quick response buffer circuits, it is characterized in that: including input stage, output stage；It is wherein defeated
Enter grade include: NMOS differential input to and PMOS Differential Input to parallel connection, the NMOS differential input connects to including that source electrode is corresponding
It connects and connects the heavy I of electric currentSS1NMOS tube MN1 and NMOS tube MN2；The PMOS Differential Input is correspondingly connected with simultaneously to including source electrode
Connect current source ISS2PMOS tube MP1 and PMOS tube MP2；NMOS tube MN1 grid is connected with PMOS tube MP2 grid and connects just
End input Vi_p, NMOS tube MN2 grid are connected with PMOS tube MP1 grid and connect negative terminal input Vi_n；The drain electrode of NMOS tube MN1
Drain electrode, operational transconductance amplifier G with PMOS tube MP9m1Anode input connection；The grid of PMOS tube MP9 is put with operational transconductance
Big device Gm1Output end, PMOS tube MP3 grid connection；The drain electrode of PMOS tube MP3 is connect with the source electrode of PMOS tube MP5；PMOS
The drain electrode of pipe MP5 is connect with the grid of the drain electrode of PMOS tube MP1, the source electrode of PMOS tube MP7, NMOS tube MN4；PMOS tube MP7's
Drain electrode is connected to ground；The grid of PMOS tube MP7 is by series with a resistor, final connection ground；The drain electrode and PMOS tube of NMOS tube MN2
The drain electrode of MP10, operational transconductance amplifier Gm2Anode input connection；The grid and operational transconductance amplifier G of PMOS tube MP10m2
Output end, PMOS tube MP4 grid connection；The drain electrode of PMOS tube MP4 is connect with the source electrode of PMOS tube MP6；PMOS tube MP6's
Drain electrode is connect with the grid of the drain electrode of PMOS tube MP2, the source electrode of PMOS tube MP8, NMOS tube MN3；The drain electrode of PMOS tube MP8 and ground
Connection；The grid of PMOS tube MP8 is by series with a resistor, final connection ground；
The output stage is the push-pull structure of two-stage, comprising: source electrode is correspondingly connected with and connects the heavy I of electric currentSS3NMOS tube MN3
Differential pair structure is constituted with NMOS tube MN4；Drain electrode, grid and the PMOS tube of the drain electrode connection PMOS tube MP11 of NMOS tube MN3
The grid of MP12；The drain electrode of NMOS tube MN4 connects the grid connection of the drain electrode of PMOS tube MP13, grid and PMOS tube MP14；
The drain electrode of PMOS tube MP12 is connect with the grid of the drain electrode of NMOS tube MN5, grid and NMOS tube MN6；The drain electrode of PMOS tube MP14
The output port Vout of buffer is connected to the drain electrode of NMOS tube MN6；Input stage realizes rail-to-rail input, and output stage is adopted
With the push-pull structure for working in AB class working condition, long arc output is realized under higher power-efficient；Wherein PMOS
Pipe MP3 source level, PMOS tube MP4 source level, PMOS tube MP9 source level, PMOS tube MP10 source level, PMOS tube MP11 source level, PMOS tube
MP12 source level, PMOS tube MP13 source level, PMOS tube MP14 source level connect high level, NMOS tube MN5 source level, NMOS tube MN6 source level
It is grounded.
2. the rail-to-rail adaptive quick response buffer circuits of one kind according to claim 1, it is characterized in that: it is described across
Lead operational amplifier Gm1With PMOS tube MP9, operational transconductance amplifier Gm2It is a controlled current source respectively with PMOS tube MP10
Load, operational transconductance amplifier can be according to the amplitude self adaptive control PMOS electric current of input signal.
3. the rail-to-rail adaptive quick response buffer circuits of one kind according to claim 1 or 2, it is characterized in that: institute
State operational transconductance amplifier Gm1The loop of a feedback, operational transconductance amplifier G are constituted with PMOS tube MP9 electric currentm2And PMOS tube
MP10 electric current constitutes the loop of a feedback, it is desirable that the loop gain of the feedback control loop of composition determines that loop is stable less than 1
's.
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| CN201611125879.8A CN106656161B (en) | 2016-12-08 | 2016-12-08 | A kind of rail-to-rail adaptive quick response buffer circuits |
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| CN201611125879.8A CN106656161B (en) | 2016-12-08 | 2016-12-08 | A kind of rail-to-rail adaptive quick response buffer circuits |
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| CN106656161B true CN106656161B (en) | 2019-07-12 |
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| CN109194330B (en) * | 2018-08-27 | 2020-08-11 | 中国电子科技集团公司第二十四研究所 | Buffer circuit and buffer |
| CN110806522B (en) * | 2019-11-12 | 2022-02-22 | 天津津航计算技术研究所 | Arc signal detection conditioning circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6806744B1 (en) * | 2003-10-03 | 2004-10-19 | National Semiconductor Corporation | High speed low voltage differential to rail-to-rail single ended converter |
| CN101419479B (en) * | 2008-12-10 | 2012-05-23 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN101727119B (en) * | 2009-11-26 | 2013-09-04 | 四川和芯微电子股份有限公司 | Low-dropout linear voltage source with effective compensation |
| CN202395750U (en) * | 2011-12-02 | 2012-08-22 | 上海贝岭股份有限公司 | Differential reference voltage buffer |
| CN105183061B (en) * | 2015-07-30 | 2017-08-04 | 中国电子科技集团公司第五十八研究所 | A kind of voltage buffer circuit |
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