CN112234973A

CN112234973A - Multistage operational amplifier suitable for driving wide-range capacitive load

Info

Publication number: CN112234973A
Application number: CN202011018963.6A
Authority: CN
Inventors: 刘术彬; 陆帅; 韩昊霖; 张效铭; 丁瑞雪; 朱樟明
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2020-09-24
Filing date: 2020-09-24
Publication date: 2021-01-15
Anticipated expiration: 2040-09-24
Also published as: CN112234973B

Abstract

The invention provides a multi-stage operational amplifier suitable for driving a wide-range capacitive load, which comprises a main operational amplifier, a programmable current source array circuit, a current detector, a dynamic logic enabling circuit and a dynamic logic circuit, wherein a programmable zero-adjusting resistor array is arranged in the main operational amplifier, the current detector detects the current of an output stage and feeds the current back to the dynamic logic enabling circuit, when the output stage determined based on the gate voltages of MA and MB needs to be compensated, the dynamic logic enabling circuit drives the dynamic logic circuit to generate a digital code, the current of the output stage is compensated to improve the slew rate, and the digital code is multiplexed to the programmable resistor array (RZ) to enable the zero point to change along with the change of a secondary pole so as to optimize the phase margin.

Description

Multistage operational amplifier suitable for driving wide-range capacitive load

Technical Field

The invention belongs to the field of digital-analog hybrid integrated circuit design, and particularly relates to a multistage operational amplifier suitable for driving a wide-range capacitive load.

Background

With the progress of chip technology, the power supply voltage of the circuit is reduced, so that the intrinsic gain of the transistor is limited, and if the small-signal working performance of the multistage combined operational amplifier circuit is greatly improved only by means of stacking cascodes, gain bootstrap and the like, the small-signal working performance is difficult under certain conditions. For example: in the application of wide-range variation of the capacitive load, the capacitive load is driven by using the multi-stage combined operational amplifier, when the capacitive load is changed to be extremely large (nF or even higher magnitude), due to the fact that the slew rate is sharply reduced, the large signal establishment time is too long, the establishment time is mostly dominated by the large signal, and the linearity of the operational amplifier is deteriorated. Furthermore, for a multi-stage combined op-amp circuit architecture typically implemented based on Miller compensation, the load capacitance magnitude is usually related to the secondary pole, and a larger load will pull closer to the secondary pole to gain-bandwidth product distance, thereby degrading small signal settling times.

Therefore, based on the above-mentioned phenomenon that the setup time of the large signal is mostly dominated by the large signal due to the over-long setup time of the slew rate due to the sharp decrease, the linearity of the operational amplifier is deteriorated, and the larger load will be closer to the distance between the secondary pole and the product of the gain bandwidth, thereby deteriorating the setup time of the small signal, a compensation scheme for the slew rate and the phase margin is awaited.

Disclosure of Invention

To solve the above problems in the prior art, the present invention provides a multi-stage operational amplifier suitable for driving a wide range capacitive load. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a multi-stage operational amplifier suitable for driving a wide-range capacitive load, which comprises: the main operational amplifier of the built-in programmable zero-setting resistor array comprises a programmable resistor array R, a programmable current source array circuit, a current detector, a dynamic logic enabling circuit and a dynamic logic circuit_ZCapacitor C_ZAnd the multistage combination operational amplifier circuit comprises: by NMOS tubeM_AAnd PMOS transistor M_BThe programmable current source array circuit is formed by sequentially connecting multiple layers of same single circuits, and the programmable resistor array R_ZIncorporating said capacitor C_ZGenerating a zero point before a secondary pole point in the multistage combined operational amplifier circuit, and controlling the programmable resistor array R of the zero point change when the secondary pole point changes along with the capacitance load_ZChanges in resistance value of M_AIs connected to a first input terminal of the programmable current source array circuit, M_BThe grid of the current detector is connected with the second input end of the programmable current source array circuit, the power end of the main operational amplifier of the built-in programmable zero setting resistor array and the power end of the programmable current source array circuit are connected with a power end VDD, and the first input end V of the current detector is connected with the second input end of the programmable current source array circuit_GPA second input terminal V of the current detector connected to the gate of the MA_GNAnd said M_BThe output end of the current detector is connected with the input end of the dynamic logic enabling circuit, the output end of the dynamic logic enabling circuit is connected with the input end of the dynamic logic circuit, and the current detector is used for detecting the M_AAnd a gate voltage of the MB, the dynamic logic enable circuit to enable the MB based on the M_AAnd when the output stage determined by the gate voltage of the MB needs to be compensated, driving the dynamic logic circuit to generate a digital code, compensating the current of the output stage to improve the slew rate, and multiplexing the digital code to the programmable resistor array R_ZThe zero is changed with the change of the secondary pole to optimize the phase margin.

Optionally, the multi-stage combined operational amplifier circuit includes: NMOS transistors M1, M2, M5, M7, M8, M9, M10, M15, M16, M17 and M18, PMOS transistors M3, M4, M6, M11, M12, M13, M14, M19, M20, capacitors Cm1a, Cm1b, Cm2, and the M18_AAnd said M_BThe source of the M1 is connected to the source of the M7, the source of the M8, the source of the M15, the source of the M16, the source of the MA, and a power supply terminal VDD, respectively, and the drain of the M1 is connected to the source of the M2, the source of the MA, and a power supply terminal VDD, respectivelyA source of M5 is connected, a drain of M2 is connected to the drain of M13 and the source of M11, a gate of M2 is connected to the gate of M3, a source of M3 is connected to the drain of M3 and the source of M3, a drain of M3 is connected to the drain of M3, the source of M3 and one end of Cm 13, a gate of M3 is connected to the gate of M3, a drain of M3 is connected to the source of M3, the drain of M3 and one end of Cm 13, a source of M3 is connected to the source of M3, the source of MB, the source of the analog ground, and a gate of M3, a gate of M3 and a gate of GND, M3 and a gate of M3, a gate of the analog ground, The drain of the M11 is connected, the gate of the M9 is connected to the gate of the M10, the drain of the M10 is connected to the drain of the M12, the gate of the M15 and the gate of the MA, the gate of the M11 is connected to the gate of the M12, the gate of the M13 is connected to the gate of the M14, the drain of the M15 is connected to the source of the M17, the drain of the M16 is connected to the source of the M18 and one end of the Cm2, the drain of the M17 is connected to the drain of the M19 and the gate of the M20, the gate of the M17 is connected to the gate of the M18, the drain of the M18 is connected to the drain of the M20 and the gate of the MB, and the programmable resistor array R is connected to the gate of the M20 and the MB_ZThe capacitor Cz is connected between the gate and the drain of the M19 in a bridging mode, the capacitor Cz is connected between the gate and the source of the M19 in a bridging mode, and the output stage is composed of the MA and the MB.

Optionally, the single circuit includes: a first sub-circuit and a second sub-circuit, the first sub-circuit and the second sub-circuit being symmetric, the first sub-circuit and the second sub-circuit comprising: the grid electrode of the MC, the drain electrode of the MC, the source electrode of the ME, the drain electrode of the MG and the source electrode of the MA in each layer of the first sub-circuit are connected together, the source electrode of the MC in each layer of the first sub-circuit is respectively connected with the source electrode of the MD in the layer of the first sub-circuit and the drain electrode of the MF in the layer of the first sub-circuit, the grid electrode of the MD in each layer of the first sub-circuit is connected with one end of the current detector, the grid electrodes of the MD in other layers of the first sub-circuit and the grid electrode of the MA, the drain electrode of the MD in each layer of the first sub-circuit is connected with an analog ground, the grid electrode of the ME in each layer of the first sub-circuit is respectively connected with the source electrode of the MF in the layer of the first sub-circuit and the source electrode of the MG in the layer of the first sub-circuit, the drain electrode of the ME in each layer of the first sub-circuit is respectively connected with one end of the load capacitor, the drain electrode of the, the gates of the MGs of each layer of the first subcircuit are respectively connected with the gates of the MG of the other layer of the first subcircuit and one end of the dynamic logic circuit, the gate of the MF of each layer of the first subcircuit is respectively connected with one end of the dynamic logic circuit and the gate of the MF of the first subcircuit of the other layer, the gate of the MC, the drain of the MG and the source of the MA are connected together, the source of the MC of each layer of the second subcircuit is respectively connected with the source of the MD of the layer of the second subcircuit and the drain of the MF of the layer of the second subcircuit, the gate of the MD of each layer of the second subcircuit is connected with one end of the current detector, the gate of the MD of the other layer of the second subcircuit and the gate of the MA, the drain of the MD of each layer of the second subcircuit is connected with an analog ground, the gate of the ME of each layer of the second subcircuit is respectively connected with the source of, The source electrodes of the MGs of the second sub-circuits of the layer are connected, the drain electrode of the ME of each layer of the second sub-circuits is respectively connected with one end of a load capacitor, the drain electrode of the ME of the first sub-circuit of the layer and the drain electrodes of the MEs of other layers, the grid electrode of the MG of each layer of the second sub-circuits is respectively connected with the grid electrode of the MG of the second sub-circuits of other layers and one end of a dynamic logic circuit, the grid electrode of the MF of each layer of the second sub-circuits is respectively connected with one end of the dynamic logic circuit and the grid electrode of the MF of the second sub-circuits of other layers, and the other end of the capacitor load is connected with an.

Optionally, the current detector includes: NMOS tubes M21, M22 and M25, P MOS tubes M23, M24 and M26, wherein the source of M21 is connected with the source of M22 and the source of M25 respectively and then connected with a power supply, and the drain of M21 is connected with the gate of the M21, the gate of M22 and the drain of M23 respectivelyThe source of the M23 is connected with the source of the M24 and the source of the M26 and then is connected to an analog ground, the grid of the M23 is connected with the grid of the MB, the drain of the M22 is connected with the drain of the M24, and the drain of the M22 outputs a voltage V_CDThe gate of the M24 is respectively connected with the gate of the M26, the drain of the M26 and the drain of the M25, and the gate of the M25 is connected with the gate of the MA.

Optionally, the dynamic logic enable circuit includes: the method comprises the following steps: comparators NCMP, PCMP, CMP, a first AND gate, a second AND gate, a third AND gate, a NAND gate, a first NOT gate and a second NOT gate, wherein the negative input end of the NCMP is connected with the negative input end of the PCMP and the output end VCD of the current detector, the output end of the NCMP is respectively connected with the first input end of the NAND gate and the first input end of the first AND gate, the output end of the PCMP is respectively connected with the second input end of the NAND gate and the second input end of the second AND gate, the output end of the NAND gate is respectively connected with the second input end of the first AND gate, the input end of the first NOT gate, the first input end of the second AND gate and the first input end of the third AND gate, the second input end of the third AND gate is connected with a clock signal CLK, the input end of the first AND gate is connected with the positive input end of the CMP, and the output end of the second AND gate is connected with the negative input end of the CMP, and the output end of the third AND gate is respectively connected with the input end of the second NOT gate and the enable end EN of the CMP.

The invention provides a multi-stage operational amplifier suitable for driving a wide-range capacitive load, which comprises a main operational amplifier, a programmable current source array circuit, a current detector, a dynamic logic enabling circuit and a dynamic logic circuit, wherein a programmable zero-adjusting resistor array is arranged in the main operational amplifier, the current detector detects the current of an output stage and feeds the current back to the dynamic logic enabling circuit, when the output stage determined based on the gate voltages of the MA and the MB needs to be compensated, the dynamic logic enabling circuit drives the dynamic logic circuit to generate a digital code, the current of the output stage is compensated to improve the slew rate, and the digital code is multiplexed to the RZ position of the programmable resistor array to enable the zero point to change along with the change of a secondary pole so as to optimize the phase margin.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic diagram of an overall structure of a multi-stage operational amplifier suitable for driving a wide-range capacitive load according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a multi-stage combined operational amplifier circuit according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a current detector according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a dynamic logic enable circuit according to an embodiment of the present invention;

fig. 5 is a flowchart illustrating an adaptive compensation mechanism according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

As shown in fig. 1, a multi-stage operational amplifier suitable for driving a wide-range capacitive load according to an embodiment of the present invention includes: the main operational amplifier of the built-in programmable zero-setting resistor array comprises a programmable resistor array R, a programmable current source array circuit, a current detector, a dynamic logic enabling circuit and a dynamic logic circuit_ZCapacitor C_ZAnd a multi-stage combined operational amplifier circuit comprising an NMOS transistor M_AAnd PMOS transistor M_BThe programmable current source array circuit is formed by sequentially connecting multiple layers of same single circuits, and the programmable resistor array R_ZIncorporating said capacitor C_ZGenerating a zero point before a secondary pole point in the multistage combined operational amplifier circuit, and controlling the programmable resistor array R of the zero point change when the secondary pole point changes along with the capacitance load_ZChanges in resistance value of M_AOf a gate electrode andthe first input ends of the programmable current source array circuits are connected, and M is_BThe grid of the current detector is connected with the second input end of the programmable current source array circuit, the power end of the main operational amplifier of the built-in programmable zero setting resistor array and the power end of the programmable current source array circuit are connected with a power end VDD, and the first input end V of the current detector is connected with the second input end of the programmable current source array circuit_GPA second input terminal V of the current detector connected to the gate of the MA_GNAnd said M_BThe output end of the current detector is connected with the input end of the dynamic logic enabling circuit, the output end of the dynamic logic enabling circuit is connected with the input end of the dynamic logic circuit, and the current detector is used for detecting the M_AAnd a gate voltage of the MB, the dynamic logic enable circuit to enable the MB based on the M_AAnd when the output stage determined by the gate voltage of the MB needs to be compensated, driving the dynamic logic circuit to generate a digital code, compensating the current of the output stage to improve the slew rate, and multiplexing the digital code to the programmable resistor array R_ZThe zero is changed with the change of the secondary pole to optimize the phase margin.

The number of layers N of the single circuit can be set according to industry experience, and can be set to 4 layers in an actual circuit. The programmable current source array circuit uses a source follower to perform level shift to provide bias voltages VBUP and VBDN for a load current source, and the current magnitude of the current source units is changed according to binary systems, namely IUP 1-2 IUP 2-4 IUP 3-8 IUP4 and IDN 1-2 IDN 2-4 IDN 3-8 IDN 4.

Whether the slew rate is limited or not is judged by detecting gate voltages VGP and VGN of MA and MB in the output stage, whether compensation is needed or not is judged, if compensation is needed, a dynamic logic enabling circuit takes effect, a subsequent successive approximation logic is driven to generate digital codes and return the digital codes to a programmable current source array, the output stage current is compensated to improve the slew rate, and the digital codes are simultaneously multiplexed to a programmable zero adjusting resistor, so that the zero position changes along with the change of a secondary pole, and the phase margin is optimized.

Example two

As shown in figure 2 of the drawings, in which,the multistage combined operational amplifier circuit comprises: NMOS transistors M1, M2, M5, M7, M8, M9, M10, M15, M16, M17 and M18, PMOS transistors M3, M4, M6, M11, M12, M13, M14, M19, M20, capacitors Cm1a, Cm1b, Cm2, and the M18_AAnd said M_BA source of the M1 is connected to the source of the M7, the source of the M8, the source of the M15, the source of the M16, the source of the MA, and a power source terminal VDD, a drain of the M1 is connected to the source of the M2 and the source of the M2, a drain of the M2 is connected to the drain of the M2 and the source of the M2, a gate of the M2 is connected to the gate of the M2, a source of the M2 is connected to the drain of the M2 and the source of the M2, a drain of the M2 is connected to the drain of the M2, the source of the M2, one end of the Cm 12, a gate of the M2 is connected to the gate of the M2, a drain of the M2 is connected to the source of the M2, a drain of the M2, a source of the M2, one end of the Cm1, and one end of the M2 is connected to, A source of the M14, a source of the M19, a source of the M20, a source of the MB, and the analog ground GND, a gate of the M7 is connected to a gate of the M8, a gate of the M16, a drain of the M9, and a drain of the M11, respectively, a gate of the M9 is connected to a gate of the M10, a drain of the M10 is connected to a drain of the M12, a gate of the M15, and a gate of the MA, a gate of the M15 is connected to a gate of the M15, a drain of the M15 is connected to a source of the M15, a drain of the M15 is connected to one end of the Cm 15, a drain of the M15 is connected to a drain of the M15, a gate of the M15, a drain of the M15 is connected to a drain of the M15, and a drain of the M15, a drain, the programmable resistor array R_ZThe capacitor Cz is connected between the gate and the drain of the M19 in a bridging mode, the capacitor Cz is connected between the gate and the source of the M19 in a bridging mode, and the output stage is composed of the MA and the MB.

As shown in fig. 2, the structure of the multi-stage combined operational amplifier circuit is schematically illustrated, and includes a first stage, a second stage and a third stage of the operational amplifier. The first stage includes a rail-to-rail input pair of M2, M3, M4, and M5 to provide a constant transconductance gm1 loaded with a cascode of M7-M14 to provide a greater output impedance. The transconductance gm2 is provided by M15 in the second stage, and a zero point which is generated by M19, CZ and RZ and is located before the secondary pole point is arranged at the second stage, which is beneficial to the improvement of unit gain bandwidth, wherein RZ is programmable, so that the following change of the zero point position to the secondary pole point position during the load change can be conveniently realized. The third stage is a Class AB push-pull stage, which is composed of MA and MB and can provide larger charge-discharge current compared with static current as an output stage to enhance the driving force to the load. Miller capacitors Cm1 and Cm2 are used for the splitting of the poles.

Referring to fig. 1, the single circuit includes: a first sub-circuit and a second sub-circuit, the first sub-circuit and the second sub-circuit being symmetric, the first sub-circuit and the second sub-circuit comprising: the grid electrode of the MC, the drain electrode of the MC, the source electrode of the ME, the drain electrode of the MG and the source electrode of the MA in each layer of the first sub-circuit are connected together, the source electrode of the MC in each layer of the first sub-circuit is respectively connected with the source electrode of the MD in the layer of the first sub-circuit and the drain electrode of the MF in the layer of the first sub-circuit, the grid electrode of the MD in each layer of the first sub-circuit is connected with one end of the current detector, the grid electrodes of the MD in other layers of the first sub-circuit and the grid electrode of the MA, the drain electrode of the MD in each layer of the first sub-circuit is connected with an analog ground, the grid electrode of the ME in each layer of the first sub-circuit is respectively connected with the source electrode of the MF in the layer of the first sub-circuit and the source electrode of the MG in the layer of the first sub-circuit, the drain electrode of the ME in each layer of the first sub-circuit is respectively connected with one end of the load capacitor, the drain electrode of the, the gates of the MGs of each layer of the first subcircuit are respectively connected with the gates of the MG of the other layer of the first subcircuit and one end of the dynamic logic circuit, the gate of the MF of each layer of the first subcircuit is respectively connected with one end of the dynamic logic circuit and the gate of the MF of the first subcircuit of the other layer, the gate of the MC, the drain of the MG and the source of the MA are connected together, the source of the MC of each layer of the second subcircuit is respectively connected with the source of the MD of the layer of the second subcircuit and the drain of the MF of the layer of the second subcircuit, the gate of the MD of each layer of the second subcircuit is connected with one end of the current detector, the gate of the MD of the other layer of the second subcircuit and the gate of the MA, the drain of the MD of each layer of the second subcircuit is connected with an analog ground, the gate of the ME of each layer of the second subcircuit is respectively connected with the source of, The source electrodes of the MGs of the second sub-circuits of the layer are connected, the drain electrode of the ME of each layer of the second sub-circuits is respectively connected with one end of a load capacitor, the drain electrode of the ME of the first sub-circuit of the layer and the drain electrodes of the MEs of other layers, the grid electrode of the MG of each layer of the second sub-circuits is respectively connected with the grid electrode of the MG of the second sub-circuits of other layers and one end of a dynamic logic circuit, the grid electrode of the MF of each layer of the second sub-circuits is respectively connected with one end of the dynamic logic circuit and the grid electrode of the MF of the second sub-circuits of other layers, and the other end of the capacitor load is connected with an.

Wherein UP < N: 1>, UPB < N: 1> is an N-bit digital code that controls the pull-UP compensation current, and UP < N: 1>, UPB < N: 1> is the opposite relationship for each digit code, DN < N: 1>, DNB < N: 1> is an N-bit digital code that controls the pull-down compensation current, and DN < N: 1>, DNB < N: 1> is the opposite relationship for each digit code. And if up -1, upB -0 corresponds to ME on, otherwise ME off, and if dn -1, dnB -0 corresponds to ME on, otherwise ME off.

As shown in fig. 3, the current detector includes: NMOS tubes M21, M22 and M25, P MOS tubes M23, M24 and M26, wherein a source of M21 is connected with a source of M22 and a source of M25 respectively and then connected to a power supply, a drain of M21 is connected with a gate of the M21, a gate of the M22 and a drain of the M23 respectively, a source of M23 is connected with a source of M24 and a source of M26 and then connected to an analog ground, a gate of M23 is connected with a gate of the MB, a drain of M22 is connected with a drain of M24, and a drain of M22 outputs a voltage V_CDThe grid of the M24 and the grid of the M26 are respectivelyThe drain of the M26 and the drain of the M25 are connected, and the gate of the M25 is connected with the gate of the MA.

In fig. 3, the gate of M25 is connected to the gate of MA in the main operational amplifier, the gate of M23 is connected to the gate of MB in the main operational amplifier, and the gate voltages are VGP and VGN, respectively, when M25 needs to provide a large charging current, which results in that M22 operates in the linear region, the voltage VCD at the output terminal of the current detector will be pulled up to VDD; similarly, when M25 needs to provide a large discharging current, which results in M24 operating in the linear region, the voltage VCD at the output of the current detector will be pulled down to GND, and when the charging and discharging current is within a reasonable range, i.e. corresponding to M22 and M24 both operating in the saturation region, the peak and valley values of VCD are VrefH and VrefL.

As shown in fig. 4, the dynamic logic enable circuit includes: comparators NCMP, PCMP, CMP, a first AND gate, a second AND gate, a third AND gate, a NAND gate, a first NOT gate and a second NOT gate, wherein the negative input end of the NCMP is connected with the negative input end of the PCMP and the output end VCD of the current detector, the output end of the NCMP is respectively connected with the first input end of the NAND gate and the first input end of the first AND gate, the output end of the PCMP is respectively connected with the second input end of the NAND gate and the second input end of the second AND gate, the output end of the NAND gate is respectively connected with the second input end of the first AND gate, the input end of the first NOT gate, the first input end of the second AND gate and the first input end of the third AND gate, the second input end of the third AND gate is connected with a clock signal CLK, the input end of the first AND gate is connected with the positive input end of the CMP, and the output end of the second AND gate is connected with the negative input end of the CMP, and the output end of the third AND gate is respectively connected with the input end of the second NOT gate and the enable end EN of the CMP.

NCMP and PCMP are clock-less comparators, and CMP is a dynamic comparator.

As shown in fig. 4, the positive input terminal voltage of NCMP is set to VrefH, the positive input terminal voltage of PCMP is set to VrefL, when the slew rate is limited, corresponding to the situation that VCD is pulled up to VDD or pulled down to GND, under the action of the logic gate, the enable terminal EN of CMP is made to be 1, the comparator starts to operate, the generated comparison results QN and QP are registered in the dynamic logic of the next stage, and the external clock CLK is transmitted to the dynamic logic circuit of the next stage. When the slew rate is within a reasonable interval, corresponding to the situation that VCD is between VrefL and VrefH, EN is 0, the comparator cannot be enabled, the clock CLK2 of the dynamic logic is kept at a low level, and the reset signal RES of the dynamic logic changes to a high level.

The dynamic logic circuit adopts successive approximation logic.

The operation principle of the multi-stage operational amplifier suitable for driving a wide-range capacitive load according to the embodiment of the present invention is specifically described with reference to fig. 5. Assuming that the number of layers of the single circuit is 4, whether the slew rate is limited is judged according to the judgment mechanism described in fig. 4, and whether compensation is needed is determined, and the compensation mode is divided into two types: when VCD is larger than Vrefh, corresponding to the case that the positive input end and the negative input end of CMP are Vref + ═ 0 and Vref- ═ 1 respectively, only compensation of pull-UP current is carried out, 4bit digital codes UP <4:1> and UPB <4:1> are generated according to the successive approximation logic and act on the programmable current source array, and UPB and UP are in an opposite relation, while DN <4:1> and DNB <4:1> keep 0000 and 1111 unchanged. Similarly, when VCD is smaller than VrefL, corresponding to the case where the positive input terminal and the negative input terminal of CMP are Vref + 1 and Vref-0, respectively, only compensation of pull-down current is performed, and 4-bit digital codes DN <4:1> and DNB <4:1> are generated and continuously generated according to successive approximation logic and applied to the programmable current source array, and DNB are in an inverse relationship, while UP <4:1> and UPB <4:1> remain 0000 and 1111 unchanged. And circularly detecting the size of the VCD and enabling the VCD to finally enter a reasonable interval, finishing compensation, enabling the operational amplifier to return to a normal working mode with the small signal establishment time being dominant, and multiplexing the digital codes generated in the process to the programmable zero setting resistor array at the same time to enable the phase margin to be always kept at a high-quality value.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. Be applicable to drive wide region electric capacity and burdenA multi-stage operational amplifier for driving a wide range capacitive load, the multi-stage operational amplifier comprising: the main operational amplifier of the built-in programmable zero-setting resistor array consists of a programmable resistor array (R), a programmable current source array circuit, a current detector, a dynamic logic enabling circuit and a dynamic logic circuit_Z) Capacitor (C)_Z) And the multistage combination operational amplifier circuit comprises: by NMOS tube M_AAnd PMOS transistor M_BThe programmable current source array circuit is formed by sequentially connecting multiple layers of same single circuits, and the programmable resistor array (R)_Z) Incorporating said capacitor (C)_Z) A programmable resistance array (R) for generating a zero before the next pole in the multi-stage combined operational amplifier circuit, the programmable resistance array (R) controlling the change of the zero when the next pole changes with the capacitance load_Z) Changes in resistance value of M_AIs connected to a first input terminal of the programmable current source array circuit, M_BThe grid of the current detector is connected with the second input end of the programmable current source array circuit, the power end of the main operational amplifier of the built-in programmable zero setting resistor array and the power end of the programmable current source array circuit are connected with a power end (VDD), and the first input end (V) of the current detector_GP) A second input terminal (V) of the current detector connected to the gate of the MA_GN) And said M_BThe output end of the current detector is connected with the input end of the dynamic logic enabling circuit, the output end of the dynamic logic enabling circuit is connected with the input end of the dynamic logic circuit, and the current detector is used for detecting the M_AAnd a gate voltage of the MB, the dynamic logic enable circuit to enable the MB based on the M_AAnd when the output stage determined by the gate voltage of the MB needs to be compensated, driving the dynamic logic circuit to generate a digital code, compensating the current of the output stage to increase slew rate, and multiplexing the digital code to the programmable resistor array (R)_Z) The zero is changed with the change of the secondary pole to optimize the phase margin.

2. The multi-stage operational amplifier suitable for driving a wide range of capacitive loads according to claim 1, wherein the multi-stage combined operational amplifier circuit comprises: NMOS transistors M1, M2, M5, M7, M8, M9, M10, M15, M16, M17 and M18, PMOS transistors M3, M4, M6, M11, M12, M13, M14, M19, M20, capacitors Cm1a, Cm1b, Cm2, and the M18_AAnd said M_BA source of the M1 is connected to the source of the M7, the source of the M8, the source of the M15, the source of the M16, the source of the MA, and a power source terminal (VDD), a drain of the M1 is connected to the source of the M2 and the source of the M2, a drain of the M2 is connected to the drain of the M2 and the source of the M2, a gate of the M2 is connected to the gate of the M2, a source of the M2 is connected to the drain of the M2 and the source of the M2, a drain of the M2 is connected to the drain of the M2, the source of the M2, one end of the Cm 12, a gate of the M2 is connected to the gate of the M2, a drain of the M2 is connected to the source of the M2, a drain of the M2, a source of the M2, one end of the Cm1, and one end of the drain of the M2 is, A source of the M14, a source of the M19, a source of the M20, a source of the MB, and the analog Ground (GND), a gate of the M7 is connected to a gate of the M8, a gate of the M16, a drain of the M9, and a drain of the M11, respectively, a gate of the M9 is connected to a gate of the M10, a drain of the M10 is connected to a drain of the M12, a gate of the M15, and a gate of the MA, a gate of the M15 is connected to a gate of the M15, a drain of the M15 is connected to a source of the M15, an end of the Cm 15, a drain of the M15 is connected to a drain of the M15, a gate of the M15 is connected to a drain of the M15, and a drain of the M15 is connected to a gate of the M15, a drain of, the programmable resistor array (R)_Z) A gate connected across the M19And a drain, the capacitor (Cz) is connected across the gate and the source of the M19, and the output stage is composed of the MA and the MB.

3. The multi-stage operational amplifier suitable for driving a wide range of capacitive loads according to claim 1, wherein the single circuit comprises: a first sub-circuit and a second sub-circuit, the first sub-circuit and the second sub-circuit being symmetric, the first sub-circuit and the second sub-circuit comprising: NMOS transistors MC, MD, ME, MF and MG, wherein the gate of MC, the drain of MC, the source of ME, the drain of MG and the source of MA are connected together in each layer of first sub-circuit, the source of MC is connected with the source of MD of the layer of first sub-circuit and the drain of MF of the layer of first sub-circuit, the gate of MD is connected with one end of the current detector, the gates of MD of other layers of first sub-circuit and the gate of MA, the drain of MD is connected with analog ground, the gate of ME is connected with the source of MF of the layer of first sub-circuit and the source of MG, the drain of ME is connected with one end of load Capacitor (CL), the drain of ME of the layer of second sub-circuit and the drain of ME of other layers, the gates of the MGs of each layer of the first subcircuit are respectively connected with the gates of the MG of the other layer of the first subcircuit and one end of the dynamic logic circuit, the gate of the MF of each layer of the first subcircuit is respectively connected with one end of the dynamic logic circuit and the gate of the MF of the first subcircuit of the other layer, the gate of the MC, the drain of the MG and the source of the MA are connected together, the source of the MC of each layer of the second subcircuit is respectively connected with the source of the MD of the layer of the second subcircuit and the drain of the MF of the layer of the second subcircuit, the gate of the MD of each layer of the second subcircuit is connected with one end of the current detector, the gate of the MD of the other layer of the second subcircuit and the gate of the MA, the drain of the MD of each layer of the second subcircuit is connected with an analog ground, the gate of the ME of each layer of the second subcircuit is respectively connected with the source of, The source electrodes of the MGs of the second sub-circuits of the layer are connected, the drain electrode of the ME of each layer of the second sub-circuits is respectively connected with one end of a load Capacitor (CL), the drain electrode of the ME of the first sub-circuit of the layer and the drain electrodes of the MEs of other layers, the grid electrode of the MG of each layer of the second sub-circuits is respectively connected with the grid electrode of the MG of the second sub-circuits of other layers and one end of the dynamic logic circuit, the grid electrode of the MF of each layer of the second sub-circuits is respectively connected with one end of the dynamic logic circuit and the grid electrode of the MF of the second sub-circuits of other layers, and the other end of the Capacitor Load (CL) is connected with an analog.

4. The multi-stage operational amplifier suitable for driving a wide range of capacitive loads according to claim 1, wherein the current detector comprises: NMOS tubes M21, M22 and M25, P MOS tubes M23, M24 and M26, wherein a source of M21 is connected with a source of M22 and a source of M25 respectively and then connected to a power supply, a drain of M21 is connected with a gate of the M21, a gate of the M22 and a drain of the M23 respectively, a source of M23 is connected with a source of M24 and a source of M26 and then connected to an analog ground, a gate of M23 is connected with a gate of the MB, a drain of M22 is connected with a drain of M24, and a drain of M22 outputs a voltage (V24)_CD) The gate of the M24 is respectively connected with the gate of the M26, the drain of the M26 and the drain of the M25, and the gate of the M25 is connected with the gate of the MA.

5. The multi-stage operational amplifier suitable for driving a wide range of capacitive loads according to claim 1, wherein the dynamic logic enable circuit comprises: the method comprises the following steps: comparators NCMP, PCMP, CMP, a first AND gate, a second AND gate, a third AND gate, a NAND gate, a first NOT gate and a second NOT gate, wherein the negative input end of the NCMP is connected with the negative input end of the PCMP and the output end (VCD) of the current detector, the output end of the NCMP is respectively connected with the first input end of the NAND gate and the first input end of the first AND gate, the output end of the PCMP is respectively connected with the second input end of the NAND gate and the second input end of the second AND gate, the output end of the NAND gate is respectively connected with the second input end of the first AND gate, the input end of the first NOT gate, the first input end of the second AND gate and the first input end of the third AND gate, the second input end of the third AND gate is connected with a clock signal (CLK), the input end of the first AND gate is connected with the positive input end of the CMP, and the output end of the second AND gate is connected with the negative input end of the CMP, and the output end of the third AND gate is respectively connected with the input end of the second NOT gate and the enable End (EN) of the CMP.