CN110912541A

CN110912541A - Comparator circuit system

Info

Publication number: CN110912541A
Application number: CN201811080625.8A
Authority: CN
Inventors: 汪鼎豪; 徐浩哲; 林倍如
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2018-09-17
Filing date: 2018-09-17
Publication date: 2020-03-24
Anticipated expiration: 2038-09-17
Also published as: CN110912541B

Abstract

The comparator circuit system comprises an input pair circuit, a load circuit and a compensation circuit. The input pair circuit is used for comparing a first input signal with a second input signal to control a first bias current. The load circuit is coupled to the input pair circuit and is used for responding to the first bias current so as to output an output signal with a first level from a first output end of the load circuit. The compensation circuit is coupled to the input pair circuit and the load circuit, and is used for drawing a compensation current from the first output end to a voltage source during the period when the load circuit generates an output signal with a first level, wherein the voltage source is used for providing a voltage with a second level.

Description

Comparator circuit system

Technical Field

The present disclosure relates to comparator circuits, and more particularly to comparator circuits suitable for high speed applications.

Background

Comparators are commonly used in various electronic devices to provide a control function for comparing or determining a predetermined condition. The precision of the comparator operations, such as the timing of operations and the quality of the output signals, affect the accuracy of the operations of other circuits of the system. For example, when the comparator is applied to high-speed data transmission, the comparator may be affected by timing jitter (timing jitter) to degrade the signal quality. The comparator circuit system provided by the scheme can improve the quality of an output signal through compensating current so as to be suitable for application of high-speed data transmission.

Disclosure of Invention

To solve the above problems, some aspects of the present invention provide a comparator circuit system, which includes an input pair circuit, a load circuit and a compensation circuit. The input pair circuit is used for comparing a first input signal with a second input signal to control a first bias current. The load circuit is coupled to the input pair circuit and is used for responding to the first bias current so as to output an output signal with a first level from a first output end of the load circuit. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to draw a compensation current from the first output terminal to a voltage source during a period when the load circuit generates the output signal having the first level, wherein the voltage source is configured to provide a voltage of a second level.

In some embodiments, the comparator circuitry further comprises a first current source circuit. The first current source circuit is coupled between the input pair circuit and the voltage source and is used for generating the first bias current according to a bias signal.

In some embodiments, the compensation circuit is activated to draw the compensation current from the first output terminal according to the first input signal, wherein the compensation current is transmitted to the voltage source through the first current source circuit.

In some embodiments, the comparator circuitry further comprises a second current source circuit. The second current source circuit is coupled between the compensation circuit and the voltage source and is used for generating a second bias current according to the bias signal.

In some embodiments, the compensation circuit is configured to be fixedly conducted with the second bias current according to the bias signal, so as to fixedly draw the compensation current from the first output terminal to the voltage source.

In some embodiments, the compensation circuit and the input pair circuit are coupled to a node, the compensation current is transmitted to the voltage source through the node, and the compensation circuit includes a first transistor and a second transistor. The first transistor is coupled between the first output end and the node and used for responding to the first input signal to be conducted so as to draw the compensation current. The second transistor is coupled between a second output end of the load circuit and the node and is used for responding to the second input signal and conducting.

In some embodiments, the compensation circuit includes a first transistor and a second transistor. The first transistor is coupled between the first output end and the voltage source and is used for responding to a bias signal and fixedly conducting so as to draw the compensation current. The second transistor is coupled between a second output end of the load circuit and the voltage source and is used for responding to the bias signal and fixedly conducting.

In some embodiments, the load circuit comprises a plurality of transistors. The plurality of transistors are coupled to the input pair circuit and are respectively coupled to the first output end and a second output end of the load circuit.

Other aspects of the present disclosure provide a comparator circuit system including a current source circuit, an input pair circuit, a load circuit, and a cross-coupled transistor pair. The current source circuit is used for providing a bias current. The input pair circuit is coupled to the current source circuit and used for comparing a first input signal with a second input signal so as to guide the bias current. The load circuit is coupled to the current source circuit and is used for generating a first output signal and a second output signal at a first output end and a second output end respectively according to the guided bias current. The cross-coupled transistor pair includes a first transistor and a second transistor. The first transistor is coupled between the first output end and the current source circuit and is conducted according to the first input signal so as to draw a first compensation current from the first output end; and the second transistor is coupled between the second output end and the current source circuit and is conducted according to the second input signal so as to draw a second compensation current from the second output end.

In still other aspects, a comparator circuit system is provided, which includes an input pair circuit, a load circuit, a first transistor and a second transistor. The input pair circuit is coupled to a first current source circuit and is used for comparing a first input signal with a second input signal so as to guide a first bias current generated by the first current source circuit. The load circuit is used for generating a first output signal and a second output signal at a first output end and a second output end respectively according to the guided first bias current. The first transistor is coupled between the first output end and a second current source circuit and is conducted according to a bias signal fixed signal to draw a first compensation current from the first output end. The second transistor is coupled between the second output terminal and the second current source circuit, and is turned on according to the bias signal fixing signal to draw a second compensation current from the second output terminal, wherein the sum of the first compensation current and the second compensation current is the same as a second bias current provided by the second current source circuit.

In summary, the comparator circuit system provided by the present disclosure can improve the quality of the output signal by compensating the current, so as to be suitable for high-speed data transmission applications.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a comparator circuitry according to some embodiments of the present disclosure;

fig. 2 is a circuit schematic diagram of the comparator circuitry of fig. 1 according to some embodiments of the disclosure;

FIG. 3 is a circuit schematic diagram of the comparator circuitry of FIG. 1 according to some embodiments of the disclosure;

FIG. 4 is a waveform diagram and an eye diagram of a related art without using a compensation circuit; and

fig. 5 illustrates a waveform diagram and an eye diagram of the comparator circuitry of fig. 2 with a compensation circuit according to some embodiments of the disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in the context of this specification is by way of example only and should not be construed as limiting the scope or meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.

As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.

Referring to fig. 1, fig. 1 is a schematic diagram of a comparator circuit system 100 according to some embodiments of the present disclosure. In some embodiments, the comparator circuit system 100 can be applied to various data transmission systems. In some embodiments, the comparator circuitry 100 includes an input pair circuit 110, a load circuit 120, a compensation circuit 130, and a current source circuit 140.

The input pair circuit 110 is coupled between the load circuit 120 and the current source circuit 140. In some embodiments, the input pair circuit 110 is configured to compare the input signal VIP with the input signal VIN to control the bias current IB1 generated by the current source circuit 140. For example, the input pair circuit 110 may be implemented by a fully differential input pair (e.g., transistors as described below). Under this condition, when the input signal VIP is greater than the input signal VIN, most of the bias current IB1 is directed to the signal path of the input pair circuit 110 for processing the input signal VIP. Conversely, when the input signal VIP is smaller than the input signal VIN, most of the bias current IB1 will be directed to the signal path of the input pair circuit 110 that processes the input signal VIN. In some embodiments, one of the input signal VIP or the input signal VIN may be a reference signal for comparison. In some embodiments, the current source circuit 140 may include a current mirror circuit implemented by one or more transistors, but the disclosure is not limited thereto.

The load circuit 120 is configured to provide at least one active load to generate the output signal VOP at the output node NOP thereof and to generate the output signal VON at the output node NON thereof in response to the current IB1 directed by the input pair circuit 110. For example, if the input signal VIP is greater than the input signal VIN, the output terminal NOP outputs the output signal VOP having a high level (e.g., a voltage VDD described later), and the output terminal NON outputs the output signal VON having a low level (e.g., a ground voltage described later). On the contrary, if the input signal VIP is lower than the input signal VIN, the output terminal NOP outputs the output signal VOP having a low level, and the output terminal NON outputs the output signal VON having a high level.

The compensation circuit 130 is used for drawing a compensation current ICP from the output node NOP to a voltage source for providing a predetermined level (e.g., the low level and/or the voltage VSS shown in fig. 2 to 3) during a period when the load circuit 120 outputs the output signal VOP having a specific level (e.g., the high level). In some embodiments, the compensation current ICP is drawn from the signal path through which less bias current IB1 flows in the input pair circuit 110 and/or the load circuit 120 during the comparison of the input signal VIN with the input signal VIP by the input pair circuit 110.

In some related arts, the comparator directly performs the comparison operation without providing the compensation circuit 130. In these techniques, the quality of the output signal generated by the comparator will depend on the switching frequency of the input signal. When the method is applied to high-speed data transmission, the input signal has a high switching frequency, so that the output of the comparator enters the next comparison operation when the output of the comparator does not completely enter a steady state. Thus, the quality of the output signal of the comparator will be degraded. By drawing the compensation current ICP, the output of the comparator circuitry 100 can enter steady state faster than in the related art described above. As such, the comparator circuit system 100 is suitable for high speed data transmission applications. The description will be described with reference to fig. 4 and 5 in the following paragraphs.

The following paragraphs will describe the implementation of the above-mentioned circuits, but the present disclosure is not limited to the following embodiments.

Referring to fig. 2, fig. 2 is a circuit schematic diagram illustrating the comparator circuitry 100 of fig. 1 according to some embodiments of the disclosure. For ease of understanding, like elements in fig. 1 and 2 will be designated with the same reference numerals.

As shown in fig. 2, the input pair circuit 110 includes a transistor MN1 and a transistor MN 2. In some embodiments, the transistors MN1 and MN2 are a differential input pair. The first terminal of the transistor MN1 is coupled to the output terminal NON of the load circuit 120, the second terminal of the transistor MN1 and the current source circuit 140 are coupled to the node ND, and the control terminal of the transistor MN1 is configured to receive the input signal VIP. The first terminal of the transistor MN2 is coupled to the output terminal NOP of the load circuit 120, the second terminal of the transistor MN2 and the current source circuit 140 are coupled to the node ND, and the control terminal of the transistor MN2 is configured to receive the input signal VIN. In this example, the current source circuit 140 includes a transistor MNB 1. A first terminal of the transistor MNB1 is coupled to the node ND, a second terminal of the transistor MNB1 is coupled to a voltage source for providing the voltage VSS, and a control terminal of the transistor MNB1 is configured to receive the bias signal VBN. The transistor MNB1 generates the bias current IB1 according to the bias signal VBN. In some embodiments, the voltage VSS is lower than the voltage VDD, wherein the voltage VSS may be a ground voltage, but the disclosure is not limited thereto.

As shown in fig. 2, the load circuit 120 includes a transistor MP1 and a transistor MP 2. The first terminals of the transistors MP1 and MP2 are coupled to a voltage source for receiving the voltage VDD. The control terminals of the transistors MP1 and MP2 are used for receiving the bias signal VBP to respectively provide an active load to the input pair circuit 110. The transistor MP1 or the transistor MP2 generates the output signals VON and VOP according to the active load and current source provided and the bias current IB1 directed to the input pair circuit 110. The second terminal of the transistor MP1 is coupled to the output terminal NON, and the second terminal of the transistor MP2 is coupled to the output terminal NOP.

As shown in fig. 2, when the input signal VIP transitions from low to high and the input signal VIN transitions from high to low, the transistor MN1 turns on and the transistor MN2 turns off. Under this condition, most of the bias current IB1 is directed to flow to the signal path of the transistors MP1 and MN 1. Thus, the load circuit 120 outputs the output signal VON with a low level and outputs the output signal VOP with a high level.

As shown in fig. 2, the compensation circuit 130 includes a transistor MN3 and a transistor MN 4. In some embodiments, the transistors MN3 and MN4 are cross-coupled (cross-coupled) transistor pairs. The first terminal of the transistor MN3 is coupled to the output terminal NOP, the second terminal of the transistor MN3 is coupled to the node ND, and the control terminal of the transistor MN3 is configured to receive the input signal VIP. The first terminal of the transistor MN4 is coupled to the output terminal NON, the second terminal of the transistor MN4 is coupled to the node ND, and the control terminal of the transistor MN4 is configured to receive the input signal VIN.

In this example, the compensation circuit 130 is configured to be enabled in response to the input signal VIN or the input signal VIP to draw the aforementioned compensation current ICP. For example, when the input signal VIP transitions from low to high and the input signal VIN transitions from high to low, the transistor MN3 turns on and the transistor MN4 turns off. Under this condition, the transistor MN3 draws the compensation current ICP from the second terminal (i.e., the output terminal NOP) of the transistor MP2 to the voltage source providing the voltage VSS. In some embodiments, when the input signal VIP transitions from a low level to a high level and the input signal VIN transitions from a high level to a low level, the level of the output signal VOP is slightly lower than the voltage VDD (as shown in fig. 5 described later).

Referring to fig. 3, fig. 3 is a circuit schematic diagram illustrating the comparator circuitry 100 of fig. 1 according to some embodiments of the disclosure. For ease of understanding, similar elements in fig. 1-3 will be designated with the same reference numerals.

Compared to fig. 2, in this example, the comparator circuit system 100 further includes a current source circuit 310. The current source circuit 310 is coupled between the compensation circuit 130 and a voltage source providing the voltage VSS, and generates a bias current IB2 according to the bias signal VBN. In addition, compared to fig. 2, in this example, the compensation circuit 130 is coupled to the current source circuit 310 and configured to be turned on constantly according to the bias signal VBN and the bias current IB2 to continuously draw the compensation current ICP1 and the compensation current ICP2 from the output terminals VON and VOP of the load circuit 120 to the voltage source providing the voltage VSS, respectively.

In detail, in some embodiments, the current source circuit 310 includes a transistor MNB 2. The first terminal of the transistor MNB2 is coupled to the second terminals of the transistors MN3 and MN4, the second terminal of the transistor MNB2 is coupled to a voltage source providing the voltage VSS, and the control terminal of the transistor MNB2 is configured to receive the bias signal VBN. The transistor MNB2 is configured to generate a bias current IB2 according to the bias signal VBN. In addition, in this example, the control terminals of the transistors MN3 and MN4 are configured to receive the bias signal VBN to be continuously turned on to draw the compensation currents ICP1 and ICP 2.

In this example, the sum of the compensation currents ICP1 and ICP2 constantly drawn by the transistors MN3 and MN4 is the same as the bias current IB 2. In some embodiments, the compensation currents ICP1 and ICP2 are each set to half the bias current IB2 by setting the device dimensions and/or bias conditions.

In some embodiments, each of the input pair circuit 110, the load circuit 120 and/or the compensation circuit 130 is configured as a differential circuit. For ease of understanding, the above operations are only described by way of example for compensation of the output signal VOP. It should be understood that, since the differential circuit has a symmetrical structure, the compensation circuit 130 can also perform a similar compensation operation on the output signal VON. For example, when the input signal VIP transitions from high to low and the input signal VIN transitions from low to high, the transistor MN4 is turned on to draw the compensation current from the output terminal NON.

The above arrangement is merely an example, and the present disclosure is not limited thereto. For example, in various embodiments, the transistors MNB2, MN3, and MN4 may also be controlled using different bias signals.

The types (P-type, N-type), types, etc. of the transistors are all examples, and the present disclosure is not limited thereto. Different types or kinds of transistors can be used to implement the comparator circuit 100 according to different operating voltages or application conditions. In addition, according to different types of transistors, the corresponding relationship between the voltage and the level mentioned in the above embodiments can also be adjusted together.

Referring to fig. 4 and 5, fig. 4 is a waveform diagram and an eye diagram of a related art without using the compensation circuit 120, and fig. 5 is a waveform diagram and an eye diagram of the comparator circuit system 100 in fig. 2 with the compensation circuit 120 according to some embodiments of the disclosure.

As mentioned above, in some related art, without using the compensation circuit 120, the output of the comparator cannot quickly enter a steady state, which results in a degradation of signal quality. For example, as shown in fig. 4, when the switching (i.e., transition) frequency of the input signal VIP is fast (e.g., two times of switching within the period T1), the state of the output signal VOP changes in response to the second switching of the input signal VIP before the input signal VIP has not completely entered the steady state and stabilized at the level of the voltage VDD (i.e., the pulse P1). In contrast, during the period T2 when the switching frequency is lower, the output signal VOP can still enter the steady state and stabilize at the level of the voltage VDD. In other words, in the related art without using the compensation circuit 120, the output signal VOP will depend on the switching frequency of the input signal VIP. Thus, by measuring the eye pattern 410 of the output signal VOP, it can be known that the output signal VOP is affected by much timing jitter (timing jitter) and the signal quality is degraded.

In contrast, as shown in fig. 5, with the compensation circuit 120, the output of the comparator circuitry 100 can instantaneously enter a steady state each time the input signal VIP switches. Thus, by measuring the eye pattern 510 of the output signal VOP, it can be known that the output signal VOP may be affected by less timing jitter). In other words, by providing the compensation circuit 120, the signal quality of the output signal VOP can be improved.

Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.

Claims

1. A comparator circuitry, comprising:

an input pair circuit for comparing a first input signal with a second input signal to control a first bias current;

a load circuit coupled to the input pair circuit and configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current; and

a compensation circuit coupled to the input pair circuit and the load circuit for drawing a compensation current from the first output terminal to a voltage source during a period when the load circuit generates the output signal having the first level, wherein the voltage source is used for providing a voltage of a second level.

2. The comparator circuitry of claim 1, further comprising:

the first current source circuit is coupled between the input pair circuit and the voltage source and is used for generating the first bias current according to a bias signal.

3. The comparator circuitry of claim 2, wherein the compensation circuit is enabled to draw the compensation current from the first output terminal according to the first input signal, wherein the compensation current is delivered to the voltage source via the first current source circuit.

4. The comparator circuitry of claim 2, further comprising:

the second current source circuit is coupled between the compensation circuit and the voltage source and used for generating a second bias current according to the bias signal.

5. The comparator circuit system of claim 4, wherein the compensation circuit is configured to be turned on according to the bias signal and the second bias current to draw the compensation current from the first output terminal to the voltage source.

6. The comparator circuitry of claim 1, wherein the compensation circuit and the input pair circuit are coupled to a node through which the compensation current is delivered to the voltage source, and the compensation circuit comprises:

a first transistor coupled between the first output terminal and the node, and configured to be turned on in response to the first input signal to draw the compensation current; and

a second transistor coupled between a second output terminal of the load circuit and the node and configured to turn on in response to the second input signal.

7. The comparator circuitry of claim 1, wherein the compensation circuit comprises:

a first transistor coupled between the first output terminal and the voltage source and configured to be turned on in response to a bias signal to draw the compensation current; and

and the second transistor is coupled between a second output end of the load circuit and the voltage source and is used for responding to the bias signal and fixedly conducting.

8. The comparator circuitry of claim 1, wherein the load circuit comprises:

and a plurality of transistors coupled to the input pair circuit and coupled to the first output terminal and a second output terminal of the load circuit, respectively.

9. A comparator circuitry, comprising:

a current source circuit for providing a bias current;

an input pair circuit coupled to the current source circuit for comparing a first input signal with a second input signal to direct the bias current;

a load circuit coupled to the current source circuit and used for generating a first output signal and a second output signal at a first output end and a second output end respectively according to the guided bias current; and

a cross-coupled transistor pair, comprising:

a first transistor coupled between the first output terminal and the current source circuit, and turned on according to the first input signal to draw a first compensation current from the first output terminal; and

and a second transistor coupled between the second output terminal and the current source circuit and turned on according to the second input signal to draw a second compensation current from the second output terminal.

10. A comparator circuitry, comprising:

an input pair circuit coupled to a first current source circuit for comparing a first input signal with a second input signal to direct a first bias current generated by the first current source circuit;

a load circuit for generating a first output signal and a second output signal at a first output terminal and a second output terminal respectively according to the first bias current after being conducted;

a first transistor coupled between the first output terminal and a second current source circuit, and turned on according to a bias signal fixing signal to draw a first compensation current from the first output terminal; and

a second transistor coupled between the second output terminal and the second current source circuit and turned on according to the bias signal fixing signal to draw a second compensation current from the second output terminal,

wherein the sum of the first compensation current and the second compensation current is the same as a second bias current provided by the second current source circuit.