JP4549273B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier that stably drives a capacitive load.

  FIG. 6 shows a configuration example (Patent Document 1) of a conventional Rail-to-Rail operational amplifier.

  In the circuit described in the prior art of Patent Document 1, the connection point of the phase compensation capacitor is between the gate and drain of the output transistor.

  P-type MOS differential input section 1 composed of transistors M1, M2, and M3, N-type MOS differential input section 2 composed of transistors M4, M5, and M6, and transistors M7, M8, M9, and M10 Pdd-type current mirror circuit 3, N-type current mirror circuit 4 composed of transistors M11, M12, M13, and M14, and push-pull output stage 5 composed of transistors M15 and M16 are the main parts, and Vdd Is a positive power supply voltage, and Vss is a negative power supply voltage.

  The non-inverting input is connected to the gates of the transistors M3 and M5, and the inverting input is connected to the gates of the transistors M2 and M4. The output of the P-type MOS differential input unit 1 from the transistors M2 and M3 is input to the current mirror circuit 4, and the output of the N-type MOS differential input unit 2 from the transistors M4 and M5 is input to the current mirror circuit 3. ing. The current mirror circuit 3 and the current mirror circuit 4 are connected by resistors R1 and R2, and the gate of the transistor M15 in the push-pull output stage 5 is connected to a connection point between the transistor M10 and one end of the resistor R2, and pushes. The gate of the transistor M16 of the pull output stage 5 is connected to the connection point between the transistor M12 and the other end of the resistor R2. Resistors R1 and R2 can also be formed of MOS transistors or the like.

  C1 and C2 are phase compensation capacitors, and Vb1 to Vb4 are bias voltages set so that each transistor constituting the circuit operates appropriately. In FIG. 6, an external load capacitor CL is connected between the output of the push-pull output stage 5 and the negative power supply voltage Vss.

  The current flowing through the transistor M1 serving as the constant current source of the P-type MOS differential input unit 1 is defined as (Im1), and the current flowing through the transistor M6 serving as the constant current source of the N-type MOS differential input unit 2 is defined as (Im6). A state where the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) are equal is defined as a steady state. In a steady state, the currents flowing through the transistors M2 and M3 of the P-type MOS differential input unit 1 are both (Im1) · (1/2), and the currents flowing through the transistors M4 and M5 of the N-type MOS differential input unit 2 are Both are (Im6) · (1/2).

  When the non-inverting input voltage (Vin +) changes from the steady state to a voltage state higher than the inverting input voltage (Vin−), most of the constant current (Im1) flows through the transistor M2 in the P-type differential input section. Since the current flowing through M13 increases and the current flowing through the transistors M12 and M14 increases due to the current mirror circuit 4, the current drawn from the phase compensation capacitors C1 and C2 increases. On the other hand, in the N-type differential input section, the current flowing through the transistor M4 decreases, so that the current flowing through the transistor M7 decreases. Since most of the current flows, the current flowing through the transistor M10 decreases, and the charging current to the phase compensation capacitors C1 and C2 decreases. At this time, the gate voltages of the output transistors M15 and M16 decrease, and the current flowing through M15 increases, so the charging current to the external load CL increases, and the current flowing through M16 decreases, so the current drawn from the external load CL decreases. As a result, the external load CL is charged and the output voltage Vout rises.

  When the non-inverted input voltage (Vin +) changes from the steady state to a voltage state lower than the inverted input voltage (Vin−), most of the constant current (Im6) flows through the transistor M4 in the N-type differential input unit. The current flowing through M7 increases, and the current flowing through the transistors M8 and M10 is increased by the current mirror circuit 3, so that the charging current to the phase compensation capacitors C1 and C2 increases. On the other hand, in the P-type differential input section, the current flowing through the transistor M2 decreases, the current flowing through the transistor M13 decreases, the current flowing through the transistor M14 decreases by the current mirror circuit 4, and a constant current (Im1) is supplied to the transistor M3. Since most of the current flows, the current flowing through the transistor M12 decreases, and the current drawn from the phase compensation capacitors C1 and C2 decreases. At this time, the gate voltages of the output transistors M15 and M16 rise, the current flowing through M15 decreases, the charging current to the external load CL decreases, and the current flowing through M16 increases, so the current drawn from the external load CL increases. As a result, the external load CL is discharged and the output voltage Vout decreases.

JP 2001-156559 A

  In the conventional Rail-to-Rail operational amplifier, the shorter the charge / discharge time of the phase compensation capacitors C1, C2, the faster the gate voltage of the output transistors M15, 16 changes, and the charge / discharge current of the load capacitor CL increases in a short time. Or decrease. That is, in order to improve the slew rate, it is necessary to shorten the charge / discharge time of the phase compensation capacitors C1 and C2, but such a function is not provided in the conventional circuit configuration.

  Further, as a means for shortening the charge / discharge time of the phase compensation capacitors C1 and C2, there is a method of increasing the steady current of the entire circuit, but there is a problem that power consumption increases.

  Further, as means for shortening the charge / discharge time of the phase compensation capacitors C1 and C2, there is a method of reducing the capacitance values of the phase compensation capacitors C1 and C2, but there is a problem that the stability of the circuit is lost.

  Therefore, an object of the present invention is to provide an operational amplifier capable of improving the slew rate without increasing the current consumption in the steady state of the entire circuit and without causing deterioration of the stability of the circuit. There is to do.

  The present invention includes a P-type differential input unit having a non-inverting input terminal and an inverting input terminal, and an N-type differential input unit having the same non-inverting input terminal and inverting input terminal as the P-type differential input unit, A first N-type current mirror circuit having an input terminal connected to the output terminal of the P-type differential input section, and a first N-type current mirror circuit having an input terminal connected to the output terminal of the N-type differential input section. A P-type current mirror circuit; a P-type output transistor having an input terminal connected to the output terminal of the first P-type current mirror circuit; and an input connected to the output terminal of the first N-type current mirror circuit. A push-pull output stage including an output terminal of the P-type output transistor and an output terminal of the N-type output transistor connected in series; and an input terminal of the P-type output transistor And before A first phase compensation capacitor connected between the output terminal, a second phase compensation capacitor connected between the input terminal and the output terminal of the N-type output transistor, and the P-type differential. A second N-type current mirror circuit having an input terminal connected to an output terminal of a non-inverting input transistor constituting the input unit; and an output terminal of a non-inverting input transistor constituting the N-type differential input unit. A third P-type current mirror circuit having a second P-type current mirror circuit having an input terminal, an input terminal connected to an output terminal of the second N-type current mirror circuit, and two output terminals And a third N-type current mirror circuit having an input terminal connected to the output terminal of the second P-type current mirror circuit, and two output terminals, and the first P-type current mirror circuit of A power terminal, one output terminal of the third P-type current mirror circuit, one output terminal of the third N-type current mirror circuit, and the P-type connected to the first phase compensation capacitor. The input terminal of the output transistor is connected, the output terminal of the first N-type current mirror circuit, the other output terminal of the third P-type current mirror circuit, and the third N-type current mirror circuit Is connected to the input terminal of the N-type output transistor to which the second phase compensation capacitor is connected to form an operational amplifier.

  The present invention includes a P-type differential input unit having a non-inverting input terminal and an inverting input terminal, and an N-type differential input unit having the same non-inverting input terminal and inverting input terminal as the P-type differential input unit, A first N-type current mirror circuit having an input terminal connected to the output terminal of the P-type differential input section, and a first N-type current mirror circuit having an input terminal connected to the output terminal of the N-type differential input section. A P-type current mirror circuit; a P-type output transistor having an input terminal connected to the output terminal of the first P-type current mirror circuit; and an input connected to the output terminal of the first N-type current mirror circuit. A push-pull output stage including an output terminal of the P-type output transistor and an output terminal of the N-type output transistor connected in series; and an input terminal of the P-type output transistor And before A first phase compensation capacitor connected between the output terminal, a second phase compensation capacitor connected between the input terminal and the output terminal of the N-type output transistor, and the P-type differential. A second N-type current mirror circuit having an input terminal connected to the output terminal of the non-inverting input transistor constituting the input unit and an output terminal connected to the input terminal of the first P-type current mirror circuit; A second input terminal connected to the output terminal of the non-inverting input transistor constituting the N-type differential input section, and an output terminal connected to the input terminal of the first N-type current mirror circuit. A P-type current mirror circuit, connecting an output terminal of the first P-type current mirror circuit and the input terminal of the P-type output transistor to which the first phase compensation capacitor is connected; Type 1 N An output terminal of the rent mirror circuit, by the second phase compensating capacitor is connected between the input terminal of the connected the N-type output transistor, it constitutes an operational amplifier.

  The second N-type current mirror circuit detects that the non-inverting input terminal is at a lower potential than the inverting input terminal, and causes a current to flow. The second P-type current mirror circuit includes the non-inverting input terminal. A current may be supplied by detecting that the input terminal is at a higher potential than the inverting input terminal.

  The slew rate may be changed by adjusting the mirror ratio of the second N-type current mirror circuit and the second P-type current mirror circuit.

  The slew rate may be changed by adjusting the mirror ratio of the third N-type current mirror circuit and the third P-type current mirror circuit.

  According to the present invention, the current mirror circuit for detecting the potential difference between the non-inverted input voltage (Vin +) and the inverted input voltage (Vin−) and supplementarily charging / discharging the phase compensation capacitor operates to operate the phase compensation capacitor. Since the charge / discharge time is shortened and the current change of the output transistor is accelerated, the charge / discharge time of the load capacitance is shortened, and the slew rate can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First example]
A first embodiment of the present invention will be described with reference to FIGS.
<Configuration>
FIG. 1 shows a circuit configuration according to the present invention.
A P-type current mirror circuit 6 composed of transistors M17 and M18; an N-type current mirror circuit 7 composed of transistors M19 and M20; a P-type current mirror circuit 8 composed of transistors M21, M22 and M23; The difference is that an N-type current mirror circuit 9 composed of transistors M24, M25, and M26 is added to the circuit of FIG. 6 showing the conventional example.

  In the P-type current mirror circuit 6, the drain of the transistor M 17 whose drain and gate are connected is connected to the drain of the transistor M 5 constituting the N-type differential input unit 1, and the drain of the transistor M 18 is connected to the N-type current mirror circuit 9. It is connected to the drain of the transistor M24 that constitutes it. In the N-type current mirror circuit 9, the drain of the transistor M25 is connected to the phase compensation capacitor C1, and the drain of the transistor M26 is connected to the phase compensation capacitor C2.

  In the N-type current mirror circuit 7, the drain of the transistor M 19 whose drain and gate are connected is connected to the drain of the transistor M 3 constituting the P-type differential input unit 2, and the drain of the transistor M 20 is connected to the P-type current mirror circuit 8. The transistor M21 is connected to the drain of the transistor M21. In the P-type current mirror circuit 8, the drain of the transistor M22 is connected to the phase compensation capacitor C1, and the drain of the transistor M23 is connected to the phase compensation capacitor C2.

  The current flowing through the resistor R1 is Ir1, and the current flowing through the resistor R2 is Ir2. In a steady state where the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) are equal, Ir1 and Ir2 are set to currents smaller than Im1 and Im6. Transistors M17 and M19 are in a cut-off state and do not pass current.

  At this time, the transistors M18, M20, M21, M22, M23, M24, M25, and M26 are in a cut-off state, and no current flows through the P-type current mirror circuits 6 and 8 and the N-type current mirror circuits 7 and 9. Therefore, in a steady state, the currents flowing through the transistors M2 and M3 of the P-type MOS differential input unit 1 are both (Im1) · (1/2) and flow through the transistors M4 and M5 of the N-type MOS differential input unit 2. The currents are both (Im6) · (1/2), and the currents flowing through the transistors M7 and M8 constituting the P-type current mirror circuit 3 are the currents Ir1 and (Im6) · (1/2) flowing through the resistor R1. The current flowing through the transistors M13 and M14 constituting the N-type current mirror circuit 4 is the sum of Ir1 and (Im1) · (1/2), and is the same steady current as the conventional circuit.

<Operation example 1>
When the non-inverting input voltage (Vin +) changes from the steady state to a voltage state higher than the inverting input voltage (Vin−), most of the constant current (Im1) flows through the transistor M2 in the P-type differential input section. Since the current flowing through M13 increases and the current flowing through the transistors M12 and M14 by the current mirror circuit 4 also increases, the current drawn from the phase compensation capacitors C1 and C2 increases. On the other hand, in the N-type differential input portion, the current flowing through the transistor M4 decreases, so the current flowing through the transistor M7 decreases, and the current flowing through the transistor M8 by the current mirror circuit 3 also decreases. Since the current flowing through M8 is smaller than the current flowing through M5, no current flows through the transistor M10, and no charging current flows into the phase compensation capacitors C1 and C2. Since M10 is in the cut-off state, the source potential is lowered, the transistor M17 of the P-type current mirror circuit 6 is turned on, and the difference between the current flowing through M5 and the current flowing through M8 flows through M17. In addition, a current flows through the transistors M18 and M24 by the P-type current mirror circuit 6, and a current flows through the transistors M25 and M26 by the N-type current mirror circuit 9, so that the current drawn from the phase compensation capacitors C1 and C2 increases as compared with the conventional case. . At this time, the gate voltages of the output transistors M15 and M16 drop faster, the current flowing through M15 increases faster, so the charging current to the external load CL also increases faster, and the current flowing through M16 decreases faster. The pull-in current from the external load CL also decreases more quickly. As a result, the external load CL is charged faster and the output voltage Vout increases rapidly, and the slew rate is improved. The slew rate can be changed by adjusting the mirror ratios of the transistors M17 and M18 of the P-type current mirror circuit 6 and the transistors M24, M25 and M26 of the N-type current mirror circuit 9, respectively.

<Operation example 2>
When the non-inverted input voltage (Vin +) changes from the steady state to a voltage state lower than the inverted input voltage (Vin−), most of the constant current (Im6) flows through the transistor M4 in the N-type differential input unit. Since the current flowing through M7 increases and the current flowing through the transistors M8 and M10 also increases due to the current mirror circuit 3, the charging current to the phase compensation capacitors C1 and C2 increases. On the other hand, in the P-type differential input portion, the current flowing through the transistor M2 decreases, so the current flowing through the transistor M13 decreases, and the current flowing through the transistor M14 by the current mirror circuit 4 also decreases. Since the current flowing through M14 is smaller than the current flowing through M3, no current flows through the transistor M12, and no current drawn from the phase compensation capacitors C1 and C2 flows. Since M12 is cut off, the source potential rises, the transistor M19 of the N-type current mirror circuit 7 is turned on, and the difference between the current flowing through M3 and the current flowing through M14 flows through M19. Further, current flows through the transistors M20 and M21 by the N-type current mirror circuit 7, and current flows through the transistors M22 and M23 by the P-type current mirror circuit 8, so that the charging current from the phase compensation capacitors C1 and C2 increases as compared with the conventional case. . At this time, the gate voltages of the output transistors M15 and M16 rise faster, the current flowing through M15 decreases faster, so the charging current to the external load CL also decreases faster, and the current flowing through M16 increases faster. The pull-in current from the external load CL also increases faster, and as a result, the external load CL is discharged faster, the output voltage Vout drops rapidly, and the slew rate is improved. The slew rate can be changed by adjusting the mirror ratios of the transistors M19 and M20 of the N-type current mirror circuit 7 and the transistors M24, M25 and M26 of the P-type current mirror circuit 8, respectively.

<Comparative example>
Each voltage follower was configured using the operational amplifier according to the present invention (Embodiment 1) and the conventional operational amplifier, and their transient analysis was performed.

  FIG. 2 shows gate voltage waveforms of the output transistors M15 and M16 when a square wave is input to a conventional operational amplifier.

  FIG. 3 shows gate voltage waveforms of the output transistors M15 and M16 when a square wave is input to the operational amplifier (Embodiment 1) according to the present invention.

  FIG. 4 is a voltage waveform of the output VOUT when a square wave is input to each operational amplifier. FIG. 4 shows that the rising and falling characteristics are greatly improved by the present invention.

  According to this example, when the voltage follower is configured using the operational amplifier, when the change in the output voltage is slow with respect to the change in the large input voltage, the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) The potential difference increases, the added current mirror circuit is turned on, the phase compensation capacitance is charged / discharged quickly, and the current change of the output transistor is accelerated, so the charge / discharge time of the external load is shortened and the slew rate is increased.

  Further, when the output voltage approaches the target value, the potential difference between the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) becomes small, and the added current mirror circuit is cut off. In other words, the added current mirror circuit flows the charge / discharge current of the phase compensation capacitor only when the potential difference between the non-inverted input voltage (Vin +) and the inverted input voltage (Vin−) is generated, and does not flow the current in a steady state. . Therefore, it is possible to improve the slew rate without increasing the current consumption of the operational amplifier while maintaining the stability.

[Second example]
A second embodiment of the present invention will be described with reference to FIG. In addition, about the same part as the 1st example mentioned above, the description is abbreviate | omitted and the same code | symbol is attached | subjected.

<Configuration>
FIG. 5 shows a circuit configuration according to the present invention.
A difference is that a P-type current mirror circuit 6 composed of transistors M17 and M18 and an N-type current mirror circuit 7 composed of transistors M19 and M20 are added to the circuit of FIG. .

  In the P-type current mirror circuit 6, the drain of the transistor M 17 whose drain and gate are connected is connected to the drain of the transistor M 5 constituting the N-type differential input unit 1, and the drain of the transistor M 18 is connected to the N-type current mirror circuit 4. It is connected to the drain of the transistor M11 that constitutes it.

  In the N-type current mirror circuit 7, the drain of the transistor M 19 whose drain and gate are connected is connected to the drain of the transistor M 3 constituting the P-type differential input unit 2, and the drain of the transistor M 20 is connected to the P-type current mirror circuit 3. The transistor M9 is connected to the drain of the transistor M9.

  The current flowing through the resistor R1 is Ir1, and the current flowing through the resistor R2 is Ir2. In a steady state where the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) are equal, Ir1 and Ir2 are set to currents smaller than Im1 and Im6. Transistors M17 and M19 are in a cut-off state and do not pass current.

  At this time, the transistors M18 and M20 are cut off, and no current flows through the P-type current mirror circuit 6 and the N-type current mirror circuit 7. Therefore, in a steady state, the currents flowing through the transistors M2 and M3 of the P-type MOS differential input unit 1 are both (Im1) · (1/2) and flow through the transistors M4 and M5 of the N-type MOS differential input unit 2. The currents are both (Im6) · (1/2), and the currents flowing through the transistors M7 and M8 constituting the P-type current mirror circuit 3 are the currents Ir1 and (Im6) · (1/2) flowing through the resistor R1. The current flowing through the transistors M13 and M14 constituting the N-type current mirror circuit 4 is the sum of Ir1 and (Im1) · (1/2), and the same steady current as in the conventional circuit flows.

<Operation example 1>
When the non-inverted input voltage (Vin +) changes from the steady state to a voltage state higher than the inverted input voltage (Vin−), most of the constant current (Im1) flows through the transistor M2 in the P-type differential input unit. Since the current flowing through M13 increases and the current flowing through the transistors M12 and M14 also increases by the current mirror circuit 4, the current drawn from the phase compensation capacitors C1 and C2 increases. On the other hand, in the N-type differential input portion, the current flowing through the transistor M4 decreases, so the current flowing through the transistor M7 decreases, and the current flowing through the transistor M8 by the current mirror circuit 3 also decreases. Since the current flowing through M8 is smaller than the current flowing through M5, no current flows through the transistor M10, and no charging current flows into the phase compensation capacitors C1 and C2. Since M10 is in the cut-off state, the source potential is lowered, the transistor M17 of the P-type current mirror circuit 6 is turned on, and the difference between the current flowing through M5 and the current flowing through M8 flows through M17. Further, current flows through the transistors M18, M11, and M13 by the P-type current mirror circuit 6, current flows through the transistors M12 and M14 by the N-type current mirror circuit 4, and the current drawn from the phase compensation capacitors C1 and C2 is larger than in the conventional case. To increase. At this time, the gate voltages of the output transistors M15 and M16 drop faster, the current flowing through M15 increases faster, so the charging current to the external load CL also increases faster, and the current flowing through M16 decreases faster. The current drawn from the external load CL also decreases more quickly. As a result, the external load CL is charged faster and the output voltage Vout rapidly increases, and the slew rate is improved. The slew rate can be changed by adjusting the mirror ratios of the transistors M17 and M18 of the P-type current mirror circuit 6, respectively.

<Operation example 2>
When the non-inverted input voltage (Vin +) changes from the steady state to a voltage state lower than the inverted input voltage (Vin−), most of the constant current (Im6) flows through the transistor M4 in the N-type differential input unit. Since the current flowing through M7 increases and the current flowing through the transistors M8 and M10 also increases due to the current mirror circuit 3, the charging current to the phase compensation capacitors C1 and C2 increases. On the other hand, in the P-type differential input portion, the current flowing through the transistor M2 decreases, so the current flowing through the transistor M13 decreases, and the current flowing through the transistor M14 by the current mirror circuit 4 also decreases. Since the current flowing through M14 is smaller than the current flowing through M3, no current flows through the transistor M12, and no current drawn from the phase compensation capacitors C1 and C2 flows. Since M12 is cut off, the source potential rises, the transistor M19 of the N-type current mirror circuit 7 is turned on, and the difference between the current flowing through M3 and the current flowing through M14 flows through M19. Also, current flows through the transistors M20, M7, and M9 by the N-type current mirror circuit 7, and current flows through the transistors M8 and M10 by the P-type current mirror circuit 3, so that the charging current to the phase compensation capacitors C1 and C2 is higher than before. To increase. At this time, the gate voltages of the output transistors M15 and M16 rise faster, the current flowing through M15 decreases faster, so the charging current to the external load CL also decreases faster, and the current flowing through M16 increases faster. The pull-in current from the external load CL also increases faster, and as a result, the external load CL is discharged faster, the output voltage Vout drops rapidly, and the slew rate is improved. The slew rate can be changed by adjusting the mirror ratios of the transistors M19 and M20 of the N-type current mirror circuit 7, respectively.

  According to the present invention, when the voltage follower is configured using the operational amplifier, when the change in the output voltage is slow with respect to the change in the large input voltage, the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) are changed. The potential difference increases, the added current mirror circuit is turned on, the phase compensation capacitance is charged / discharged quickly, and the current change of the output transistor is accelerated, so the charge / discharge time of the external load is shortened and the slew rate is increased.

  Further, when the output voltage approaches the target value, the potential difference between the non-inverting input voltage (Vin +) and the inverting input voltage (Vin−) becomes small, and the added current mirror circuit is cut off. In other words, the added current mirror circuit flows the charge / discharge current of the phase compensation capacitor only when the potential difference between the non-inverted input voltage (Vin +) and the inverted input voltage (Vin−) is generated, and does not flow the current in a steady state. . Therefore, it is possible to improve the slew rate without increasing the current consumption of the operational amplifier while maintaining the stability.

1 is a circuit diagram illustrating a circuit configuration of an operational amplifier according to a first embodiment of the present invention. It is a wave form diagram which shows the gate voltage waveform of output transistor M15, M16 when a square wave is input into the operational amplifier of a prior art. It is a wave form diagram which shows the gate voltage waveform of the output transistors M15 and M16 when a square wave is input into the operational amplifier of FIG. It is a wave form diagram which shows the voltage waveform of output VOUT when a square wave is input into each operational amplifier. It is a circuit diagram which shows the circuit structure of the operational amplifier which is the 2nd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the conventional operational amplifier.

Explanation of symbols

1 P-type MOS differential input section (P-type differential input section)
2 N-type MOS differential input section (N-type differential input section)
3 Current mirror circuit (first P-type current mirror circuit)
4 Current mirror circuit (first N-type current mirror circuit)
5 Push-pull output stage 6 Current mirror circuit (second P-type current mirror circuit)
7 Current mirror circuit (second N-type current mirror circuit)
8 Current mirror circuit (third P-type current mirror circuit)
9 Current mirror circuit (third N-type current mirror circuit)
(Vin +) Non-inverting input voltage (Vin-) Inverting input voltage (Vout) Output voltage

Claims (5)

A P-type differential input section having a non-inverting input terminal and an inverting input terminal;
An N-type differential input unit having the same non-inverting input terminal and inverting input terminal as the P-type differential input unit;
A first N-type current mirror circuit having an input terminal connected to the output terminal of the P-type differential input unit;
A first P-type current mirror circuit having an input terminal connected to an output terminal of the N-type differential input unit;
A P-type output transistor having an input terminal connected to the output terminal of the first P-type current mirror circuit, and an N-type output transistor having an input terminal connected to the output terminal of the first N-type current mirror circuit A push-pull output stage in which an output terminal of the P-type output transistor and an output terminal of the N-type output transistor are connected in series;
A first phase compensation capacitor connected between the input terminal and the output terminal of the P-type output transistor;
A second phase compensation capacitor connected between the input terminal and the output terminal of the N-type output transistor;
A second N-type current mirror circuit having an input terminal connected to an output terminal of a non-inverting input transistor constituting the P-type differential input unit;
A second P-type current mirror circuit having an input terminal connected to an output terminal of a non-inverting input transistor constituting the N-type differential input unit;
A third P-type current mirror circuit having an input terminal connected to the output terminal of the second N-type current mirror circuit, and two output terminals;
A third N-type current mirror circuit having an input terminal connected to the output terminal of the second P-type current mirror circuit and two output terminals;
An output terminal of the first P-type current mirror circuit; one output terminal of the third P-type current mirror circuit; one output terminal of the third N-type current mirror circuit; Connecting the input terminal of the P-type output transistor to which a phase compensation capacitor is connected;
An output terminal of the first N-type current mirror circuit; another output terminal of the third P-type current mirror circuit; another output terminal of the third N-type current mirror circuit; An operational amplifier, wherein the input terminal of the N-type output transistor to which a phase compensation capacitor is connected is connected. A P-type differential input section having a non-inverting input terminal and an inverting input terminal;
An N-type differential input unit having the same non-inverting input terminal and inverting input terminal as the P-type differential input unit;
A first N-type current mirror circuit having an input terminal connected to the output terminal of the P-type differential input unit;
A first P-type current mirror circuit having an input terminal connected to an output terminal of the N-type differential input unit;
A P-type output transistor having an input terminal connected to the output terminal of the first P-type current mirror circuit, and an N-type output transistor having an input terminal connected to the output terminal of the first N-type current mirror circuit A push-pull output stage in which an output terminal of the P-type output transistor and an output terminal of the N-type output transistor are connected in series;
A first phase compensation capacitor connected between the input terminal and the output terminal of the P-type output transistor;
A second phase compensation capacitor connected between the input terminal and the output terminal of the N-type output transistor;
A second N having an input terminal connected to the output terminal of the non-inverting input transistor constituting the P-type differential input section, and an output terminal connected to the input terminal of the first P-type current mirror circuit. Type current mirror circuit,
A second P having an input terminal connected to the output terminal of the non-inverting input transistor constituting the N-type differential input section, and an output terminal connected to the input terminal of the first N-type current mirror circuit. Type current mirror circuit,
Connecting the output terminal of the first P-type current mirror circuit and the input terminal of the P-type output transistor to which the first phase compensation capacitor is connected;
An operational amplifier comprising: an output terminal of the first N-type current mirror circuit and an input terminal of the N-type output transistor to which the second phase compensation capacitor is connected. The second N-type current mirror circuit detects that the non-inverting input terminal is at a lower potential than the inverting input terminal, and causes a current to flow;
3. The operational amplifier according to claim 1, wherein the second P-type current mirror circuit detects that the non-inverting input terminal is at a higher potential than the inverting input terminal and allows a current to flow. 4.   3. The operational amplifier according to claim 1, wherein the slew rate is changed by adjusting a mirror ratio of the second N-type current mirror circuit and the second P-type current mirror circuit. 2. The operational amplifier according to claim 1, wherein a slew rate is changed by adjusting a mirror ratio of the third N-type current mirror circuit and the third P-type current mirror circuit.

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