WO2023176762A1 - Output circuit display driver, and display device - Google Patents

Output circuit display driver, and display device Download PDF

Info

Publication number
WO2023176762A1
WO2023176762A1 PCT/JP2023/009582 JP2023009582W WO2023176762A1 WO 2023176762 A1 WO2023176762 A1 WO 2023176762A1 JP 2023009582 W JP2023009582 W JP 2023009582W WO 2023176762 A1 WO2023176762 A1 WO 2023176762A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
node
voltage
circuit
signal
Prior art date
Application number
PCT/JP2023/009582
Other languages
French (fr)
Japanese (ja)
Inventor
兼一 椎林
Original Assignee
ラピステクノロジー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ラピステクノロジー株式会社 filed Critical ラピステクノロジー株式会社
Publication of WO2023176762A1 publication Critical patent/WO2023176762A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • the present invention relates to an output circuit that outputs a voltage signal that drives a load, a display driver that includes the output circuit, and a display device.
  • Such a display device is equipped with a display panel in which display cells connected to a plurality of data lines are arranged in a matrix, and a data driver of a semiconductor IC for driving the display panel.
  • the data driver receives a video data signal, generates a gradation voltage having a voltage value corresponding to the brightness level indicated by the video data signal, and amplifies this with an output amplifier and sends an output signal to the data line of the display panel. supply Thereby, the data driver causes the display panel to display an image based on the video data signal.
  • an output amplifier of such a data driver in order to maintain the voltage value of the output signal at the voltage value of the gradation voltage regardless of load fluctuations on the data line, a current corresponding to the difference between the output signal and the gradation voltage is generated.
  • a differential amplifier is used that outputs the signal to the data line (for example, see Patent Document 1).
  • the load capacitance parasitic on the data lines of the display panel that must be driven by the data driver has increased, and the number of loads that the data driver must drive the data lines has increased.
  • the driving period per pixel is shorter.
  • the voltage value of the output signal corresponds to the video data signal.
  • the time it takes to rise (or fall) to the voltage value of the gradation voltage becomes longer.
  • an object of the present invention is to provide an output circuit that can suppress power consumption and realize high-speed output response, and a display driver and display device including the output circuit.
  • An output circuit is an output circuit that receives an input voltage signal, generates a signal obtained by amplifying the input voltage signal as an output voltage signal at an output node, and outputs this from an output terminal.
  • a control voltage generation unit that generates a first control voltage based on the input voltage signal at a first node, and generates a second control voltage based on the input voltage signal at a second node;
  • a P-channel type first output transistor that receives the first control voltage at its gate and sends a first output current corresponding to the first control voltage to the output node;
  • an N-channel type second output transistor that receives the second control voltage at its gate and extracts a second output current corresponding to the second control voltage from the output node; a floating current source connected between the second nodes; and a high-speed system that reduces the voltage at the second node or increases the voltage at the first node in response to fluctuations in the input voltage signal. It has a circuit.
  • the display driver transfers the first to nth (n is an integer of 2 or more) display data pieces representing the brightness level of each pixel based on the video signal to the first to nth (n is an integer of 2 or more) display data pieces, each having a voltage value corresponding to the brightness level.
  • a DA converter that converts the first to nth grayscale voltage signals into the first to nth grayscale voltage signals; and the first to nth output voltage signals obtained by individually amplifying the first to nth grayscale voltage signals to first to nth output circuits that supply the first to nth data lines, and each of the first to nth output circuits outputs a first control voltage based on the gray scale voltage signal to the first to nth output circuits.
  • a control voltage generating section that generates a second control voltage at a second node based on the input voltage signal; a P-channel type first output transistor that receives the first output current at the first control voltage and sends the first output current to the output node according to the first control voltage, and the second control voltage generated at the second node; an N-channel type second output transistor that receives a second output current at its gate and extracts a second output current corresponding to the second control voltage from the output node, and is connected between the first node and the second node. and a high-speed circuit that reduces the voltage at the second node or increases the voltage at the first node in accordance with fluctuations in the grayscale voltage signal.
  • a display device includes a display panel having first to n-th (n is an integer of 2 or more) data lines, each of which has a plurality of pixels, and a display panel that controls the brightness level of each pixel based on a video signal.
  • a DA converter that converts the first to nth display data pieces represented into first to nth gradation voltage signals each having a voltage value corresponding to the luminance level, and the first to nth gradation levels; first to nth output circuits that supply first to nth output voltage signals obtained by individually amplifying voltage signals to the first to nth data lines of the display panel, Each of the first to nth output circuits generates a first control voltage based on the grayscale voltage signal at a first node, and generates a second control voltage based on the input voltage signal at a second node.
  • a control voltage generating section that generates a control voltage at the first node; a channel-type first output transistor; a gate receives the second control voltage generated at the second node; and a second output current corresponding to the second control voltage is extracted from the output node.
  • an N-channel type second output transistor a floating current source connected between the first node and the second node; and a floating current source connected between the first node and the second node; and a speed-up circuit that reduces the voltage or increases the voltage of the first node.
  • the present invention provides an output circuit that generates an output voltage signal obtained by amplifying an input voltage signal by using the following control voltage generation section, an N-channel type output transistor, and a P-channel type output transistor. It is equipped with a circuit.
  • the control voltage generation section generates first and second control voltages based on the input voltage signal, and generates them respectively at first and second nodes connected via the floating current source. Then, the P-channel type output transistor sends a first output current according to the first control voltage to the output node, and the N-channel type output transistor sends a second output current according to the second control voltage. By pulling out from the output node, an output voltage signal is generated at the output node.
  • the speed-up circuit reduces the voltage at the second node or increases the voltage at the first node in response to fluctuations in the input voltage signal.
  • the speed-up circuit reduces the voltage at the second node.
  • the time required for the N-channel type output transistor to transition from the on state to the off state is shortened.
  • the first control voltage decreases sharply, and the P-channel type The output current that the output transistor outputs to the output node increases. Therefore, the time required for the voltage value of the output voltage signal to increase to the voltage value corresponding to the input voltage signal is shortened by the amount that the output current increases.
  • the speed-up circuit increases the voltage at the first node in response to fluctuations in the input voltage signal
  • the time it takes for the P-channel type output transistor to transition from the on state to the off state is shortened.
  • a current is supplied to the second node via the first node and the floating current source, so the second control voltage increases sharply, and the N-channel The output current that the type output transistor draws from the output node increases. Therefore, the time required for the voltage value of the output voltage signal to decrease to the voltage value corresponding to the input voltage signal is shortened by the amount that the output current increases.
  • FIG. 1 is a circuit diagram showing the configuration of an output circuit 100 according to a first embodiment of the present invention.
  • FIG. 3 is a waveform diagram showing the internal operation of the output circuit 100.
  • FIG. 2 is a circuit diagram of the output circuit 100 describing the direction of current flowing in the output circuit 100.
  • FIG. FIG. 3 is a circuit diagram showing the configuration of an output circuit 100A according to a second embodiment of the present invention.
  • FIG. 3 is a waveform diagram showing the internal operation of the output circuit 100A. It is a circuit diagram of the output circuit 100 describing the direction of current flowing in the output circuit 100A.
  • FIG. 7 is a circuit diagram showing the configuration of an output circuit 100B according to a third embodiment of the present invention.
  • 1 is a block diagram showing a schematic configuration of a display device 200 including an output circuit according to the present invention.
  • 2 is a block diagram showing the configuration of a data driver 103 included in a display device 200.
  • FIG. 1 is a circuit diagram showing the configuration of an output circuit 100 according to a first embodiment of the present invention.
  • the output circuit 100 amplifies the input voltage signal VI received at the input terminal TI to generate a signal having a voltage value corresponding to the input voltage signal VI, and outputs the signal as an output voltage signal VO via the output terminal TO.
  • This is a so-called voltage follower operational amplifier circuit that outputs as follows.
  • the output circuit 100 includes transistors N1 to N7 as N-channel MOS (metal oxide semiconductor) transistors, transistors P1 to P8 as P-channel MOS transistors, current sources G1 and G2, floating current sources Gf1 and Gf2, and capacitors. C1, C2, and a high speed circuit BST.
  • MOS metal oxide semiconductor
  • a power supply voltage VDD is applied to the sources of each of transistors P1 and P2, and their gates are connected to each other.
  • the drain of transistor P1 is connected to the source of transistor P3 via node n1.
  • the drain of transistor P2 is connected to the source of transistor P4 via node n2.
  • a common bias voltage VBH is applied to the gates of each of transistors P3 and P4.
  • the drain of the transistor P3 is connected to one end of the floating current source Gf1 and the gates of the transistors P1 and P2 via a node n5.
  • the drain of transistor P4 is connected to one end of floating current source Gf2 via node n6.
  • the transistors P1 to P4 described above constitute a first cascode current mirror circuit, and the drains of transistors P4 and P3, that is, the nodes n6 and n5 are the first terminal and the first terminal of the first cascode current mirror circuit, respectively. There will be 2 terminals.
  • a ground voltage VSS is applied to the sources of each of the transistors N1 and N2, and their gates are connected to each other.
  • the drain of transistor N1 is connected to the source of transistor N3 via node n7.
  • the drain of transistor N2 is connected to the source of transistor N4 via node n8.
  • a common bias voltage VBL is applied to the gates of each of transistors N3 and N4.
  • the drain of the transistor N3 is connected to the other end of the floating current source Gf1 and the gates of the transistors N1 and N2 via a node n9.
  • the drain of transistor N4 is connected to the other end of floating current source Gf2 via node n10.
  • the transistors N1 to N4 described above constitute a second cascode current mirror circuit, and the drains of transistors N4 and N3, that is, nodes n8 and n7, are the first terminal and the terminal of the second cascode current mirror circuit, respectively. There will be 2 terminals.
  • the floating current source Gf1 supplies a predetermined constant current to the second terminal (node n5) of the first cascode current mirror circuit (P1 to P4) and the second terminal of the second cascode current mirror circuit (N1 to N4). It flows between the terminals (node n9).
  • Floating current source Gf2 causes a predetermined constant current to flow between the first terminal (node n6) of the first cascode current mirror circuit and the first terminal (node n10) of the second cascode current mirror circuit.
  • the gate of the transistor N5 is connected to the input terminal TI, and the drain thereof is connected to the node n2.
  • the gate of transistor N6 is connected to output node n0, and the drain thereof is connected to node n1.
  • the sources of transistors N5 and N6 are connected to one end of current source G1.
  • a ground voltage VSS is applied to the other end of the current source G1.
  • a dynamic pair is constructed.
  • the gate of the transistor P5 is connected to the input terminal TI, and the drain thereof is connected to the node n8.
  • the gate of transistor P6 is connected to output node n0, and the drain thereof is connected to node n7.
  • the sources of transistors P5 and P6 are connected to one end of current source G2.
  • a power supply voltage VDD is applied to the other end of the current source G2.
  • These transistors P5, P6 and current source G2 apply a second difference between the current pair corresponding to the difference between the input voltage signal and the output voltage to nodes n8 and n7 in the second cascode current mirror circuit (N1 to N4).
  • a dynamic pair is constructed.
  • capacitor C1 One end of the capacitor C1 is connected to the node n2, and the other end is connected to the output node n0 and one end of the capacitor C2.
  • the other end of capacitor C2 is connected to node n8. Note that these capacitors C1 and C2 are provided as phase compensation capacitors for stabilizing the output of the output circuit 100.
  • the first control voltage generation section including the first differential pair (N5, N6, G1) and the first cascode current mirror circuit (P1 to P4) receives the input voltage generated at the node n6.
  • a voltage based on the difference between voltage signal VI and output voltage FB is output as control voltage PG for controlling transistor P7.
  • a second control voltage generation section including a second differential pair (P5, P6, G2) and a second cascode current mirror circuit (N1 to N4) generates an input voltage signal VI generated at the node n10.
  • a voltage based on the difference between the output voltage FB and the output voltage FB is output as a control voltage NG for controlling the transistor N7.
  • a power supply voltage VDD is applied to the source of the transistor P7, and its gate is connected to the node n6.
  • Ground voltage VSS is applied to the source of transistor N7, and its gate is connected to node n10.
  • the drains of transistors P7 and N7 are connected to output node n0.
  • the transistor P7 supplies an output current corresponding to the voltage PG of the first terminal (node n6) of the first cascode current mirror circuit (P1 to P4) to the output node n0, thereby increasing the output voltage whose voltage value increases. It functions as a first output transistor generated on output node n0. Note that when the transistor P7 stops supplying the output current to the output node n0, the voltage value of the output voltage generated at the output node n0 maintains the state just before that.
  • Transistor N7 outputs an output voltage whose voltage value decreases by pulling out an output current corresponding to voltage NG at the first terminal (node n10) of the second cascode current mirror circuit (N1 to N4) from output node n0. It functions as a second output transistor generated on node n0. Note that when the transistor N7 stops drawing out the output current from the output node n0, the voltage value of the output voltage generated at the output node n0 maintains the state just before that.
  • Transistor P8 receives a binary clock signal CLK1 (logic level 0 or 1), remains on only while the clock signal CLK1 is at logic level 0, and outputs the output voltage of output node n0 as output voltage signal VO. , is output via the output terminal TO. On the other hand, while the clock signal CLK1 is at logic level 1, the transistor P8 is turned off, cutting off the connection between the output node n0 and the output terminal TO. That is, the transistor P8 functions as an output switch that outputs the output voltage generated at the output node n0 as the output voltage signal VO, or stops the output.
  • CLK1 binary clock signal
  • the speed-up circuit BST includes a capacitor Cs, a reset circuit Rs, a transistor Qs as an N-channel MOS transistor, and a current source Gs.
  • One end of the capacitor Cs is connected to the sources of the transistors N5 and N6 via the node n11, and the other end is connected to the gate of the transistor Qs via the node ns.
  • the transistor Qs has its own drain connected to the node n10, and its own source connected to one end of the current source Gs.
  • a ground voltage VSS is applied to the other end of the current source Gs. Note that the transistor Qs is in an off state when the voltage between the node ns connected to its gate and its source is lower than a threshold voltage, and is in an on state when the voltage is equal to or higher than the threshold voltage. It functions as a switching element that lowers the voltage of VSS toward the ground voltage VSS.
  • the reset circuit Rs receives an inverted clock signal XCLK1 obtained by inverting the logic level of the clock signal CLK1 as a reset control signal.
  • the reset circuit Rs sets the gate of the transistor Qs to a voltage that resets the transistor Qs to an off state, for example, the ground voltage VSS.
  • the reset circuit Rs releases the reset state.
  • the reset circuit Rs is an N-channel MOS transistor whose drain is connected to the node ns, whose source is applied with the ground voltage VSS, and whose gate receives the inverted clock signal XCLK1. It is configured.
  • a resistive element or a current source having one end connected to the node ns and the ground voltage VSS applied to the other end may be employed.
  • FIG. 2 shows the internal waveform of the output circuit 100 when the voltage value of the input voltage signal VI received at time t1 increases than the voltage value of the input voltage signal VI received immediately before the time t1.
  • FIG. 3 is a circuit diagram describing the direction of current flowing in the output circuit 100 during the operation shown in FIG. 2.
  • the voltage value of the input voltage signal VI increases at time t1 of the rising edge of the clock signal CLK1 with the period TP.
  • the voltage value of the voltage at output node n0 (output voltage FB) shown in FIG. 3 maintains the value immediately before time t1. That is, immediately after time t1, the voltage value of input voltage signal VI is greater than the voltage value of output voltage FB.
  • the transistor N5 of the first differential pair (N5, N6, G1) has a higher voltage (VI, A current I2 that is larger by an amount corresponding to the difference in FB) is extracted from the node n2 of the first cascode current mirror circuit.
  • the voltage PG at the node n6 of the first cascode current mirror circuit decreases, and the transistor P7 as an output transistor supplies the output current Iout to the output node n0. Therefore, as shown in FIG. 2, the voltage value of the output voltage FB generated at the output node n0 increases after time t1.
  • the transistor P8 is in the off state, so the output voltage FB is sent to the output terminal TO.
  • the voltage value of the output voltage FB gradually increases from time t1 to time t2 when the clock signal CLK1 maintains the state of logic level 1, but the voltage value is not output from the output terminal TO.
  • the voltage value of the output voltage signal VO maintains the voltage Vr before time t1.
  • the reset circuit Rs of the speed-up circuit BST is in the reset state, and by applying a predetermined low voltage (for example, ground voltage VSS) to the node ns, the speed is increased.
  • a predetermined low voltage for example, ground voltage VSS
  • the clock signal CLK1 is at logic level 1, for example from time t1 to t2 shown in FIG. 2, the reset state of the reset circuit Rs is released.
  • the capacitor Cs of the speed-up circuit BST which receives the increasing change in the voltage NTL via the node n11, generates the voltage MON whose voltage value increases in a pulse-like manner as shown in FIG. The signal is supplied to the transistor Qs through the transistor Qs.
  • the N-channel transistor Qs is turned on in response to the high voltage MON between time t1 and time t2.
  • the voltage NG at the node n10 sharply decreases toward the ground voltage VSS, so that the time it takes for the transistor N7 to transition from the on state to the off state is shortened.
  • the current Ib flows through the path shown by the thick broken line in FIG. 3, which includes the node n6, the floating current source Gf2, the node n10, the transistor Qs, and the current source Gs. Therefore, since current Ib is extracted from node n6, the voltage PG at node n6, that is, the gate voltage of transistor P7, sharply decreases, and accordingly, the output current Iout output from transistor P7 to output node n0 increases. Therefore, the time required for the voltage value of the output voltage FB to increase to the voltage value of the input voltage signal VI is reduced by the amount that the output current Iout increases.
  • the output voltage signal is It becomes possible to speed up the rise of VO.
  • FIG. 4 is a circuit diagram showing the configuration of an output circuit 100A according to a second embodiment of the present invention.
  • the output circuit 100A shown in FIG. 4 has the same configuration as that shown in FIG. 1, except that a speed-up circuit BSTA is used instead of the speed-up circuit BST in order to speed up the fall of the input voltage signal VI. is the same as Therefore, only the configuration and operation of the speed-up circuit BSTA will be described below.
  • the speed-up circuit BSTA includes a capacitor CsA, a reset circuit RsA, a transistor QsA as a P-channel MOS transistor, and a current source GsA.
  • the capacitor CsA has one end connected to the sources of the transistors P5 and P6 in the second differential pair (P5, P6) via the node n12, and the other end connected to the gate of the transistor QsA via the node ns. It is connected to the.
  • the transistor QsA has its own drain connected to the node n6, and its own source connected to one end of the current source GsA.
  • a power supply voltage VDD is applied to the other end of the current source GsA.
  • the transistor QsA is in an OFF state when the voltage between the node ns connected to its gate and its source is lower than a threshold voltage, and is in an ON state when the voltage is equal to or higher than the threshold voltage. It functions as a switching element that increases the voltage of VDD toward the power supply voltage VDD.
  • the reset circuit RsA receives the clock signal CLK1 as a reset control signal.
  • the reset circuit RsA sets the gate of the transistor QsA to a voltage that resets the transistor QsA to an off state, for example, the power supply voltage VDD, when the clock signal CLK1 as a reset control signal is at logic level 0.
  • the reset circuit RsA releases its reset state.
  • the reset circuit RsA is composed of a P-channel MOS transistor whose drain is connected to the node ns, whose source is applied with the power supply voltage VDD, and whose gate receives the clock signal CLK1. has been done.
  • a resistive element or a current source having one end connected to the node ns and the power supply voltage VDD applied to the other end may be employed.
  • FIG. 5 shows the internal waveform of the output circuit 100A when the voltage value of the input voltage signal VI received at time t1 becomes lower than the voltage value of the input voltage signal VI received immediately before the time t1.
  • FIG. 6 is a circuit diagram describing the direction of current flowing in the output circuit 100A during the operation shown in FIG. 5.
  • the voltage value of the input voltage signal VI decreases at time t1 of the rising edge of the clock signal CLK1 with the period TP.
  • the voltage value of output voltage FB at output node n0 shown in FIG. 6 maintains the value immediately before time t1. That is, immediately after time t1, the voltage value of input voltage signal VI is smaller than the voltage value of output voltage FB.
  • the transistor P5 of the second differential pair receives both voltages (VI, FB ) is supplied to node n8 of the second cascode current mirror circuit.
  • the voltage NG at the node n10 of the second cascode current mirror circuit increases, and the transistor N7 as an output transistor pulls out the output current Iout from the output node n0. Therefore, as shown in FIG. 5, the voltage value of the output voltage FB generated at the output node n0 decreases after time t1.
  • the reset circuit Rs of the speed-up circuit BSTA is in a reset state, and by applying a predetermined high voltage (for example, power supply voltage VDD) to the node ns, the speed is increased.
  • Transistor QsA of circuit BSTA is forcibly turned off.
  • the reset state of the reset circuit Rs is released.
  • the capacitor CsA of the speed-up circuit BSTA which receives the decreasing change in the voltage NTL via the node n12, generates the voltage MON whose voltage value decreases in a pulse-like manner as shown in FIG. It is supplied to the transistor QsA through the transistor QsA.
  • the P-channel transistor QsA is turned on in response to the low voltage MON between time t1 and time t2.
  • the voltage PG at the node n6 rises steeply toward the power supply voltage VDD, so that the time required for the transistor P7 to transition from the on state to the off state is shortened.
  • a current Ic flows through the path shown by the thick broken line in FIG. 6, which includes the current source GsA, the transistor QsA, the node n6, the floating current source Gf2, and the node n10. Therefore, since the current Ic flows into the node n10, the voltage NG at the node n10, that is, the gate voltage of the transistor N7 increases sharply, and accordingly, the output current Iout drawn from the output node n0 by the transistor N7 increases. Therefore, the time required for the voltage value of the output voltage FB to decrease to the voltage value of the input voltage signal VI is shortened by an amount corresponding to the increase in the output current Iout drawn from the output node n0.
  • the speed-up circuit BSTA the current flowing through the cascode current mirror circuit (P1 to P4, N1 to N4) according to the bias voltage (VBL, VBH) is generated by the current source (G1, G2, Gf1, Gf2). It is possible to speed up the fall of the output voltage signal VO without increasing the amount of current.
  • FIG. 7 is a circuit diagram showing the configuration of an output circuit 100B according to a third embodiment of the present invention. Note that the output circuit 100B shown in FIG. 7 has one end of the capacitor Cs of the high-speed circuit BST connected to the input terminal TI instead of connecting it to the sources of the transistors N5 and N6 of the first differential pair. The other configurations are the same as the output circuit 100 shown in FIG.
  • the input voltage signal VI received at the input terminal TI is supplied to one end of the capacitor Cs of the speed-up circuit BST via the node n13. Even when such a configuration is adopted, as shown in FIG. 2, the transistor Qs of the speed-up circuit BST is turned on in response to the voltage MON generated at the other end of the capacitor Cs when the input voltage signal VI rises.
  • the rise of the output voltage FB is sped up by the speed-up circuit BST.
  • one end of the capacitor CsA included in the speed-up circuit BSTA may be connected to the input terminal TI via the node n12.
  • a current source Gs (GsA) is connected to the source of the transistor Qs (QsA), but a resistance element may be connected instead of the current source, or a resistor element may be connected to the source of the transistor Qs (QsA).
  • the ground voltage VSS power supply voltage VDD may be applied directly to the source.
  • the speed-up circuit BST (BSTA) generates one pulse voltage (MON) in response to the rise or fall of the input voltage signal VI, and uses this pulse voltage to forcibly lower or reduce the voltage at the node n6 or n10.
  • MON pulse voltage
  • any configuration may be used as long as the voltage at the node n6 or n10 is forcibly decreased or increased when a fluctuation in the input voltage signal VI is detected.
  • an output switch (P8) is provided between the output node n0 and the output terminal TO, but instead of using this, the output terminal It is also possible to connect TO.
  • the output circuit (100, 100A, 100B) includes the following control voltage generation section, P-channel type and N-channel type first and second output transistors, floating current source, and high-speed circuit. It is fine as long as it includes.
  • the control voltage generation section (P1 to P6, N1 to N6, G1, G2) generates a first control voltage (PG) based on the input voltage signal (VI) at the first node (n6), A second control voltage (NG) based on the input voltage signal is generated at the second node (n10).
  • the first node (n6) and the second node (n10) are connected via a floating current source (Gf2).
  • the first output transistor (P7) receives a first control voltage (PG) at its gate, sends out a first output current corresponding to the first control voltage to the output node (n0), and outputs a first output current corresponding to the first control voltage to the output node (n0).
  • the output transistor (N7) receives the second control voltage (NG) at its gate and draws a second output current corresponding to the second control voltage from the output node (n0).
  • the speed-up circuit (BST, BSTA) reduces the voltage at the second node (n10) or increases the voltage at the first node (n6) in response to fluctuations in the input voltage signal.
  • FIG. 8 is a block diagram showing a schematic configuration of a display device 200 equipped with a display driver including an output circuit (100, 100A, 100B) according to the present invention.
  • the display device 200 includes a display panel 80, a drive control section 101, a scan driver 102, and a data driver 103.
  • the display panel 80 is made of, for example, a liquid crystal or organic EL panel, and has r horizontal scanning lines S1 to Sr (r is a natural number of 2 or more) extending in the horizontal direction of the two-dimensional screen, and horizontal scanning lines S1 to Sr extending in the vertical direction of the two-dimensional screen.
  • n (n is a natural number of 2 or more) data lines D1 to Dn that extend.
  • a display cell serving as a pixel is formed at each intersection of the horizontal scanning line and the data line.
  • the drive control unit 101 receives the video signal VD, generates a scan timing signal for generating a horizontal scan pulse to be supplied to each horizontal scan line based on the video signal VD, and supplies it to the scan driver 102.
  • the drive control unit 101 generates a video digital signal DVS including various control signals such as a clock signal CLK1 and a series of display data pieces representing the brightness level of each pixel in 8 bits, for example, based on the video signal VD,
  • the data is supplied to the data driver 103.
  • the scan driver 102 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S1 to Sr of the display panel 80 based on the scan timing signal supplied from the drive control unit 101.
  • the data driver 103 takes in a series of display data pieces included in the video digital signal DVS in response to a control signal supplied from the drive control unit 101. Then, the data driver 103 converts the captured display data pieces for each horizontal scanning line (n pieces) into n output voltage signals V1 to Vn having voltage values corresponding to the respective brightness levels. , are supplied to the data lines D1 to Dn of the display panel 80, respectively.
  • FIG. 9 is a block diagram showing the internal configuration of the data driver 103.
  • the data driver 103 is formed on a semiconductor IC chip, and includes a grayscale voltage generation circuit 130, a data acquisition section 131, a DA conversion section 132, and an output section 133.
  • the gradation voltage generation circuit 130 generates gradation voltages X0 to X255 representing different voltage values representing the range of luminance levels that can be expressed by the video signal, for example, in 256 steps, and supplies them to the DA converter 132.
  • the data acquisition unit 131 In synchronization with a clock signal CLK1 having a period of one horizontal scanning period, the data acquisition unit 131 extracts data for one horizontal scanning line from a series of display data pieces included in the video signal DVS every horizontal scanning period. The n display data pieces are sequentially taken in and supplied to the DA converter 132 as display data PD1 to PDn, respectively.
  • the DA converter 132 uses the grayscale voltages X0 to X255 to convert the display data PD1 to PDn into grayscale voltage signals Q1 to Qn each having an analog voltage value. That is, the DA converter 132 selects, for each of the display data PD1 to PDn, a grayscale voltage having a voltage value corresponding to the brightness level indicated by the display data PD from among the grayscale voltages X0 to X255. do. Then, the DA converter 132 obtains grayscale voltage signals Q1 to Qn, each of which has a grayscale voltage selected for each of the display data PD1 to PDw. The DA converter 132 supplies grayscale voltage signals Q1 to Qn to the output unit 133.
  • the output unit 133 outputs output voltage signals V1 to Vn obtained by individually amplifying the grayscale voltage signals Q1 to Qn, and supplies them to the data lines D1 to Dn of the display panel 80, respectively.
  • output section 133 includes output circuits AM1 to AMn each having a configuration shown in FIG. 1, FIG. 4, or FIG. 7.
  • the output circuit AM2 receives the gray scale voltage signal Q2 as the input voltage signal VI at its own input terminal TI, and outputs the output voltage signal VO output from the output terminal VO in accordance with the gray scale voltage signal Q2. It is supplied to the data line D2 of the display panel 80 as a voltage signal V2.
  • output circuits AM1 to AMn each having the configuration shown in FIG. 1, FIG. 4, or FIG. 7 as the output section 133 of the data driver 103, power consumption can be suppressed and the display panel can be driven at high speed. becomes possible.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Amplifiers (AREA)

Abstract

An output circuit according to the present invention comprises: a control voltage generation unit that generates in a first node a first control voltage based on an input voltage signal and generates in a second node a second control voltage based on an input voltage signal; a P channel-type first output transistor that sends to an output node a first output current in accordance with the first control voltage; an N channel-type second output transistor that draws from the output node a second output current in accordance with the second control voltage; a floating current source that is connected between the first node and the second node; and a speed-up circuit that, in accordance with fluctuation in the input voltage signal, decreases the voltage of the second node or increases the voltage of the first node.

Description

出力回路、表示ドライバ及び表示装置Output circuit, display driver and display device
　本発明は、負荷を駆動する電圧信号を出力する出力回路、当該出力回路を含む表示ドライバ及び表示装置に関する。 The present invention relates to an output circuit that outputs a voltage signal that drives a load, a display driver that includes the output circuit, and a display device.
　現在、表示装置として、アクティブマトリクス型の液晶表示装置、或いは有機ＥＬ表示装置等が主流となっている。このような表示装置には、複数のデータ線に接続されている表示セルがマトリクス状に配列された表示パネルと共に、これを駆動する半導体ＩＣのデータドライバが搭載されている。 Currently, active matrix type liquid crystal display devices, organic EL display devices, etc. are the mainstream display devices. Such a display device is equipped with a display panel in which display cells connected to a plurality of data lines are arranged in a matrix, and a data driver of a semiconductor IC for driving the display panel.
　データドライバは、映像データ信号を受け、当該映像データ信号にて示される輝度レベルに対応した電圧値を有する階調電圧を生成し、これを出力アンプで増幅した出力信号を表示パネルのデータ線に供給する。これにより、データドライバは、映像データ信号に基づく画像を表示パネルに表示させる。 The data driver receives a video data signal, generates a gradation voltage having a voltage value corresponding to the brightness level indicated by the video data signal, and amplifies this with an output amplifier and sends an output signal to the data line of the display panel. supply Thereby, the data driver causes the display panel to display an image based on the video data signal.
　尚、このようなデータドライバの出力アンプとして、データ線の負荷変動に拘わらず、出力信号の電圧値を階調電圧の電圧値に維持させるべく、出力信号と諧調電圧との差分に対応した電流をデータ線に出力する差動増幅器が用いられている（例えば特許文献１参照）。 In addition, as an output amplifier of such a data driver, in order to maintain the voltage value of the output signal at the voltage value of the gradation voltage regardless of load fluctuations on the data line, a current corresponding to the difference between the output signal and the gradation voltage is generated. A differential amplifier is used that outputs the signal to the data line (for example, see Patent Document 1).
特開２００７－１８１０２６号公報Japanese Patent Application Publication No. 2007-181026
　ところで、近時、表示パネルの大画面化及び高解像度化に伴い、データドライバが駆動しなければならない表示パネルのデータ線に寄生する負荷容量が増加すると共に、データドライバがデータ線を駆動する１画素あたりの駆動期間が短くなっている。 Incidentally, in recent years, as display panels have become larger and have higher resolutions, the load capacitance parasitic on the data lines of the display panel that must be driven by the data driver has increased, and the number of loads that the data driver must drive the data lines has increased. The driving period per pixel is shorter.
　この際、当該負荷容量の増加によると、出力アンプが階調電圧と出力信号との差分に対応した電流をデータ線に出力開始してから、当該出力信号の電圧値が、映像データ信号に対応した階調電圧の電圧値まで上昇（又は下降）するまでに掛かる時間が長くなる。 At this time, due to the increase in the load capacitance, after the output amplifier starts outputting a current corresponding to the difference between the gradation voltage and the output signal to the data line, the voltage value of the output signal corresponds to the video data signal. The time it takes to rise (or fall) to the voltage value of the gradation voltage becomes longer.
　したがって、表示パネルの大画面化及び高解像度化に伴い１画素あたりの駆動期間が短くなると、その期間内で出力信号の電圧値を映像データ信号に対応した階調電圧の電圧値に至らせることができず、画質劣化を引き起す場合があった。 Therefore, as the drive period per pixel becomes shorter as the display panel becomes larger and has higher resolution, it is difficult to make the voltage value of the output signal reach the voltage value of the gradation voltage corresponding to the video data signal within that period. In some cases, this may cause deterioration in image quality.
　尚、このような問題を解決すべく、出力アンプの内部動作電流を増加することで高速応答を図ることも考えられるが、消費電力の増加を招くという問題が生じる。 In order to solve this problem, it may be possible to achieve a high-speed response by increasing the internal operating current of the output amplifier, but this results in the problem of increased power consumption.
　そこで、本発明は、消費電力を抑えて、高速な出力応答を実現することが可能な出力回路、当該出力回路を含む表示ドライバ及び表示装置を提供することを目的とする。 Therefore, an object of the present invention is to provide an output circuit that can suppress power consumption and realize high-speed output response, and a display driver and display device including the output circuit.
　本発明に係る出力回路は、入力電圧信号を受け、前記入力電圧信号を増幅した信号を出力電圧信号として出力ノードに生成しこれを出力端子から出力する出力回路であって、前記入力電圧信号に基づく第１の制御電圧を第１のノードに生成すると共に、前記入力電圧信号に基づく第２の制御電圧を第２のノードに生成する制御電圧生成部と、前記第１のノードに生成された前記第１の制御電圧をゲートで受け、前記第１の制御電圧に応じた第１の出力電流を前記出力ノードに送出するＰチャネル型の第１の出力トランジスタと、前記第２のノードに生成された前記第２の制御電圧をゲートで受け、前記第２の制御電圧に応じた第２の出力電流を前記出力ノードから引き抜くＮチャネル型の第２の出力トランジスタと、前記第１のノード及び前記第２のノード間に接続されている浮遊電流源と、前記入力電圧信号の変動に応じて、前記第２のノードの電圧を低下させる、又は前記第１のノードの電圧を増加させる高速化回路と、を有する。 An output circuit according to the present invention is an output circuit that receives an input voltage signal, generates a signal obtained by amplifying the input voltage signal as an output voltage signal at an output node, and outputs this from an output terminal. a control voltage generation unit that generates a first control voltage based on the input voltage signal at a first node, and generates a second control voltage based on the input voltage signal at a second node; a P-channel type first output transistor that receives the first control voltage at its gate and sends a first output current corresponding to the first control voltage to the output node; an N-channel type second output transistor that receives the second control voltage at its gate and extracts a second output current corresponding to the second control voltage from the output node; a floating current source connected between the second nodes; and a high-speed system that reduces the voltage at the second node or increases the voltage at the first node in response to fluctuations in the input voltage signal. It has a circuit.
　本発明に係る表示ドライバは、映像信号に基づく各画素の輝度レベルを表す第１～第ｎ（ｎは２以上の整数）の表示データ片を、夫々前記輝度レベルに対応した電圧値を有する第１～第ｎの階調電圧信号に変換するＤＡ変換部と、前記第１～第ｎの階調電圧信号を個別に増幅して得た第１～第ｎの出力電圧信号を表示パネルの第１～第ｎのデータ線に供給する第１～第ｎの出力回路と、を含み、前記第１～第ｎの出力回路の各々は、前記階調電圧信号に基づく第１の制御電圧を第１のノードに生成すると共に、前記入力電圧信号に基づく第２の制御電圧を第２のノードに生成する制御電圧生成部と、前記第１のノードに生成された前記第１の制御電圧をゲートで受け、前記第１の制御電圧に応じた第１の出力電流を出力ノードに送出するＰチャネル型の第１の出力トランジスタと、前記第２のノードに生成された前記第２の制御電圧をゲートで受け、前記第２の制御電圧に応じた第２の出力電流を前記出力ノードから引き抜くＮチャネル型の第２の出力トランジスタと、前記第１のノード及び前記第２のノード間に接続されている浮遊電流源と、前記階調電圧信号の変動に応じて、前記第２のノードの電圧を低下させる、又は前記第１のノードの電圧を増加させる高速化回路と、を有する。 The display driver according to the present invention transfers the first to nth (n is an integer of 2 or more) display data pieces representing the brightness level of each pixel based on the video signal to the first to nth (n is an integer of 2 or more) display data pieces, each having a voltage value corresponding to the brightness level. a DA converter that converts the first to nth grayscale voltage signals into the first to nth grayscale voltage signals; and the first to nth output voltage signals obtained by individually amplifying the first to nth grayscale voltage signals to first to nth output circuits that supply the first to nth data lines, and each of the first to nth output circuits outputs a first control voltage based on the gray scale voltage signal to the first to nth output circuits. a control voltage generating section that generates a second control voltage at a second node based on the input voltage signal; a P-channel type first output transistor that receives the first output current at the first control voltage and sends the first output current to the output node according to the first control voltage, and the second control voltage generated at the second node; an N-channel type second output transistor that receives a second output current at its gate and extracts a second output current corresponding to the second control voltage from the output node, and is connected between the first node and the second node. and a high-speed circuit that reduces the voltage at the second node or increases the voltage at the first node in accordance with fluctuations in the grayscale voltage signal.
　本発明に係る表示装置は、夫々に複数の画素が形成されている第１～第ｎ（ｎは２以上の整数）のデータ線を有する表示パネルと、映像信号に基づく各画素の輝度レベルを表す第１～第ｎの表示データ片を、夫々前記輝度レベルに対応した電圧値を有する第１～第ｎの階調電圧信号に変換するＤＡ変換部と、前記第１～第ｎの階調電圧信号を個別に増幅して得た第１～第ｎの出力電圧信号を前記表示パネルの前記第１～第ｎのデータ線に供給する第１～第ｎの出力回路と、を含み、前記第１～第ｎの出力回路の各々は、前記階調電圧信号に基づく第１の制御電圧を第１のノードに生成すると共に、前記入力電圧信号に基づく第２の制御電圧を第２のノードに生成する制御電圧生成部と、前記第１のノードに生成された前記第１の制御電圧をゲートで受け、前記第１の制御電圧に応じた第１の出力電流を出力ノードに送出するＰチャネル型の第１の出力トランジスタと、前記第２のノードに生成された前記第２の制御電圧をゲートで受け、前記第２の制御電圧に応じた第２の出力電流を前記出力ノードから引き抜くＮチャネル型の第２の出力トランジスタと、前記第１のノード及び前記第２のノード間に接続されている浮遊電流源と、前記階調電圧信号の変動に応じて、前記第２のノードの電圧を低下させる、又は前記第１のノードの電圧を増加させる高速化回路と、を有する。 A display device according to the present invention includes a display panel having first to n-th (n is an integer of 2 or more) data lines, each of which has a plurality of pixels, and a display panel that controls the brightness level of each pixel based on a video signal. a DA converter that converts the first to nth display data pieces represented into first to nth gradation voltage signals each having a voltage value corresponding to the luminance level, and the first to nth gradation levels; first to nth output circuits that supply first to nth output voltage signals obtained by individually amplifying voltage signals to the first to nth data lines of the display panel, Each of the first to nth output circuits generates a first control voltage based on the grayscale voltage signal at a first node, and generates a second control voltage based on the input voltage signal at a second node. a control voltage generating section that generates a control voltage at the first node; a channel-type first output transistor; a gate receives the second control voltage generated at the second node; and a second output current corresponding to the second control voltage is extracted from the output node. an N-channel type second output transistor; a floating current source connected between the first node and the second node; and a floating current source connected between the first node and the second node; and a speed-up circuit that reduces the voltage or increases the voltage of the first node.
　本発明は、以下の制御電圧生成部、Ｎチャネル型の出力トランジスタ及びＰチャネル型の出力トランジスタにより、入力電圧信号を増幅した出力電圧信号を生成する出力回路に、応答速度を高速化する高速化回路を設けたものである。制御電圧生成部は、入力電圧信号に基づく第１及び第２の制御電圧を生成し、夫々を浮遊電流源を介して接続されている第１及び第２のノードに生成する。そして、Ｐチャネル型の出力トランジスタが第１の制御電圧に応じた第１の出力電流を出力ノードに送出すると共にＮチャネル型の出力トランジスタで第２の制御電圧に応じた第２の出力電流を出力ノードから引き抜くことで当該出力ノードに出力電圧信号を生成する。高速化回路は、入力電圧信号の変動に応じて、第２のノードの電圧を低下させる、又は第１のノードの電圧を増加させる
　ここで、高速化回路が第２のノードの電圧を低下させると、Ｎチャネル型の出力トランジスタがオン状態からオフ状態に遷移する時間が短縮される。更に、第２のノードの電圧を低下させることで、第１のノードから浮遊電流源及び第２のノードを介して電流が引き抜かれるので、第１の制御電圧が急峻に低下し、Ｐチャネル型の出力トランジスタが出力ノードに出力する出力電流が増加する。よって、この出力電流が増加した分だけ、出力電圧信号の電圧値が入力電圧信号に対応した電圧値まで増加するのに費やされる時間が短縮される。 The present invention provides an output circuit that generates an output voltage signal obtained by amplifying an input voltage signal by using the following control voltage generation section, an N-channel type output transistor, and a P-channel type output transistor. It is equipped with a circuit. The control voltage generation section generates first and second control voltages based on the input voltage signal, and generates them respectively at first and second nodes connected via the floating current source. Then, the P-channel type output transistor sends a first output current according to the first control voltage to the output node, and the N-channel type output transistor sends a second output current according to the second control voltage. By pulling out from the output node, an output voltage signal is generated at the output node. The speed-up circuit reduces the voltage at the second node or increases the voltage at the first node in response to fluctuations in the input voltage signal. Here, the speed-up circuit reduces the voltage at the second node. As a result, the time required for the N-channel type output transistor to transition from the on state to the off state is shortened. Furthermore, by lowering the voltage at the second node, current is extracted from the first node via the floating current source and the second node, so the first control voltage decreases sharply, and the P-channel type The output current that the output transistor outputs to the output node increases. Therefore, the time required for the voltage value of the output voltage signal to increase to the voltage value corresponding to the input voltage signal is shortened by the amount that the output current increases.
　また、高速化回路が入力電圧信号の変動に応じて第１のノードの電圧を増加させると、Ｐチャネル型の出力トランジスタがオン状態からオフ状態に遷移する時間が短縮される。更に、第１のノードの電圧を増加させることで、第１のノード及び浮遊電流源を介して第２のノードに電流が供給されるので、第２の制御電圧が急峻に増加し、Ｎチャネル型の出力トランジスタが出力ノードから引き抜く出力電流が増加する。よって、かかる出力電流が増加した分だけ、出力電圧信号の電圧値が入力電圧信号に対応した電圧値まで低下するのに費やされる時間が短縮される。 Additionally, when the speed-up circuit increases the voltage at the first node in response to fluctuations in the input voltage signal, the time it takes for the P-channel type output transistor to transition from the on state to the off state is shortened. Furthermore, by increasing the voltage at the first node, a current is supplied to the second node via the first node and the floating current source, so the second control voltage increases sharply, and the N-channel The output current that the type output transistor draws from the output node increases. Therefore, the time required for the voltage value of the output voltage signal to decrease to the voltage value corresponding to the input voltage signal is shortened by the amount that the output current increases.
　よって、本発明によれば、内部動作電流を増加することなく、高速な出力応答を実現することが可能となる。 Therefore, according to the present invention, it is possible to realize a high-speed output response without increasing the internal operating current.
本発明の第１の実施例による出力回路１００の構成を示す回路図である。1 is a circuit diagram showing the configuration of an output circuit 100 according to a first embodiment of the present invention. FIG. 出力回路１００の内部動作を示す波形図である。3 is a waveform diagram showing the internal operation of the output circuit 100. FIG. 出力回路１００内に流れる電流の方向を記述した、出力回路１００の回路図である。2 is a circuit diagram of the output circuit 100 describing the direction of current flowing in the output circuit 100. FIG. 本発明の第２の実施例による出力回路１００Ａの構成を示す回路図である。FIG. 3 is a circuit diagram showing the configuration of an output circuit 100A according to a second embodiment of the present invention. 出力回路１００Ａの内部動作を示す波形図である。FIG. 3 is a waveform diagram showing the internal operation of the output circuit 100A. 出力回路１００Ａ内に流れる電流の方向を記述した、出力回路１００の回路図であるIt is a circuit diagram of the output circuit 100 describing the direction of current flowing in the output circuit 100A. 本発明の第３の実施例による出力回路１００Ｂの構成を示す回路図である。FIG. 7 is a circuit diagram showing the configuration of an output circuit 100B according to a third embodiment of the present invention. 本発明に係る出力回路を含む表示装置２００の概略構成を示すブロック図である。1 is a block diagram showing a schematic configuration of a display device 200 including an output circuit according to the present invention. 表示装置２００に含まれるデータドライバ１０３の構成を示すブロック図である。2 is a block diagram showing the configuration of a data driver 103 included in a display device 200. FIG.
　以下、本発明の実施例について図面を参照しつつ詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　図１は、本発明に係る第１の実施例による出力回路１００の構成を示す回路図である。 FIG. 1 is a circuit diagram showing the configuration of an output circuit 100 according to a first embodiment of the present invention.
　出力回路１００は、入力端子ＴＩで受けた入力電圧信号ＶＩを増幅することで、当該入力電圧信号ＶＩに対応した電圧値を有する信号を生成し、これを出力端子ＴＯを介して出力電圧信号ＶＯとして出力する、いわゆるボルテージフォロワの演算増幅回路である。 The output circuit 100 amplifies the input voltage signal VI received at the input terminal TI to generate a signal having a voltage value corresponding to the input voltage signal VI, and outputs the signal as an output voltage signal VO via the output terminal TO. This is a so-called voltage follower operational amplifier circuit that outputs as follows.
　出力回路１００は、Ｎチャネル型のＭＯＳ（metal oxide semiconductor）トランジスタとしてのトランジスタＮ１～Ｎ７、Ｐチャネル型のＭＯＳトランジスタとしてのトランジスタＰ１～Ｐ８、電流源Ｇ１、Ｇ２、浮遊電流源Ｇｆ１、Ｇｆ２、コンデンサＣ１、Ｃ２、及び高速化回路ＢＳＴを含む。 The output circuit 100 includes transistors N1 to N7 as N-channel MOS (metal oxide semiconductor) transistors, transistors P1 to P8 as P-channel MOS transistors, current sources G1 and G2, floating current sources Gf1 and Gf2, and capacitors. C1, C2, and a high speed circuit BST.
　図１において、トランジスＰ１及びＰ２各々のソースには電源電圧ＶＤＤが印加されており、夫々のゲートが互いに接続されている。トランジスタＰ１のドレインはノードｎ１を介してトランジスタＰ３のソースに接続されている。トランジスタＰ２のドレインはノードｎ２を介してトランジスタＰ４のソースに接続されている。トランジスタＰ３及びＰ４各々のゲートには共通のバイアス電圧ＶＢＨが印加されている。トランジスタＰ３のドレインは、ノードｎ５を介して、浮遊電流源Ｇｆ１の一端と、トランジスタＰ１及びＰ２各々のゲートに接続されている。トランジスタＰ４のドレインは、ノードｎ６を介して浮遊電流源Ｇｆ２の一端に接続されている。 In FIG. 1, a power supply voltage VDD is applied to the sources of each of transistors P1 and P2, and their gates are connected to each other. The drain of transistor P1 is connected to the source of transistor P3 via node n1. The drain of transistor P2 is connected to the source of transistor P4 via node n2. A common bias voltage VBH is applied to the gates of each of transistors P3 and P4. The drain of the transistor P3 is connected to one end of the floating current source Gf1 and the gates of the transistors P1 and P2 via a node n5. The drain of transistor P4 is connected to one end of floating current source Gf2 via node n6.
　上記したトランジスタＰ１～Ｐ４により、第１のカスコードカレントミラー回路を構成しており、トランジスタＰ４及びＰ３各々のドレイン、つまりノードｎ６及びｎ５が夫々、第１のカスコードカレントミラー回路の第１端子及び第２端子となる。 The transistors P1 to P4 described above constitute a first cascode current mirror circuit, and the drains of transistors P4 and P3, that is, the nodes n6 and n5 are the first terminal and the first terminal of the first cascode current mirror circuit, respectively. There will be 2 terminals.
　トランジスＮ１及びＮ２各々のソースには接地電圧ＶＳＳが印加されており、夫々のゲートが互いに接続されている。トランジスタＮ１のドレインはノードｎ７を介してトランジスタＮ３のソースに接続されている。トランジスタＮ２のドレインはノードｎ８を介してトランジスタＮ４のソースに接続されている。トランジスタＮ３及びＮ４各々のゲートには共通のバイアス電圧ＶＢＬが印加されている。トランジスタＮ３のドレインは、ノードｎ９を介して、浮遊電流源Ｇｆ１の他端と、トランジスタＮ１及びＮ２各々のゲートに接続されている。トランジスタＮ４のドレインは、ノードｎ１０を介して浮遊電流源Ｇｆ２の他端に接続されている。 A ground voltage VSS is applied to the sources of each of the transistors N1 and N2, and their gates are connected to each other. The drain of transistor N1 is connected to the source of transistor N3 via node n7. The drain of transistor N2 is connected to the source of transistor N4 via node n8. A common bias voltage VBL is applied to the gates of each of transistors N3 and N4. The drain of the transistor N3 is connected to the other end of the floating current source Gf1 and the gates of the transistors N1 and N2 via a node n9. The drain of transistor N4 is connected to the other end of floating current source Gf2 via node n10.
　上記したトランジスタＮ１～Ｎ４により、第２のカスコードカレントミラー回路を構成しており、トランジスタＮ４及びＮ３各々のドレイン、つまりノードｎ８及びｎ７が夫々、第２のカスコードカレントミラー回路の第１端子及び第２端子となる。 The transistors N1 to N4 described above constitute a second cascode current mirror circuit, and the drains of transistors N4 and N3, that is, nodes n8 and n7, are the first terminal and the terminal of the second cascode current mirror circuit, respectively. There will be 2 terminals.
　また、浮遊電流源Ｇｆ１は、所定の定電流を、第１のカスコードカレントミラー回路（Ｐ１～Ｐ４）の第２端子（ノードｎ５）及び第２のカスコードカレントミラー回路（Ｎ１～Ｎ４）の第２端子（ノードｎ９）間に流す。浮遊電流源Ｇｆ２は、所定の一定電流を、第１のカスコードカレントミラー回路の第１端子（ノードｎ６）及び第２のカスコードカレントミラー回路の第１端子（ノードｎ１０）間に流す。 Furthermore, the floating current source Gf1 supplies a predetermined constant current to the second terminal (node n5) of the first cascode current mirror circuit (P1 to P4) and the second terminal of the second cascode current mirror circuit (N1 to N4). It flows between the terminals (node n9). Floating current source Gf2 causes a predetermined constant current to flow between the first terminal (node n6) of the first cascode current mirror circuit and the first terminal (node n10) of the second cascode current mirror circuit.
　トランジスタＮ５のゲートは入力端子ＴＩに接続されており、そのドレインはノードｎ２に接続されている。トランジスタＮ６のゲートは出力ノードｎ０に接続されており、そのドレインはノードｎ１に接続されている。トランジスタＮ５及びＮ６のソースは電流源Ｇ１の一端に接続されている。当該電流源Ｇ１の他端には接地電圧ＶＳＳが印加されている。 The gate of the transistor N5 is connected to the input terminal TI, and the drain thereof is connected to the node n2. The gate of transistor N6 is connected to output node n0, and the drain thereof is connected to node n1. The sources of transistors N5 and N6 are connected to one end of current source G1. A ground voltage VSS is applied to the other end of the current source G1.
　これらトランジスタＮ５、Ｎ６及び電流源Ｇ１により、入力電圧信号と出力電圧との差分に対応した電流対を第１のカスコードカレントミラー回路（Ｐ１～Ｐ４）内のノードｎ２及びｎ１から引き抜く第１の差動対が構成される。 A first difference in which a current pair corresponding to the difference between the input voltage signal and the output voltage is extracted from nodes n2 and n1 in the first cascode current mirror circuit (P1 to P4) by these transistors N5, N6 and current source G1. A dynamic pair is constructed.
　トランジスタＰ５のゲートは入力端子ＴＩに接続されており、そのドレインはノードｎ８に接続されている。トランジスタＰ６のゲートは出力ノードｎ０に接続されており、そのドレインはノードｎ７に接続されている。トランジスタＰ５及びＰ６のソースは電流源Ｇ２の一端に接続されている。当該電流源Ｇ２の他端には電源電圧ＶＤＤが印加されている。 The gate of the transistor P5 is connected to the input terminal TI, and the drain thereof is connected to the node n8. The gate of transistor P6 is connected to output node n0, and the drain thereof is connected to node n7. The sources of transistors P5 and P6 are connected to one end of current source G2. A power supply voltage VDD is applied to the other end of the current source G2.
　これらトランジスタＰ５、Ｐ６及び電流源Ｇ２により、入力電圧信号と出力電圧との差分に対応した電流対を第２のカスコードカレントミラー回路（Ｎ１～Ｎ４）内のノードｎ８及びｎ７に加える第２の差動対が構成される。 These transistors P5, P6 and current source G2 apply a second difference between the current pair corresponding to the difference between the input voltage signal and the output voltage to nodes n8 and n7 in the second cascode current mirror circuit (N1 to N4). A dynamic pair is constructed.
　コンデンサＣ１は、自身の一端がノードｎ２に接続されており、他端が出力ノードｎ０及びコンデンサＣ２の一端に接続されている。コンデンサＣ２の他端はノードｎ８に接続されている。尚、これらコンデンサＣ１及びＣ２は、出力回路１００の出力安定化を図る位相補償用のコンデンサとして設けられている。 One end of the capacitor C1 is connected to the node n2, and the other end is connected to the output node n0 and one end of the capacitor C2. The other end of capacitor C2 is connected to node n8. Note that these capacitors C1 and C2 are provided as phase compensation capacitors for stabilizing the output of the output circuit 100.
　上記した構成により、第１の差動対（Ｎ５、Ｎ６、Ｇ１）及び第１のカスコードカレントミラー回路（Ｐ１～Ｐ４）を含む第１の制御電圧生成部は、ノードｎ６に生成された、入力電圧信号ＶＩと出力電圧ＦＢとの差分に基づく電圧を、トランジスタＰ７を制御する制御電圧ＰＧとして出力する。また、第２の差動対（Ｐ５、Ｐ６、Ｇ２）及び第２のカスコードカレントミラー回路（Ｎ１～Ｎ４）を含む第２の制御電圧生成部は、ノードｎ１０に生成された、入力電圧信号ＶＩと出力電圧ＦＢとの差分に基づく電圧を、トランジスタＮ７を制御する制御電圧ＮＧとして出力する。 With the above-described configuration, the first control voltage generation section including the first differential pair (N5, N6, G1) and the first cascode current mirror circuit (P1 to P4) receives the input voltage generated at the node n6. A voltage based on the difference between voltage signal VI and output voltage FB is output as control voltage PG for controlling transistor P7. Further, a second control voltage generation section including a second differential pair (P5, P6, G2) and a second cascode current mirror circuit (N1 to N4) generates an input voltage signal VI generated at the node n10. A voltage based on the difference between the output voltage FB and the output voltage FB is output as a control voltage NG for controlling the transistor N7.
　トランジスタＰ７のソースには電源電圧ＶＤＤが印加されており、そのゲートはノードｎ６に接続されている。トランジスタＮ７のソースには接地電圧ＶＳＳが印加されており、そのゲートはノードｎ１０に接続されている。トランジスタＰ７及びＮ７のドレインは出力ノードｎ０に接続されている。 A power supply voltage VDD is applied to the source of the transistor P7, and its gate is connected to the node n6. Ground voltage VSS is applied to the source of transistor N7, and its gate is connected to node n10. The drains of transistors P7 and N7 are connected to output node n0.
　トランジスタＰ７は、第１のカスコードカレントミラー回路（Ｐ１～Ｐ４）の第１端子（ノードｎ６）の電圧ＰＧに対応した出力電流を出力ノードｎ０に供給することで、電圧値が上昇する出力電圧を出力ノードｎ０上に生成する第１の出力トランジスタとして機能する。尚、トランジスタＰ７が出力ノードｎ０への出力電流の供給を停止すると、出力ノードｎ０に生成された出力電圧の電圧値は、その直前までの状態を維持する。 The transistor P7 supplies an output current corresponding to the voltage PG of the first terminal (node n6) of the first cascode current mirror circuit (P1 to P4) to the output node n0, thereby increasing the output voltage whose voltage value increases. It functions as a first output transistor generated on output node n0. Note that when the transistor P7 stops supplying the output current to the output node n0, the voltage value of the output voltage generated at the output node n0 maintains the state just before that.
　トランジスタＮ７は、第２のカスコードカレントミラー回路（Ｎ１～Ｎ４）の第１端子（ノードｎ１０）の電圧ＮＧに対応した出力電流を出力ノードｎ０から引き抜くことで、電圧値が下降する出力電圧を出力ノードｎ０上に生成する第２の出力トランジスタとして機能する。尚、トランジスタＮ７が出力ノードｎ０からの出力電流の引き抜きを停止すると、出力ノードｎ０に生成された出力電圧の電圧値は、その直前までの状態を維持する。 Transistor N7 outputs an output voltage whose voltage value decreases by pulling out an output current corresponding to voltage NG at the first terminal (node n10) of the second cascode current mirror circuit (N1 to N4) from output node n0. It functions as a second output transistor generated on node n0. Note that when the transistor N7 stops drawing out the output current from the output node n0, the voltage value of the output voltage generated at the output node n0 maintains the state just before that.
　トランジスタＰ８は、２値（論理レベル０又は１）のクロック信号ＣＬＫ１を受け、当該クロック信号ＣＬＫ１が論理レベル０となっている間だけオン状態となり、出力ノードｎ０の出力電圧を出力電圧信号ＶＯとして、出力端子ＴＯを介して出力する。一方、クロック信号ＣＬＫ１が論理レベル１となっている間は、トランジスタＰ８はオフ状態となり、出力ノードｎ０及び出力端子ＴＯ間の接続を遮断する。すなわち、トランジスタＰ８は、出力ノードｎ０に生成された出力電圧を出力電圧信号ＶＯとして出力する、或いは出力を停止する出力スイッチとして機能する。 Transistor P8 receives a binary clock signal CLK1 (logic level 0 or 1), remains on only while the clock signal CLK1 is at logic level 0, and outputs the output voltage of output node n0 as output voltage signal VO. , is output via the output terminal TO. On the other hand, while the clock signal CLK1 is at logic level 1, the transistor P8 is turned off, cutting off the connection between the output node n0 and the output terminal TO. That is, the transistor P8 functions as an output switch that outputs the output voltage generated at the output node n0 as the output voltage signal VO, or stops the output.
　高速化回路ＢＳＴは、コンデンサＣｓ、リセット回路Ｒｓ、Ｎチャネル型のＭＯＳトランジスタとしてのトランジスタＱｓ及び電流源Ｇｓを含む。 The speed-up circuit BST includes a capacitor Cs, a reset circuit Rs, a transistor Qs as an N-channel MOS transistor, and a current source Gs.
　コンデンサＣｓは、自身の一端がノードｎ１１を介してトランジスタＮ５及びＮ６のソースに接続されており、他端がノードｎｓを介してトランジスタＱｓのゲートに接続されている。 One end of the capacitor Cs is connected to the sources of the transistors N5 and N6 via the node n11, and the other end is connected to the gate of the transistor Qs via the node ns.
　トランジスタＱｓは、自身のドレインがノードｎ１０に接続されており、自身のソースが電流源Ｇｓの一端に接続されている。電流源Ｇｓの他端には接地電圧ＶＳＳが印加されている。尚、トランジスタＱｓは、自身のゲートに接続されているノードｎｓ及び自身のソース間の電圧が閾値電圧より低い場合にはオフ状態、当該閾値電圧以上である場合にはオン状態となってノードｎｓの電圧を接地電圧ＶＳＳに向けて低下させるスイッチ素子として機能する。 The transistor Qs has its own drain connected to the node n10, and its own source connected to one end of the current source Gs. A ground voltage VSS is applied to the other end of the current source Gs. Note that the transistor Qs is in an off state when the voltage between the node ns connected to its gate and its source is lower than a threshold voltage, and is in an on state when the voltage is equal to or higher than the threshold voltage. It functions as a switching element that lowers the voltage of VSS toward the ground voltage VSS.
　リセット回路Ｒｓは、クロック信号ＣＬＫ１の論理レベルを反転させた反転クロック信号ＸＣＬＫ１をリセット制御信号として受ける。リセット回路Ｒｓは、リセット制御信号としての反転クロック信号ＸＣＬＫが論理レベル１である場合に、トランジスタＱｓのゲートを、当該トランジスタＱｓをオフ状態にリセットする電圧、例えば接地電圧ＶＳＳに設定する。一方、反転クロック信号ＸＣＬＫ１が論理レベル０である場合には、リセット回路Ｒｓは、リセット状態を解除する。 The reset circuit Rs receives an inverted clock signal XCLK1 obtained by inverting the logic level of the clock signal CLK1 as a reset control signal. When the inverted clock signal XCLK as a reset control signal is at logic level 1, the reset circuit Rs sets the gate of the transistor Qs to a voltage that resets the transistor Qs to an off state, for example, the ground voltage VSS. On the other hand, when the inverted clock signal XCLK1 is at logic level 0, the reset circuit Rs releases the reset state.
　例えば、リセット回路Ｒｓは、図１に示すように、ドレインがノードｎｓに接続されており、ソースに接地電圧ＶＳＳが印加されており、ゲートで反転クロック信号ＸＣＬＫ１を受けるＮチャネル型のＭＯＳトランジスタで構成されている。 For example, as shown in FIG. 1, the reset circuit Rs is an N-channel MOS transistor whose drain is connected to the node ns, whose source is applied with the ground voltage VSS, and whose gate receives the inverted clock signal XCLK1. It is configured.
　尚、リセット回路Ｒｓに代えて、ノードｎｓに一端が接続されており他端に接地電圧ＶＳＳが印加されている抵抗素子又は電流源を採用しても良い。 Incidentally, instead of the reset circuit Rs, a resistive element or a current source having one end connected to the node ns and the ground voltage VSS applied to the other end may be employed.
　以下に、図１に示す高速化回路ＢＳＴを中心に、出力回路１００の内部動作について図２及び図３に示す一例をもって説明する。 Hereinafter, the internal operation of the output circuit 100 will be described with reference to examples shown in FIGS. 2 and 3, focusing on the high-speed circuit BST shown in FIG. 1.
　尚、図２は、時点ｔ１で受けた入力電圧信号ＶＩの電圧値が、当該時点ｔ１の直前まで受けていた入力電圧信号ＶＩの電圧値よりも増加した場合における、出力回路１００の内部の波形を示す波形図である。また、図３は、図２に示す動作時に出力回路１００内に流れる電流の方向を記述した回路図である。 Note that FIG. 2 shows the internal waveform of the output circuit 100 when the voltage value of the input voltage signal VI received at time t1 increases than the voltage value of the input voltage signal VI received immediately before the time t1. FIG. Further, FIG. 3 is a circuit diagram describing the direction of current flowing in the output circuit 100 during the operation shown in FIG. 2.
　先ず、図２に示すように、周期ＴＰのクロック信号ＣＬＫ１の立ち上がりエッジの時点ｔ１で入力電圧信号ＶＩの電圧値が増加する。この際、時点ｔ１の直後の段階では、図３に示す出力ノードｎ０の電圧（出力電圧ＦＢ）の電圧値は、時点ｔ１直前の値を維持している。つまり、時点ｔ１の直後は、入力電圧信号ＶＩの電圧値は出力電圧ＦＢの電圧値よりも大きい。 First, as shown in FIG. 2, the voltage value of the input voltage signal VI increases at time t1 of the rising edge of the clock signal CLK1 with the period TP. At this time, at a stage immediately after time t1, the voltage value of the voltage at output node n0 (output voltage FB) shown in FIG. 3 maintains the value immediately before time t1. That is, immediately after time t1, the voltage value of input voltage signal VI is greater than the voltage value of output voltage FB.
　よって、第１の差動対（Ｎ５、Ｎ６、Ｇ１）のトランジスタＮ５は、トランジスタＮ６が第１のカスコードカレントミラー回路（Ｐ１～Ｐ４）のノードｎ１から引き抜く電流Ｉ１よりも、両電圧（ＶＩ、ＦＢ）の差分に対応した分だけ大なる電流Ｉ２を、第１のカスコードカレントミラー回路のノードｎ２から引き抜く。 Therefore, the transistor N5 of the first differential pair (N5, N6, G1) has a higher voltage (VI, A current I2 that is larger by an amount corresponding to the difference in FB) is extracted from the node n2 of the first cascode current mirror circuit.
　これにより、第１のカスコードカレントミラー回路（Ｐ１～Ｐ４）のノードｎ６の電圧ＰＧが低下し、出力トランジスタとしてのトランジスタＰ７が出力電流Ｉｏｕｔを出力ノードｎ０に供給する。したがって、図２に示すように、時点ｔ１以降、出力ノードｎ０に生じる出力電圧ＦＢの電圧値が上昇する。 As a result, the voltage PG at the node n6 of the first cascode current mirror circuit (P1 to P4) decreases, and the transistor P7 as an output transistor supplies the output current Iout to the output node n0. Therefore, as shown in FIG. 2, the voltage value of the output voltage FB generated at the output node n0 increases after time t1.
　尚、図１に示す構成では、クロック信号ＣＬＫ１が論理レベル１となっている間は、図２に示すように、トランジスタＰ８はオフ状態であるため、出力電圧ＦＢが出力端子ＴＯに送出されることはない。よって、図２に示すように、クロック信号ＣＬＫ１が論理レベル１の状態を維持する時点ｔ１から時点ｔ２の間に亘り、出力電圧ＦＢの電圧値は徐々に上昇するものの、出力端子ＴＯから出力される出力電圧信号ＶＯの電圧値は、時点ｔ１以前の電圧Ｖｒを維持する。 Note that in the configuration shown in FIG. 1, while the clock signal CLK1 is at logic level 1, as shown in FIG. 2, the transistor P8 is in the off state, so the output voltage FB is sent to the output terminal TO. Never. Therefore, as shown in FIG. 2, the voltage value of the output voltage FB gradually increases from time t1 to time t2 when the clock signal CLK1 maintains the state of logic level 1, but the voltage value is not output from the output terminal TO. The voltage value of the output voltage signal VO maintains the voltage Vr before time t1.
　また、クロック信号ＣＬＫ１が論理レベル０となっている間は、高速化回路ＢＳＴのリセット回路Ｒｓがリセット状態となり、所定の低電圧（例えば接地電圧ＶＳＳ）をノードｎｓに印加することで、高速化回路ＢＳＴのトランジスタＱｓを強制的にオフ状態にする。一方、クロック信号ＣＬＫ１が論理レベル１となっている間、例えば図２に示す時点ｔ１～ｔ２の間は、上記したリセット回路Ｒｓのリセット状態が解除される。 Furthermore, while the clock signal CLK1 is at logic level 0, the reset circuit Rs of the speed-up circuit BST is in the reset state, and by applying a predetermined low voltage (for example, ground voltage VSS) to the node ns, the speed is increased. The transistor Qs of the circuit BST is forcibly turned off. On the other hand, while the clock signal CLK1 is at logic level 1, for example from time t1 to t2 shown in FIG. 2, the reset state of the reset circuit Rs is released.
　更に、図２に示すように、入力電圧信号ＶＩの電圧値の増加に追従して、第１の差動対（Ｎ５、Ｎ６、Ｇ１）のノードｎ１１の電圧ＮＴＬも増加する。よって、電圧ＮＴＬの増加変化をノードｎ１１を介して受けた、高速化回路ＢＳＴのコンデンサＣｓは、図２に示すようにパルス状に電圧値が増加する電圧ＭＯＮを生成し、これをノードｎｓを介してトランジスタＱｓに供給する。 Further, as shown in FIG. 2, following the increase in the voltage value of the input voltage signal VI, the voltage NTL at the node n11 of the first differential pair (N5, N6, G1) also increases. Therefore, the capacitor Cs of the speed-up circuit BST, which receives the increasing change in the voltage NTL via the node n11, generates the voltage MON whose voltage value increases in a pulse-like manner as shown in FIG. The signal is supplied to the transistor Qs through the transistor Qs.
　これにより、時点ｔ１～時点ｔ２の間において高電圧の電圧ＭＯＮに応じて、Ｎチャネル型のトランジスタＱｓがオン状態となる。この際、トランジスタＱｓがオン状態になることで、ノードｎ１０の電圧ＮＧが接地電圧ＶＳＳに向けて急峻に低下するので、トランジスタＮ７がオン状態からオフ状態に遷移する時間が短縮される。 As a result, the N-channel transistor Qs is turned on in response to the high voltage MON between time t1 and time t2. At this time, by turning on the transistor Qs, the voltage NG at the node n10 sharply decreases toward the ground voltage VSS, so that the time it takes for the transistor N7 to transition from the on state to the off state is shortened.
　更に、トランジスタＱｓがオン状態になることで、図３の太線破線にて示される、ノードｎ６、浮遊電流源Ｇｆ２、ノードｎ１０、トランジスタＱｓ及び電流源Ｇｓからなる経路に電流Ｉｂが流れる。よって、ノードｎ６から電流Ｉｂが引き抜かれるので、当該ノードｎ６の電圧ＰＧ、つまりトランジスタＰ７のゲート電圧が急峻に低下し、それに伴い、トランジスタＰ７が出力ノードｎ０に出力する出力電流Ｉｏｕｔが増加する。したがって、出力電流Ｉｏｕｔが増加した分だけ、出力電圧ＦＢの電圧値が入力電圧信号ＶＩの電圧値まで増加するのに費やされる時間が短縮される。 Further, when the transistor Qs is turned on, the current Ib flows through the path shown by the thick broken line in FIG. 3, which includes the node n6, the floating current source Gf2, the node n10, the transistor Qs, and the current source Gs. Therefore, since current Ib is extracted from node n6, the voltage PG at node n6, that is, the gate voltage of transistor P7, sharply decreases, and accordingly, the output current Iout output from transistor P7 to output node n0 increases. Therefore, the time required for the voltage value of the output voltage FB to increase to the voltage value of the input voltage signal VI is reduced by the amount that the output current Iout increases.
　そして、図２に示すように、時点ｔ２以降の論理レベル０のクロック信号ＣＬＫ１に応じて、出力スイッチとしてのトランジスタＰ８がオン状態となり、出力ノードｎ０と出力端子ＴＯとが接続される。よって、時点ｔ２の直後から、出力ノードｎ０に生成された出力電圧ＦＢにより出力端子ＴＯ及び当該出力端子ＴＯに接続されている負荷（図示せず）が充電される。これにより、出力端子ＴＯから出力される出力電圧信号ＶＯの電圧値が図２に示すように増加し、直ちに、入力電圧信号ＶＩの電圧値に対応した電圧値ＶＰＲに到達する。 Then, as shown in FIG. 2, in response to the clock signal CLK1 of logic level 0 after time t2, the transistor P8 as an output switch is turned on, and the output node n0 and the output terminal TO are connected. Therefore, immediately after time t2, the output terminal TO and the load (not shown) connected to the output terminal TO are charged by the output voltage FB generated at the output node n0. As a result, the voltage value of the output voltage signal VO output from the output terminal TO increases as shown in FIG. 2, and immediately reaches the voltage value VPR corresponding to the voltage value of the input voltage signal VI.
　このように、高速化回路ＢＳＴによれば、カスコードカレントミラー回路（Ｐ１～Ｐ４、Ｎ１～Ｎ４）や電流源（Ｇ１、Ｇ２、Ｇｆ１、Ｇｆ２）で流す内部動作電流を増やすことなく、出力電圧信号ＶＯの立ち上がりを高速化することが可能となる。 In this way, according to the high-speed circuit BST, the output voltage signal is It becomes possible to speed up the rise of VO.
　図４は、本発明に係る第２の実施例による出力回路１００Ａの構成を示す回路図である。 FIG. 4 is a circuit diagram showing the configuration of an output circuit 100A according to a second embodiment of the present invention.
　尚、図４に示す出力回路１００Ａは、入力電圧信号ＶＩの立下りを高速化すべく、高速化回路ＢＳＴに代えて高速化回路ＢＳＴＡを採用した点を除く他の構成は図１に示されるものと同一である。よって、以下に、高速化回路ＢＳＴＡの構成及びその動作のみを説明する。 The output circuit 100A shown in FIG. 4 has the same configuration as that shown in FIG. 1, except that a speed-up circuit BSTA is used instead of the speed-up circuit BST in order to speed up the fall of the input voltage signal VI. is the same as Therefore, only the configuration and operation of the speed-up circuit BSTA will be described below.
　高速化回路ＢＳＴＡは、コンデンサＣｓＡ、リセット回路ＲｓＡ、Ｐチャネル型のＭＯＳトランジスタとしてのトランジスタＱｓＡ及び電流源ＧｓＡを含む。 The speed-up circuit BSTA includes a capacitor CsA, a reset circuit RsA, a transistor QsA as a P-channel MOS transistor, and a current source GsA.
　コンデンサＣｓＡは、自身の一端がノードｎ１２を介して、第２の差動対（Ｐ５、Ｐ６）におけるトランジスタＰ５及びＰ６のソースに接続されており、他端がノードｎｓを介してトランジスタＱｓＡのゲートに接続されている。 The capacitor CsA has one end connected to the sources of the transistors P5 and P6 in the second differential pair (P5, P6) via the node n12, and the other end connected to the gate of the transistor QsA via the node ns. It is connected to the.
　トランジスタＱｓＡは、自身のドレインがノードｎ６に接続されており、自身のソースが電流源ＧｓＡ一端に接続されている。電流源ＧｓＡの他端には電源電圧ＶＤＤが印加されている。尚、トランジスタＱｓＡは、自身のゲートに接続されているノードｎｓ及び自身のソース間の電圧が閾値電圧より低い場合にはオフ状態、当該閾値電圧以上である場合にはオン状態となってノードｎｓの電圧を電源電圧ＶＤＤに向けて増加するスイッチ素子として機能する。 The transistor QsA has its own drain connected to the node n6, and its own source connected to one end of the current source GsA. A power supply voltage VDD is applied to the other end of the current source GsA. Note that the transistor QsA is in an OFF state when the voltage between the node ns connected to its gate and its source is lower than a threshold voltage, and is in an ON state when the voltage is equal to or higher than the threshold voltage. It functions as a switching element that increases the voltage of VDD toward the power supply voltage VDD.
　リセット回路ＲｓＡは、クロック信号ＣＬＫ１をリセット制御信号として受ける。リセット回路ＲｓＡは、リセット制御信号としてのクロック信号ＣＬＫ１が論理レベル０である場合に、トランジスタＱｓＡのゲートを、当該トランジスタＱｓＡをオフ状態にリセットする電圧、例えば電源電圧ＶＤＤに設定する。一方、クロック信号ＣＬＫ１が論理レベル１である場合には、リセット回路ＲｓＡは、そのリセット状態を解除する。　 The reset circuit RsA receives the clock signal CLK1 as a reset control signal. The reset circuit RsA sets the gate of the transistor QsA to a voltage that resets the transistor QsA to an off state, for example, the power supply voltage VDD, when the clock signal CLK1 as a reset control signal is at logic level 0. On the other hand, when the clock signal CLK1 is at logic level 1, the reset circuit RsA releases its reset state.　
　例えば、リセット回路ＲｓＡは、図４に示すように、ドレインがノードｎｓに接続されており、ソースに電源電圧ＶＤＤが印加されており、ゲートでクロック信号ＣＬＫ１を受けるＰチャネル型のＭＯＳトランジスタで構成されている。 For example, as shown in FIG. 4, the reset circuit RsA is composed of a P-channel MOS transistor whose drain is connected to the node ns, whose source is applied with the power supply voltage VDD, and whose gate receives the clock signal CLK1. has been done.
　尚、リセット回路ＲｓＡに代えて、ノードｎｓに一端が接続されており他端に電源電圧ＶＤＤが印加されている抵抗素子又は電流源を採用しても良い。 Incidentally, instead of the reset circuit RsA, a resistive element or a current source having one end connected to the node ns and the power supply voltage VDD applied to the other end may be employed.
　以下に、図４に示す高速化回路ＢＳＴＡを中心に、出力回路１００Ａの動作について図５及び図６に示す一例をもって説明する。 Hereinafter, the operation of the output circuit 100A will be described with reference to examples shown in FIGS. 5 and 6, focusing on the high-speed circuit BSTA shown in FIG. 4.
　尚、図５は、時点ｔ１で受けた入力電圧信号ＶＩの電圧値が、当該時点ｔ１の直前まで受けていた入力電圧信号ＶＩの電圧値よりも低下した場合における、出力回路１００Ａの内部の波形を示す波形図である。また、図６は、図５に示す動作時に出力回路１００Ａ内に流れる電流の方向を記述した回路図である。 Note that FIG. 5 shows the internal waveform of the output circuit 100A when the voltage value of the input voltage signal VI received at time t1 becomes lower than the voltage value of the input voltage signal VI received immediately before the time t1. FIG. Further, FIG. 6 is a circuit diagram describing the direction of current flowing in the output circuit 100A during the operation shown in FIG. 5.
　先ず、図５に示すように、周期ＴＰのクロック信号ＣＬＫ１の立ち上がりエッジの時点ｔ１で入力電圧信号ＶＩの電圧値が低下する。この際、時点ｔ１の直後の段階では、図６に示す出力ノードｎ０の出力電圧ＦＢの電圧値は、時点ｔ１直前の値を維持している。つまり、時点ｔ１の直後は、入力電圧信号ＶＩの電圧値は出力電圧ＦＢの電圧値よりも小さい。 First, as shown in FIG. 5, the voltage value of the input voltage signal VI decreases at time t1 of the rising edge of the clock signal CLK1 with the period TP. At this time, at a stage immediately after time t1, the voltage value of output voltage FB at output node n0 shown in FIG. 6 maintains the value immediately before time t1. That is, immediately after time t1, the voltage value of input voltage signal VI is smaller than the voltage value of output voltage FB.
　よって、第２の差動対（Ｐ５、Ｐ６）のトランジスタＰ５は、トランジスタＰ６が第２のカスコードカレントミラー回路（Ｎ１～Ｎ４）のノードｎ７に供給する電流Ｉ１よりも、両電圧（ＶＩ、ＦＢ）の差分に対応した分だけ大なる電流Ｉ２を、第２のカスコードカレントミラー回路のノードｎ８に供給する。 Therefore, the transistor P5 of the second differential pair (P5, P6) receives both voltages (VI, FB ) is supplied to node n8 of the second cascode current mirror circuit.
　これにより、第２のカスコードカレントミラー回路（Ｎ１～Ｎ４）のノードｎ１０の電圧ＮＧが増加し、出力トランジスタとしてのトランジスタＮ７が出力電流Ｉｏｕｔを出力ノードｎ０から引き抜く。したがって、図５に示すように、時点ｔ１以降、出力ノードｎ０に生じる出力電圧ＦＢの電圧値が下降する。 As a result, the voltage NG at the node n10 of the second cascode current mirror circuit (N1 to N4) increases, and the transistor N7 as an output transistor pulls out the output current Iout from the output node n0. Therefore, as shown in FIG. 5, the voltage value of the output voltage FB generated at the output node n0 decreases after time t1.
　尚、クロック信号ＣＬＫ１が論理レベル１となっている間は、図５に示すように、トランジスタＰ８はオフ状態であるため、出力電圧ＦＢが出力端子ＴＯに送出されることはない。よって、図５に示すように、クロック信号ＣＬＫ１が論理レベル１の状態を維持する時点ｔ１から時点ｔ２の間に亘り、出力電圧ＦＢの電圧値は徐々に下降するものの、出力端子ＴＯから出力される出力電圧信号ＶＯの電圧値は、時点ｔ１以前の電圧Ｖｒを維持する。 Note that while the clock signal CLK1 is at logic level 1, as shown in FIG. 5, the transistor P8 is in the off state, so the output voltage FB is not sent to the output terminal TO. Therefore, as shown in FIG. 5, from time t1 to time t2, when the clock signal CLK1 maintains the state of logic level 1, the voltage value of the output voltage FB gradually decreases, but the voltage value is not output from the output terminal TO. The voltage value of the output voltage signal VO maintains the voltage Vr before time t1.
　また、クロック信号ＣＬＫ１が論理レベル０となっている間は、高速化回路ＢＳＴＡのリセット回路Ｒｓがリセット状態となり、所定の高電圧（例えば電源電圧ＶＤＤ）をノードｎｓに印加することで、高速化回路ＢＳＴＡのトランジスタＱｓＡを強制的にオフ状態にする。一方、クロック信号ＣＬＫ１が論理レベル１となっている時点ｔ１～ｔ２の間は、上記したリセット回路Ｒｓのリセット状態が解除される。 In addition, while the clock signal CLK1 is at logic level 0, the reset circuit Rs of the speed-up circuit BSTA is in a reset state, and by applying a predetermined high voltage (for example, power supply voltage VDD) to the node ns, the speed is increased. Transistor QsA of circuit BSTA is forcibly turned off. On the other hand, during the time period t1 to t2 when the clock signal CLK1 is at logic level 1, the reset state of the reset circuit Rs is released.
　更に、図５に示すように、入力電圧信号ＶＩの電圧値の低下に追従して、第２の差動対（Ｐ５、Ｐ６）のノードｎ１２の電圧ＮＴＬも低下する。よって、電圧ＮＴＬの低下変化をノードｎ１２を介して受けた、高速化回路ＢＳＴＡのコンデンサＣｓＡは、図５に示すようにパルス状に電圧値が低下する電圧ＭＯＮを生成し、これをノードｎｓを介してトランジスタＱｓＡに供給する。 Further, as shown in FIG. 5, following the decrease in the voltage value of the input voltage signal VI, the voltage NTL at the node n12 of the second differential pair (P5, P6) also decreases. Therefore, the capacitor CsA of the speed-up circuit BSTA, which receives the decreasing change in the voltage NTL via the node n12, generates the voltage MON whose voltage value decreases in a pulse-like manner as shown in FIG. It is supplied to the transistor QsA through the transistor QsA.
　これにより、時点ｔ１～時点ｔ２の間において低電圧の電圧ＭＯＮに応じて、Ｐチャネル型のトランジスタＱｓＡがオン状態となる。この際、トランジスタＱｓＡがオン状態になることで、ノードｎ６の電圧ＰＧが電源電圧ＶＤＤに向けて急峻に上昇するので、トランジスタＰ７がオン状態からオフ状態に遷移する時間が短縮される。 As a result, the P-channel transistor QsA is turned on in response to the low voltage MON between time t1 and time t2. At this time, by turning on the transistor QsA, the voltage PG at the node n6 rises steeply toward the power supply voltage VDD, so that the time required for the transistor P7 to transition from the on state to the off state is shortened.
　更に、トランジスタＱｓＡがオン状態になることで、図６の太線破線にて示される、電流源ＧｓＡ、トランジスタＱｓＡ、ノードｎ６、浮遊電流源Ｇｆ２、及びノードｎ１０からなる経路に電流Ｉｃが流れる。よって、ノードｎ１０に電流Ｉｃが流れ込むので、ノードｎ１０の電圧ＮＧ、つまりトランジスタＮ７のゲート電圧が急峻に増加し、それに伴い、トランジスタＮ７が出力ノードｎ０から引き抜く出力電流Ｉｏｕｔが増加する。したがって、出力ノードｎ０から引き抜かれる出力電流Ｉｏｕｔが増加した分だけ、出力電圧ＦＢの電圧値が入力電圧信号ＶＩの電圧値まで低下するのに費やされる時間が短縮される。 Furthermore, by turning on the transistor QsA, a current Ic flows through the path shown by the thick broken line in FIG. 6, which includes the current source GsA, the transistor QsA, the node n6, the floating current source Gf2, and the node n10. Therefore, since the current Ic flows into the node n10, the voltage NG at the node n10, that is, the gate voltage of the transistor N7 increases sharply, and accordingly, the output current Iout drawn from the output node n0 by the transistor N7 increases. Therefore, the time required for the voltage value of the output voltage FB to decrease to the voltage value of the input voltage signal VI is shortened by an amount corresponding to the increase in the output current Iout drawn from the output node n0.
　そして、図５に示すように、時点ｔ２以降の論理レベル０のクロック信号ＣＬＫ１に応じて、出力スイッチとしてのトランジスタＰ８がオン状態となり、出力ノードｎ０と出力端子ＴＯとが接続される。よって、時点ｔ２の直後から、出力ノードｎ０に生成された出力電圧ＦＢにより出力端子ＴＯ及び当該出力端子ＴＯに接続されている負荷（図示せず）が充電される。これにより、出力端子ＴＯから出力される出力電圧信号ＶＯの電圧値が図５に示すように低下し、直ちに、入力電圧信号ＶＩの電圧値に対応した電圧値ＶＰＲに到達する。 Then, as shown in FIG. 5, in response to the clock signal CLK1 of logic level 0 after time t2, the transistor P8 as an output switch is turned on, and the output node n0 and the output terminal TO are connected. Therefore, immediately after time t2, the output terminal TO and the load (not shown) connected to the output terminal TO are charged by the output voltage FB generated at the output node n0. As a result, the voltage value of the output voltage signal VO output from the output terminal TO decreases as shown in FIG. 5, and immediately reaches the voltage value VPR corresponding to the voltage value of the input voltage signal VI.
　したがって、高速化回路ＢＳＴＡによれば、バイアス電圧（ＶＢＬ、ＶＢＨ）に応じてカスコードカレントミラー回路（Ｐ１～Ｐ４、Ｎ１～Ｎ４）に流す電流、電流源（Ｇ１、Ｇ２、Ｇｆ１、Ｇｆ２）で生成する電流の電流量を増やすことなく、出力電圧信号ＶＯの立ち下がりを高速化することが可能となる。 Therefore, according to the speed-up circuit BSTA, the current flowing through the cascode current mirror circuit (P1 to P4, N1 to N4) according to the bias voltage (VBL, VBH) is generated by the current source (G1, G2, Gf1, Gf2). It is possible to speed up the fall of the output voltage signal VO without increasing the amount of current.
　図７は、本発明に係る第３の実施例による出力回路１００Ｂの構成を示す回路図である。尚、図７に示す出力回路１００Ｂは、高速化回路ＢＳＴのコンデンサＣｓの一端を、第１の差動対のトランジスタＮ５及びＮ６各々のソースに接続するのではなく、入力端子ＴＩに接続したものであり、その他の構成は図１に示す出力回路１００と同一である。 FIG. 7 is a circuit diagram showing the configuration of an output circuit 100B according to a third embodiment of the present invention. Note that the output circuit 100B shown in FIG. 7 has one end of the capacitor Cs of the high-speed circuit BST connected to the input terminal TI instead of connecting it to the sources of the transistors N5 and N6 of the first differential pair. The other configurations are the same as the output circuit 100 shown in FIG.
　すなわち、出力回路１００Ｂでは、入力端子ＴＩで受けた入力電圧信号ＶＩを、ノードｎ１３を介して高速化回路ＢＳＴのコンデンサＣｓの一端に供給する。かかる構成を採用した場合にも、図２に示すように、入力電圧信号ＶＩの立ち上がり時にコンデンサＣｓの他端に生じた電圧ＭＯＮに応じて、高速化回路ＢＳＴのトランジスタＱｓがオン状態となる。 That is, in the output circuit 100B, the input voltage signal VI received at the input terminal TI is supplied to one end of the capacitor Cs of the speed-up circuit BST via the node n13. Even when such a configuration is adopted, as shown in FIG. 2, the transistor Qs of the speed-up circuit BST is turned on in response to the voltage MON generated at the other end of the capacitor Cs when the input voltage signal VI rises.
　よって、出力回路１００Ｂにおいても出力回路１００と同様に、高速化回路ＢＳＴにより、出力電圧ＦＢの立ち上がりが高速化する。 Therefore, similarly to the output circuit 100, in the output circuit 100B, the rise of the output voltage FB is sped up by the speed-up circuit BST.
　尚、出力電圧ＦＢの立ち下がりを高速化する高速化回路ＢＳＴＡを設ける場合には、高速化回路ＢＳＴＡに含まれるコンデンサＣｓＡの一端をノードｎ１２を介して、入力端子ＴＩに接続すれば良い。 Note that in the case of providing a speed-up circuit BSTA that speeds up the fall of the output voltage FB, one end of the capacitor CsA included in the speed-up circuit BSTA may be connected to the input terminal TI via the node n12.
　また、高速化回路ＢＳＴ（ＢＳＴＡ）では、トランジスタＱｓ（ＱｓＡ）のソースに電流源Ｇｓ（ＧｓＡ）を接続しているが、電流源に代えて抵抗素子を接続するようにしてよく、或いはトランジスタのソースに直に接地電圧ＶＳＳ（電源電圧ＶＤＤ）を印加しても良い。 In addition, in the high-speed circuit BST (BSTA), a current source Gs (GsA) is connected to the source of the transistor Qs (QsA), but a resistance element may be connected instead of the current source, or a resistor element may be connected to the source of the transistor Qs (QsA). The ground voltage VSS (power supply voltage VDD) may be applied directly to the source.
　また、高速化回路ＢＳＴ（ＢＳＴＡ）では、入力電圧信号ＶＩの立ち上がり又は立下りに応じて１つのパルス電圧（ＭＯＮ）を生成し、このパルス電圧によりノードｎ６又はｎ１０の電圧を強制的に低下又は増加させているが、入力電圧信号ＶＩの変動を検知した場合に、ノードｎ６又はｎ１０の電圧を強制的に低下又は増加させる構成であれば良い。 In addition, the speed-up circuit BST (BSTA) generates one pulse voltage (MON) in response to the rise or fall of the input voltage signal VI, and uses this pulse voltage to forcibly lower or reduce the voltage at the node n6 or n10. However, any configuration may be used as long as the voltage at the node n6 or n10 is forcibly decreased or increased when a fluctuation in the input voltage signal VI is detected.
　また、図１、図３及び図７に示す構成では、出力ノードｎ０及び出力端子ＴＯ間に、出力スイッチ（Ｐ８）を設けているが、これを用いずに、出力ノードｎ０に直接、出力端子ＴＯを接続するようにしても良い。 In addition, in the configurations shown in FIGS. 1, 3, and 7, an output switch (P8) is provided between the output node n0 and the output terminal TO, but instead of using this, the output terminal It is also possible to connect TO.
　要するに、本発明に係る出力回路（１００、１００Ａ、１００Ｂ）としては、以下の制御電圧生成部、Ｐチャネル型及びＮチャネル型の第１及び第２の出力トランジスタ、浮遊電流源及び高速化回路を含むものであれば良い。 In short, the output circuit (100, 100A, 100B) according to the present invention includes the following control voltage generation section, P-channel type and N-channel type first and second output transistors, floating current source, and high-speed circuit. It is fine as long as it includes.
　すなわち、制御電圧生成部（Ｐ１～Ｐ６、Ｎ１～Ｎ６、Ｇ１、Ｇ２）は、入力電圧信号（ＶＩ）に基づく第１の制御電圧（ＰＧ）を第１のノード（ｎ６）に生成すると共に、当該入力電圧信号に基づく第２の制御電圧（ＮＧ）を第２のノード（ｎ１０）に生成する。尚、第１のノード（ｎ６）及び第２のノード（ｎ１０）は浮遊電流源（Ｇｆ２）を介して接続されている。第１の出力トランジスタ（Ｐ７）は、第１の制御電圧（ＰＧ）をゲートで受け、当該第１の制御電圧に応じた第１の出力電流を出力ノード（ｎ０）に送出し、第２の出力トランジスタ（Ｎ７）は、第２の制御電圧（ＮＧ）をゲートで受け、当該第２の制御電圧に応じた第２の出力電流を出力ノード（ｎ０）から引き抜く。高速化回路（ＢＳＴ、ＢＳＴＡ）は、入力電圧信号の変動に応じて、第２のノード（ｎ１０）の電圧を低下させる、又は第１のノード（ｎ６）の電圧を増加させる。 That is, the control voltage generation section (P1 to P6, N1 to N6, G1, G2) generates a first control voltage (PG) based on the input voltage signal (VI) at the first node (n6), A second control voltage (NG) based on the input voltage signal is generated at the second node (n10). Note that the first node (n6) and the second node (n10) are connected via a floating current source (Gf2). The first output transistor (P7) receives a first control voltage (PG) at its gate, sends out a first output current corresponding to the first control voltage to the output node (n0), and outputs a first output current corresponding to the first control voltage to the output node (n0). The output transistor (N7) receives the second control voltage (NG) at its gate and draws a second output current corresponding to the second control voltage from the output node (n0). The speed-up circuit (BST, BSTA) reduces the voltage at the second node (n10) or increases the voltage at the first node (n6) in response to fluctuations in the input voltage signal.
　図８は、本発明に係る出力回路（１００、１００Ａ、１００Ｂ）を含む表示ドライバを搭載した表示装置２００の概略構成を示すブロック図である。 FIG. 8 is a block diagram showing a schematic configuration of a display device 200 equipped with a display driver including an output circuit (100, 100A, 100B) according to the present invention.
　表示装置２００は、表示パネル８０、駆動制御部１０１、走査ドライバ１０２及びデータドライバ１０３を有する。 The display device 200 includes a display panel 80, a drive control section 101, a scan driver 102, and a data driver 103.
　表示パネル８０は、例えば液晶又は有機ＥＬパネル等からなり、２次元画面の水平方向に伸張するｒ個（ｒは２以上の自然数）の水平走査線Ｓ１～Ｓｒと、２次元画面の垂直方向に伸張するｎ個（ｎは２以上の自然数）のデータ線Ｄ１～Ｄｎと、を含む。水平走査線及びデータ線の各交叉部には、画素を担う表示セルが形成されている。 The display panel 80 is made of, for example, a liquid crystal or organic EL panel, and has r horizontal scanning lines S1 to Sr (r is a natural number of 2 or more) extending in the horizontal direction of the two-dimensional screen, and horizontal scanning lines S1 to Sr extending in the vertical direction of the two-dimensional screen. n (n is a natural number of 2 or more) data lines D1 to Dn that extend. A display cell serving as a pixel is formed at each intersection of the horizontal scanning line and the data line.
　駆動制御部１０１は、映像信号ＶＤを受け当該映像信号ＶＤに基づき、各水平走査線に供給する水平走査パルスを生成する為の走査タイミング信号を生成し、走査ドライバ１０２に供給する。 The drive control unit 101 receives the video signal VD, generates a scan timing signal for generating a horizontal scan pulse to be supplied to each horizontal scan line based on the video signal VD, and supplies it to the scan driver 102.
　更に、駆動制御部１０１は、映像信号ＶＤに基づき、クロック信号ＣＬＫ１等の各種制御信号、及び各画素の輝度レベルを例えば８ビットで表す表示データ片の系列を含む映像デジタル信号ＤＶＳを生成し、データドライバ１０３に供給する。 Further, the drive control unit 101 generates a video digital signal DVS including various control signals such as a clock signal CLK1 and a series of display data pieces representing the brightness level of each pixel in 8 bits, for example, based on the video signal VD, The data is supplied to the data driver 103.
　走査ドライバ１０２は、駆動制御部１０１から供給された走査タイミング信号に基づいて、水平走査パルスを表示パネル８０の水平走査線Ｓ１～Ｓｒの各々に順次印加する。 The scan driver 102 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S1 to Sr of the display panel 80 based on the scan timing signal supplied from the drive control unit 101.
　データドライバ１０３は、駆動制御部１０１から供給された制御信号に応じて、映像デジタル信号ＤＶＳに含まれる表示データ片の系列を取り込む。そして、データドライバ１０３は、取り込んだ表示データ片を１水平走査線分（ｎ個）ずつ、それぞれの輝度レベルに対応した大きさの電圧値を有するｎ個の出力電圧信号Ｖ１～Ｖｎに変換し、夫々を表示パネル８０のデータ線Ｄ１～Ｄｎに供給する。 The data driver 103 takes in a series of display data pieces included in the video digital signal DVS in response to a control signal supplied from the drive control unit 101. Then, the data driver 103 converts the captured display data pieces for each horizontal scanning line (n pieces) into n output voltage signals V1 to Vn having voltage values corresponding to the respective brightness levels. , are supplied to the data lines D1 to Dn of the display panel 80, respectively.
　図９は、データドライバ１０３の内部構成を示すブロック図である。 FIG. 9 is a block diagram showing the internal configuration of the data driver 103.
　データドライバ１０３は、半導体ＩＣチップに形成されており、階調電圧生成回路１３０、データ取込部１３１、ＤＡ変換部１３２、及び出力部１３３を有する。 The data driver 103 is formed on a semiconductor IC chip, and includes a grayscale voltage generation circuit 130, a data acquisition section 131, a DA conversion section 132, and an output section 133.
　階調電圧生成回路１３０は、映像信号によって表現可能な輝度レベルの範囲を例えば２５６段階で表す、互いに異なる電圧値を示す階調電圧Ｘ０～Ｘ２５５を生成し、ＤＡ変換部１３２に供給する。 The gradation voltage generation circuit 130 generates gradation voltages X0 to X255 representing different voltage values representing the range of luminance levels that can be expressed by the video signal, for example, in 256 steps, and supplies them to the DA converter 132.
　データ取込部１３１は、１水平走査期間の周期を有するクロック信号ＣＬＫ１に同期して、１水平走査期間毎に、映像信号ＤＶＳに含まれる表示データ片の系列中から、１水平走査ライン分のｎ個の表示データ片を順次取り込み、夫々を表示データＰＤ１～ＰＤｎとしてＤＡ変換部１３２に供給する。 In synchronization with a clock signal CLK1 having a period of one horizontal scanning period, the data acquisition unit 131 extracts data for one horizontal scanning line from a series of display data pieces included in the video signal DVS every horizontal scanning period. The n display data pieces are sequentially taken in and supplied to the DA converter 132 as display data PD1 to PDn, respectively.
　ＤＡ変換部１３２は、階調電圧Ｘ０～Ｘ２５５を用いて、表示データＰＤ１～ＰＤｎを夫々アナログの電圧値を有する階調電圧信号Ｑ１～Ｑｎに変換する。すなわち、ＤＡ変換部１３２は、表示データＰＤ１～ＰＤｎの各々毎に、階調電圧Ｘ０～Ｘ２５５のうちから、その表示データＰＤにて示される輝度レベルに対応した電圧値を有する階調電圧を選択する。そして、ＤＡ変換部１３２は、表示データＰＤ１～ＰＤｗの各々毎に選択した階調電圧を夫々が有する階調電圧信号Ｑ１～Ｑｎを得る。ＤＡ変換部１３２は、階調電圧信号Ｑ１～Ｑｎを出力部１３３に供給する。 The DA converter 132 uses the grayscale voltages X0 to X255 to convert the display data PD1 to PDn into grayscale voltage signals Q1 to Qn each having an analog voltage value. That is, the DA converter 132 selects, for each of the display data PD1 to PDn, a grayscale voltage having a voltage value corresponding to the brightness level indicated by the display data PD from among the grayscale voltages X0 to X255. do. Then, the DA converter 132 obtains grayscale voltage signals Q1 to Qn, each of which has a grayscale voltage selected for each of the display data PD1 to PDw. The DA converter 132 supplies grayscale voltage signals Q1 to Qn to the output unit 133.
　出力部１３３は、階調電圧信号Ｑ１～Ｑｎを夫々個別に増幅して得た出力電圧信号Ｖ１～Ｖｎを出力し、夫々を表示パネル８０のデータ線Ｄ１～Ｄｎに供給する。 The output unit 133 outputs output voltage signals V1 to Vn obtained by individually amplifying the grayscale voltage signals Q1 to Qn, and supplies them to the data lines D1 to Dn of the display panel 80, respectively.
　尚、出力部１３３は、夫々が図１、図４又は図７に示す構成からなる出力回路ＡＭ１～ＡＭｎを含む。 Note that the output section 133 includes output circuits AM1 to AMn each having a configuration shown in FIG. 1, FIG. 4, or FIG. 7.
　すなわち、例えば出力回路ＡＭ２は、階調電圧信号Ｑ２を入力電圧信号ＶＩとして自身の入力端子ＴＩで受け、当該階調電圧信号Ｑ２に応じて出力端子ＶＯから出力された出力電圧信号ＶＯを、出力電圧信号Ｖ２として表示パネル８０のデータ線Ｄ２に供給する。 That is, for example, the output circuit AM2 receives the gray scale voltage signal Q2 as the input voltage signal VI at its own input terminal TI, and outputs the output voltage signal VO output from the output terminal VO in accordance with the gray scale voltage signal Q2. It is supplied to the data line D2 of the display panel 80 as a voltage signal V2.
　よって、データドライバ１０３の出力部１３３として、夫々が図１、図４又は図７に示す構成からなる出力回路ＡＭ１～ＡＭｎを採用することで、消費電力を抑えて、表示パネルの高速駆動を行うことが可能となる。 Therefore, by employing output circuits AM1 to AMn each having the configuration shown in FIG. 1, FIG. 4, or FIG. 7 as the output section 133 of the data driver 103, power consumption can be suppressed and the display panel can be driven at high speed. becomes possible.
１００、１００Ａ、１００Ｂ　　出力回路
１０３　　　　　　　　　　　　データドライバ
２００　　　　　　　　　　　　表示装置
ＡＭ１～ＡＭｎ　　　　　　　　出力回路
ＢＳＴ、ＢＳＴＡ　　　　　　　高速化回路
Ｃｓ、ＣｓＡ　　　　　　　　　コンデンサ
Ｇｓ、ＧｓＡ　　　　　　　　　電流源
Ｑｓ、ＱｓＡ　　　　　　　　　トランジスタ
Ｒｓ、ＲｓＡ　　　　　　　　　リセット回路
　
　　       100, 100A, 100B Output circuit 103 Data driver 200 Display device AM1 to AMn Output circuit BST, BSTA Speed-up circuit Cs, CsA Capacitor Gs, GsA Current source Qs, QsA Transistor Rs, RsA Reset circuit

Claims (12)

  1. 　入力電圧信号を受け、前記入力電圧信号を増幅した信号を出力電圧信号として出力ノードに生成しこれを出力端子から出力する出力回路であって、
    　前記入力電圧信号に基づく第１の制御電圧を第１のノードに生成すると共に、前記入力電圧信号に基づく第２の制御電圧を第２のノードに生成する制御電圧生成部と、
    　前記第１のノードに生成された前記第１の制御電圧をゲートで受け、前記第１の制御電圧に応じた第１の出力電流を前記出力ノードに送出するＰチャネル型の第１の出力トランジスタと、
    　前記第２のノードに生成された前記第２の制御電圧をゲートで受け、前記第２の制御電圧に応じた第２の出力電流を前記出力ノードから引き抜くＮチャネル型の第２の出力トランジスタと、
    　前記第１のノード及び前記第２のノード間に接続されている浮遊電流源と、
    　前記入力電圧信号の変動に応じて、前記第２のノードの電圧を低下させる、又は前記第１のノードの電圧を増加させる高速化回路と、を有することを特徴とする出力回路。     An output circuit that receives an input voltage signal, generates a signal obtained by amplifying the input voltage signal as an output voltage signal at an output node, and outputs this from an output terminal,
    a control voltage generation unit that generates a first control voltage based on the input voltage signal at a first node and a second control voltage based on the input voltage signal at a second node;
    a P-channel type first output transistor that receives the first control voltage generated at the first node at its gate and sends a first output current corresponding to the first control voltage to the output node; and,
    an N-channel type second output transistor that receives the second control voltage generated at the second node at its gate and draws a second output current corresponding to the second control voltage from the output node; ,
    a floating current source connected between the first node and the second node;
    An output circuit comprising: a speed-up circuit that reduces the voltage at the second node or increases the voltage at the first node in accordance with fluctuations in the input voltage signal.
  2. 　前記高速化回路は、前記入力電圧信号の変動に応じて、前記第２のノードに所定の低電圧を接続する、又は前記第１のノードに所定の高電圧を接続することを特徴とする請求項１に記載の出力回路。 A claim characterized in that the speed-up circuit connects a predetermined low voltage to the second node or connects a predetermined high voltage to the first node in accordance with fluctuations in the input voltage signal. The output circuit according to item 1.
  3. 　前記制御電圧生成部は、
    　第１のカレントミラー回路と、
    　第１の電流源と、前記第１の電流源に夫々のソースが接続されており、前記入力電圧信号と前記出力電圧信号との差分に対応した電流対を夫々のドレインを介して前記第１のカレントミラー回路の一次側及び二次側から引き抜く一対のトランジスタと、を含む第１の差動対と、
    　第２のカレントミラー回路と、
    　第２の電流源と、前記第２の電流源に夫々のソースが接続されており、前記入力電圧信号と前記出力電圧信号との差分に対応した電流対を夫々のドレインを介して前記第２のカレントミラー回路の一次側及び二次側に供給する一対のトランジスタと、を含む第２の差動対と、を有することを特徴とする請求項１又は２に記載の出力回路。     The control voltage generation section includes:
    a first current mirror circuit;
    A first current source, and respective sources are connected to the first current source, and a current pair corresponding to the difference between the input voltage signal and the output voltage signal is connected to the first current source through the respective drains. a first differential pair including a pair of transistors extracted from the primary side and secondary side of the current mirror circuit;
    a second current mirror circuit;
    a second current source, and respective sources are connected to the second current source, and a current pair corresponding to the difference between the input voltage signal and the output voltage signal is connected to the second current source through the respective drains. 3. The output circuit according to claim 1, further comprising: a second differential pair including a pair of transistors supplied to the primary side and the secondary side of the current mirror circuit.
  4. 　前記高速化回路は、
    　前記入力電圧信号を一端で受けるコンデンサと、
    　前記コンデンサの他端の電圧に応じてオン状態又はオフ状態に設定され、オン状態に設定された場合に、接地電圧を前記第２のノードに印加する、又は電源電圧を前記第１のノードに印加するスイッチ素子と、を含むことを特徴とする請求項１～３のいずれか１に記載の出力回路。     The speed-up circuit is
    a capacitor receiving the input voltage signal at one end;
    The capacitor is set to an on state or an off state depending on the voltage at the other end of the capacitor, and when set to an on state, a ground voltage is applied to the second node or a power supply voltage is applied to the first node. 4. The output circuit according to claim 1, further comprising a switch element for applying voltage.
  5. 　前記高速化回路は、
    　前記第１の差動対の前記一対のトランジスタ各々のソース、又は前記第２の差動対の前記一対のトランジスタ各々のソースに一端が接続されているコンデンサと、
    　前記コンデンサの他端の電圧に応じてオン状態又はオフ状態に設定され、オン状態に設定された場合に、接地電圧を前記第２のノードに印加する、又は電源電圧を前記第１のノードに印加するスイッチ素子と、を含むことを特徴とする請求項３に記載の出力回路。     The speed-up circuit is
    a capacitor having one end connected to a source of each of the pair of transistors of the first differential pair or a source of each of the pair of transistors of the second differential pair;
    The capacitor is set to an on state or an off state depending on the voltage at the other end of the capacitor, and when set to an on state, a ground voltage is applied to the second node or a power supply voltage is applied to the first node. 4. The output circuit according to claim 3, further comprising a switch element for applying voltage.
  6. 　前記スイッチ素子は、電流源又は抵抗素子を介して自身のドレインが前記第１のノード又は前記第２のノードに接続されており、自身のゲートが前記コンデンサの他端に接続されているトランジスタを含むことを特徴とする請求項４又は５に記載の出力回路。 The switch element includes a transistor whose drain is connected to the first node or the second node via a current source or a resistance element, and whose gate is connected to the other end of the capacitor. The output circuit according to claim 4 or 5, characterized in that the output circuit includes:
  7. 　前記高速化回路は、リセット制御信号に応じて、前記スイッチ素子をオフ状態に初期化する電圧を前記スイッチ素子のゲートに印加するリセット回路を含むことを特徴とする請求項４～６のいずれか１に記載の出力回路。 7. The speed-up circuit includes a reset circuit that applies a voltage to the gate of the switch element to initialize the switch element to an off state in response to a reset control signal. 1. The output circuit according to 1.
  8. 　前記リセット回路は、前記リセット制御信号をゲートで受けると共に前記スイッチ素子をオフ状態に初期化する電圧をソースで受け、前記リセット制御信号に応じてオン状態になった場合に、前記スイッチ素子をオフ状態に初期化する電圧を自身のドレインを介して前記スイッチ素子のゲートに印加するトランジスタを含むことを特徴とする請求項７に記載の出力回路。 The reset circuit receives the reset control signal at a gate and receives a voltage for initializing the switch element to an off state at a source, and turns off the switch element when the switch element is turned on in response to the reset control signal. 8. The output circuit according to claim 7, further comprising a transistor that applies a voltage initializing the state to the gate of the switch element via its drain.
  9. 　前記高速化回路は、
    　前記スイッチ素子のゲートに一端が接続されており他端に前記前記スイッチ素子をオフ状態に初期化する電圧が印加されている抵抗素子又は電流源を含むことを特徴とする請求項４～６のいずれか１に記載の出力回路。     The speed-up circuit is
    7. The device according to claim 4, further comprising a resistive element or a current source, one end of which is connected to the gate of the switching element, and the other end of which is applied a voltage for initializing the switching element to an OFF state. The output circuit according to any one of the above.
  10. 　前記出力ノードと前記出力端子との間に接続されており、オン状態時に前記出力ノードと前記出力端子とを接続する一方、オフ状態時には前記出力ノードと前記出力端子との接続を遮断する出力スイッチを含むことを特徴とする請求項１～９のいずれか１に記載の出力回路。 an output switch connected between the output node and the output terminal, which connects the output node and the output terminal in an on state, and disconnects the output node and the output terminal in an off state; The output circuit according to any one of claims 1 to 9, characterized in that the output circuit includes:
  11. 　映像信号に基づく各画素の輝度レベルを表す第１～第ｎ（ｎは２以上の整数）の表示データ片を、夫々前記輝度レベルに対応した電圧値を有する第１～第ｎの階調電圧信号に変換するＤＡ変換部と、
    　前記第１～第ｎの階調電圧信号を個別に増幅して得た第１～第ｎの出力電圧信号を表示パネルの第１～第ｎのデータ線に供給する第１～第ｎの出力回路と、を含み、
    　前記第１～第ｎの出力回路の各々は、
    　前記階調電圧信号に基づく第１の制御電圧を第１のノードに生成すると共に、前記入力電圧信号に基づく第２の制御電圧を第２のノードに生成する制御電圧生成部と、
    　前記第１のノードに生成された前記第１の制御電圧をゲートで受け、前記第１の制御電圧に応じた第１の出力電流を出力ノードに送出するＰチャネル型の第１の出力トランジスタと、
    　前記第２のノードに生成された前記第２の制御電圧をゲートで受け、前記第２の制御電圧に応じた第２の出力電流を前記出力ノードから引き抜くＮチャネル型の第２の出力トランジスタと、
    　前記第１のノード及び前記第２のノード間に接続されている浮遊電流源と、
    　前記階調電圧信号の変動に応じて、前記第２のノードの電圧を低下させる、又は前記第１のノードの電圧を増加させる高速化回路と、を有することを特徴とする表示ドライバ。     The first to nth (n is an integer of 2 or more) display data pieces representing the brightness level of each pixel based on the video signal are converted into first to nth gradation voltages each having a voltage value corresponding to the brightness level. a DA converter that converts into a signal;
    1st to nth outputs that supply first to nth output voltage signals obtained by individually amplifying the first to nth gradation voltage signals to first to nth data lines of the display panel; a circuit;
    Each of the first to nth output circuits is
    a control voltage generation unit that generates a first control voltage based on the grayscale voltage signal at a first node and a second control voltage based on the input voltage signal at a second node;
    a P-channel type first output transistor that receives the first control voltage generated at the first node at its gate and sends a first output current corresponding to the first control voltage to the output node; ,
    an N-channel type second output transistor that receives the second control voltage generated at the second node at its gate and draws a second output current corresponding to the second control voltage from the output node; ,
    a floating current source connected between the first node and the second node;
    A display driver comprising: a speed-up circuit that reduces the voltage at the second node or increases the voltage at the first node in accordance with fluctuations in the gray scale voltage signal.
  12. 　夫々に複数の画素が形成されている第１～第ｎ（ｎは２以上の整数）のデータ線を有する表示パネルと、
    　映像信号に基づく各画素の輝度レベルを表す第１～第ｎの表示データ片を、夫々前記輝度レベルに対応した電圧値を有する第１～第ｎの階調電圧信号に変換するＤＡ変換部と、
    　前記第１～第ｎの階調電圧信号を個別に増幅して得た第１～第ｎの出力電圧信号を前記表示パネルの前記第１～第ｎのデータ線に供給する第１～第ｎの出力回路と、を含み、
    　前記第１～第ｎの出力回路の各々は、
    　前記階調電圧信号に基づく第１の制御電圧を第１のノードに生成すると共に、前記入力電圧信号に基づく第２の制御電圧を第２のノードに生成する制御電圧生成部と、
    　前記第１のノードに生成された前記第１の制御電圧をゲートで受け、前記第１の制御電圧に応じた第１の出力電流を出力ノードに送出するＰチャネル型の第１の出力トランジスタと、
    　前記第２のノードに生成された前記第２の制御電圧をゲートで受け、前記第２の制御電圧に応じた第２の出力電流を前記出力ノードから引き抜くＮチャネル型の第２の出力トランジスタと、
    　前記第１のノード及び前記第２のノード間に接続されている浮遊電流源と、
    　前記階調電圧信号の変動に応じて、前記第２のノードの電圧を低下させる、又は前記第１のノードの電圧を増加させる高速化回路と、を有することを特徴とする表示装置。
          a display panel having first to nth (n is an integer of 2 or more) data lines, each of which has a plurality of pixels;
    a DA converter that converts first to nth display data pieces representing the brightness level of each pixel based on the video signal into first to nth grayscale voltage signals each having a voltage value corresponding to the brightness level; ,
    first to nth output voltage signals obtained by individually amplifying the first to nth gradation voltage signals to the first to nth data lines of the display panel; an output circuit;
    Each of the first to nth output circuits is
    a control voltage generation unit that generates a first control voltage based on the grayscale voltage signal at a first node and a second control voltage based on the input voltage signal at a second node;
    a P-channel type first output transistor that receives the first control voltage generated at the first node at its gate and sends a first output current corresponding to the first control voltage to the output node; ,
    an N-channel type second output transistor that receives the second control voltage generated at the second node at its gate and draws a second output current corresponding to the second control voltage from the output node; ,
    a floating current source connected between the first node and the second node;
    A display device comprising: a speed-up circuit that reduces the voltage at the second node or increases the voltage at the first node in accordance with fluctuations in the gray scale voltage signal.
PCT/JP2023/009582 2022-03-17 2023-03-13 Output circuit display driver, and display device WO2023176762A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-042286 2022-03-17
JP2022042286 2022-03-17

Publications (1)

Publication Number Publication Date
WO2023176762A1 true WO2023176762A1 (en) 2023-09-21

Family

ID=88023720

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/009582 WO2023176762A1 (en) 2022-03-17 2023-03-13 Output circuit display driver, and display device

Country Status (1)

Country Link
WO (1) WO2023176762A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067525A (en) * 2005-08-29 2007-03-15 Toshiba Corp Amplifier circuit
JP2007110233A (en) * 2005-10-11 2007-04-26 Asahi Kasei Microsystems Kk Operational amplifier
JP2008122567A (en) * 2006-11-10 2008-05-29 Nec Electronics Corp Data driver and display apparatus
JP2011182229A (en) * 2010-03-02 2011-09-15 Renesas Electronics Corp Differential amplifier circuit, display panel driver, and display device
JP2013219509A (en) * 2012-04-06 2013-10-24 Renesas Electronics Corp Differential amplification circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007067525A (en) * 2005-08-29 2007-03-15 Toshiba Corp Amplifier circuit
JP2007110233A (en) * 2005-10-11 2007-04-26 Asahi Kasei Microsystems Kk Operational amplifier
JP2008122567A (en) * 2006-11-10 2008-05-29 Nec Electronics Corp Data driver and display apparatus
JP2011182229A (en) * 2010-03-02 2011-09-15 Renesas Electronics Corp Differential amplifier circuit, display panel driver, and display device
JP2013219509A (en) * 2012-04-06 2013-10-24 Renesas Electronics Corp Differential amplification circuit

Similar Documents

Publication Publication Date Title
US10777119B2 (en) Semiconductor device
US10255847B2 (en) Level shift circuit and display driver
US6014122A (en) Liquid crystal driving circuit for driving a liquid crystal display panel
US6946905B2 (en) Offset cancel circuit of voltage follower equipped with operational amplifier
JP4515821B2 (en) Drive circuit, operation state detection circuit, and display device
JP3368819B2 (en) LCD drive circuit
US7463231B2 (en) Grayscale voltage generating circuit and method
US11538432B2 (en) Output buffer increasing slew rate of output signal voltage without increasing current consumption
JP6917178B2 (en) Output circuit, data line driver and display device
US12073804B2 (en) Signal level shift conversion circuit for display driver and display device converting input voltage signal at synchronized timing
JP7283939B2 (en) Semiconductor device and data driver
US20230377521A1 (en) Drive circuit, display device, and drive method
JP2007086391A (en) Gray scale voltage generating circuit
US11837132B2 (en) Output buffer, data driver, and display device having the same
US10607560B2 (en) Semiconductor device and data driver
JP2002290172A (en) Voltage follower circuit and drive device for display device
WO2023176762A1 (en) Output circuit display driver, and display device
US20070103131A1 (en) DC-DC converter and organic light emitting display using the same
JP2004350256A (en) Offset compensation circuit, drive circuit with offset-compensation function using the same, and liquid-crystal display device
JP7379486B2 (en) Display drivers, semiconductor devices and amplifier circuits
JP7510814B2 (en) Digital-to-analog conversion circuit, data driver and display device
US20240321233A1 (en) Output amplifier, source driver, and display apparatus
US20240153432A1 (en) Data driving device
JP2024134636A (en) Driver, electro-optical device and electronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23770717

Country of ref document: EP

Kind code of ref document: A1