JPH11340753A - Arithmetic amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a through-rate or settling in the step response of an operation amplifier without changing the circuit constitution of the operation amplifier by providing an active element whose resistance value is made variable and a difference controlling means for changing the resistance value of the active element based on the difference of the input of the arithmetic amplifying means. SOLUTION: This arithmetic amplifier is provided with an active element (nMOS transistor M20) whose resistance value is made variable and a difference controlling means (differential stage of a block 13) for changing the resistance value of the active element based on the difference of the inputs of an arithmetic amplifying means. The difference controlling means detects a differential voltage between the input voltage and output voltage of operation amplifiers 10-12, and converts it into currents, and the currents are transmitted by the current mirror circuits of MOS transistors M13-M18. The transmitted currents are converted into a voltage by using an MOS transistor M19 whose gate and drain are short-circuited as load resistance, and a voltage converted as a value based on a difference between the input voltage and output voltage of the operating amplifier is added to the gate of an nMOS transistor M20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an operational amplifier, and more particularly, to an operational amplifier for amplifying a signal.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a configuration example of a conventional operational amplifier (hereinafter referred to as an operational amplifier). The operational amplifier shown in FIG. 6 is a so-called folded-cascode type. In FIG. 6, a block 10 represents an input differential stage, a block 11 represents a voltage amplifying stage including a grounded gate circuit, and a block 12 represents an output buffer stage. . Also, M1,
M2, M5 to M8 are nMOS transistors, M3, M
4, M9 and M10 are pMOS transistors, and I1
To I5 are constant current sources for setting the bias of the transistor, C1
Is the phase compensation capacitance, C2 is the load capacitance attached to the output terminal 4, V
Reference numeral 1 denotes a voltage source that applies a gate bias to the common-gate transistors M5 and M6. Terminal 1 is a power supply terminal, 2 is a positive input terminal, 3 is a negative input terminal, and 4 is an output terminal. When the output terminal 4 and the negative input terminal 3 are short-circuited, this operational amplifier operates as a voltage follower.

[0003]

When such an operational amplifier is used to amplify the output from various signal sources typified by a sensor such as a CCD, the characteristics of the operational amplifier require low random noise, high speed, and high performance. Stability, low power consumption, high accuracy (high open loop gain), etc.

With respect to random noise, the direct signal S
Since it affects the / N ratio and the dynamic range, it is important to suppress it. If it is required to sample the sensor output that changes stepwise in order to digitally process the signal output of the CCD sensor that handles high-definition video signals, the step response output of the operational amplifier changes quickly according to the input. And quickly settle to the final value. In such a case, high speed,
High stability is important. When the operational amplifier is used as a voltage follower as in the example of FIG. 6, the accuracy of the output voltage is proportional to the open loop gain of the operational amplifier. Desired. For example, many products that handle images are battery-powered, so it is necessary to extend the operable time of the product. In such a case, low power consumption is important.

However, the performances required for the above-described operational amplifiers have a trade-off relationship with each other as described below.

The random noise generated in the operational amplifier shown in FIG. 6 includes flicker noise having a so-called 1 / f (f is frequency) characteristic and thermal noise due to channel resistance of a MOS transistor and the like. These are the MOS transistors M1 and M2. Particularly, a broadband amplifier has a large influence on thermal noise having no frequency dependence in the magnitude of the noise. With the gate input,
When converted as a noise voltage source, the magnitude V of the thermal noise is represented by the following equation (1).

[0007]

(Equation 1) (1) the thermal noise as is clear from equation is inversely proportional to the transconductance g _m of the transistor.

On the other hand, the value of the open loop voltage gain of the operational amplifier in FIG. 6 in a low frequency region can be expressed as g _{mi RL} . Here, g _mi is the mutual conductance of the input MOS transistors M1 and M2, and R _L is the impedance at point A in FIG. FIG. 7 shows a frequency characteristic diagram of the open loop voltage gain of the operational amplifier. Here, ω _P1 represents a first pole, ω _P2 represents a second pole, and usually ω _P1 is determined by the value of the phase compensation capacitance C1 and the impedance _RL of the point A in FIG. 6, and ω _P2 is an output MOS transistor. M8, M
It is determined by the value of the combined output impedance of 10 and the load capacitance C2.

Settling time indicating the stability of the amplifier (when a step input is given to the op-amp, the output of the op-amp changes accordingly and finally becomes ± 0.1% or ± 0.01% of the settled value). %) Depends on the magnitude of the open loop gain at the frequency ω _P2 , and is less than or equal to 0 db. The smaller the magnitude is, the smaller the ringing in the step response becomes, so that the settling time becomes shorter. Since often the size of the load capacitance C2 can not be reduced to the normal way you want, it is required that the moving frequency omega _P2 to a higher frequency to increase the g _m of the output transistor M8, M9, the output transistor is in it The ratio (W / L) of the gate width W and the gate length L of M8 and M9 may be increased to increase the drain current. However, increasing the W / L leads to an increase in cost because the area occupied by the semiconductor chip increases. Also, an increase in drain current naturally leads to an increase in current consumption. Therefore, ω _P2 cannot actually move to the high frequency side.

Therefore, in order to increase the stability of the amplifier, the position of the frequency ω _P1 is moved to the lower frequency side, or the open loop gain itself is reduced. But ω
To move _P1 to the lower frequency side, it is necessary to increase the phase compensation capacitance, but that leads to a decrease in the slew rate, which indicates the high speed of the amplifier.

Therefore, the remaining method is to reduce the open-loop gain, which requires a reduction in the input transistor g _m . However, g _m of the input transistor is thus created a conflicting situation that can not be reduced to participate directly in a random noise as described above.

An object of the present invention is to provide an operational amplifier capable of achieving both required performance and the conventional trade-off relationship.

Another object of the present invention is to provide an operational amplifier which suppresses ringing and has a high slew rate and performs a high-speed operation at high stability.

[0014]

Means and Functions for Solving the Problems The first aspect of the present invention is as follows.
The operational amplifier includes an operational amplifier having a phase compensation capacitor, an active element connected in series with the phase compensation capacitor and having a variable resistance value, and the active amplifier based on a difference between inputs of the operational amplifier. And differential control means for changing the resistance value of the element.

According to a second operational amplifier of the present invention, in the first operational amplifier, the differential control means has an offset applied to a differential input thereof, so that a differential input is provided between two inputs of the operational amplifier means. When there is a difference equal to or larger than the offset value, the resistance value of the active element is increased,
When the difference between the two inputs becomes smaller than the offset value, the resistance of the active element is controlled to decrease.

In a third operational amplifier according to the present invention, in the first or second operational amplifier, the active element is a field effect transistor, and the output of the differential control means is the field effect transistor. Are connected to the gates of the respective cells.

According to a fourth operational amplifier of the present invention, in the first or second operational amplifier, the active element is a bipolar transistor, and an output of the differential control means is connected to a base of the bipolar transistor. It is characterized by having been done.

According to the present invention, for example, an active element is connected in series with a phase compensation capacitor, and its resistance is changed according to the state of the operational amplifier. For example, when the difference between the two inputs is large in the step response, the resistance of the active element connected in series to the phase compensation capacitor is increased to prevent a decrease in the slew rate, and the difference between the two inputs is reduced. Or when the operational amplifier approaches an equilibrium state, the resistance of the active element is reduced to move ω _P1 to a lower frequency side, thereby increasing the stability of the amplifier.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing the principle of the configuration of the present invention. OP represents an original operational amplifier for amplifying an input signal, VR represents an active element having a variable resistance characteristic, and receives an output of an amplifier 13 as differential control means. The resistance is changed according to the output. C1 is a phase compensation capacitance used for the operational amplifier OP. The amplifier 13 detects a voltage difference between the positive input and the negative input of the operational amplifier OP to control the resistance value of the variable resistance element VR, and outputs an output based on the difference to the VR.
Differential amplifier to be supplied to the An offset is given to the differential input of the amplifier 13, and the polarity thereof is, as described above, when the output voltage of the operational amplifier OP is equal to or more than the offset value with respect to the input voltage applied to its input terminal. The resistance value is set so that the resistance value of the active element is reduced when the output voltage of the operational amplifier OP becomes smaller than the offset value with respect to the input voltage applied to its input terminal. The optimum offset value is determined in consideration of the slew rate and settling in the step response of the operational amplifier OP.

The active element serving as the variable resistance element VR used in the present invention includes a field effect transistor and a bipolar transistor.

Here, the technical background of the present invention will be described while again explaining the operation of the conventional op-amp shown in FIG.

When the negative input terminal (hereinafter referred to as (-) input) and the output terminal of the operational amplifier shown in FIG. 6 are short-circuited, the positive input terminal of the operational amplifier (hereinafter, referred to as "-") is connected to the output terminal.
A voltage that is substantially equal to the voltage applied to the (+) input) appears, and becomes a so-called “voltage follower”. The case where a step input is applied to the (+) input terminal in a state where negative feedback is applied, such as a voltage follower, will be described as an example.

When an input whose change is faster than the maximum slew rate of the operational amplifier is given, the relationship between the output and the input of the operational amplifier is usually as shown in FIG. AB on the time axis
In the section (1), the balance of transistors forming a differential pair in the differential stage of the block 10 for amplifying the signal inside the operational amplifier and the voltage amplifying stage of the block 11 is lost, and the drain current of the MOS transistor M1 is almost supplied to the bias constant current source I3. The values are equal, and MOS transistor M2 is almost cut off. The drain current of the MOS transistor M1 becomes a charging current for the phase compensation capacitor C1 via the MOS transistors M3 and M4 forming a current mirror circuit together with the common-gate MOS transistor M5. In this state, FIG.
The relationship between the gain and the stability at the time of the small signal operation described in (1) does not hold, so that the oscillation and the stability do not deteriorate even without the phase compensation.

Furthermore, if there is no phase compensation capacitance C1, the voltage at point A in FIG. 6 rises at a very high speed. However, after time B in FIG. 2, the output of the operational amplifier is very close to the input voltage.
Since the differential stage and the like have almost returned to a balanced state, the above-described small signal theory holds. If the open loop gain at the frequency ω _P2 shown in FIG. 7 is not 0 dB or less, ringing occurs in the output of the operational amplifier. Generation or oscillation occurs. Therefore, after time B in FIG. 2, a phase compensation capacity of a certain value or more is required.

From the above, in the step response of the operational amplifier, it is preferable that the phase compensation capacitance is not provided when the voltage difference between the input and the output is large, and when the voltage difference between the input and the output is smaller than a certain value (the theory of small signal operation is This holds true, when the balance of the input transistors forming the differential pair of the input differential stage is not significantly disturbed, so as to form ω _P1 such that the gain at ω _P2 in FIG. 7 becomes 0 db. Phase compensation capacitance).

In the present invention, in order to effectively change the value of the capacitance, a variable resistor is connected in series with the phase compensation capacitor, and the value is changed. It is desirable that the value of the resistor connected in series to the phase compensation capacitor can be changed from infinity to 0, but in practice the object can be achieved if the value is not more than a certain value without being reduced to 0. The resistance to be made can be constituted by an active element such as a transistor. The ON resistance can be changed by changing the voltage applied to the gate when the transistor serving as the variable resistor is a MOS transistor, and by changing the voltage applied to the base when the transistor is a bipolar transistor.

FIG. 3 is a circuit diagram showing an embodiment of the present invention. 3, 1 is a power supply terminal, 2 is a positive input terminal, 3 is a negative input terminal, 4 is an output terminal, I1 to I6.
Is a constant current source for supplying a bias current in each circuit block, C1 is a phase compensation capacitor, V1 is a constant voltage source for supplying a gate bias voltage of the common gate transistors M5 and M6, and block 10 is a first input differential. Moving stage, block 1
Reference numeral 1 denotes a voltage amplification stage including a common-gate transistor, block 12 denotes an output buffer stage, and block 13 denotes a second input for controlling the ON resistance of a transistor M20 having a variable resistance function and connected in series to the phase compensation capacitor C1. The differential stage, block 14, is a load resistor nM that converts the output current from the input differential stage of block 13 to a voltage.
An OS transistor M19, the nMOS transistor M20 whose ON resistance changes in response to a voltage generated by the nMOS transistor M19, and the phase compensation capacitor C
1 is a circuit stage. In each block, M
1, M2, M5 to M8, M11, M12, M17 to M2
0 is an nMOS transistor, M3, M4, M9, M1
0, M13 to M16 are pMOS transistors.

The operation of the above circuit will be described below.

In the circuit shown in FIG. 3, the active element serving as the variable resistor is the nMOS transistor M20, and the block 1
3 is a differential control means, which detects a difference between the input voltage and the output voltage of the operational amplifiers 10, 11, and 12, converts the difference voltage into a current, and
The current is transmitted by current mirror circuits 13 to M18.
The transmitted current is converted to a voltage by using the nMOS transistor M19 having the gate-drain short circuit as a load resistance,
The converted voltage is applied to the gate of the OS transistor M20 as a value based on the difference between the input voltage and the output voltage of the operational amplifier.

Next, in the step response of the operational amplifier shown in FIG. 2, how the output voltage approaches the input voltage and from which the ON resistance of the nMOS transistor M20 starts to be changed will be described.

In the section from time A to time C in FIG. 2, the resistance of the nMOS transistor M20 is almost ∞, the slew rate of the operational amplifier is maximized, and from time C to time B, the ON resistance of the nMOS transistor M20 is In the vicinity of time B, the nMOS transistor M
It is desirable that the ON resistance of the capacitor 20 be sufficiently small, the capacitor C1 performs the function of phase compensation, the stability of the operational amplifier is improved, and the output of the operational amplifier quickly approaches the input voltage without ringing. Therefore, nMO
It is desirable that the second differential input stage of the block 13 in FIG. 3 that controls the ON resistance of the S transistor M20 intentionally has an offset voltage corresponding to ΔV in FIG.

The operation when the second differential input stage assumes that the input of the MOS transistor M11 has a higher polarity than the input of the MOS transistor M12 and has an offset by a voltage of ΔV will be described.

In the step response as shown in FIG. 2, the input voltage and the output voltage of the operational amplifier are substantially equal until time A, so that the MO connected to the (+) input in FIG.
Since the respective voltages of the input of the S transistor M12 and the input of the MOS transistor M11 connected to the (-) input are substantially equal and have the above-described offset voltage ΔV, the output of the block 13 of the second differential input stage is output. Is g
The output current of _m ΔV (g _m is the mutual conductance of the second input differential stage) appears, the voltage is converted by the MOS transistor M19, the voltage is applied to the gate of the MOS transistor M20, and the MOS transistor M20 receives the voltage based on the voltage. It exhibits ON resistance.

From time A to time C in FIG. 2, the (+) input voltage of the operational amplifier is higher than the output voltage (=
(−) Input voltage), the voltage is lower by ΔV or more than the (−) input voltage.
The transistor M12 is substantially cut off, and a current substantially equal to the constant current source I6 flows through the drain of the MOS transistor M11. Therefore, no current is supplied to the MOS transistor M19. Therefore, the gate voltage of the MOS transistor M20 also becomes 0V. The resistance of the MOS transistor M20 has a very large value.

Since the voltage difference between the (+) input and the output of the operational amplifier is smaller than ΔV from time C to time B in FIG. 2, the output of the block 13 of the second input differential stage in FIG. Indicates that the output current gradually appears and the MOS transistor M
A voltage starts to appear at the drain of 19 (= the gate of the MOS transistor M20), and the ON resistance of the MOS transistor M20 decreases. The operation after time B in FIG. 2 is the same as the period from the beginning to time A.

As described above, the MO in the step response
While the output voltage of the operational amplifier is transitioning due to a change in the resistance of the S transistor M20, the phase compensation capacitance is substantially disconnected from the output terminal of the voltage amplification stage 11, and the phase compensation function does not work. When the output voltage approaches the input voltage to some extent, the phase compensation capacitance functions gradually.

FIG. 4 shows the operational amplifier output waveform 100 of this embodiment having the same step response as that of FIG. 2, and the M in FIG. 3 at that time.
4 is a SPICE simulation result showing a gate voltage waveform 101 of an OS transistor M20. As can be seen from FIG. 4, only when the amplifier output is transitioning to the lower side
The gate voltage of S transistor M20 has decreased (therefore, the resistance of MOS transistor M20 has increased). Further, when the output approaches the input, the gate voltage of the MOS transistor M20 starts to increase and the phase compensation functions, and no ringing occurs in the output of the amplifier. FIG. 5 is a diagram showing a comparison with a conventional phase compensation type, in which a step response 104 of a conventional amplifier in which a resistor is not connected in series with a phase compensation capacitor, a variable ON-resistance MOS transistor M20 as a phase compensation capacitor. This is a step response 103 of the embodiment of the present invention in which the control amplifier is added and the amplifier main body is not changed. It can be seen that the slew rate and settling of the amplifier have been improved.

FIG. 3 shows an embodiment of the present invention.
The S transistor M20 is not limited to an element as long as it is an active element whose ON resistance value is variable according to its input.

The block 13 of the second input differential stage in FIG. 3 outputs a voltage or a current for changing the resistance value of the variable resistance element connected in series to the phase compensation capacitor, and the output is the output of the operational amplifier. The circuit is not limited to the one shown in FIG. 3 as long as the circuit compares the voltages of the input and the (+) input and has a value corresponding to the magnitude. The polarity of the offset (corresponding to ΔV in FIG. 2) when comparing the output voltage of the operational amplifier and the (+) input voltage is set in series with the phase compensation capacitance during the transition period of the operational amplifier output in the step response of the amplifier. The resistance value of the connected variable resistance element is large,
The setting may be such that the output becomes smaller when the output of the operational amplifier approaches the input. The offset values are determined by transistors M11 and M12, M13 and M14, M15 and M16, M
A desired value can be appropriately set by changing the size of a pair of transistors such as 17 and M18 or changing the value of a resistor connected to the source.

[0041]

As described above, according to the present invention,
The slew rate and settling in the step response of the operational amplifier are improved without changing the circuit configuration of the operational amplifier, constants such as transistor size, resistance, and capacitance.
The g _m open loop gain (transconductance) and an operational amplifier of the first stage input transistor of the operational amplifier than conventional it becomes possible to increase, thus low noise, and also possible to improve important characteristics of the operational amplifier and high-precision output Become.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the configuration of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between an output and an input of an operational amplifier.

FIG. 3 is a circuit configuration diagram showing one embodiment of the present invention.

FIG. 4 is a diagram showing a SPICE simulation result showing an operational amplifier output waveform of the present invention as a step response and a gate voltage waveform of a MOS transistor M20 at that time.

FIG. 5 is a characteristic diagram showing a comparison between the present embodiment and a conventional phase compensation type.

FIG. 6 is a circuit configuration diagram showing a configuration example of a conventional operational amplifier.

FIG. 7 is a characteristic diagram showing a frequency characteristic of an open loop voltage gain of the operational amplifier.

[Explanation of symbols]

Reference Signs List 1 power supply terminal 2 positive input terminal 3 negative input terminal 4 output terminal I1 to I6 constant current source C1 phase compensation capacitance V1 constant voltage source a block (first input differential stage) b block (voltage amplification stage) c block (Output buffer stage) d block (second input differential stage) e block M1, M2, M5 to M8, M11, M12, M17 to M
20 NMOS transistors M3, M4, M9, M10, M13 to M16 PMOS
Transistor

Claims (4)

[Claims] An operational amplifier having a phase compensation capacity;
Based on a difference between the active element connected in series with the phase compensation capacitor and having a variable resistance value and the input of the operational amplifier means,
An operational amplifier, comprising: differential control means for changing a resistance value of the active element. 2. The operational amplifier according to claim 1, wherein
The differential control means increases the resistance value of the active element when an offset is given to the differential input and there is a difference equal to or more than the offset value between the two inputs of the operational amplification means, An operational amplifier for reducing the resistance of said active element when the difference between the two inputs of said means is less than said offset value. 3. The operational amplifier according to claim 1, wherein said active element is a field effect transistor, and an output terminal of said differential control means is connected to a gate of said field effect transistor. An operational amplifier. 4. The operational amplifier according to claim 1, wherein said active element is a bipolar transistor, and an output terminal of said differential control means is connected to a base of said bipolar transistor. Operational amplifier.