JPS6123403A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To widen the input voltage range and to attain ease of offset adjustment by changing a control voltage of a sub load element connected in parallel with a load element of a differential amplifier pair. CONSTITUTION:Load MOS13, 14 are formed by connecting a load MOS13a and a sub load MOS13b, and a load MOS14a and a sub load MOS14b respectively in parallel. Then an inverting input terminal 1 and an output terminal 3 are connected, a level of a non-inverting input terminal 2 is brought into a ground potential to change a voltage impressed to an offset adjusting terminal 4b thereby adjusting a voltage at the terminal 3 to be zero. Thus, the control voltage of the MOS14b is changed and the current of the MOS14b corresponds to the increase/ decrease in the current of the amplifier circuit comprising drive MOS12, MOS 14a, 14b. On the other hand, the current of the other amplifier circuit changes reversely and the offset adjustment is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a differential amplifier circuit, and particularly to a differential amplifier circuit suitable for performing offset adjustment well.

[Background of the invention]

As an example of a conventional monolithic differential amplifier circuit with offset adjustment, there is a CMO8 amplifier circuit having a circuit configuration as shown in FIG. In Figure 1, 1 is an inverting input terminal, 2 is a non-inverting input terminal, 3 is an output terminal, 4a and 4b are offset adjustment terminals, 5 is a high potential power supply voltage terminal, 6 is a low potential power supply voltage terminal, and blue current source 10, drive MO8II,
12, the load MOS 13.14 and the resistor 15.16 constitute a first amplification stage, the constant current 20 and drive MO821 constitute a second amplification stage, and the constant current source 30 and drive MO
831 constitutes a source follower type output stage, and a frequency compensation capacitor 32 is further provided.

Offset adjustment is performed using the load MO81 as shown in Figure 1.
A variable resistor is connected externally to the offset adjustment terminals 4a and 4b to maintain balance so that the potentials at the respective connection points of the circuit in which resistors 15 and 16 are connected in series with terminals 3 and 14 are equal. be.

However, for offset adjustment the load MO813.14
By connecting resistors 15 and 16 in series to each, the voltage shared by the loads MO815 and 16 increases, and the drive M
This has the disadvantage that the operating range of o511 and o512 is narrowed, and as a result, the range of input voltage that can be handled is narrowed. That is, the configuration shown in FIG. 1 has a problem in that it cannot handle quiescent voltage when operated with a single power supply.

[Purpose of the invention]

The present invention has been made in view of the above, and its purpose is to provide a wide input voltage range, and also to be able to perform offset adjustment favorably. An object of the present invention is to provide a differential amplifier circuit.

[Summary of the invention]

The present invention is characterized by a configuration in which a sub-load element is connected in parallel to one or both load elements of a differential amplifier pair of a differential amplifier circuit, and the control voltage of one or both of the sub-load elements is made variable. That's the point.

[Embodiments of the Invention] The present invention will be described in detail below with reference to the embodiments shown in FIGS. 2 to 4, 6, and 7, and FIG. 5.

FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals and will be explained here. In FIG. 2, the load MO813,1 in FIG.
4 as load MO813a and load-resistant MO813b, respectively.
The load MO 814a and the load-resistant MO 814b are connected in parallel instead, and these are connected as shown in the figure to eliminate the resistors 15 and 16. In addition, the drive MO
811 and 12 are of P-channel type, and the others are of N-channel type. Also, in the drive MO831 where the substrate electrode is not shown, the P-channel type is connected to the low potential power supply voltage terminal 5, The N-channel type is connected to the low potential power supply voltage terminal 6. And load MO81
When setting the dimensions of 3a, 14a and load-resistant MO813b, 14b, they may be divided so that they have the dimensions of load MO813, 14 in Fig. 1, and are the same as load MO813, 14. Dimensional load MO
813a and 14a have load-bearing MO813b.

14b may be added, however, in this case, it is necessary to make only the gate width dimension variable and to fix the gate length to the same dimension.

Next, an offset adjustment method will be explained.

After connecting the inverting input terminal 1 and the output terminal 3 and setting the non-inverting input terminal 2 to the ground potential, the voltage applied to the offset adjustment terminal 4b is changed so that the voltage at the output terminal 3 becomes zero.

By such offset adjustment operation, the load MO814
Since the control voltage V of the load-resistant MO 814b changes in parallel to a, the current 1. □ is M
Considering the operation in the saturation region of the OS, it will change according to the relationship of the following equation, and the first
Amplification circuit of the amplification stage (drive MO812, load MO8j4
a, the portion consisting of the load-resistant MO 814b).

Here, β; process constant W/L of sub-load MO814b;
Dimensional ratio v of load-bearing MO814b? ;Threshold voltage of load-resistant MO814b, that is, ■
When , increases, the current of the amplifier circuit on the offset adjustment terminal 4b side increases, and when , decreases, the current I Rum
decreases. On the other hand, the current flowing through the amplifier circuit on the side opposite to the side where the offset adjustment terminal 4b is located changes in the opposite direction to that in the above case. As a result, the pair of amplification ports and paths on both sides of the first amplification stage can be balanced, and the offset can be adjusted.

In addition, the input voltage on the low potential side that can be applied to the inverting input terminal 1 or the non-inverting input terminal 2 is
■□ threshold voltage respectively. , load MO813a and load-resistant MO813b, and load MO814a and load-resistant M
If the threshold voltage of O814b is vl, then MO
In the range where S operates in the saturation region, it is Ivy. 1-v
It can handle up to the value of o. Therefore, since the input voltage depends only on the threshold voltage of the MOS used, the voltage amplitude loss remains at a minimum despite offset adjustment, and a wide operating range can be obtained. and,
IV,,1. If v□ is selected to have approximately the same threshold voltage value, the substrate bias effect will be added to drive MO8II and 12, so that 1v01 will be large.
vt, l −V? It fully satisfies the condition of L > 0 and can handle up to 0 input voltage in single power supply operation,
A wide input voltage range can be obtained.

According to the embodiment of the present invention described above, the first
Load MO813a, 14 of the amplifier circuit that is a pair of amplifier stages of
a and a load-resistant MO813b, respectively.

14b is provided in parallel, and its load-resistant MO813b.

By controlling 14b, the currents of the respective amplifier circuits can be varied in opposite directions, so that offset adjustment is possible.

In addition, load-resistant MO81 added for offset adjustment.
3b and 14b are the loads MO813a and 1 of each of the above amplifier circuits.
4a, so there is no voltage loss and the input voltage range can be widened.

In the embodiment shown in FIG. 2, the offset is adjusted by controlling the load-resistant MO 814b, but as shown in FIG. 3, the other load-resistant MO 813b is also provided with an offset adjustment terminal 4a. The offset adjustment may be performed by a second person, and the same effect can be obtained.

Moreover, FIG. 4 is a circuit diagram corresponding to FIG. 2 showing another embodiment of the present invention, and the same parts as in FIG. 2 are indicated by the same symbols. The difference from Fig. 2 is that the load capacity MO814b is MO81
4c constitutes a current mirror, and offset adjustment terminal 4
The reason is that it is controlled by injecting a current into b. The effect of this is that the current in the first amplification stage can be made very small by the current mirror, and when comparing the circuits of FIG. 2 and FIG. In the figure, V, 1. is the converted value of current) and the voltage obtained at output terminal 3. Which relationship is )
The result is as shown in FIG. In FIG. 5, curve a is for the circuit shown in FIG. 2, curve 5 is for the circuit shown in FIGS.

/V-g* is preferably smaller, and the case of 5 curves is better. This means that the range of V a t t can be widened; This shows that even if vo is changed significantly, the change in vo can be made small. Therefore, compared to the circuit shown in FIG. 2, fine adjustment during offset adjustment is easier, and offset adjustment can be performed more stably. Moreover, in this case, as in the case of the circuit shown in FIG. 2, no voltage amplitude loss occurs in the first amplification stage due to offset adjustment, so that a wide range of input voltages can be handled.

Moreover, FIG. 6 shows a second @ showing still another embodiment of the present invention.
In this circuit diagram, the same parts as in FIGS. 2 and 4 are designated by the same reference numerals. The differences between Figure 6 and Figure 4 are as follows:
A resistor 4 is connected between the MO814c and the offset adjustment terminal 4b.
It is at the point where 1 is connected. According to FIG. 6, the offset adjustment in FIG. 4 was performed using a current, but is now performed using a voltage, and the effect is the same.

In addition, in all the embodiments described above, P-channel type MO8 is used as the drive MO8 811, 12 of the first amplification stage, but it is also possible to use N-channel type MO8. It is shown in FIG. In Fig. 7, 100, 200°30 are constant current sources, 101, 102
is the drive MO8, 103, 104 of the first amplification stage is the load M
O8, 105, 108 are each load MO8103゜1
The load-resistant MO8, 201 provided in parallel with 04 is the drive MO8, 31 of the second amplification stage, and the drive MO8, 32 of the output stage is a capacitor. The offset adjustment terminal 4a is taken out from a load-resistant MO 8105 connected in parallel to the load MOS 103 on the self-bias side. In this case, as in the previous embodiments, the load-resistant MO 8106 may be controlled, and the same effect can be obtained in either case. In this case, in single power supply operation, the constant current source 10
0 is attached to the low-potential power supply voltage terminal 6 side, it cannot handle a 0-input voltage, but since the range on the high-potential voltage side is expanded, the effect of widening the input voltage range can be obtained. Further, the circuit shown in FIG. 7 has the same effects as those shown in FIGS. 4 and 6.

Further, although the differential amplifier circuit described so far uses the CMO8, it may be configured using a single channel MO8, bipolar transistors, etc., and the same effect can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the input voltage range can be widened, and offset adjustment can be performed satisfactorily.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional monolithic differential amplifier circuit with offset adjustment, FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit of the present invention, and FIGS. 3 and 4. 6 and 7 are circuit diagrams corresponding to FIG. 2 showing other embodiments of the present invention, and FIG. 5 shows the voltage V0. ．． FIG. 3 is a diagram showing a comparison of the relationship between the voltage V obtained at the output terminal and the voltage V obtained at the output terminal. 1... Inverting input terminal, 2... Non-inverting input terminal, 3...
...output terminal, 4a, 4b...offset adjustment terminal,
5... High potential power supply voltage terminal, 6... Low potential power supply voltage terminal, 10.20, 30. j-00,200...constant current source, 11.12,21,81,101,102,20
1... Drive MO5, 13g, 14a, 103, 104
...Load MO8, 13b, 14b, 105, 106'
fy5fl.

Claims (1)

[Claims] 1. In a differential amplifier circuit having a differential amplifier pair, in order to perform offset adjustment of the differential amplifier circuit, an auxiliary load element is provided as one or both load elements of the differential amplifier pair. What is claimed is: 1. A differential amplifier circuit, characterized in that the sub-load elements are connected in parallel and have a configuration in which the control voltage of one or both of the sub-load elements is variable. 2. The auxiliary load element is configured to have elements of the same type connected to form a current mirror, and to perform offset adjustment by varying the current flowing through the elements of the same type. The differential amplifier circuit according to item 1.