JPS58220508A - Operational amplifier - Google Patents

Abstract

PURPOSE:To operate stably a titled amplifier by reducing a phase delay in a high frequency area even if a phase compensating circuit is not provided additionally, by providing an input to source terminals of p and n channel type outputting MOS transistors, respectively, and connecting both its drain terminals to the output terminal. CONSTITUTION:The input part executes an operation for converting the voltage to a current, is constituted so that only the output stage obtains the voltage gain, and also the output stage consists of a complementary cascode amplifying circuit, therefore, input capacity of a transistor 29 and 32 is small, voltage of a connecting point (a) and a' can be varied at a high speed, and also since impedance of the connecting point (a) and a' is low, a phase delay of a signal generated by a current conversion of the input part is extremely small. The output stage generates a phase delay in a high frequency area, but the amplifying stage is one stage and its phase delay is 90 degrees at the most, therefore, it is possible to execute the feedback stably without adding any phase compensating circuit. Also, the offset voltage combines the input part and the output stage and realizes a function of a differential amplifying circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS transistor operational amplifier that reduces phase delay by integrating a differential amplifier circuit and an output circuit, and operates stably even in a high frequency range.

Figure 1 shows an example of a circuit diagram of a conventional operational amplifier suitable for wideband amplification. Source follower circuit of phase compensation buffer and transistors 8, 9 and 1
Output stage cascode circuit consisting of 0 and phase compensation capacitor 1
1. Note that 12 is an inverting input terminal;
13 is a non-inverting input terminal, 14 is an output terminal, 15 and 16
indicates a power supply terminal, and VB and VB□ are bias voltages that determine the operating point of each amplification stage.

In the operational amplifier configured in this way, the voltage gain is obtained by the differential amplifier circuit made up of transistors 1 to 5 and the output stage made up of transistors 8, 9, and 10. The phase delay for high frequencies reaches 90 degrees at each stage, and the total is 18 degrees.
If it exceeds C, when this circuit is applied to a negative feedback circuit, it will cause unstable operation such as oscillation in a high frequency region. A phase compensation circuit is required for stability in the high frequency range, which is achieved here by limiting the frequency band of the differential amplifier circuit. Therefore, even if an attempt is made to widen the frequency band of the differential amplifier circuit by adopting a cascode circuit in the output stage and reducing the input capacitance, the phase compensation capacitor 11
The disadvantage is that the effect decreases due to the addition of , making it difficult to realize an operational amplifier that operates stably over a wide band.

In addition, the source follower circuit of the phase compensation circuit needs to have a wide band, which has the disadvantage of increasing power consumption.Furthermore, it requires a capacitive element, which complicates the manufacturing process when it is built into an integrated circuit. It also had the disadvantage of being uneconomical.

In order to solve these drawbacks, the present invention aims to provide an operational amplifier that can stably operate with little phase delay in a high frequency range without adding a phase compensation circuit.

FIG. 2 shows the circuit configuration of one embodiment of the present invention.
2 is an inverting input terminal, 13 is a non-inverting input terminal, 14 is an output terminal, 15 and 16 are power supply terminals as in the case of FIG. 1, 21 to 28 are transistors constituting the input stage, and 29 32 are transistors constituting the output stage, and '811 VB2' B3 and VB4 are bias voltages that determine the operating points of each part.

Here, P-channel type and N-channel type transistors 25 and 26 have the functions of first and second constant current sources, and N-channel type transistor pair 22 and 27 and P-channel type transistor pair 23 and 28 transistors 27 and 28 form a differential pair with transistors having the same characteristics, but transistors 27 and 28 do not have a load element and are directly connected to the power supply terminal 1.
5 and 16.

Depending on the input potential difference between the inverting input terminal 12 and the non-inverting input terminal 13, the current flowing through the pair of transistors 22 and 27 and 23 and 28 forming the differential pair changes.

Current changes in transistors 22 and 23 are transmitted to P-channel type and -N-channel type transistors 21 and 24.

P-channel type transistors 21 and 29 and N-channel type transistors 24 and 32 each constitute a current mirror circuit, so transistor 21 (or 24
) and the current of the transistor 29 (or 32) take a constant ratio determined by the transistor size ratio,
Therefore, the ratio between the current of transistor 22 (or 23) and the current of transistor 29 (or 32) is always constant.

Otherwise, when the voltage at non-inverting input terminal 13 becomes higher than the voltage at inverting input terminal 12, the current in transistor 22 increases and the current in transistor 29 also increases. Also, the current of the transistor 23 decreases, and -
The current in transistor 32 also decreases.

The current changes of the transistors 29 and 32 cause the terminal voltage of the output terminal 14 to rise together using the P-channel type and N-channel type transistors 30 and 31 as loads, converting it into a large voltage change, and realizing a large differential voltage gain. can.

If an in-phase voltage change is applied to the inverting input terminal 12 and the non-inverting input terminal 13, equal currents flow through the transistors 22 and 27 and 23 and 28, and the transistor 21
No current change occurs in and 24, and a large common-mode signal rejection ratio can be achieved.

As is clear from the above explanation of the operation, the operational amplifier of the present invention is configured such that the input section converts voltage into current, only the output stage obtains voltage gain, and the output stage is a complementary cascode. Since they constitute an amplifier circuit, the input capacitance of the transistors 29 and 32 is small, the voltages Va and va' at the connection points a and a' can change rapidly, and the impedance at the connection points a and a' is low. Therefore, the phase delay of the signal caused by current conversion at the input section is extremely small. Note that a phase lag occurs in the high frequency range in the output stage, but since the amplification stage according to the present invention is one stage and the phase lag is at most 90 degrees, it is possible to stably apply feedback without adding any phase compensation circuit. It is possible.

Offset voltage of an operational amplifier is generally caused by imbalance in a differential amplifier circuit. In the example shown in FIG. 2, the input section and output stage are combined to realize the function of a differential amplifier circuit. Therefore, in order to reduce the offset voltage, in addition to using transistors 22 and 27 and transistors 23 and 28 forming the differential pair with the same characteristics, it is necessary to use transistors with the same characteristics. Operating point current of 25, 26 S21+ S24+ S29+ 832...
・Transiter 21.

24, 29. Dimension ratio of 32 It should be designed under the following conditions.

As explained above, the phase delay of the operational amplifier of the present invention is small even in a high frequency range, and it operates stably without a phase compensation circuit, so it has the advantage that a wide band operational amplifier can be easily realized.

In addition, since a phase compensation circuit is not required, it has the advantage of being compact and low power.Furthermore, since the input section has no voltage gain, there is no increase in input capacitance due to the Miller effect, and the input capacitance is extremely small. It also has the advantage of

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a circuit diagram of a conventional operational amplifier, and FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention. 1 to 5...Transistors forming a differential amplifier circuit, 6, 7...Transistors forming a source follower circuit of a phase compensation buffer, 8,9.10
...Pa...transistor that constitutes the cascode circuit of the output stage, 11 -Pa°°...phase compensation capacitor, 12.
......Inverting input terminal, 13...
・Non-inverting input terminal, 14...output terminal,
15.16......Power terminal, 21~2
8・°゛... Transistor forming the input stage, 29
~32...Transistor forming the output stage, VDI~vB4...Bias voltage. .

Claims (1)

[Claims] A pair of N-channel type transistors having a common source terminal and forming a differential pair MO8) A pair of transistors and a P-channel type MO8) Having a transistor, each having a common source terminal connected to the first and second constant current sources Connect to the above N and P
One gate terminal of the channel type pair MO8 transistors is connected to an inverting input terminal, and the other gate terminal is connected to a non-inverting input terminal, respectively, and the N and P channel type pair MO8 transistors are connected to each other.
The current output of the S transistor is input to the source terminals of P and N channel type output MOS transistors whose gate terminals are biased using a current mirror circuit, and the drain terminals of the output MO8) transistors are both output terminals. An operational amplifier characterized by being connected to.