JP3052902B2 - Cascode circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cascode circuit, and more particularly, to a cascode circuit that enables a wide band operation.

[0002]

2. Description of the Related Art Among conventional cascode circuits of this kind,
There is a circuit called a "regulated cascode circuit", and for example, reference is made to the description of JP-A-7-86842 by the same inventor as the present application.

FIG. 4 is a diagram showing a configuration of a cascode circuit described in the above publication. Referring to FIG. 4, this conventional cascode circuit includes a series connection circuit of transistors 1 and 2 connected in series between an output terminal 71 and a lower power supply potential GND, and an input terminal 70 to which the gate electrode of transistor 1 is connected. And the source electrode is connected to the series connection point A of the transistors 1 and 2, and the higher power supply potential VDD
And a transistor 3 connected in series between the lower power supply potential GND and a gate grounded at the series connection point, and transistors 48 and 49 having a polarity opposite to that of the transistors 1, 2, and 3, and a higher power supply potential VDD.
, A constant current source 43 that is a load of the transistor 49 and is connected to the lower power supply potential GND, and a drain electrode of the transistor 49 that is a phase compensation element and the lower power supply potential GND. And a capacitor 59 connected to the current mirror circuit. The input terminal B of the current mirror circuit is connected to the drain electrode of the transistor 3 and the output terminal C is connected to the gate electrode of the transistor 2.

[0004] The cascode circuit having the above-described configuration includes a gain stage 1 via transistors 3 → 48 → 49 → 2 → 3.
It has a negative feedback loop of stages. For this reason, the drain potential of the transistor 1 is firmly fixed. Therefore, the drain current of the transistor 1 determined by the voltage supplied to the voltage input terminal 70 is hardly affected by the DC potential of the current output terminal 71. Therefore, the output impedance of the cascode circuit becomes very high.

On the other hand, the lowest output signal voltage is determined by the lower limit value of the operating voltage of the current output terminal 71, and is substantially equal to the drain potential VD1 of the transistor 1. Now, the gate-source voltages of the transistors 3 and 6 are respectively VGS3 and VG
In the case of S6, VD1 is given by the following equation (1).

VD1 = VGS6-VGS3 (1)

Therefore, by adjusting VGS3 and VGS6, the drain potential VD1 of the transistor 1 can be set to about 0.5 V, which is the saturation voltage of the transistor.

The minimum operating power supply voltage is a value obtained by adding the saturation voltage of the transistors 1 and 49 and the gate-source voltage of the transistor 2 and is about 2V.

As described above, the cascode circuit shown in FIG. 4 has a high output impedance and a low minimum output signal voltage and a minimum operating power supply voltage. For this reason, if the circuit is used for the amplification stage of the operational amplifier, a low power supply voltage operation is possible and a large amplification degree can be obtained.

[0010]

The frequency characteristic of the conventional cascode circuit shown in FIG. 4 is determined substantially by the frequency characteristic of the negative feedback loop passing through the aforementioned transistors 3 → 48 → 49 → 2 → 3. .

Next, the open loop voltage gain of the negative feedback loop will be considered.

The broken line in FIG. 2 shows the characteristics of the conventional circuit. Here, the band is determined by 2
This is the next pole p2 '. The reason for this is that in order to secure a phase margin, it is necessary to arrange p2 'in a high frequency region at least twice the unity gain frequency.

When the transconductance of the transistor 48 is represented by gm48 and the capacitance generated between the gate of the transistor 48 and the higher power supply potential VDD is represented by Cs ', p2' is given by the following equation (2).

P2 '=-gm48 / Cs' (2)

Here, Cs' is the gate of the transistors 48 and 49 constituting the current mirror circuit.
Assuming that the capacitance between the sources is dominant and the mirror ratio is 1 to 1, the capacitance between the gate and the source of the transistor 48 is approximately 2%.
Double.

Accordingly, in order to widen the cascode circuit, the transconductance gm4
8 or the capacitance Cs' must be reduced. In order to reduce Cs' without lowering the transconductance, the channel length must be reduced. However, if the channel length of the transistor 48 (therefore, the transistor 49 that forms a current mirror circuit with the transistor 48) is extremely short, relative accuracy cannot be obtained, and the mirror ratio deteriorates.

When the bias current of the transistor 48 (and therefore the transistor 49) is increased, the feedback voltage gain at DC decreases. This is because the open loop voltage gain at DC is determined substantially by the transconductance of the transistor 49 and the output impedance of the transistor 49 and the constant current source 43.

As a result, the feedback amount of the negative feedback loop decreases, and the output impedance of the cascode circuit decreases.

Therefore, this circuit has a problem that when the band is widened, the output impedance of the circuit is reduced.

Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art, and the object is to
It is an object of the present invention to provide a cascode circuit having a wide band and a high output impedance in a MOS process.

[0021]

In order to achieve the above object, a cascode circuit according to the present invention comprises: a first transistor having a drain electrode led to an output terminal; and a source electrode having a source electrode of the first transistor. A second transistor connected and grounded at the gate, a current source for drain load of the second transistor, a drain electrode connected to the first and second source electrodes, and a gate electrode led to an input terminal. And a source-grounded third transistor, a gate electrode of which is connected to a drain electrode of the second transistor, and a source-grounded first transistor.
A fourth transistor having a polarity opposite to that of the second and third transistors, and a fifth transistor which is a drain load and is diode-connected and grounded at a source; Are connected to a gate electrode of the first transistor.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the cascode circuit of the present invention, a first transistor (2 in FIG. 1) having a drain electrode led to an output terminal and a source electrode of the first transistor are connected to the first transistor. Connected to the source electrode,
And a second transistor whose gate is grounded (3 in FIG. 1)
A drain load current source of the second transistor (40 in FIG. 1); a drain electrode connected to the source electrodes of the first and second transistors; a gate electrode led out to the input terminal; The third transistor (1 in FIG. 1) and the gate electrode are connected to the drain electrode of the second transistor (3 in FIG. 1) and are grounded at the source, and are opposite to the first, second, and third transistors. A fourth transistor having a polarity (4 in FIG. 1) and a fifth transistor (5 in FIG. 1) which is a drain load of the fourth transistor and is diode-connected and grounded at the source; The drain electrode of the fourth transistor (4 in FIG. 1) is connected to the gate electrode of the first transistor (2 in FIG. 1).

In the embodiment of the present invention, in order to fix the drain potential of the third transistor which is an input transistor, a second transistor whose gate is grounded,
A load current source, a source-grounded fourth transistor, a diode-connected fifth transistor,
A phase compensating element, which constitutes an amplifier circuit including the gate electrode of the fourth transistor and a capacitor (50 in FIG. 1) connected to the higher power supply potential, and a feedback output from the amplifier circuit is an output transistor. First transistor (2 in FIG. 1)
Back to the gate electrode. Further, a voltage generating circuit for fixing the gate potential of the second transistor (3 in FIG. 1) is replaced with a diode-connected sixth transistor (FIG. 1).
6) and a constant current source (41 in FIG. 1).

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention. Referring to FIG. 1, the cascode of this embodiment has an output terminal 71 and a lower power supply potential GND.
A series connection circuit of transistors 1 and 2 connected in series, an input terminal 70 to which the gate electrode of transistor 1 is connected, a source electrode connected to series connection point A, and a higher power supply potential VDD and a lower power supply A transistor 3 connected in series between the potentials GND and grounded at the gate by the direct connection point; a constant current source 40 which is a load of the transistor 3 and is connected to the higher power supply potential VDD; A transistor 4, which is connected to the electrodes and has a polarity opposite to that of the transistors 1, 2, and 3; and a load of the transistor 4, which is connected to the lower power supply potential GND, and the transistors 1, 2, and 3
A diode-connected transistor 5 having the same polarity as
And a capacitor 50 that is a phase compensation element and is connected to the gate electrode of the transistor 4 and the higher power supply potential VDD. The gate electrode of the transistor 4 is connected to the drain electrode of the transistor 3. Are connected to the gate electrode of the transistor 2.

Here, the frequency characteristics of the feedback loop, particularly, the open loop voltage gain will be analyzed. The characteristic shown by the solid line in FIG. 2 is the characteristic in the circuit of this embodiment.

In the circuit of this embodiment, the band is determined by the secondary pole p2, as in the prior art shown in FIG.
It is. It is the same as the above-mentioned prior art that p2 needs to be arranged in a high band in order to widen the circuit bandwidth.

Now, the transconductance of the transistor 5 is gm5, and the capacitance between the connection point between the drain electrode and the gate electrode of the transistor 5 and the lower power supply potential GND is Cm.
When represented by s, p2 is given by the following equation (3).

P2 = -gm5 / Cs (3)

Therefore, as in the prior art, in order to increase the bandwidth of the circuit, it is necessary to increase the transconductance gm5 of the transistor 5 or to reduce the capacitance Cs.

In the present embodiment, Cs is dominated by the gate-source capacitance of the transistor 5.

As a result, the value of the capacitance Cs is about 1/2 of the capacitance Cs' in the prior art shown in FIG. However,
This is a case where a transistor having the same size as the transistor 5 is used as the transistor 48 and the transistor 49 in the related art shown in FIG.

Therefore, assuming that the transconductance gm5 is equal to the transconductance gm48 of the prior art shown in FIG. 4, p2 is about twice as large as p2 ', so that the circuit of the present embodiment has the same phase margin. Is about twice that of the prior art shown in FIG.

Next, consider increasing the value of the transconductance gm5 of the transistor 5 by increasing the bias current of the transistor 5. This current increase can be achieved by increasing the bias current of transistor 4, but the effect of the current increase on the open loop voltage gain will be examined.

The open loop voltage gain at DC in this embodiment is determined substantially by the transconductance of the transistor 3 and the output impedance of the transistor 3 and the constant current source 40.

Here, since these values do not change by increasing the bias current of the transistor 4, there is no effect on the gain.

As a result, it is possible to independently increase the bandwidth of the circuit and increase the output impedance.

On the other hand, the lowest output signal voltage is determined by the lower limit value of the operating voltage of the current output terminal 71, and is substantially equal to the drain potential VD1 of the transistor 1. Now, the gate-source voltages of the transistors 3 and 6 are respectively VGS3 and VG
In the case of S6, VD1 becomes the following equation (4) as in the related art.

VD1 = VGS6-VGS3 (4)

Therefore, by adjusting VGS3 and VGS6, VD1 can be set to about 0.5 V, which is the saturation voltage of the transistor.

The minimum operating power supply voltage is approximately 2 V as the sum of the saturation voltage of the transistors 1 and 4 and the gate-source voltage of the transistor 2.

From the above results, it can be seen that both values are exactly the same as in the conventional example.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention. Referring to FIG. 3, a circuit of the present invention is used in an output stage of an operational amplifier circuit, and is a balanced output type circuit. Referring to FIG. 3, cascode circuits 101 and 102 including transistors 13, 14, 25, 26, 29 to 32, a capacitor 52, and transistors 36 to 39, 42, 43, and a capacitor 53 are provided in the first embodiment. The transistor 1 corresponds to the cascode circuit shown.
In the first embodiment, the cascode circuits 100 and 103 composed of the capacitors 51, 42, 24, 27, 28, the capacitor 51 and the transistors 40, 41, 44 to 47, and the capacitor 54 are P-channel type and N-channel type. MO of mold
This corresponds to a cascode circuit configured by exchanging the polarity of the S transistor.

That is, this operational amplifier circuit includes cascode circuits 100 to 103 at the output stage.

More specifically, the cascode circuit 101
A series connection circuit of transistors 25 and 26 connected in series between the output terminal 74 and the lower power supply potential GND;
A transistor 3 having a source electrode connected to the series connection point A, connected in series between the higher power supply potential VDD and the lower power supply potential GND, and having its gate grounded by its direct connection point
0, the load of the transistor 30, the transistor 29 connected to the higher power supply potential VDD, and the gate electrode connected to the drain electrode of the transistor 30, which have the opposite polarity to the transistors 25, 26, and 30. The transistor 32 and the load of the transistor 32, which are connected to the lower power supply potential GND,
6, a diode-connected transistor 31 having the same polarity as that of each of the transistors 6 and 30; and a capacitor 52 which is a phase compensation element and is connected to the gate electrode of the transistor 32 and the higher power supply potential VDD. The gate electrode of the transistor 32 is connected to the drain electrode of the transistor 30, and the drain electrode of the transistor 32 is connected to the gate electrode of the transistor 26.

The cascode circuit 102 has the same configuration as that of the cascode circuit 101, and the reference numeral 2
5 and 43, 26 and 42, 29 and 39, 30 and 38, 31
And 37, 32 and 36, 52 and 53, and connection points A and A ', respectively.

The cascode circuit 100 is a P-channel type and N-channel type MO of the cascode circuit 101.
The configuration is such that the polarity of the S transistor is switched.

Further, the cascode circuit 103 has the same configuration as the cascode circuit 100, and the reference numerals 21 and 47, 22 and 46, 23 and 45, 24 and 44, 2
7 and 41, 28 and 40, 51 and 54, connection points A 'and A "
Correspond respectively.

On the other hand, the input stage of this operational amplifier circuit comprises a constant current source transistor between the common source electrode of differential transistor pairs 33 and 35 connecting the gate electrodes to input terminals 72 and 73, respectively, and the lower power supply potential GND. 34 are connected. The drain electrodes of the differential transistor pairs 33 and 35 are cascode circuits 100 and 103, respectively.
Are connected to connection points A ′ and A ″.

Output terminals 74 and 75 are connected to lower power supply potential GND by transistors 25 and 26 and transistors 42 and 43, respectively. Transistor 23
The gate electrodes of 45 and 45 are supplied with the output potential of a constant voltage generating circuit in which diode-connected transistor 18 is driven at a constant current by transistor 17, while the gate electrodes of transistors 30 and 38 have diode-connected transistor 13. Is supplied with an output potential of a constant voltage generating circuit driven by a transistor 14 at a constant current.

Transistors 28 and 29 and 39 and 4
A bias current value of 0 means that these transistors are output transistors and the diode-connected transistor 1
The transistor 20 is driven by a constant current and fixed in a current mirror circuit having 9 as an input transistor.

On the other hand, the bias current values of the transistors 17, 20, 24, and 34 and 44 are determined by the transistor 15 in a current mirror circuit in which these transistors are output transistors and the diode-connected transistor 16 is an input transistor. Current driven and fixed.

Further, transistors 11 and 14 and 1
A bias current value of 5 indicates that these transistors are output transistors and that
It is driven and fixed by a constant current source 42 in a current mirror circuit having 0 as an input transistor.

The output terminals 74 and 75 are connected to the capacitive element 55
And 56 include switch elements 60 and 61 and 62 and 6
3, the common-mode feedback circuit is formed by selectively connecting the capacitance elements 57 and 58 in parallel.

The output potential of the constant voltage generating circuit in which the diode-connected transistor 12 is driven at a constant current by the transistor 11 is supplied to the in-phase feedback circuit, and the input terminal 76 is supplied with a reference potential from the outside.

With the above-described configuration, current consumption is greatly reduced, and a high gain and a wide band characteristic can be obtained with a low power supply voltage operation.

The operation of the operational amplifier circuit shown in FIG. 3 is similar to that of a normal operational amplifier circuit, and will not be described.

[0058]

As described above, according to the present invention,
Broadband and high output impedance of the circuit can be achieved independently, and the minimum output signal voltage (between output terminal and power supply or ground) can be about 0.5V even in a normal CMOS process as in the case of the conventional regulated cascode circuit. In addition, there is an effect that the minimum operation power supply voltage can be reduced to about 2V.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of one embodiment of the present invention and characteristics of a conventional cascode circuit as a comparative example.

FIG. 3 is a diagram showing a circuit configuration of another embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a circuit configuration of a conventional cascode circuit.

[Explanation of symbols]

 1 to 6, 10 to 49 Transistor 40 to 43 Constant current source 50 to 59 Capacity 60 to 63 Switch 70, 72, 73, 76 Input terminal 71, 74, 75 Output terminal

Claims (2)

(57) [Claims] A first electrode connected to an output terminal;
A second transistor whose source electrode is connected to the source electrode of the first transistor and whose gate is grounded, a current source for drain load of the second transistor, and a drain electrode of the first and second transistors. Connected to the source electrode of the second transistor, the gate electrode is led to the input terminal,
A source-grounded third transistor, a gate electrode connected to the drain electrode of the second transistor, and the source-grounded first, second, and third transistors.
A fourth transistor having a polarity opposite to that of the fourth transistor, and a fifth transistor which is a drain load of the fourth transistor and is diode-connected and grounded at the source. A cascode circuit, wherein an electrode is connected to a gate electrode of the first transistor. An output transistor and an input transistor connected in series between an output terminal and a second power supply, wherein a gate electrode of the input transistor is connected to an input terminal; A third transistor connected to one signal electrode and grounded at a gate; a load current source connected between a second signal electrode of the third transistor and a first power supply; A fourth transistor connected to a second signal electrode of the fourth transistor; a capacitor, which is a phase compensation element, connected between a gate electrode of the fourth transistor and the first power supply; A fifth transistor, which is a load and is diode-connected, forms an amplifier circuit, and outputs a feedback output from the amplifier circuit to the output transistor. Cascode circuit back to the gate electrode, characterized by comprising a voltage generation circuit for fixing the gate potential of the third transistor.