JPH01126811A - Common mode feedback circuit for full differential amplifier - Google Patents

Abstract

PURPOSE:To expand the output operating range by obtaining a common feedback without increasing stacked output stage transistors(TRs). CONSTITUTION:A 1st voltage controlled current circuit 100 giving a current proportional to a positive output terminal potential of full differential amplifiers Q21-Q33, a 2nd voltage controlled current circuit 200 giving a current proportional to a negative output terminal potential, a sum current voltage circuit 300 giving a current being the sum of output currents of the 1st and 2nd voltage controlled current circuits 100, 200, and a reference current transfer circuit 400 transferring a current proportional to the reference voltage are provided. Then the common mode output potential is controlled to be equal to the reference potential to feed back a current difference between the current of the sum current transfer circuit 300 and the current of the reference current transfer circuit 400 to a control electrode of TRs Q32-Q30 being active loads of the full differential amplifiers Q21-Q33. Thus, number of stages of TRs between 1st and 2nd power supplies VDD, VSS is decreased more than that of a conventional circuit. Thus, the operating range is widened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a common mode feedback circuit for a fully differential amplifier used in an operational amplifier of an electronic device.

(Prior art) The common mode feedback circuit of a fully differential amplifier is described in the technical book rAnalog MOS Integrated
Cjrcuits POR5IGNAL PROCES
It is described on page 225 of SING J. The circuit is shown in FIG. 3 and will be explained.

Input terminal 1 is supplied with a negative phase input, and input terminal 2 is supplied with a positive phase input. Input terminals 1 and 2 are connected to the gates of MOS transistors Ql and Q2. The transistors Ql and Q2 constitute a differential amplifier, and their sources are connected to the drain of the transistor Q13, the source of the transistor QL3 is connected to the second power supply line 3, and the gate is connected to the fourth bias potential terminal 4. It is connected. The drain of transistor Q1 is connected to the drain of transistor Q5, and the drain of transistor Q2 is connected to the drain of transistor Q6.

Transistor Q5. The drains of QB are connected to transistors Q7. Q8 are connected to the sources of transistors Q3. 'Connected to the drain of Q4. Transistor Q3. The source of Q4 is the first power supply line 5
connected to.

Transistor Q7. The drains of Q8 are connected to the positive output terminal 6. connected to the negative output terminal 7 and the transistor Q
9. QIO is connected to the drain of transistor Q9.
The sources of QIO are each transistor Q11.
connected to the drain of Q12, transistor Qll,
The source of Q12 is connected to the second power supply line 3.

The first bias potential VB1 is the transistor Q5゜QB
A second bias potential VB2 is applied to the gate of transistor Q7. A third bias potential VB3 is applied to the gate of transistor Q9. To the gate of QIO, the fourth bias potential VB4 is applied to the transistor Q13°Q11. Q1
2 gates.

In the above circuit, the positive output terminal 6 is connected to the gate of the transistor Q3, and the negative output terminal 7 is connected to the gate of the transistor Q4, forming a feedback path.

As a result, if the common mode potential of the positive and negative output terminals 6 and 7 is lower than the arbitrarily set potential, the transistor Q3
, the gate potential of transistor Q4 decreases, and the gate potential of transistor Q3. Q5
．． Q7. Q4. By increasing the current flowing through QB and QB, a feedback operation is obtained to raise the output potential, and the positive and negative output terminals 6,
If the common mode potential of transistor Q7 is higher than the arbitrarily set potential, the gate potential of transistors Q3 and Q4 increases,
Transistor Q3. Q5. Q7. Q4. Feedback operation is obtained to reduce the current flowing through QB and QB and lower the output potential.

(M1 point while the invention is trying to solve the problem) According to the above conventional common mode feedback circuit,
As many as five transistors are connected in series between the positive power supply VDD and the negative power supply vSS. For this reason, there is a problem that the output operating range becomes narrow. Furthermore, although this is done by adjusting the element area in order to set an arbitrary output potential, there is a problem in that the design combination is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a common mode feedback circuit for a fully differential amplifier that has a wide output operating range, allows easy output potential setting, and is suitable for integrated circuits.

[Structure of the Invention (Means for Solving Problems)] The present invention includes a first voltage-controlled current circuit that flows a current proportional to the positive output terminal potential of a fully differential amplifier; a second voltage controlled current circuit that flows a proportional current; It includes a sum current voltage circuit that transmits a current that is the sum of the output currents of the second voltage controlled current circuit, and a reference current transmission circuit that transmits a current that is proportional to the reference voltage, and the common mode output potential is equal to the reference potential. A difference current between the current of the sum current transfer circuit and the current of the reference current voltage circuit is fed back to the control electrode of the transistor serving as the active load of the fully differential amplifier by a differential current feedback circuit that controls the current to be equal. This is what I did.

(Function) With the above means, when the output potential of the fully differential amplifier operates accurately differentially, the sum current does not change, but when it operates in-phase, the sum current changes, so the sum current value and The current of the transistor serving as the active load of the fully differential amplifier is controlled by the difference current value from the reference current value, thereby stabilizing the output. By obtaining this operation, common feedback can be obtained without increasing the stack of transistors in the output stage.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an input terminal 11 is supplied with a negative phase input, and an input terminal 12 is supplied with a positive phase input. Input terminals 11 and 12 are MOS) transistor Q2
1. Q22 is connected to the gate of transistor Q21. The source of Q22 is commonly connected to the transistor Q.
It is connected to the drain of 31. Transistor Q21
．． ．． The drain of Q22 is connected to the transistor Q
23. connected to the drain of Q24, transistor 0
23. The source of Q 24 is connected to the first power supply line 13 . Further, the drains of transistors Q23°Q24 are connected to the drains of transistors Q25°Q10, respectively, and the sources of transistors Q25°Q26 are connected to transistors Q27, . It is connected to the drain of Q28 and to the gates of transistors Q33 and Q32. The sources of transistors Q27° and Q28 are connected to transistors Q29. Q30 is connected to the drain of transistor Q29. The sources of Q30 and Q31 are connected to the second power supply line 14.

The transistors Q21 to Q33 described above constitute a fully differential amplifier, and among them, the transistors 032 to Q30 constitute an active load circuit. Transistor Q 23.
The common gate of the transistors Q24 is connected to the first bias potential vB1 via the terminal 15, and the common gate of the transistors Q25 and Q10 is connected to the second bias potential VB2 via the terminal 16.
, transistor Q29. A third bias potential VB3 is supplied to the gates of Q30 and Q31 via the terminal 17.

Transistor Q25. From the output terminals 18 and 19 provided at the source of Q10, positive outputs Vo(+) and
A negative output Vo(-) is derived. This output is further supplied to voltage controlled current circuits 200 and 100. The first voltage controlled current circuit 100 includes transistors Q32. Resistance R1
The second voltage controlled current circuit includes transistors Q33. It is composed of a resistor R2. 1st. Second
The output currents of the voltage controlled current circuits 100 and 200 become the sum current I4, and are transmitted to the illustrated point A via the sum current transmission circuit 300. The sum current transfer circuit 300 includes transistors Q32. A transistor Q34. whose source and gate are connected to the common drain of Q33. ) transistor Q34
The transistor Q35 has its gate connected to the gate of the transistor Q35. Transistor Q34. The drain of Q35 is connected to the first power supply line 13, and the drain of transistor Q35 is connected to the first power supply line 13.
The source of transistor Q35 is connected to the drain of transistor Q3G and to the common gate of transistor Q27028.

Transistors Q38 to Q40 are part of the reference current transmission circuit 40.
It constitutes 0. The sources of transistors 03B and Q37 are connected to the second power supply line 14, and the gates and drains of transistor Q37 are connected to the drain of transistor Q38. The source of transistor Q3g is
It is connected to the first power supply line 13, its gate is connected to the gate and drain of a transistor Q39, its source is connected to the first power supply line 13, and its drain is connected to the drain of a transistor Q40. A reference potential V REF is supplied to the gate of the transistor Q40, and the source is connected to the second power supply line 14 via a resistor R3.

In the above embodiment, the relationship between the resistors R1 and R2°R3 is R1=R2=2R3, and the transistor Q32°Q3
3 and Q40 have the same gate length, and transistor Q
The gate width of 40 is twice the gate width of transistors Q32 and Q33. Furthermore, transistors Q34 and Q35. Q3B and Q37. The element shapes of each pair of Q38 and Q39 are formed to be equal. With this configuration, due to the current mirror effect, the current relationship of each part shown in the figure is 14=I5. l1=I8.

Now transistor Q 32. Q33 gate potential (
If the output potential) is higher than the reference potential VREP,
I2 +13 = I4 > If that is, I5 > I6, and the difference current flows into the gates of transistors Q27 and Q28,
This acts to raise the gate potential of Q28.

Therefore, the gate potentials of transistors Q32 and Q33 decrease.

Conversely, transistor Q32. When the gate potential (output potential) of i3 becomes lower than the reference potential V REF, I2 +
I3 = I4 > If In other words, 9.15 < I6, and transistors Q27 and Q
It acts in the direction of lowering the gate potential of 28. Therefore, transistor Q32. The gate potential of Q33 becomes high.

Feedback operation is obtained as described above, and in common mode, transistors Q32. The gate potential of Q33 is the reference potential V
It operates to be equal to REP. Output potential Vo(
+) and Vo(-) are output differentially, the sum current I4 does not change and is held constant, and the transistor Q27
．． The gate potential of Q28 is also approximately constant and does not affect differential operation.

FIG. 2 shows another embodiment of the invention.

The input terminal 21 is supplied with a negative phase input, and the input terminal 22 is supplied with a positive phase input. Input terminals 21 and 22 are connected to transistors Q41. Q42 is connected to the gate of transistor Q41. The source of Q42 is connected to the second power supply line 24 via the current source 23. Transistor Q4
The drain of transistor Q43 and the drain of transistor Q43. The drain of transistor Q42 is connected to the gate of transistor Q45, the drain of transistor Q44, and the drain of transistor Q44. Connected to the gate of Q10. Transistor Q43. The source of Q45 is connected to the first power supply line 25, the drain of transistor Q45 is connected to one end of capacitor C1, the gate of transistor Q49, and the drain of transistor Q47, and the drain of transistor Q4B is connected to one end of capacitor C2, transistor Q50. The gate of the transistor Q4g is connected to the drain of the transistor Q4g.

Transistor Q 49. The source of the transistor Q47 is connected to the second power supply line 24, the drain of the transistor Q49 is connected to the other end of the capacitor C1 and to the output terminal 28, and is further connected to the first power supply line 25 via the current source 26. Connected. Further, the source of the transistor Q5 (1, Q4g is connected to the second power supply line 24, and the source of the transistor Q5
The drain of the capacitor C2 is connected to the other end of the capacitor C2, is connected to two output ends, and is further connected to the first power supply line 25 via the current source 27.

The output terminal 28 is connected to the gate of the transistor 033 constituting the second voltage controlled current circuit 200, and the output terminal 29
is connected to the gate of the transistor Q32 constituting the first voltage controlled current circuit 100.

1st. The second voltage controlled current circuits 100, 200, the sum current transfer circuit 300 section, and the reference current transfer circuit 400 section have the same circuit configuration as shown in FIG. However, feedback circuit 5
00 are connected differently; in this embodiment, the drain of transistor Q37 and the transistor Q47. Q4
8 common gates.

Also in this embodiment, in the common mode, the potential of the output terminals 28 and 29 is the reference potential V l? It operates in the same way as EF.

[Effects of the Invention] As explained above, according to the present invention, the number of transistor stages between the first and second power supplies is smaller than in the conventional circuit, and the operating range can be widened, making it suitable for low voltage operation.

Further, since the output operating point potential can be set using the reference potential, this setting becomes easy. This circuit is thus suitable for integrated circuits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, and Fig. 3 is a diagram showing a common mode feedback circuit of a conventional fully differential amplifier. be. 100.200...Voltage control current circuit, 300...
Sum current transfer circuit, 400...Reference current transfer circuit, Q2
1-Q50...transistor. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (1)

[Claims] In a common mode feedback circuit that sets the operating point potential of both positive and negative output ends of a fully differential amplifier, a first voltage control current circuit that flows a current proportional to the positive output end potential, and a first voltage control current circuit that flows a current proportional to the negative output end potential; a second voltage-controlled current circuit that flows a proportional current; a sum current-voltage circuit that transmits a current that is the sum of the output currents of the first and second voltage-controlled current circuits; and a sum current-voltage circuit that transmits a current that is proportional to a reference voltage. A reference current transfer circuit and a current difference between the current of the sum current transfer circuit and the current of the reference current voltage circuit are fed back to the control electrode of the transistor serving as the active load of the fully differential amplifier, and the common mode output potential is A common mode feedback circuit for a fully differential amplifier, comprising a differential current feedback circuit that controls the current to be equal to a reference potential.