CN109728809A - Phase-locked loop frequency integrator - Google Patents
Phase-locked loop frequency integrator Download PDFInfo
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Abstract
The invention discloses a kind of phase-locked loop frequency integrators, including phase frequency detector, charge pump, sef-adapting filter, voltage controlled oscillator, frequency divider and decoder, the phase frequency detector, charge pump, sef-adapting filter, voltage controlled oscillator, frequency divider is followed in series to form feedback loop, the decoder is connected between frequency divider and sef-adapting filter, the decoder is used to carry out the frequency dividing ratio of the frequency divider decoding processing and provides corresponding control signal to the sef-adapting filter, the sef-adapting filter includes the adaptive conducting resistance network for having different resistance values under the control signal control and the loop bandwidth of the phase-locked loop frequency integrator being enabled to keep constant.The bandwidth that phase-locked loop frequency integrator of the present invention realizes loop does not change with output frequency and is changed, and has preferable system stability and response speed.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of biggish phase-locked loop frequency of reference frequency output are comprehensive
Device.
Background technique
Phase-locked loop frequency integrator is the key modules in wireless telecommunications and image sensor system, with output signal
The feature that frequency spectrum is pure, implementation and application is at low cost is widely used in requiring transmission speed relatively high occasion, at the same again by
Different in the scene and mode of application, output frequency is constantly changing, it is desirable that frequency synthesis its can quickly and stably ring
Answer the switching of output frequency, the steady operation of safeguards system.
The output frequency of existing phase-locked loop frequency integrator is different according to actual application scenarios, frequency range
It is very big, cause phase-locked loop frequency integrator in frequency error factor, locking time is uncertain, can not fast and stable response output
The switching of frequency, limits its application；On the other hand, since the resistance of filter etc. is when technique is realized, resistance value can exist
It is inclined to even result in phase margin it is possible that bandwidth is caused to deviate the set value of chip design for 10% or more unknown deviation
From excessive, to influence the stability of loop.
Summary of the invention
The object of the present invention is to provide a kind of phase-locked loop frequency integrator with preferable system stability and response speed.
One aspect of the present invention discloses a kind of phase-locked loop frequency integrator comprising phase frequency detector, charge pump, from
Adaptive filter, voltage controlled oscillator, frequency divider and decoder, it is the phase frequency detector, charge pump, sef-adapting filter, voltage-controlled
Oscillator, frequency divider are followed in series to form feedback loop, and the decoder is connected between frequency divider and sef-adapting filter, institute
Decoder is stated for carrying out decoding processing to the frequency dividing ratio of the frequency divider and providing corresponding control signal to described adaptive
Filter, the sef-adapting filter are included under the control signal control with different resistance values and enable to the lock
The adaptive conducting resistance network that the loop bandwidth of phase ring frequency synthesizer is kept constant.
Optionally, the sef-adapting filter includes resistance locking transistor, multiple resistance selection transistors, the first electricity
Hold, the second capacitor and amplifier, supply voltage connect the electrode input end and locking electricity of amplifier by a reference current source
The drain electrode of transistor, the negative input of a reference voltage source connection amplifier are hindered, the output end of the amplifier connects institute
The grid of resistance locking transistor is stated, and is also connected to the grid of the first to the n-th transistor by multiple conducting switches respectively,
The grid of the multiple resistance selection transistor respectively by earthing switch connect ground voltage, the locking resistance transistor with it is more
The source electrode of a resistance selection transistor connects ground voltage, and the multiple resistance selection transistor constitutes adaptive conducting resistance net
Network.
Optionally, the sef-adapting filter further comprises first capacitor and the second capacitor, the multiple resistance selection
One end of the drain electrode connection first capacitor of transistor, the other end of the first capacitor receive the electric current from charge pump and connection
The other end to one end of the second capacitor, second capacitor connects ground voltage, the adaptive conducting resistance network and first
The series arm of capacitor composition and the second capacitor are in parallel.
Optionally, the reference voltage source is low voltage reference voltage source, the drain voltage etc. of the resistance locking transistor
In the reference voltage source voltage, the conducting resistance that the resistance locks transistor is steady state value.
Optionally, the multiple resistance selection transistor include the first to the n-th (n > 0) transistor, described the first to the n-th
The conducting resistance of transistor meetsIts
Middle R is the conducting resistance that the resistance locks transistor, the electric conduction of the first transistor and resistance locking transistor
It hinders equal.
Optionally, the phase frequency detector can export corresponding pulse signal according to the phase difference of input signal, described
The pulse signal that charge pump can be exported according to the phase frequency detector generates corresponding output electric current, the sef-adapting filter
It can be provided according to the output electric current of the charge pump and control voltage to the voltage controlled oscillator, the voltage controlled oscillator being capable of root
The output signal of different frequency is generated according to the control voltage.
Optionally, the decoder can generate the adaptive conducting resistance network for controlling the sef-adapting filter
Switch control signal, enable the phase-locked loop frequency integrator that there is constant loop band for different frequency dividing ratios
It is wide.
Optionally, the conducting switch includes the first to the n-th conducting switch, and the earthing switch connects including the first to the n-th
Ground switch, the switch control signal includes that the first to the n-th conductivity control signal and the first to the n-th ground connection control signal, described
The first to the n-th conductivity control signal is respectively used to the first to the n-th conducting switch conduction of control or shutdown, and described the first to the n-th connects
Ground control signal is respectively used to the on or off of the first to the n-th earthing switch of control, by controlling the first to the n-th conducting
The on or off of switch, and the on or off of the first to the n-th earthing switch of control, can control the adaptive conducting
Resistor network has different resistance values.
Optionally, when the frequency dividing ratio of the frequency divider is k (0 < k≤n), kth conductivity control signal and kth ground connection control
Signal controls kth conducting switch conduction and kth earthing switch turns off, and other resistance selection transistors all keep earthing switch to lead
Logical, conducting switch OFF, so that the adaptive conducting resistance that only kth transistor is formed accesses in the sef-adapting filter.
Optionally, the resistance locking and resistance selection transistor are NMOS transistor.
Compared to the prior art, phase-locked loop frequency integrator of the present invention uses sef-adapting filter, has and adaptively leads
Logical resistor network can have different conduction resistance values according to different frequency dividing ratios, so that the phase-locked loop frequency is comprehensive
The loop bandwidth that device is kept constant.In addition, it is smaller than the size of traditional resistor using the size of the adaptive resistance of transistor realization,
To reduce the chip area of chip.The bandwidth that phase-locked loop frequency integrator of the present invention realizes loop does not change with output frequency
And change, there is preferable system stability and response speed.
Detailed description of the invention
Fig. 1 is the schematic diagram of one embodiment of the present of invention；
Fig. 2 is the circuit diagram of the sef-adapting filter of one embodiment of the present of invention；
Fig. 3 is the decoder schematic illustration of one embodiment of the present of invention；
Fig. 4 and Fig. 5 is the input and output signal schematic diagram of the phase frequency detector of one embodiment of the present of invention；
Fig. 6 to Fig. 8 is existing phase-locked loop circuit accompanying drawings.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Feature described in present specification, structure can be incorporated in one or more implementations in any suitable manner
In mode.In the following description, many details are provided so as to fully understand presently filed embodiment.However,
One of ordinary skill in the art would recognize that even if without one or more in the specific detail, or the other structures of use,
Constituent element etc. can also practice the technical solution of the application.In other cases, it is not shown in detail or describes known features or behaviour
Make the emphasis to avoid fuzzy the application.
Please with refering to Fig. 6, a kind of typical phase-locked loop frequency integrator includes phase frequency detector (phase frequency
Detector, PFD), charge pump (charge pump, CP), filter (low pass filter, LPF), voltage controlled oscillator
(voltage controlled oscillator, VCO) and frequency divider (Divider) composition.The working principle of phaselocked loop is inspection
Survey the phase difference of input signal and output signal, and by phase discriminator to be converted into voltage signal defeated for the phase signal that will test out
Out, the control voltage that voltage controlled oscillator is formed after low-pass filtered device filtering, implements control to the frequency of oscillator output signal,
Pass through frequency, phase feedback to phase frequency detector of the feedback network oscillator output signal again.In order to guarantee phase-locked loop frequency
The stability of synthesizer, loop bandwidth are usually less than 1/10th of minimum input frequency.
In order to realize biggish bandwidth, preferable loop stability and moderate complexity in circuits, phase-locked loop circuit
Filter generally uses second order low frequency filtering, pole that there are two the transfer function tools of filter circuit as shown in Figure 7 (including one
Zero pole point) and a zero point.
Linear modelling is carried out to the entire loop of phase-locked loop frequency integrator, is less than the 1/ of frequency input signal in loop bandwidth
When 10, small-signal model as shown in Figure 8 can be established, wherein KPFD+CP(s)、KLPF(s) and KVCO(s) frequency and phase discrimination is respectively indicated
The transfer function of device and electric charge pump module, filter module and voltage-control oscillator module.
Wherein, for phase frequency detector and electric charge pump module, it is assumed that the turn-on time of charge pump is ton, phase frequency detector
The phase difference of input signal is θ e, available:
Wherein, TREFFor the period of input signal Fin, the average current i as caused by phase differencedAre as follows:
The expression formula of the phase frequency detector and electric charge pump module transfer function can be obtained are as follows:
For filter module, the expression formula of transfer function are as follows:
For voltage-controlled oscillator (VCO) module, since output phase is the integral of frequency, so having:
θo=KVCO∫Vcdt
Laplace transform is carried out to the formula to obtain:
Then the transfer function of voltage-controlled oscillator (VCO) module is obtained are as follows:
It can thus be concluded that the output function of the loop open loop of the phase-locked loop frequency integrator are as follows:
Wherein, N is the frequency dividing ratio of frequency divider.In order to which system obtains enough phase margins, loop bandwidth ωcPositioned at compensation
Between pole and zero.Due to s=j ω, according to the definition of bandwidth, as ω=ωcShi You:
Loop bandwidth ω can be derived bycExpression formula it is as follows:
It can be seen that the phaselocked loop application for fixed input frequency and output frequency from above-mentioned expression formula, due to dividing
Frequency ratio N is constant, so loop bandwidth is constant；But when being applied to frequency synthesizer for phaselocked loop, input frequency is kept not
Become, and output frequency is different according to actual application scenarios, frequency range is very big.The variation of general its frequency dividing ratio N
Range reaches 2 times or more, and when N changes k times, loop bandwidth can also follow k times of variation, so that phase-locked loop frequency
For synthesizer in frequency error factor, locking time is uncertain, and variation range is larger, to limit application；On the other hand, due to filter
For the resistance of wave device etc. when technique is realized, resistance value can have 10% or more unknown deviation, it is possible that bandwidth is caused to deviate
The set value of design, even result in phase margin deviate it is excessive, to influence the stability of loop.
In view of this, in order to improve response speed and stability of the phase-locked loop circuit on frequency synthesizer, the present invention is mentioned
For a kind of phase-locked loop circuit that loop bandwidth adaptively locks.
Referring to Fig. 1, a kind of phase-locked loop frequency that loop bandwidth adaptively locks is comprehensive in one embodiment of the present of invention
Device includes phase frequency detector 10, charge pump 20, sef-adapting filter 30, voltage controlled oscillator 40, frequency divider 50 and decoder 60.Institute
It states phase frequency detector 10, charge pump 20, sef-adapting filter 30, voltage controlled oscillator 40, frequency divider 50 and is followed in series to form feedback
Circuit, the decoder 60 are connected between frequency divider 50 and sef-adapting filter 30.The phase frequency detector 10 being capable of basis
The phase difference of input signal exports corresponding pulse signal, what the charge pump 20 can be exported according to the phase frequency detector 10
Pulse signal generates corresponding output electric current, and the sef-adapting filter 30 can be mentioned according to the output electric current of the charge pump 20
For controlling voltage to the voltage controlled oscillator 40, the voltage controlled oscillator 40 can generate different frequency according to the control voltage
Output signal.
Specifically, outer clock circuit generates input signal Fin and is applied to the frequency discrimination of the phase-locked loop frequency integrator
The reference input of phase discriminator 10.Feedback after the divided frequency dividing of device 50 of the output signal Fout of the phase-locked loop frequency integrator
Feedback input end of the signal Ffb feed back input to the phase frequency detector 10.The phase frequency detector 10 is according to reference input
The phase difference of signal and feed back input end signal exports the first output signals UP and the second output signal DN to the charge pump 20.
The phase frequency detector 10 is the important module in phase-locked loop frequency integrator, is used to detect two input signals Fin and Ffb
Between phase difference and the corresponding output signals UP of generation and DN based on the phase difference.10 working principle of phase frequency detector
It is described below:
Referring to Fig. 4, when the phase of the input signal Fin is ahead of the feedback signal Ffb, the input signal
When the rising edge of Fin makes the first output signals UP become high level and continue to that the rising edge of the feedback signal Ffb arrives,
First output signals UP becomes low level at this time；In the above process, the second output signal DN is low level always.
Referring to Fig. 5, when the phase of the input signal Fin lags behind the feedback signal Ffb, the feedback signal
When the rising edge of Ffb makes the second output signal DN become high level and continue to that the rising edge of the input signal Fin arrives,
The second output signal DN becomes low level at this time；In the above process, first output signals UP is low level always.
The charge pump 20 is when the first output signals UP is high level and the second output signal DN is low level, output electricity
Icp is flowed to charge to the filter.The charge pump 20 is low level and the second output signal in first output signals UP
When DN is high level, electric current Icp is exported to the filter discharge.First output signals UP is low level and the second output signal
When DN is low level, the charge pump 20 is in hold mode, and output electric current Icp is 0, and the sef-adapting filter 30 does not charge
Also it does not discharge.
The sef-adapting filter 30 can be low-pass filter (LPF), may include filtered electrical for example shown in Fig. 2
Road.The output control voltage Vctrl that shown sef-adapting filter 30 can be used in generating to the output electric current Icp is filtered
Wave, the control voltage Vctrl connection voltage controlled oscillator 40.The control voltage Vctrl can be used in controlling the pressure
Control the oscillation frequency of oscillator 40.When the sef-adapting filter 30 is electrically charged, the control voltage Vctrl increases, and works as institute
When stating sef-adapting filter 30 and being discharged, the control voltage Vctrl reduces.It is described when charge pump 20 is in hold mode
The control voltage Vctrl that sef-adapting filter 30 exports is remained unchanged.
The voltage controlled oscillator 40 generates output signal Fin, on the one hand the output signal Fin is used as phaselocked loop of the present invention
The output signal of the entire loop of frequency synthesizer is input to frequency discrimination as feedback signal Ffb after on the one hand dividing by frequency divider
Phase discriminator 10.
In one embodiment of the present of invention, the sef-adapting filter 30 includes resistance locking transistor, the choosing of multiple resistance
Transistor, first capacitor, the second capacitor and amplifier are selected, supply voltage connects the anode of amplifier by a reference current source
The drain electrode of input terminal and locking resistance transistor, the negative input of a reference voltage source connection amplifier, the amplifier
Output end connect the grid of resistance locking transistor, and the first to the n-th transistor is also connected to by switch respectively
Grid, the grid of the multiple resistance selection transistor pass through respectively switch connection ground voltage, the locking resistance transistor
Ground voltage is connected with the source electrode of multiple resistance selection transistors, the multiple resistance selection transistor constitutes adaptive conducting resistance
Network.
In further embodiment, one end of the drain electrode connection first capacitor of the multiple resistance selection transistor is described
The other end of first capacitor receives the electric current from charge pump and is connected to one end of the second capacitor, second capacitor it is another
End connection ground voltage, the multiple resistance selection transistor constitute adaptive conducting resistance network, the adaptive conducting resistance
The series arm and the second capacitor of network and first capacitor composition are in parallel.
Referring to Fig. 2, being the circuit diagram of the sef-adapting filter 30 of one embodiment of the present of invention.It is adaptive in Fig. 2
It answers the partial circuit of filter 30 to can be regarded as a kind of of the resistance R of filter circuit in Fig. 4 and realizes changing for adaptive resistance
Into mode.The sef-adapting filter 30 includes that resistance locks transistor Mc, the first to the n-th (n > 0 and n is positive integer) crystal
Pipe M1 to Mn, first capacitor C1, the second capacitor C2 and amplifier A.Supply voltage VDD is put by a reference current source Ib connection
The drain electrode (drain) of the electrode input end and transistor Mc of big device A.The cathode of one reference voltage source Vb connection amplifier A is defeated
Enter end, amplifier A output end output voltage Vg.The output end of the amplifier A connects the grid of the resistance locking transistor Mc
Pole (gate), and also by multiple conducting switch Sc1 to Scn, (as the first to the n-th conducting is switched in the present embodiment respectively
Sc1 to Scn) is connected to the grid of the first to the n-th transistor M1 to Mn.The grid of the first to the n-th transistor M1 to Mn point
Not Tong Guo multiple earthing switch Sr1 to Srn (be the first to the n-th earthing switch Sr1 to Srn) connection ground voltage in the present embodiment
VSS.The source electrode (source) of transistor Mc and the first to the n-th transistor M1 to Mn connects ground voltage VSS.The transistor
One end of the drain electrode connection first capacitor C1 of M1 to Mn, the other end of the first capacitor C1 are connected to the defeated of voltage controlled oscillator 40
Enter end control voltage Vctrl.And it is connected to one end of the second capacitor C2, the other end of the second capacitor C2 connects ground voltage
VSS.The first to the n-th transistor M1 to Mn constitutes adaptive conducting resistance network 100, the adaptive conducting resistance network
The series arm of 100 and first capacitor C1 composition and the second capacitor C2 are in parallel.Above-mentioned supply voltage VDD and ground voltage VSS again may be used
Referred to as drain voltage and source voltage.
Wherein, Ib is benchmark current source, and Vb is low voltage reference voltage source, and amplifier A is operational amplifier, and resistance locking is brilliant
Body pipe Mc is that a resistance locks transistor, and the first to the n-th transistor M1 to Mn constitutes adaptive conducting resistance network 100, opens
It closes Sc1 to ScN and constitutes the switching network that network switching is connected for the adaptive resistance with switch Sr1 to SrN.Above-mentioned first
Multiple resistance selection transistors are considered as to the n-th transistor M1 to Mn.According to negative-feedback principle, resistance locks transistor Mc's
Drain voltage is equal to the reference voltage source voltage Vb, simultaneously because Vb voltage is lower, so that transistor Mc work is online
Property area, thus the resistance locking transistor Mc conducting resistance RMcSize are as follows:
The breadth length ratio and conducting resistance of the first transistor M1 and resistance locking transistor Mc are equal.
And the breadth length ratio of the transistor M1 to Mn meets:
So the conducting resistance of transistor Mc and transistor M1 to Mn are than meeting:
Wherein, R is conducting resistance that the resistance locks transistor, the first transistor M1 and the resistance in above formula
The conducting resistance for locking transistor Mc is equal.
Shown decoder 60 is m to n bit decoder, can be used in carrying out decoding processing to the frequency dividing ratio of the frequency divider 50
And corresponding control signal is provided to the sef-adapting filter 30.In the present embodiment, the decoder 60 can arrive for binary system
Decimal decoder.M to the n bit decoder concrete implementation mode is as shown in figure 3, the decoder 60 can generate is used for
The switch control signal of the adaptive conducting resistance network of the sef-adapting filter is selected and adjusts, so that phaselocked loop frequency
Rate synthesizer can have different frequency dividing ratios constant loop bandwidth.The switch control signal includes multiple conducting controls
Signal Sc<1>processed to Sc<n>and multiple ground connection control signal Sr<1>to Sr<n>.In the present embodiment, the multiple conducting control
Signal Sc<1>to Sc<n>is the first to the n-th conductivity control signal Sc<1>to Sc<n>, and the multiple ground connection control signal Sr<
1>to Sr<n>be the first to the n-th ground connection control signal Sr<1>to Sr<n>.The first to the n-th conductivity control signal Sc<1>
The the first to the n-th conducting switch Sc1 of control is respectively used to Scn on or off to Sc<n>.The first to the n-th ground connection control
Signal Sr<1>to Sr<n>is respectively used to the on or off of the first to the n-th earthing switch Sr1 to Srn of control.Pass through control institute
The on or off of the first to the n-th conducting switch Sc1 to Scn is stated, and controls leading for the first to the n-th earthing switch Sr1 to Srn
Logical or shutdown can control the adaptive conducting resistance network with different resistance values.
Such as, but not limited to, when the first to the n-th conductivity control signal Sc<1>to Sc<n>is 1 or 0, the first to the n-th conducting
Switch Sc1 to Scn corresponds on or off.Certainly, in the present invention other or change embodiment, it is also possible to have first to the
When n conductivity control signal Sc<1>to Sc<n>is 0 or 1, the first to the n-th conducting switch Sc1 to Scn corresponds to the feelings of on or off
Shape.Similarly, for the first to the n-th ground connection control signal Sr<1>to Sr<n>and the first to the n-th earthing switch Sr1 to Srn's
Also there is above-mentioned different implementation situation, such as, but not limited to, the first to the n-th ground connection control signal Sr<1>to Sr<n>is 1 or 0
When, the first to the n-th earthing switch Sr1 to Srn corresponds on or off or the first to the n-th ground connection control signal Sr<1>to Sr
When<n>is 0 or 1, the first to the n-th earthing switch Sr1 to Srn corresponds on or off.Above-mentioned conductivity control signal or ground connection control
Signal processed can be expressed as low level or high level for 0 or 1 in some embodiments.
It should be pointed out that it will be understood by those skilled in the art that without creative efforts, the present invention
Some or all of embodiment, and the deformation for some or all of embodiment, replacement, change, fractionation, combination, extension
Deng being considered as being covered by innovation and creation thought of the invention, belong to the scope of protection of the present invention.
Return to the description previously with regard to embodiment, wherein the multiple conductivity control signal Sc<1>to Sc<n>and multiple
Ground connection control signal Sr<1>to Sr<n>is for control selections or the resistance value of the adjustment adaptive conducting resistance network, in turn
Enable the phase-locked loop frequency integrator that there is constant loop bandwidth for different frequency dividing ratios.In the frequency dividing of frequency divider
When than for k (0 < k≤n), kth conductivity control signal Sc<k>=1, kth ground connection control signal Sr<k>=0, so that kth is connected
Switch Sck conducting, kth earthing switch Srk shutdown；Others conducting switch Sc1 to Sc (k-1), Sc (k+1) to Scn shutdown, connect
Ground switch Sr1 to Sr (k-1), Sr (k+1) to Srn conducting.To except the transistor M1 to Mk-1 except kth transistor Mk
Earthing switch Sr conducting, conducting switch Sc shutdown are all kept with Mk+1 to Mn, so that only kth transistor Mk formation is adaptive
Conducting resistance accesses in the sef-adapting filter 30, size k*R, the adaptive conducting resistance network 100 described at this time
Resistance value is equal to k*R, therefore the loop bandwidth size of phase-locked loop frequency integrator at this time are as follows:
As can be seen that the loop bandwidth size in the above embodiment of the present invention is unrelated with output signal frequency dividing ratio k, remain
Steady state value (const indicates steady state value).
In above-described embodiment, the transistor Mc and M1 to Mn is NMOS transistor.It should be noted that the present invention is not
As limit, in some change embodiments of the invention, transistor Mc and M1 to Mn can also be other types transistor, such as
PMOS transistor or other types metal-oxide-semiconductor or other can be realized the circuit or element of adaptive conducting resistance 100.
Compared to the prior art, phase-locked loop frequency integrator of the present invention uses sef-adapting filter, has and adaptively leads
Logical resistor network can have different conduction resistance values according to different frequency dividing ratios, so that the phase-locked loop frequency is comprehensive
The loop bandwidth that device is kept constant.Phase-locked loop frequency integrator of the present invention realize the bandwidth of loop not with output frequency variation and
Variation, to improve the system stability of phase-locked loop frequency integrator and there is more stable response speed.In addition, passing through
Can be realized accurate resistance in the transistor of linear zone with negative feedback mechanism and work, avoid prior art resistance with
Technique bring deviation.In addition, it is smaller than the size of traditional resistor using the size of the adaptive resistance of transistor realization, to subtract
The chip area of small chip, it is ensured that the circuit actual motion index of frequency synthesizer is within scope of design.
" length " that is likely to occur in description of the invention, " width ", "upper", "lower", "front", "rear", " back side ", " just
The orientation or positional relationship of the instructions such as face ", "vertical", "horizontal", " top ", " bottom ", " inside ", " outside " is based on attached drawing
Shown in orientation or positional relationship, be merely for convenience of the description embodiment of the present invention and simplify description, rather than indication or suggestion
Signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to this
The limitation of invention.In addition, " first ", " second " etc. are used for description purposes only, it is not understood to indicate or imply relatively important
Property or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Person implicitly includes at least one described feature.In the description of the present invention, " a variety of " are meant that at least two, unless otherwise
Clear specific restriction.In description of the invention, it is also necessary to which explanation is unless specifically defined or limited otherwise, " setting ",
" installation ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally connect
It connects；It can be mechanical connection, be also possible to be electrically connected；It can be and be directly connected to, be also possible to be indirectly connected with by intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, above-mentioned art can be understood with concrete condition
The concrete meaning of language in the present invention.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Term used in claims, which should not be construed as to invent, is limited to this explanation
Specific embodiment disclosed in book.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of phase-locked loop frequency integrator, which is characterized in that including phase frequency detector, charge pump, sef-adapting filter, voltage-controlled
Oscillator, frequency divider and decoder, the phase frequency detector, charge pump, sef-adapting filter, voltage controlled oscillator, frequency divider according to
Secondary feedback loop in series, the decoder are connected between frequency divider and sef-adapting filter, the decoder for pair
The frequency dividing ratio of the frequency divider carries out decoding processing and provides corresponding control signal to the sef-adapting filter, described adaptive
Answering filter to be included in, the control signal control is lower to be had different resistance values and enables to the phase-locked loop frequency integrator
The adaptive conducting resistance network that keeps constant of loop bandwidth.
2. phase-locked loop frequency integrator according to claim 1, which is characterized in that the sef-adapting filter includes resistance
Transistor, multiple resistance selection transistors, first capacitor, the second capacitor and amplifier are locked, supply voltage passes through a benchmark
Current source connects the drain electrode of the electrode input end and locking resistance transistor of amplifier, and a reference voltage source connects amplifier
Negative input, the output end of the amplifier connect the grid of the resistance locking transistor, and also respectively by multiple
Conducting switch is connected to the grid of the first to the n-th transistor, and the grid of the multiple resistance selection transistor passes through ground connection respectively
Switch connection ground voltage, the locking resistance transistor connects ground voltage with the source electrode of multiple resistance selection transistors, described more
A resistance selection transistor constitutes adaptive conducting resistance network.
3. phase-locked loop frequency integrator according to claim 2, which is characterized in that the sef-adapting filter further wraps
First capacitor and the second capacitor are included, draining for the multiple resistance selection transistor connects one end of first capacitor, and described first
The other end of capacitor receives the electric current from charge pump and is connected to one end of the second capacitor, and the other end of second capacitor connects
Ground voltage, the series arm and the second capacitor of the adaptive conducting resistance network and first capacitor composition are in parallel.
4. phase-locked loop frequency integrator according to claim 3, which is characterized in that the reference voltage source is low voltage reference
The drain voltage of voltage source, the resistance locking transistor is equal to the reference voltage source voltage, and the resistance locks transistor
Conducting resistance be steady state value.
5. phase-locked loop frequency integrator according to claim 4, which is characterized in that the multiple resistance selection transistor includes the
The conducting resistance of one to the n-th (n > 0) transistor, the first to the n-th transistor meets Wherein R is the conducting resistance that the resistance locks transistor, the first transistor and institute
The conducting resistance for stating resistance locking transistor is equal.
6. phase-locked loop frequency integrator according to claim 1, which is characterized in that the phase frequency detector can be according to defeated
The phase difference for entering signal exports corresponding pulse signal, and the pulse that the charge pump can be exported according to the phase frequency detector is believed
Number corresponding output electric current is generated, the sef-adapting filter can provide control voltage according to the output electric current of the charge pump
To the voltage controlled oscillator, the voltage controlled oscillator can generate the output signal of different frequency according to the control voltage.
7. phase-locked loop frequency integrator according to claim 1, which is characterized in that the decoder can be generated for controlling
The switch control signal for making the adaptive conducting resistance network of the sef-adapting filter, so that the phase-locked loop frequency integrator
There can be constant loop bandwidth for different frequency dividing ratios.
8. phase-locked loop frequency integrator according to claim 7, which is characterized in that conducting switch includes first to the
N conducting switch, the earthing switch include the first to the n-th earthing switch, and the switch control signal includes the first to the n-th conducting
Signal and the first to the n-th ground connection control signal are controlled, the first to the n-th conductivity control signal is respectively used to control first to the
Switch conduction or shutdown is connected in n, and the first to the n-th ground connection control signal is respectively used to the first to the n-th earthing switch of control
On or off, the on or off switched by controlling the first to the n-th conducting, and the first to the n-th ground connection of control are opened
The on or off of pass can control the adaptive conducting resistance network with different resistance values.
9. phase-locked loop frequency integrator according to claim 8, which is characterized in that the frequency dividing ratio of the frequency divider is k (0
< k≤n) when, kth conductivity control signal and kth ground connection control signal control kth conducting switch conduction and kth earthing switch close
Disconnected, other resistance selection transistors all keep earthing switch conducting, conducting switch OFF, so that only kth transistor is formed
Adaptive conducting resistance access in the sef-adapting filter.
10. -9 any phase-locked loop frequency integrator according to claim 1, which is characterized in that the resistance locking and electricity
Resistance selection transistor is NMOS transistor.
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| CN113315509A (en) * | 2021-05-26 | 2021-08-27 | 深圳市国微电子有限公司 | Phase-locked loop circuit and communication chip |
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