CN111585569A - Novel charge pump structure for phase-locked loop - Google Patents
Novel charge pump structure for phase-locked loop Download PDFInfo
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- CN111585569A CN111585569A CN202010530397.0A CN202010530397A CN111585569A CN 111585569 A CN111585569 A CN 111585569A CN 202010530397 A CN202010530397 A CN 202010530397A CN 111585569 A CN111585569 A CN 111585569A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
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Abstract
The invention relates to a novel charge pump structure applied to a phase-locked loop, which comprises a phase frequency detector and an improved charge pump, wherein the phase frequency detector is composed of a D trigger, a logic module reset part and an RS trigger, the improved charge pump establishes two complementary charge pump control states by adding the RS trigger module on the basis of the traditional charge pump, and an operational amplifier feedback module is added to reduce phase noise due to current mismatch.
Description
Technical Field
The invention relates to the technical field of integrated circuit radio frequency circuits, in particular to a novel charge pump structure for a phase-locked loop.
Background
In recent years, due to the rapid development of wireless communication systems and the arrival of the age of 5G everything interconnection, radio frequency circuits have been widely used in radio transmission, space satellites and geological exploration. Among them, the phase-locked loop circuit is one of the most basic baseband signal processing modules in the radio frequency technology, and the phase frequency detector in the form of a charge pump in the phase-locked loop circuit is widely used due to its excellent high-frequency performance. In a wireless communication system, it is necessary to use a phase-locked loop circuit to constitute a high-speed clock, which can be said to be a "heart" of a high-frequency circuit. However, phase noise has always been the greatest difficulty in conventional charge pump designs, and thus the proposed dual-path charge pump employs feedback to reduce overall phase noise and improve overall performance. In addition, with the development of CMOS integrated circuit technology, the smaller and smaller feature sizes and power supply voltages make the frequency response of the charge pump more and more affected by fluctuations in technology, voltage, temperature, and the like, so that the realization of accurate and stable zero frequency and ripple suppression is made to be a design focus and difficult point.
Disclosure of Invention
The invention aims to provide a novel charge pump structure applied to a phase-locked loop, which can effectively solve the problems, the interference of non-ideal factors of the charge pump mainly comprising phase noise is reduced by a feedback technology, a constructed loop zero point enables a loop to be more stable, and ripples are inhibited by an extra capacitor.
In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a novel charge pump structure for phase-locked loop, set part and phase frequency detector including D flip-flop, digital NAND gate control, phase frequency detector comprises D flip-flop and logic module reset portion RS flip-flop in addition, RS flip-flop has realized improved generation charge pump's feedback control, the phase frequency detector who constitutes from D flip-flop realizes two kinds of state control charge pump currents through RS flip-flop, reduce phase noise and other non-ideal effect errors through the feedback of unity gain fortune, the series structure of resistance and electric capacity constructs a zero point and stabilizes the whole loop, another less electric capacity is used for reducing the ripple.
Preferably, the operational amplifier is an input-output full swing, and is used as a voltage following connection mode, one end branch output of the charge pump is fed back to the other branch, the operational amplifier is different from the traditional full input-output swing operational amplifier in a current mirror mode, and the output of the P tube is transmitted to the drain end of the N tube in the current mirror mode.
Preferably, the RS flip-flop consists of two nand gates and an inverter, and the size of the nand gates inside the RS flip-flop structure is adjusted to a suitable value to minimize the delay caused by the flip-flop.
Preferably, the digital NAND gate is connected in multiple stages, so that the position end can be controlled by an external SPI input end, the charge pump control part performs double-end control by using the output of the RS flip-flop, the output of one end is fed back to the output of the other end by using an operational amplifier with full input and output swing, and a zero point is constructed in a form of series connection of a capacitor and a resistor to stabilize a loop, and a capacitor is additionally added to suppress ripples.
The novel charge pump structure for the phase-locked loop has the advantages that: the invention forms two control parts of the phase frequency detector through the RS trigger, thereby realizing two paths of controlled switches with the effect similar to differential input, reducing error influence through a feedback loop, the charge pump module is formed by two current sources and four controlled MOS switches, realizing two paths of output, taking one path of output as the input of a voltage following connection type feedback operational amplifier, and reducing error through feedback.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a D flip-flop and a NAND set control schematic diagram;
FIG. 3 is a circuit diagram of a NAND gate and an inverter;
FIG. 4 is a schematic diagram of an RS flip-flop;
FIG. 5 is a schematic diagram of an improved two-way controlled charge pump;
FIG. 6 is a circuit diagram of a full input output operational amplifier;
fig. 7 is a schematic diagram of a feedback connection.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical scheme adopted by the invention is shown in figure 1, a novel charge pump structure applied to a phase-locked loop comprises a D trigger, a NAND digital circuit used for setting, and a phase frequency detector consisting of an RS trigger, a two-way controlled charge pump part and a full-input-output swing amplitude operational amplifier, wherein the D trigger senses frequency difference and outputs voltage, two groups of control voltage are formed by the RS trigger, the two groups of control voltage respectively control two ways of charge pumps sharing a tail current source, one way of output is used as the input of a feedback circuit, the output of the feedback is connected with the other way of branch to be used as the output of the charge pump, the current mismatch of the upper and lower ways is stored at the current end of the feedback operational amplifier output, and the current mismatch is reduced by the mode, in addition, because the two controlled branches are controlled by the SR trigger, the controlled branches can not be conducted simultaneously, when one branch is conducted, the corresponding MOS tube of the other branch circuit is equivalent to the virtual tube of the other branch circuit, the influence of charge injection and clock feed-through is reduced, a resistance-capacitance series structure is added to the final output branch circuit to construct a zero-point stable loop, and the extra capacitor is added to suppress ripples.
FIG. 2 is a schematic diagram of a D flip-flop; when the clock input is zero, it remains unchanged; when the clock input changes to high level, the data input is copied to the output, when the reset input is activated, the output of the flip-flop will change to low level independently of the clock and data inputs, the first NAND gate receives the output voltages of the two D flip-flops, and the second NAND gate receives the control signal and the output of the first NAND gate to implement the control of the external voltage signal.
FIG. 3 is a circuit diagram of a NAND gate and an inverter; m1 and M2 are PMOS tubes, and M3 and M4 are NMOS tubes. The P tube parts are connected in parallel, the N tube parts are connected in series to realize a NAND gate with two inputs, M5 is a PMOS tube and an NMOS tube of M6 form an inverter, and the sizes of the tubes are reasonably set to optimize the performance.
FIG. 4 is a schematic diagram of an SR flip-flop; the structure is that the input ends and the output ends of two NAND gates are connected in a cross way, the output ends of two input ends of the NAND gates are the reverse direction of the output of a D trigger through an inverter, so the input ends of the D trigger are in two complementary states 01, the output ends of the D trigger are also in two stable complementary states, the output of the D trigger controls the switches of two paths of charge pumps, each path of charge pump of the D trigger cannot be conducted simultaneously because the output ends of the D trigger are in the complementary states, the drain end voltage of a current source is kept relatively stable through a feedback voltage, and the influence of a channel length modulation effect is.
FIG. 5 is a circuit diagram of an improved two-way controlled charge pump; UP _ N, UP _ P, DN _ N, DN _ P are complementary outputs of the upper and lower branches of the SR flip-flop in fig. 4, BIAS1 and BIAS2 are biases of the D current source and the N current source of the P transistor, respectively, and the entire charge pump adopts a drain terminal switching mode, and because the outputs of the SR flip-flop are complementary outputs, two branches cannot be simultaneously turned on. When one branch circuit is not conducted, the MOS tubes of the same type at the other end are equivalent to virtual tubes of a working tube, gate capacitance charges and channel charges stored in the MOS tubes can generate the influence of charge injection and clock feed-through when SR output is reversed, the influence of non-ideal effects can be effectively reduced through the novel structure, in addition, a current source of an N tube and a current source of a P tube can generate current mismatch, a feedback operational amplifier can store the current mismatch on an output capacitor of the feedback operational amplifier and then act on a tail current source to offset the influence of the current mismatch, when the N tube of the output branch circuit is opened, the P tube is closed, the P tube of the feedback branch circuit is opened, and when the N tube is closed, the feedback output end can follow the output voltage of the output branch circuit, so that the drain end voltage of the current sources of the P tube and the N tube can be kept relatively constant. The phase error and ripple effect can be reduced by this new structure.
FIG. 6 is a schematic diagram of a circuit structure of an input/output full swing operational amplifier; the operational amplifier is a feedback operational amplifier of an output end, actually, the input end of the negative end of the operational amplifier is connected with the output end, M1-M5 is a P tube input end, M9-M15 is an N tube input end, the amplified current of a P tube passes through M4, M14 and M5, the M15 current mirror combination transmits the current to the N tube input end, differential input is converted into single-ended output at the N tube input end, so that full swing amplitude can be realized without an additional output stage, a compensation circuit is not needed, more power consumption is saved compared with the traditional structure, M6-M8 is used as an external switch control end part, one port controls the switch of the whole operational amplifier, the efficiency is improved, and the grid ends of M3 and M12 are directly connected with the output end, and the unity gain feedback is integrally made.
Fig. 7 is a schematic diagram of feedback connection, in which specific circuits and connection modes of the operational amplifier are shown in fig. 5, an input terminal is an output branch, and the output branch can be directly output to a VCO circuit at a later stage, and an output voltage is sampled and input to the operational amplifier in a voltage following connection mode, and a current error is transferred to a capacitor at an output terminal of the operational amplifier, and then applied to a corresponding current source to reduce the error in a mode conversion process, wherein a series connection form of the capacitor and a resistor on the output branch provides a zero point for the whole circuit to make the structure more stable, and an additional small capacitor is used for reducing ripples.
In a word, the invention can effectively reduce phase noise and ripple waves, simultaneously introduces a zero point to solve the stability problem of the cascade feedback structure of the charge pump and the VCO, and reduces the influence of current mismatch by adopting the feedback structure, thereby reducing the phase noise.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A novel charge pump structure for a phase locked loop, characterized by: the phase frequency detector comprises a D trigger, a setting part controlled by a digital NAND gate and a phase frequency detector, wherein the phase frequency detector comprises the D trigger, a logic module reset part and an RS trigger, the RS trigger realizes the feedback control of an improved charge pump, the phase frequency detector formed by the D trigger realizes the control of the current of the charge pump in two states through the RS trigger, the phase noise and other non-ideal effect errors are reduced through the feedback of unit gain operational amplifier, a zero point is constructed by a series structure of a resistor and a capacitor to stabilize the whole loop, and another smaller capacitor is used for reducing ripples.
2. The novel charge pump architecture for a phase locked loop of claim 1, wherein: the operational amplifier is used as an input and output full swing and is used as a voltage following connection mode, one end branch output of the charge pump is fed back to the other branch, the operational amplifier is different from the traditional full input and output swing operational amplifier in a current mirror mode, and the P tube output is transmitted to the drain end of the N tube in the current mirror mode.
3. The novel charge pump architecture for a phase locked loop of claim 1, wherein: the RS trigger consists of two NAND gates and an inverter, and the size of the NAND gates in the RS trigger structure is adjusted to a proper value so as to minimize the delay brought by the trigger.
4. The novel charge pump architecture for a phase locked loop of claim 1, wherein: the digital NAND gate adopts multi-stage connection, so that a position end can be controlled by an external SPI input end, the charge pump control part adopts the output of an RS trigger to carry out double-end control, the output of one end is fed back to the output of the other end through the operational amplifier of full input and output swing, meanwhile, a zero point is constructed in a mode of series connection of a capacitor and a resistor to stabilize a loop, and a capacitor is additionally added to suppress ripples.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010530397.0A CN111585569A (en) | 2020-06-11 | 2020-06-11 | Novel charge pump structure for phase-locked loop |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010530397.0A CN111585569A (en) | 2020-06-11 | 2020-06-11 | Novel charge pump structure for phase-locked loop |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6166670A (en) * | 1998-11-09 | 2000-12-26 | O'shaughnessy; Timothy G. | Self calibrating current mirror and digital to analog converter |
| US20050168291A1 (en) * | 2004-01-23 | 2005-08-04 | Zarlink Semiconductor Ab | PLL phase/frequency detector with fully differential output charge pump |
| US20050189973A1 (en) * | 2004-02-27 | 2005-09-01 | Broadcom Corporation | Wide output-range charge pump with active biasing current |
| JP2007259215A (en) * | 2006-03-24 | 2007-10-04 | Toppan Printing Co Ltd | Pll circuit |
| JP2007274033A (en) * | 2006-03-30 | 2007-10-18 | Toyota Industries Corp | Pll circuit and driving method of charge pump circuit |
| US7385429B1 (en) * | 2005-05-31 | 2008-06-10 | Altera Corporation | Charge pump with reduced current mismatch |
| CN101309079A (en) * | 2007-05-14 | 2008-11-19 | 深圳艾科创新微电子有限公司 | Charge pump construction for phase lock loop circuit |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of being locked quickly |
| CN106301360A (en) * | 2015-05-28 | 2017-01-04 | 上海东软载波微电子有限公司 | Phase frequency detector, electric charge pump and phase-locked loop circuit |
-
2020
- 2020-06-11 CN CN202010530397.0A patent/CN111585569A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6166670A (en) * | 1998-11-09 | 2000-12-26 | O'shaughnessy; Timothy G. | Self calibrating current mirror and digital to analog converter |
| US20050168291A1 (en) * | 2004-01-23 | 2005-08-04 | Zarlink Semiconductor Ab | PLL phase/frequency detector with fully differential output charge pump |
| US20050189973A1 (en) * | 2004-02-27 | 2005-09-01 | Broadcom Corporation | Wide output-range charge pump with active biasing current |
| US7385429B1 (en) * | 2005-05-31 | 2008-06-10 | Altera Corporation | Charge pump with reduced current mismatch |
| JP2007259215A (en) * | 2006-03-24 | 2007-10-04 | Toppan Printing Co Ltd | Pll circuit |
| JP2007274033A (en) * | 2006-03-30 | 2007-10-18 | Toyota Industries Corp | Pll circuit and driving method of charge pump circuit |
| CN101309079A (en) * | 2007-05-14 | 2008-11-19 | 深圳艾科创新微电子有限公司 | Charge pump construction for phase lock loop circuit |
| CN103297042A (en) * | 2013-06-24 | 2013-09-11 | 中国科学院微电子研究所 | Charge pump phase-locked loop circuit capable of being locked quickly |
| CN106301360A (en) * | 2015-05-28 | 2017-01-04 | 上海东软载波微电子有限公司 | Phase frequency detector, electric charge pump and phase-locked loop circuit |
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Application publication date: 20200825 |
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