CN113938131A - Real-time fractional frequency division sub-sampling phase-locked loop - Google Patents

Real-time fractional frequency division sub-sampling phase-locked loop Download PDF

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CN113938131A
CN113938131A CN202111153059.0A CN202111153059A CN113938131A CN 113938131 A CN113938131 A CN 113938131A CN 202111153059 A CN202111153059 A CN 202111153059A CN 113938131 A CN113938131 A CN 113938131A
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phase
switch
sampling
sub
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CN113938131B (en
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张岩龙
贾国樑
耿莉
樊超
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Xian Jiaotong University
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Xian Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer

Abstract

The invention discloses a real-time fractional frequency division sub-sampling phase-locked loop, which comprises a reference clock input end, a common mode voltage input end, a frequency division control word input end, a radio frequency signal output end, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator and a frequency-locked loop.

Description

Real-time fractional frequency division sub-sampling phase-locked loop
Technical Field
The invention belongs to the technical field of electronics, and relates to a real-time fractional frequency division sub-sampling phase-locked loop.
Background
The phase-locked loop is one of important functional modules in a radio frequency/microwave communication system and a computer system, and is widely applied to generation of carrier signals, clock signals, frequency modulation signals and phase modulation signals due to the advantages of good frequency tracking characteristic, low phase noise, small stray component, high system stability and the like.
Compared with the traditional phase-locked loop based on a phase frequency detector-charge pump structure, the sub-sampling phase-locked loop directly utilizes the reference signal to sample the high-frequency signal output by the oscillator, an additional frequency divider is not needed, and noise introduced by the frequency divider and power consumption of the frequency divider are eliminated. In addition, the gain of the sub-sampling phase detector in the sub-sampling phase-locked loop is higher than that of a phase detector with a phase frequency detector-charge pump structure, so that the phase noise in the loop bandwidth can be better suppressed by the phase-locked loop, and the phase-locked loop is a research hotspot of the current phase-locked loop with low power consumption and low phase noise. The sub-sampling phase detector is lack of a mechanism for distinguishing the period of the oscillator, so that the sub-sampling phase detector cannot be directly used for a fractional-N phase-locked loop. To solve this problem, the most common method in the reported work at home and abroad is to modulate the phase of the reference signal by using a digital-to-time converter and change the sampling time to realize fractional division. However, the noise of the digital-to-time converter modulates the phase of the reference signal, introducing additional phase noise, and this phase noise is not effectively suppressed by the sub-sampling phase detector, thereby degrading the phase noise characteristics of the sub-sampling phase-locked loop. In addition, the accuracy and dynamic range of digital-to-time converters are susceptible to integrated circuit processes, chip supply voltages, ambient temperature, and output signal cycles, requiring real-time calibration to ensure accurate fractional frequency division. Furthermore, the non-linear characteristics of the digital-to-time converter cause noise folding, further degrading the phase noise characteristics of the sub-sampling phase-locked loop. The defects of the existing fractional-N sub-sampling phase-locked loop limit the wide application of the sub-sampling phase-locked loop in the current radio frequency/microwave communication system and computer system.
Although the sub-sampling phase-locked loop effectively suppresses phase noise within the system loop bandwidth, for fractional sub-sampling phase-locked loops, phase noise outside the loop bandwidth is still dominated by fractional quantization noise. Researchers at home and abroad in the last two decades have proposed a plurality of quantization noise suppression methods, such as feedforward compensation technology based on a digital-analog converter and a digital-time converter, phase difference value technology, filtering preprocessing method based on a finite impulse response filter, space-time mean fractional frequency division technology, and the like. However, these techniques have poor compatibility with the sub-sampling phase-locked loop, cannot be directly combined with the sub-sampling phase detector, and have limitations.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a real-time fractional frequency division sub-sampling phase-locked loop system framework, and the phase-locked loop has the advantage of low phase noise in the loop bandwidth of the sub-sampling phase-locked loop and can effectively inhibit the phase noise generated by fractional frequency division.
In order to achieve the above purpose, the sub-sampling phase-locked loop of the real-time fractional frequency division of the invention comprises a reference clock input end, a common mode voltage input end, a frequency division control word input end, a radio frequency signal output end, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator and a frequency-locked loop;
the first single-ended input end of the sub-sampling decimal phase discriminator is connected with the input end of a reference clock, the fourth single-ended input end of the sub-sampling decimal phase discriminator is connected with the input end of a common-mode voltage, the positive end and the negative end of the differential input end of a transconductance amplifier are respectively connected with the input end of the common-mode voltage and the output end of the sub-sampling decimal phase discriminator, the output end of the transconductance amplifier and the output end of a frequency-locking loop are connected with the input end of a low-pass filter, the output end of the low-pass filter is connected with the input end of a voltage-controlled oscillator, the single-ended output end of the voltage-controlled oscillator is connected with the input end of an output buffer and the first input end of the frequency-locking loop, the output end of the output buffer is connected with the output end of a radio-frequency signal, the second input end of the frequency-locking loop is connected with the input end of the reference clock, and the differential signal output end of the voltage-controlled oscillator is respectively connected with the first input end and the second input end of the sampling phase generator, the first output end and the second output end of the sampling phase generator are respectively connected with the second single-ended input end and the third single-ended input end of the sub-sampling decimal phase discriminator, the input end of the sampling and frequency division control signal generator is connected with the input end of a frequency division control word, the scalar output end of the sampling and frequency division control signal generator is connected with the control end of the frequency locking loop, the first vector output end of the sampling and frequency division control signal generator is connected with the vector control end of the sub-sampling decimal phase discriminator, and the second vector output end of the sampling and frequency division control signal generator is connected with the vector control end of the sampling phase generator.
The sub-sampling fractional phase discriminator comprises a mean voltage output end, a ramp signal generator, a first bootstrap switch, a second bootstrap switch, a sample-hold signal generator, mean logic, a fifth switch and a plurality of sub-sampling phase discrimination units;
each sub-sampling phase discrimination unit comprises a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor and a first inverter;
the first output end and the second output end of the sampling phase generator are respectively connected with the first input end and the second input end of a ramp signal generator, the first output end of the ramp signal generator is connected with the input end of a first bootstrap switch, the second output end of the ramp signal generator is connected with the input end of a second bootstrap switch, the reference clock input end is respectively connected with the control end of the first bootstrap switch, the control end of the second bootstrap switch and the input end of the sampling-holding signal generator, the output end of the first bootstrap switch is connected with one end of a first switch in each sub-sampling phase discrimination unit, and the output end of the second bootstrap switch is connected with one end of a second switch in each sub-sampling phase discrimination unit; in each sub-sampling phase demodulation unit, the other end of the first switch is connected with one end of the first capacitor and one end of the third switch, the other end of the second switch is connected with one end of the second capacitor and one end of the fourth switch, the other end of the first capacitor and the other end of the second capacitor are both grounded, the other end of the third switch in all sub-sampling phase demodulation units and the other end of the fourth switch in all sub-sampling phase demodulation units are connected with one end of the fifth switch to be used as the average voltage output end of the sub-sampling decimal phase demodulation unit, the first clock output end of the sample-hold signal generator is connected with the control end of the first switch in each sub-sampling phase demodulation unit and the control end of the second switch in each sub-sampling phase demodulation unit, the second clock output end of the sample-hold signal generator is connected with the scalar input end of the average logic, and the hold signal output end of the average logic is connected with the control end of the third switch in the corresponding sub-sampling phase demodulation unit and the control end of the corresponding sub-sampling single phase demodulation unit The input end of the first phase inverter in each sub-sampling phase demodulation unit is connected, the output end of the first phase inverter in each sub-sampling phase demodulation unit is connected with the control end of the fourth switch in the corresponding sub-sampling phase demodulation unit, the mean value control end is connected with the vector control end of the mean value logic, the third clock output end of the sampling-holding signal generator is connected with the control end of the fifth switch, and the other end of the fifth switch is connected with the common-mode voltage input end.
The slope signal generator comprises a frequency/phase discriminator, a second phase inverter, a third phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first resistor and a second resistor;
the first output end and the second output end of the sampling phase generator are respectively connected with the first input end and the second input end of the frequency/phase discriminator, the first output end of the frequency/phase discriminator is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube, the source electrode of the first PMOS tube is connected with the power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the source electrode of the first NMOS tube is grounded, the other end of the first resistor is connected with the drain electrode of the first NMOS tube and then serves as a first voltage signal output end, the second output end of the frequency/phase discriminator is connected with the input end of the third phase inverter, the output end of the third phase inverter is connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with one end of the second resistor, the source electrode of the second NMOS tube is grounded, and the other end of the second resistor is connected with the drain electrode of the second NMOS tube and then serves as a second voltage signal output end.
The sample-hold signal generator comprises a first delay unit, a fourth inverter, a second delay unit, a first buffer, a third delay unit and a fifth inverter;
the reference clock input end is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the input end of the fourth phase inverter, the output end of the fourth phase inverter is connected with the input end of the second delay unit and the input end of the third delay unit, the output end of the fourth phase inverter is used as the first clock output end, the output end of the second delay unit is connected with the input end of the first buffer, the output end of the first buffer is used as the second clock output end, the output end of the third delay unit is connected with the input end of the fifth phase inverter, and the output end of the fifth phase inverter is used as the third clock output end.
The average logic comprises a plurality of holding signal output ends and a plurality of average logic units, wherein each average logic unit comprises a sixth inverter and a first AND gate;
the first vector output end of the sampling and frequency division control signal generator comprises a plurality of sub-input ends, wherein one sub-input end corresponds to one mean value logic unit and one sub-sampling phase discrimination unit, each sub-input end is connected with the input end of a sixth phase inverter in the corresponding mean value logic unit, the output end of the sixth phase inverter in each mean value logic unit is connected with the first input end of a first AND gate, the second clock output end of the sampling-holding signal generator is connected with the second input end of the first AND gate in all the mean value logic units, and the output end of each first AND gate serving as the corresponding holding signal output end is connected with the control end of a third switch in the corresponding sub-sampling phase discrimination unit and the input end of the first phase inverter.
The sampling phase generator comprises an orthogonal/2 frequency divider, a multiplexer, a first phase interpolation unit, a third capacitor, a second phase interpolation unit, a fourth capacitor, a third phase interpolation unit, a fifth capacitor, a fourth phase interpolation unit, a sixth capacitor, a fifth phase interpolation unit, a seventh capacitor, a sixth phase interpolation unit, an eighth capacitor, a seventh phase interpolation unit, a ninth capacitor, an eighth phase interpolation unit, a tenth capacitor, a ninth phase interpolation unit, an eleventh capacitor, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch and an eleventh switch;
the differential input end of the orthogonal/2 frequency divider is connected with the differential signal output end of the voltage-controlled oscillator, the first output end, the second output end, the third output end and the fourth output end of the orthogonal/2 frequency divider are respectively connected with the first input end, the second input end, the third input end and the fourth input end of the multi-path selector, and the first control end and the second control end of the multi-path selector are respectively connected with the fourth sub-input end and the fifth sub-input end of the second vector output end of the sampling and frequency division control signal generator;
the first output end of the multi-path selector is connected with the first input end of the first phase interpolation unit, the second input end of the first phase interpolation unit and the first input end of the second phase interpolation unit, the second output end of the multi-path selector is connected with the second input end of the second phase interpolation unit, the first input end of the third phase interpolation unit and the second input end of the third phase interpolation unit, the output end of the first phase interpolation unit is connected with one end of the third capacitor and the first selection end of the sixth switch, the other end of the third capacitor is grounded, the output end of the second phase interpolation unit is connected with one end of the fourth capacitor, the second selection end of the sixth switch and the first selection end of the seventh switch, the other end of the fourth capacitor is grounded, the output end of the third phase interpolation unit is connected with one end of the fifth capacitor and the second selection end of the seventh switch, the other end of the fifth capacitor is grounded, and a third sub-input end of a second vector output end of the sampling and frequency division control signal generator is connected with a control end of the sixth switch and a control end of the seventh switch;
the fixed end of the sixth switch is connected with the first input end of the fourth phase interpolation unit, the second input end of the fourth phase interpolation unit and the first input end of the fifth phase interpolation unit, the fixed end of the seventh switch is connected with the second input end of the fifth phase interpolation unit, the first input end of the sixth phase interpolation unit and the second input end of the sixth phase interpolation unit, the output end of the fourth phase interpolation unit is connected with one end of the sixth capacitor and the first selection end of the eighth switch, the other end of the sixth capacitor is grounded, the output end of the fifth phase interpolation unit is connected with one end of the seventh capacitor, the second selection end of the eighth switch and the first selection end of the ninth switch, the other end of the seventh capacitor is grounded, the output end of the sixth phase interpolation unit is connected with one end of the eighth capacitor and the second selection end of the ninth switch, the other end of the eighth capacitor is grounded, a second sub-input end of a second vector output end of the sampling and frequency division control signal generator is connected with a control end of the eighth switch and a control end of the ninth switch;
the fixed end of the eighth switch is connected with the first input end of the seventh phase interpolation unit, the second input end of the seventh phase interpolation unit and the first input end of the eighth phase interpolation unit, the fixed end of the ninth switch is connected with the second input end of the eighth phase interpolation unit, the first input end of the ninth phase interpolation unit and the second input end of the ninth phase interpolation unit, the output end of the seventh phase interpolation unit is connected with one end of the ninth capacitor and the first selection end of the tenth switch, the other end of the ninth capacitor is grounded, the output end of the eighth phase interpolation unit is connected with one end of the tenth capacitor, the second selection end of the tenth switch and the first selection end of the eleventh switch, the other end of the tenth capacitor is grounded, the output end of the ninth phase interpolation unit is connected with one end of the eleventh capacitor and the second selection end of the eleventh switch, and the other end of the eleventh capacitor is grounded, and a first input end of a second vector output end of the sampling and frequency division control signal generator is connected with a control end of the tenth switch and a control end of the eleventh switch, and a fixed end of the tenth switch and a fixed end of the eleventh switch are respectively used as a first output end and a second output end of the sampling phase generator.
Each phase interpolation unit comprises a first current source, a second current source, a third PMOS (P-channel metal oxide semiconductor) tube, a fourth PMOS tube, a third NMOS (N-channel metal oxide semiconductor) tube, a fourth NMOS tube and a second AND gate;
the first input end of the phase interpolation unit is connected with the grid electrode of a third PMOS tube and the first input end of a second AND gate, the source electrode of the third PMOS tube is connected with one end of a first current source, the other end of the first current source is connected with a power supply, the second input end of the phase interpolation unit is connected with the grid electrode of a fourth PMOS tube and the second input end of the second AND gate, the source electrode of the fourth PMOS tube is connected with one end of a second current source, the other end of the second current source is connected with the power supply, the output end of the second AND gate is connected with the grid electrode of a third NMOS tube and the grid electrode of a fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are connected and then serve as the output end of the phase interpolation unit.
The sampling and frequency division control signal generator comprises a decimal delta-sigma modulator, a first adder, a second adder, an accumulator and a data weight mean value module;
the number of bits of the input end of the frequency division control word is 25 bits, the input end of the frequency division control word is connected with the input end of the decimal delta-sigma modulator, the 5-bit wide first output end of the decimal delta-sigma modulator is connected with the input end of the adder, the 5-bit wide second output end of the decimal delta-sigma modulator is connected with the input end of the accumulator, the 6-bit wide third output end of the decimal delta-sigma modulator is connected with the input end of the data weight mean value module, the 5-bit wide output end of the first adder is used as the scalar output end of the sampling and frequency division control signal generator, the 6-bit wide output end of the accumulator is connected with the 6-bit wide input end of the second adder, the 1-bit output end of the data weight mean value module is connected with the 1-bit wide input end of the second adder, the highest 1 bit of the 6-bit wide output end of the second adder is connected with the 1-bit wide input end of the first adder, and the lower 5 bits of the 6-bit wide output end of the second adder are used as the second input end of the sampling and frequency division control signal generator And the vector output end and the 64-unit vector output end of the data weight average module are used as a first vector output end of the sampling and frequency division control signal generator.
The invention has the following beneficial effects:
when the real-time fractional-N sub-sampling phase-locked loop is in specific operation, the structure of the sub-sampling fractional-N phase discriminator based on the voltage mean value is adopted, the fractional-N is realized under the condition of no need of the assistance of a digital-time converter, the problems that the digital-time converter deteriorates the phase noise characteristic of a reference clock and the module is easily influenced by the integrated circuit process, the chip power supply voltage and the environmental temperature are solved, the phase noise source of the fractional-N sub-sampling phase-locked loop is remarkably reduced, and the fractional-N sub-sampling phase-locked loop with lower phase noise is favorably realized. In addition, the voltage mean value is completed by utilizing the sub-sampling fractional phase discriminator, the process is not influenced by the periodic variation of the output signal of the voltage controlled oscillator, the problem that the gain of the digital-time converter needs to be calibrated in real time in the traditional fractional frequency division based sub-sampling phase-locked loop of the digital-time converter is solved, the fractional frequency division function can be realized in the sub-sampling phase-locked loop without calibration, the complexity and the power consumption of a system are reduced, and the low-power consumption fractional frequency division sub-sampling phase-locked loop is favorably realized. Finally, the control circuit of the space-time mean value technology is mainly realized by a digital circuit, so that the method has good immunity to errors caused by process, voltage and temperature fluctuation, has good process reconfigurability and is convenient for automatic design, and can further reduce power consumption and hardware overhead along with the continuous progress of an integrated circuit manufacturing process. In addition, the data weight average module for controlling the spatial average process can perform first-order high-pass shaping on the mismatch of the capacitors in the sub-sampling decimal phase discriminator unit array, and output stray caused by the mismatch of the capacitors in the sub-sampling decimal phase discriminator is reduced.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a sub-sampling fractional phase detector of the present invention;
FIG. 3 is a schematic diagram of a ramp signal generator according to the present invention;
FIG. 4 is a schematic diagram of a sample-and-hold signal generator of the present invention;
FIG. 5 is a schematic diagram of the mean logic of the present invention;
FIG. 6 is a block diagram of a sampling phase generator according to the present invention;
FIG. 7 is a schematic diagram of a phase interpolation unit according to the present invention;
FIG. 8 is a block diagram of a sampling and frequency division control signal generator according to the present invention;
FIG. 9 is a schematic diagram of the quadrature/2 divider and the timing diagram of the present invention;
fig. 10 is a block diagram of the frequency-locked loop according to the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
There is shown in the drawings a schematic block diagram of a disclosed embodiment in accordance with the invention. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, according to actual needs.
Referring to fig. 1, the sub-sampling phase-locked loop of the real-time fractional frequency division of the present invention includes a reference clock input terminal, a common mode voltage input terminal, a frequency division control word input terminal, a radio frequency signal output terminal, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator, and a frequency-locked loop;
first single-end input end and reference clock input end phi of sub-sampling fractional phase discriminatorrefConnected, the fourth single-end input end of the sub-sampling decimal phase discriminator and the common-mode voltage input end VCMConnected with the positive terminal and the negative terminal of the differential input terminal of the transconductance amplifier and the common-mode voltage input terminal V respectivelyCMAnd the output end V of the sub-sampling decimal phase discriminatorHoldConnected, output terminal I of transconductance amplifierCP,PLLAnd the output end I of the frequency-locked loopCP,FLLAnd an input terminal I of a low-pass filterCPConnected, low-pass filter outputTerminal VCConnected to the input of a voltage-controlled oscillator, the single-ended output of which is phifvcoConnected with the input end of the output buffer and the first input end of the frequency-locked loop, and the output end of the output buffer and the radio-frequency signal output end phiPLLConnected, the second input of the frequency-locked loop and the reference clock input phirefDifferential signal output of phase-connected voltage-controlled oscillatorVCOPAnd phiVCONRespectively connected with the first input end and the second input end of a sampling phase generator, and the first output end phi of the sampling phase generatorLEADAnd a second output phiLAGThe sampling and frequency division control signal generator is connected with the second single-ended input end and the third single-ended input end of the sub-sampling fractional phase discriminator respectively, the input end of the sampling and frequency division control signal generator is connected with the input end N + alpha of the frequency division control word, and the scalar output end N of the sampling and frequency division control signal generator is connected with the scalar output end NdivA first vector output end connected with the control end of the frequency-locking loop and used for sampling and frequency-dividing control signal generator
Figure BDA0003287692300000121
A second vector output end connected with the vector control end of the sub-sampling decimal phase discriminator and used for sampling and frequency division control signal generator
Figure BDA0003287692300000122
Connected with the vector control end of the sampling phase generator.
Referring to fig. 2, the sub-sampling fractional phase detector includes a ramp signal generator, a first bootstrap switch BSW1A second bootstrap switch BSW2A sample-and-hold signal generator, an averaging logic, a fifth switch SW5And a plurality of sub-sampling phase discrimination units;
wherein each sub-sampling phase discrimination unit comprises a first switch SW1A second switch SW2A third switch SW3A fourth switch SW4A first capacitor C1A second capacitor C2And a first inverter INV1；
First output of a sampling phase generatorLEADAnd a second outputEnd phiLAGRespectively connected with the first input end and the second input end of a ramp signal generator, and the first output end V of the ramp signal generatorLeadAnd a first bootstrap switch BSW1Is connected to the second output terminal V of the ramp signal generatorLagAnd a second bootstrap switch BSW2Are connected with reference clock input phirefRespectively connected with the first bootstrap switch BSW1Control terminal of the first bootstrap switch BSW2Is connected to the input of the sample-and-hold signal generator, a first bootstrap switch BSW1And the output end of each sub-sampling phase discrimination unit1Is connected to a second bootstrap switch BSW2And the output end of each sub-sampling phase discrimination unit2One end of the two ends are connected; first switch SW1And the other end of the first capacitor C1And a third switch SW3Is connected to one end of a second switch SW2And the other end of the first capacitor C2And a fourth switch SW4Is connected to a first capacitor C1And the other end of the second capacitor C2The other ends of the two sub-sampling phase demodulation units are all grounded, and the third switches SW in all the sub-sampling phase demodulation units3And the other end of the first switch SW and the fourth switches SW in all the sub-sampling phase discrimination units4And the other end of the first switch and a fifth switch SW5One end of the sub-sampling fractional phase discriminator is connected and then used as a mean voltage output end V of the sub-sampling fractional phase discriminatorHoldFirst clock output of sample-and-hold signal generator phiSampAnd a first switch SW in each sub-sampling phase discrimination unit1Control terminal and second switch SW in each sub-sampling phase discrimination unit2Is connected to the second clock output phi of the sample-and-hold signal generatorHoldConnected with the input end of the mean logic, Hold signal output end Hold of the mean logiciAnd the third switch SW in the ith sub-sampling phase discrimination unit3The control end and the first inverter INV in the ith sub-sampling phase discrimination unit1Is connected with the input end of the first inverter INV1And the output end of the first sub-sampling phase discrimination unit and a fourth switch SW in the ith sub-sampling phase discrimination unit4Are connected with the control end of the mean value control end
Figure BDA0003287692300000131
A third clock output of the sample-and-hold signal generator, coupled to the vector input of the mean logicCLRAnd a fifth switch SW5Is connected with the control end of the fifth switch SW5And the other end of the common mode voltage input terminal VCMAre connected.
When the sub-sampling decimal phase discriminator works, the input end phi of the reference clockrefThe input reference clock signal controls the first bootstrap switch BSW1And a second bootstrap switch BSW2First clock output of sample-and-hold signal generator phiSampControlling a first switch SW in each sub-sampling phase detector unit1And a second switch SW2Two paths of voltage signals V output by the ramp signal generator are respectively usedLeadAnd VLagSampling to a first capacitor C1And a second capacitor C2Second clock output phi of the sample-and-hold signal generator, recorded in the form of an electric chargeHoldControlling a third switch SW in each sub-sampling phase discriminator unit through mean logic3And a fourth switch SW4Third clock output end phi of real-time fractional frequency division, sampling-holding signal generator by voltage mean valueCLRControl of the third switch SW3For the first capacitor C1And a second capacitor C2Resetting is performed.
Referring to fig. 3, the ramp signal generator includes a frequency/phase detector, a second inverter INV2A third inverter INV3The first PMOS transistor MP1And a second PMOS transistor MP2A first NMOS transistor MN1A second NMOS transistor MN2A first resistor R1And a second resistor R2；
First output of a sampling phase generatorLEADAnd a second output phiLAGConnected with the first input end and the second input end of the frequency/phase discriminator respectively, and the first output end of the frequency/phase discriminator and the second inverter INV2Is connected to the input end of the second inverter INV2Output end of and the first PMOS transistor MP1Gate and first NMOS transistor MN1Is connected with the grid electrode of the first PMOS transistor MP1The source of the first PMOS transistor MP is connected with a power supply1And the first resistor R1Is connected with the first NMOS transistor MN1Is grounded, a first resistor R1And the other end of the first NMOS transistor MN1Is connected as a first voltage signal output terminal VLeadThe second output end of the frequency/phase discriminator and the third inverter INV3Is connected to the input end of the third inverter INV3Output end of the first PMOS transistor MP2Gate and second NMOS transistor MN2The grid of the first PMOS transistor MP is connected with the grid of the second PMOS transistor MP2The source of the second PMOS tube MP is connected with a power supply2And the second resistor R2Is connected with one end of the second NMOS tube MN2Is grounded, and a second resistor R2And the other end of the second NMOS transistor MN2The drain electrode is connected to serve as a second voltage signal output end VLag。
Referring to fig. 4, the sample-and-hold signal generator includes a first Delay unit Delay1And a fourth inverter INV4A second Delay unit Delay2A first buffer BUFF1And a third Delay unit Delay3And a fifth inverter INV5；
Reference clock input phirefAnd a first Delay unit Delay1Is connected with the input end of the first Delay unit Delay1And the output end of the fourth inverter INV4Is connected to the input end of the fourth inverter INV4And the output end of the first Delay unit Delay2Input terminal and third Delay unit Delay3Is connected to the input terminal of the fourth inverter INV4As the first clock output phiSampA second Delay unit Delay2And the output terminal of the first buffer BUFF1Are connected to the input terminal of a first buffer BUFF1As a second clock output phiHoldA third Delay unit Delay3And the output end of the fifth inverter INV5Is connected to the input terminal of the fifth inverter INV5As the third clock output phiCLR。
Referring to FIG. 5, the averaging logic includes several Hold signal outputs HoldiAnd a plurality of average logic units, wherein each average logic unit comprises a sixth inverter INV6AND a first AND gate AND1；
First vector output terminal of sampling and frequency division control signal generator
Figure BDA0003287692300000151
The digital phase detector comprises a plurality of sub-input ends, wherein one sub-input end corresponds to an average logic unit and a sub-sampling phase detection unit, and each sub-input end corresponds to a sixth inverter INV in the average logic unit6Is connected with the input end of the first inverter INV in each mean value logic unit6AND the output terminal of (1) is AND-gate1Is connected to the first input terminal of the sample-and-hold signal generator, and a second clock output terminal phi of the sample-and-hold signal generatorHoldAND gate AND with the first AND gate in all mean logic units1Is connected with the first AND gate AND in the ith mean logic unit1As the corresponding ith Hold signal output terminal HoldiCorresponding to the third switch SW in the ith sub-sampling phase discrimination unit3Control terminal and first inverter INV1Are connected.
Referring to fig. 6, the sample phase generator comprises a quadrature/2 divider, a multiplexer MUX1First phase interpolation unit Cell1A third capacitor C3Second phase interpolation unit Cell2A fourth capacitor C4A third phase interpolation unit Cell3A fifth capacitor C5A fourth phase interpolation unit Cell4A sixth capacitor C6The fifth phase interpolation unit Cell5A seventh capacitor C7Sixth phase interpolation unit Cell6An eighth capacitor C8The seventh phase interpolation unit Cell7A ninth capacitor C9The eighth phase interpolation unit Cell8A tenth capacitor C10The ninth phase interpolation unit Cell9An eleventh capacitor C11A sixth switch SW6And a seventh switch SW7An eighth switch SW8And a ninth switch SW9The tenth switch SW10And an eleventh switch SW11；
Differential input end of quadrature/2 frequency divider and differential signal output end phi of voltage-controlled oscillatorVCOPAnd phiVCONFirst output phi of phase-connected, quadrature/2 frequency dividerIAnd a second output terminal phiQAnd a third output phiIBAnd a fourth output phiQBRespectively connected with a multiplexer MUX1Is connected to the first, second, third and fourth input terminals, a multiplexer MUX1The first control end and the second control end of the frequency divider are respectively connected with the second vector output end of the sampling and frequency dividing control signal generator
Figure BDA0003287692300000161
Fourth sub-input terminal NPS,3And a fifth sub-input terminal NPS,4Connecting;
multiplexer MUX1First output end and first phase interpolation unit Cell1First input terminal, first phase interpolation unit Cell1Second input terminal and second phase interpolation unit Cell2Are connected to a first input terminal of a multiplexer MUX1Second output terminal of the first phase interpolation unit and the second phase interpolation unit Cell2Second input terminal, third phase interpolation unit Cell3First input terminal and third phase interpolation unit Cell3Is connected to the first phase interpolation unit Cell1And the output terminal of the third capacitor C3And a sixth switch SW6Is connected to the third capacitor C3The other end of the first phase interpolation unit is grounded, and the second phase interpolation unit Cell2And the output terminal of the fourth capacitor C4One end of, a sixth switch SW6Second selection terminal and seventh switch SW7Is connected with the first selection terminal, and a fourth capacitor C4The other end of the first phase interpolation unit is grounded, and the third phase interpolation unit Cell3And the output terminal of the fifth capacitor C5And a seventh switch SW7Is connected with the second selection terminal, and a fifth capacitor C5The other end of the sampling and frequency division control signal generator is grounded, and a second vector output end of the sampling and frequency division control signal generator
Figure BDA0003287692300000171
Third sub-input terminal N ofPS,2And a sixth switch SW6Control terminal and seventh switch SW7The control ends are connected;
sixth switch SW6Fixed end and fourth phase interpolation unit Cell4First input terminal, fourth phase interpolation unit Cell4Second input terminal and fifth phase interpolation unit Cell5Is connected to the first input terminal of the seventh switch SW7Fixed end and fifth phase interpolation unit Cell5Second input terminal of, sixth phase interpolation unit Cell6First input terminal and sixth phase interpolation unit Cell6Is connected to the fourth phase interpolation unit Cell4And the output end of the sixth capacitor C6And an eighth switch SW8Is connected with the sixth capacitor C6The other end of the first phase interpolation unit is grounded, and a fifth phase interpolation unit Cell5And the output end of the seventh capacitor C7One end of, an eighth switch SW8Second selection terminal and ninth switch SW9Is connected with the first selection terminal, and a seventh capacitor C7Is grounded, a sixth phase interpolation unit Cell6And an eighth capacitor C8And a ninth switch SW9Is connected with the eighth capacitor C8The other end of the sampling and frequency division control signal generator is grounded, and a second vector output end of the sampling and frequency division control signal generator
Figure BDA0003287692300000172
Second sub-input terminal N ofPS,1And an eighth switch SW8Control terminal and ninth switch SW9The control ends are connected;
eighth switch SW8Fixed end and seventh phase interpolation unit Cell7First input end, seventh phase interpolationCell7Second input terminal and eighth phase interpolation unit Cell8Is connected to the first input terminal of the ninth switch SW9Fixed end and eighth phase interpolation unit Cell8Second input terminal, ninth phase interpolation unit Cell9First input terminal and ninth phase interpolation unit Cell9Is connected to the seventh phase interpolation unit Cell7And the ninth capacitor C9And a tenth switch SW10Is connected with the first selection terminal, and a ninth capacitor C9The other end of the first phase interpolation unit is grounded, and the eighth phase interpolation unit Cell8And the output terminal of the tenth capacitor C10One end of, a tenth switch SW10Second selection terminal and eleventh switch SW11Is connected with the tenth capacitor C10The other end of the first phase interpolation unit is grounded, and the ninth phase interpolation unit Cell9And the output end of the eleventh capacitor C11And an eleventh switch SW11Is connected with the eleventh capacitor C11The other end of the sampling and frequency division control signal generator is grounded, and a second vector output end of the sampling and frequency division control signal generator
Figure BDA0003287692300000181
First input terminal N ofPS,0And a tenth switch SW10Control terminal and eleventh switch SW11Is connected with the control end of the tenth switch SW10Fixed end and eleventh switch SW11Respectively as a first output phi of the sampling phase generatorLEADAnd a second output phiLAG。
When the sampling phase generator works, the orthogonal/2 frequency divider firstly divides the input differential signal phiVCOPAnd phiVCONFrequency division by two to generate four orthogonal signals phiI、ΦIQ、ΦIB、ΦQBThen, the phase difference value is realized by a streamline phase interpolator to generate an output signal phiLEADAnd phiLAGI.e. the sampling phase generator controls the terminal by selecting phase
Figure BDA0003287692300000182
Of (2) a fifth input terminal NPS,4And a fourth input terminal NPS,3Controlling the multiplexer to perform coarse interpolation on the output signal, and controlling the phase selection control terminal
Figure BDA0003287692300000183
Third input terminal N ofPS,2A second input terminal NPS,1And a first input terminal NPS,0Controlling the pipelined phase interpolator to perform fine interpolation on the output signal to output a sampling signal phiLEADAnd phiLAGWith the appropriate phase.
Referring to fig. 7, each phase interpolation unit includes a first current source CS1A second current source CS2And the third PMOS transistor MP3And the fourth PMOS transistor MP4And a third NMOS transistor MN3And a fourth NMOS transistor MN4AND second AND gate AND2；
First input end phi of phase interpolation unitin1And a third PMOS transistor MP3AND second AND gate AND2The first input end of the first PMOS tube MP is connected with the second PMOS tube MP3Source and first current source CS1Is connected to a first current source CS1Is connected to a power supply, and a second input end phi of the phase interpolation unitin2And a fourth PMOS transistor MP4AND second AND gate AND2The second input end of the fourth PMOS tube MP is connected with the first output end of the first PMOS tube MP4Source and second current source CS2Is connected to a second current source CS2Is connected with the power supply, a second AND gate AND2And the output end of the third NMOS transistor MN3Grid and fourth NMOS transistor MN4Is connected with the grid electrode of the third NMOS tube MN3The source electrode of the NMOS transistor is grounded, and the fourth NMOS transistor MN4The source electrode of the PMOS transistor is grounded, and a third PMOS transistor MP3Drain electrode of the fourth PMOS transistor MP4Drain electrode of the third NMOS transistor MN3Drain electrode of and fourth NMOS transistor MN4Connected as the output of the phase interpolation unitout。
Referring to fig. 8, the sampling and frequency division control signal generator includes a fractional delta sigma modulator, a first adderADD1And a second adder ADD2ACC accumulator1And a data weight average module;
the number of bits of the frequency division control word input end N + alpha is 25 bits, the frequency division control word input end N + alpha is connected with the input end of the decimal delta-sigma modulator, and the first output end d with 5 bits wide of the decimal delta-sigma modulatorinteAnd adder ADD1Are connected, the 5-bit wide second output terminal d of the small-number delta-sigma modulatorfrac,MSBAnd accumulator ACC1Are connected, the 6-bit wide third output d of the small-number delta-sigma modulatorfrac,LSBA first adder ADD connected with the input end of the data weight average module1The 5-bit wide output end of the sampling and frequency division control signal generator is used as a scalar output end N of the sampling and frequency division control signal generatordivAccumulator ACC1And the 6-bit wide output end of the second adder ADD2Is connected with the input end with 6 bit width, and the 1 bit output end N of the data weight average value modulerefAnd a second adder ADD2Is connected with the 1 bit wide input end of the second adder ADD2The highest 1 bit of the 6-bit wide output end of the adder and the first adder ADD1Is connected with the 1 bit wide input end of the second adder ADD2The lower 5 bits of the 6-bit wide output end are used as the second vector output end of the sampling and frequency division control signal generator
Figure BDA0003287692300000191
The 64-unit vector output end of the data weight mean value module is used as the first vector output end of the sampling and frequency division control signal generator
Figure BDA0003287692300000192
Referring to the schematic circuit diagram of fig. 9, the quadrature/2 divider includes a first D flip-flop DFF1And a second D flip-flop DFF2；
First differential signal input end phiVCOPAnd a first D flip-flop DFF1Is connected to the clock input terminal of the first D flip-flop DFF1As the first clock output phiIFirst D flip-flop DFF1Negative output terminal ofAnd a first D flip-flop DFF1As a second clock output phi after being connectedIBSecond differential signal input terminal phiVCONAnd a second D flip-flop DFF2Is connected to the clock input terminal of a second D flip-flop DFF2As a third clock output phiQSecond D flip-flop DFF2And the second D flip-flop DFF2After being connected, the data input ends of the four-way clock are used as the output end phi of the fourth clockQB。
Referring to the time domain waveform diagram in fig. 9, the input signal of the quadrature/2 frequency divider is two clock signals with a phase difference of pi, the output signal is a four clock signal with a period twice as long as the period of the input signal, and the output signal phiIAnd phiQ、ΦQAnd phiIB、ΦIBAnd phiQB、ΦQBAnd phiIThe phase difference between the four clock signals is pi/2, namely the four output signals are orthogonal clock signals.
Referring to fig. 10, the frequency locked loop includes a seventh inverter INV7The frequency discrimination phase discriminator with the dead zone comprises a multi-mode frequency divider, a frequency discrimination phase discriminator with the dead zone and a charge pump;
reference clock input phirefINV and a seventh inverter7Is connected with the input end of the seventh inverter INV7Output of phirefnA single-ended output end phi of the voltage-controlled oscillator connected with the first input end of the phase frequency detector with dead zonefvcoA scalar output end N connected with the input end of the multi-mode frequency divider and used for sampling and frequency division control signal generatordivConnected with the 5-bit wide control end of the multi-mode frequency divider, and the output end phi of the multi-mode frequency dividerfdivThe first output end UP of the phase frequency detector with the dead zone is connected with the first input end of a charge pump, the second output end DN of the phase frequency detector with the dead zone is connected with the second input end of the charge pump, and the output end of the charge pump is used as the output end I of a frequency-locked loopCP,FLL。
Two-way input clock signal phi of phase frequency detector with dead zonerefnAnd phifdivIs greater thanWhen the phase frequency detector with the dead zone is in a phase frequency detection state, the two output ends of the phase frequency detector with the dead zone control the charge pump to charge/discharge the low-pass filter, so that the frequency locking of the phase-locked loop is realized; two-way input clock signal phi of phase frequency detector with dead zonerefnAnd phifdivWhen the phase difference between the phase difference signals is smaller than the dead zone range, the phase frequency detector with the dead zone stops working, two output ends of the phase frequency detector with the dead zone keep logic low level, the charge pump is closed, and the phase-locked loop is controlled by the sub-sampling decimal phase detector to complete phase locking.

Claims (8)

1. A real-time fractional frequency division sub-sampling phase-locked loop is characterized by comprising a reference clock input end, a common mode voltage input end, a frequency division control word input end, a radio frequency signal output end, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator and a frequency locking loop;
a first single-ended input terminal and a reference clock input terminal (phi) of the sub-sampled fractional phase detectorref) Connected, the fourth single-ended input terminal of the sub-sampling fractional phase detector and the common-mode voltage input terminal (V)CM) Connected to the common-mode voltage input (V) via the positive and negative terminals of the differential input of the transconductance amplifierCM) And the output end (V) of the sub-sampling decimal phase discriminatorHold) Connected, output terminal (I) of transconductance amplifierCP,PLL) And the output (I) of the frequency-locked loopCP,FLL) And the input (I) of the low-pass filterCP) Connected, the output (V) of the low-pass filterC) A single-ended output (phi) of the voltage-controlled oscillator connected to the input of the voltage-controlled oscillatorfvco) Connected with the input end of the output buffer and the first input end of the frequency locking loop, and the output end of the output buffer and the radio frequency signal output end (phi)PLL) Connected, the second input of the frequency-locked loop and the reference clock input (phi)ref) Differential signal output (phi) of phase-connected, voltage-controlled oscillatorVCOP) And (phi)VCON) Respectively connected with first inputs of the sampling phase generatorsTerminal connected to the second input terminal, a first output terminal (phi) of the sampling phase generatorLEAD) And a second output terminal (phi)LAG) Respectively connected with the second single-end input end and the third single-end input end of the sub-sampling fractional phase discriminator, the input end of the sampling and frequency division control signal generator is connected with the input end of the frequency division control word (N + alpha), and the scalar output end (N + alpha) of the sampling and frequency division control signal generatordiv) A first vector output end connected with the control end of the frequency-locking loop and used for sampling and frequency-dividing control signal generator
Figure FDA0003287692290000011
A second vector output end connected with the vector control end of the sub-sampling decimal phase discriminator and used for sampling and frequency division control signal generator
Figure FDA0003287692290000012
Connected with the vector control end of the sampling phase generator.
2. The real-time fractional-N sub-sampled PLL of claim 1, wherein the sub-sampled fractional-N phase detector comprises a ramp signal generator, a first Bootstrap Switch (BSW)1) A second Bootstrap Switch (BSW)2) Sample-and-hold signal generator, averaging logic, fifth Switch (SW)5) And a plurality of sub-sampling phase discrimination units;
wherein each sub-sampling phase discrimination unit comprises a first Switch (SW)1) A second Switch (SW)2) And a third Switch (SW)3) And a fourth Switch (SW)4) A first capacitor (C)1) A second capacitor (C)2) And a first Inverter (INV)1)；
First output terminal (phi) of sampling phase generatorLEAD) And a second output terminal (phi)LAG) Respectively connected with the first input terminal and the second input terminal of the ramp signal generator, and the first output terminal (V) of the ramp signal generatorLead) And a first Bootstrap Switch (BSW)1) Is connected to the input of the ramp signal generator, and a second output (V) of the ramp signal generatorLag) And a secondBootstrap Switch (BSW)2) Are connected to the reference clock input (phi)ref) Respectively connected with a first Bootstrap Switch (BSW)1) Control terminal of (1), second Bootstrap Switch (BSW)2) Is connected to the input of the sample-and-hold signal generator, a first Bootstrap Switch (BSW)1) And the first Switch (SW) in each sub-sampling phase discrimination unit1) Is connected to a second Bootstrap Switch (BSW)2) And the second Switch (SW) in each sub-sampling phase discrimination unit2) One end of the two ends are connected; in each sub-sampling phase discrimination unit, a first Switch (SW)1) And the other terminal of (C) and a first capacitor (C)1) And a third Switch (SW)3) Is connected to one end of a second Switch (SW)2) And the other terminal of (C) and a second capacitor (C)2) And a fourth Switch (SW)4) Is connected to a first capacitor (C)1) And the other terminal of (C) and a second capacitor (C)2) And the other end of the phase detector is grounded, and third Switches (SW) in all the sub-sampling phase detection units3) And a fourth Switch (SW) in all sub-sampling phase detection units4) And the other end of the first Switch (SW) and a fifth Switch (SW)5) One end of the sub-sampling fractional phase discriminator is connected to be used as an average voltage output end (V) of the sub-sampling fractional phase discriminatorHold) First clock output terminal (phi) of the sample-and-hold signal generatorSamp) With the first Switch (SW) of each sub-sampling phase-discrimination unit1) And a second Switch (SW) in each sub-sampling phase discrimination unit2) Is connected to the second clock output terminal (phi) of the sample-and-hold signal generatorHold) Connected to the scalar input of the mean logic, the Hold signal output (Hold) of the mean logici) And a third Switch (SW) in the ith sub-sampling phase discrimination unit3) And the first Inverter (INV) in the ith sub-sampling phase discrimination unit1) Is connected with the input end of the first phase Inverter (INV) in the ith sub-sampling phase detection unit1) And the output terminal of the (i) th sub-sampling phase discrimination unit with the fourth Switch (SW)4) Are connected with the control end of the mean value control end
Figure FDA0003287692290000031
And-means logicThe vector inputs of the inputs being connected, and a third clock output (phi) of the sample-and-hold signal generatorCLR) And a fifth Switch (SW)5) Is connected to a fifth Switch (SW)5) And the other end of (V) and a common mode voltage input terminal (V)CM) Are connected.
3. The real-time fractional-N sub-sampling phase-locked loop of claim 1, wherein the ramp signal generator comprises a frequency/phase detector, a second Inverter (INV)2) And a third Inverter (INV)3) A first PMOS transistor (MP)1) And a second PMOS transistor (MP)2) A first NMOS transistor (MN)1) And a second NMOS transistor (MN)2) A first resistor (R)1) And a second resistor (R)2)；
First output terminal (phi) of sampling phase generatorLEAD) And a second output terminal (phi)LAG) Respectively connected with the first input end and the second input end of the frequency/phase discriminator, and the first output end of the frequency/phase discriminator and the second Inverter (INV)2) Is connected to the input terminal of the first Inverter (INV)2) And the output end of the first PMOS tube (MP)1) Gate of (1) and first NMOS transistor (MN)1) Is connected with the grid of the first PMOS transistor (MP)1) Is connected with a power supply, a first PMOS tube (MP)1) And a first resistor (R)1) Is connected to a first NMOS transistor (MN)1) Is grounded, a first resistor (R)1) And the other end of the first NMOS transistor (MN)1) Is connected as a first voltage signal output terminal (V)Lead) A second output terminal of the frequency/phase discriminator and a third Inverter (INV)3) Is connected to the input terminal of the third Inverter (INV)3) And the output end of the second PMOS tube (MP)2) Gate of (1) and second NMOS transistor (MN)2) Is connected with the grid of the second PMOS tube (MP)2) Is connected with a power supply, a second PMOS tube (MP)2) And a second resistor (R)2) Is connected to a second NMOS transistor (MN)2) Is grounded, and a second resistor (R)2) And the other end of the first NMOS transistor (MN) and a second NMOS transistor (MN)2) The drain electrode is connected and then is used as a second voltage signal outputTerminal (V)Lag)。
4. The real-time fractional-N sub-sampling phase-locked loop of claim 1, wherein the sample-and-hold signal generator comprises a first Delay unit (Delay)1) And a fourth Inverter (INV)4) A second Delay unit (Delay)2) A first Buffer (BUFF)1) And a third Delay unit (Delay)3) And a fifth Inverter (INV)5)；
Reference clock input (phi)ref) And a first Delay unit (Delay)1) Is connected to the input of a first Delay unit (Delay)1) And the fourth Inverter (INV)4) Is connected to the input terminal of a fourth Inverter (INV)4) And a second Delay unit (Delay)2) And a third Delay unit (Delay)3) Is connected to the input terminal of the first Inverter (INV), and a fourth Inverter (INV)4) As a first clock output (phi)Samp) Second Delay element (Delay)2) And a first Buffer (BUFF)1) Are connected to a first Buffer (BUFF)1) As a second clock output (phi)Hold) Third Delay Unit (Delay)3) And the output end of the fifth Inverter (INV)5) Is connected to the input terminal of a fifth Inverter (INV)5) As a third clock output (phi)CLR)。
5. The real-time fractional-N sub-sampled phase-locked loop of claim 1, wherein the averaging logic comprises Hold signal outputs (Hold)i) And a plurality of average logic units, wherein each average logic unit comprises a sixth Inverter (INV)6) AND a first AND gate (AND)1)；
First vector output terminal of sampling and frequency division control signal generator
Figure FDA0003287692290000041
Comprises a plurality of sub-input ends, wherein one sub-input end corresponds to one sub-input endA mean logic unit and a sub-sampling phase discrimination unit, wherein each sub-input end corresponds to the sixth Inverter (INV) in the mean logic unit6) Is connected to the input terminal of the first logic unit, in each mean value logic unit, a sixth Inverter (INV)6) With a first AND-gate (AND)1) Is connected to the first input terminal of the sample-and-hold signal generator, and a second clock output terminal (phi) of the sample-and-hold signal generatorHold) AND gate (AND) with the first of all mean logic cells1) Is connected to the first AND gate (AND) in the ith mean logic cell1) As the corresponding ith Hold signal output terminal (Hold)i) Corresponding to the third Switch (SW) in the ith sub-sampling phase discrimination unit3) Control terminal and first Inverter (INV)1) Are connected.
6. The real-time fractional-N sub-sampled PLL of claim 1 wherein said sample phase generator comprises a quadrature/2 divider, a Multiplexer (MUX)1) First phase interpolation unit (Cell)1) A third capacitor (C)3) And a second phase interpolation unit (Cell)2) A fourth capacitor (C)4) A third phase interpolation unit (Cell)3) A fifth capacitor (C)5) A fourth phase interpolation unit (Cell)4) A sixth capacitor (C)6) The fifth phase interpolation unit (Cell)5) A seventh capacitor (C)7) Sixth phase interpolation unit (Cell)6) An eighth capacitor (C)8) Seventh phase interpolation unit (Cell)7) A ninth capacitor (C)9) The eighth phase interpolation unit (Cell)8) A tenth capacitor (C)10) The ninth phase interpolation unit (Cell)9) An eleventh capacitor (C)11) And a sixth Switch (SW)6) And a seventh Switch (SW)7) And an eighth Switch (SW)8) And a ninth Switch (SW)9) And a tenth Switch (SW)10) And an eleventh Switch (SW)11)；
Differential input of quadrature/2 frequency divider and differential signal output of voltage controlled oscillator (phi)VCOP) And (phi)VCON) Phase-connected, quadrature/2 frequency dividerFirst output terminal (phi)I) A second output terminal (phi)Q) And a third output terminal (phi)IB) And a fourth output terminal (phi)QB) Respectively associated with a Multiplexer (MUX)1) Is connected to the first, second, third and fourth input terminals, a Multiplexer (MUX)1) The first control end and the second control end of the frequency divider are respectively connected with the second vector output end of the sampling and frequency dividing control signal generator
Figure FDA0003287692290000051
Fourth sub-input terminal (N)PS,3) And a fifth sub-input terminal (N)PS,4) Connecting;
multiplexer (MUX)1) And a first phase interpolation unit (Cell)1) First input terminal of (1), first phase interpolation unit (Cell)1) Second input terminal of (1) and second phase interpolation unit (Cell)2) Is connected to a first input terminal of a Multiplexer (MUX)1) And a second phase interpolation unit (Cell)2) Second input terminal, third phase interpolation unit (Cell)3) And a third phase interpolation unit (Cell)3) Is connected to the first phase interpolation unit (Cell)1) And the third capacitor (C)3) And a sixth Switch (SW)6) Is connected to a third capacitor (C)3) Is grounded, and a second phase interpolation unit (Cell)2) And the fourth capacitor (C)4) One end of (1), a sixth Switch (SW)6) And a seventh Switch (SW)7) Is connected to a fourth capacitor (C)4) The other end of the first phase interpolation unit (Cell) is grounded, and a third phase interpolation unit (Cell)3) And the output terminal of the fifth capacitor (C)5) And a seventh Switch (SW)7) Is connected to the fifth capacitor (C)5) The other end of the sampling and frequency division control signal generator is grounded, and a second vector output end of the sampling and frequency division control signal generator
Figure FDA0003287692290000061
Third sub-input of (2)Terminal (N)PS,2) And a sixth Switch (SW)6) Control terminal and seventh Switch (SW)7) The control ends are connected;
sixth Switch (SW)6) Fixed end of and fourth phase interpolation unit (Cell)4) First input terminal of (1), fourth phase interpolation unit (Cell)4) Second input terminal and fifth phase interpolation unit (Cell)5) Is connected to the first input terminal, a seventh Switch (SW)7) Fixed end of and fifth phase interpolation unit (Cell)5) Second input terminal of (1), sixth phase interpolation unit (Cell)6) First input terminal and sixth phase interpolation unit (Cell)6) Is connected to the second input terminal of the fourth phase interpolation unit (Cell)4) And the sixth capacitor (C)6) And an eighth Switch (SW)8) Is connected to a sixth capacitor (C)6) The other end of the first phase interpolation unit (Cell) is grounded, and a fifth phase interpolation unit (Cell)5) And the seventh capacitor (C)7) One end of, an eighth Switch (SW)8) And a ninth Switch (SW)9) Is connected to a seventh capacitor (C)7) Is grounded, a sixth phase interpolation unit (Cell)6) And an eighth capacitor (C)8) And a ninth Switch (SW)9) Is connected to the eighth capacitor (C)8) The other end of the sampling and frequency division control signal generator is grounded, and a second vector output end of the sampling and frequency division control signal generator
Figure FDA0003287692290000062
Second sub-input terminal (N)PS,1) And an eighth Switch (SW)8) Control terminal and ninth Switch (SW)9) The control ends are connected;
eighth Switch (SW)8) Fixed end and seventh phase interpolation unit (Cell)7) First input terminal of (1), seventh phase interpolation unit (Cell)7) Second input terminal and eighth phase interpolation unit (Cell)8) Is connected to the first input terminal, a ninth Switch (SW)9) Fixed end and eighth phase interpolation unit (Cell)8) Second input terminal, ninth phase interpolation unit (Cell)9) First input terminal and ninth phase interpolation unit (Cell)9) Is connected to the seventh phase interpolation unit (Cell)7) And the ninth capacitor (C)9) And a tenth Switch (SW)10) Is connected to the ninth capacitor (C)9) The other end of the first phase interpolation unit (Cell) is grounded, and the eighth phase interpolation unit (Cell)8) And the tenth capacitor (C)10) One end of (1), tenth Switch (SW)10) And an eleventh Switch (SW)11) Is connected to the tenth capacitor (C)10) The other end of the first phase interpolation unit (Cell) is grounded, and a ninth phase interpolation unit (Cell)9) And the eleventh capacitor (C)11) And an eleventh Switch (SW)11) Is connected to the eleventh capacitor (C)11) The other end of the sampling and frequency division control signal generator is grounded, and a second vector output end of the sampling and frequency division control signal generator
Figure FDA0003287692290000071
First input terminal (N)PS,0) And a tenth Switch (SW)10) Control terminal and eleventh Switch (SW)11) Is connected to a tenth Switch (SW)10) Fixed end and eleventh Switch (SW)11) Respectively as a first output terminal (phi) of the sampling phase generatorLEAD) And a second output terminal (phi)LAG)。
7. A real-time fractional-N sub-sampling phase-locked loop according to claim 1, characterized in that each phase interpolation unit comprises a first Current Source (CS)1) A second Current Source (CS)2) And the third PMOS tube (MP)3) And the fourth PMOS tube (MP)4) And the third NMOS transistor (MN)3) And the fourth NMOS transistor (MN)4) AND a second AND gate (AND)2)；
First input terminal (phi) of phase interpolation unitin1) And a third PMOS tube (MP)3) AND a second AND gate (AND)2) Is connected to the first input terminal of the third PMOS transistor (MP)3) And a first Current Source (CS)1) Is connected to a first current source(CS1) Is connected to a power supply, a second input terminal (phi) of the phase interpolation unitin2) And a fourth PMOS tube (MP)4) AND a second AND gate (AND)2) Is connected to the fourth PMOS transistor (MP)4) And a second Current Source (CS)2) Is connected to a second Current Source (CS)2) Is connected to a power supply, a second AND gate (AND)2) And the output end of the third NMOS transistor (MN)3) Gate of (1) and fourth NMOS transistor (MN)4) Is connected to the gate of the third NMOS transistor (MN)3) Is grounded, and a fourth NMOS transistor (MN)4) Is grounded, and a third PMOS tube (MP)3) Drain electrode of (1), fourth PMOS tube (MP)4) Drain electrode of (1), third NMOS transistor (MN)3) Drain electrode of (1) and fourth NMOS transistor (MN)4) Is connected as the output terminal (phi) of the phase interpolation unitout)。
8. Real-time fractional-N sub-sampling phase-locked loop according to claim 1, characterized in that the sampling and frequency-division control signal generator comprises a fractional- Δ Σ modulator, a first Adder (ADD)1) A second Adder (ADD)2) Accumulator (ACC)1) And a data weight average module;
the number of bits of the frequency division control word input end N + alpha is 25 bits, the frequency division control word input end N + alpha is connected with the input end of the decimal delta-sigma modulator, and the first output end d with 5 bits wide of the decimal delta-sigma modulatorinteAnd Adder (ADD)1) Are connected to the input terminals of a 5-bit wide second output terminal (d) of the small-number delta-sigma modulatorfrac,MSB) And Accumulator (ACC)1) Are connected, a 6-bit wide third output (d) of the small-number delta sigma modulatorfrac,LSB) A first Adder (ADD) connected to the input of the data weight average module1) As the scalar output (N) of the sampling and frequency division control signal generatordiv) Accumulator (ACC)1) And a second Adder (ADD)2) Is connected with the 6-bit wide input end of the data weight average value module, and the 1-bit output end (N) of the data weight average value moduleref) And a second Adder (ADD)2) Is connected to the 1-bit wide input terminalThen, a second Adder (ADD)2) And a first Adder (ADD) with the highest 1 bit of the 6-bit wide output of the first adder1) Is connected to the 1-bit wide input terminal of the second Adder (ADD)2) The lower 5 bits of the 6-bit wide output end are used as the second vector output end of the sampling and frequency division control signal generator
Figure FDA0003287692290000081
The 64-unit vector output end of the data weight mean value module is used as the first vector output end of the sampling and frequency division control signal generator
Figure FDA0003287692290000091
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107623521A (en) * 2017-09-29 2018-01-23 中国科学院半导体研究所 A kind of pll clock generator
CN110808735A (en) * 2019-11-18 2020-02-18 华南理工大学 Digital-analog hybrid phase-locked loop capable of achieving rapid frequency locking
WO2021068326A1 (en) * 2019-10-07 2021-04-15 珠海市一微半导体有限公司 Control signal pulse width extraction-based phase-locked acceleration circuit and phase-locked loop system
CN113037282A (en) * 2021-02-25 2021-06-25 西安交通大学 Fractional frequency division reference sampling frequency synthesizer based on voltage mean value

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107623521A (en) * 2017-09-29 2018-01-23 中国科学院半导体研究所 A kind of pll clock generator
WO2021068326A1 (en) * 2019-10-07 2021-04-15 珠海市一微半导体有限公司 Control signal pulse width extraction-based phase-locked acceleration circuit and phase-locked loop system
CN110808735A (en) * 2019-11-18 2020-02-18 华南理工大学 Digital-analog hybrid phase-locked loop capable of achieving rapid frequency locking
CN113037282A (en) * 2021-02-25 2021-06-25 西安交通大学 Fractional frequency division reference sampling frequency synthesizer based on voltage mean value

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