CN116827336A - Decimal frequency division sampling phase-locked loop based on voltage space average value - Google Patents

Decimal frequency division sampling phase-locked loop based on voltage space average value Download PDF

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CN116827336A
CN116827336A CN202310788093.8A CN202310788093A CN116827336A CN 116827336 A CN116827336 A CN 116827336A CN 202310788093 A CN202310788093 A CN 202310788093A CN 116827336 A CN116827336 A CN 116827336A
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input
output
sampling
gate
clock
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张岩龙
郑郝乐
贾国樑
耿莉
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Xian Jiaotong University
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Xian Jiaotong University
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a fractional frequency division sampling phase-locked loop system architecture based on a voltage space average value, which comprises a reference clock input end, a first reference voltage input end, a second reference voltage input end, a common-mode voltage input end, a frequency control word input end, a microwave signal output end, a radio frequency signal output end, a voltage average value sampling fractional frequency discriminator, a transconductance amplifier, a low-pass loop filter, a voltage-controlled oscillator, a differential-single-ended converter, a 2 frequency divider, a single-ended buffer, a frequency control word input end, a sampling phase generator and a frequency division and sampling control signal generator.

Description

Decimal frequency division sampling phase-locked loop based on voltage space average value
Technical Field
The invention belongs to the technical field of electronics, and relates to a decimal frequency division sampling phase-locked loop based on a voltage space average value.
Background
The phase-locked loop is one of important functional modules in a radio frequency/microwave communication system and a computer system, and is widely applied to the generation of carrier signals, clock signals, frequency modulation signals and phase modulation signals due to the advantages of good frequency tracking characteristic, low phase noise, small spurious component, high system stability and the like.
Compared with the traditional phase-locked loop based on the phase frequency detector-charge pump structure, the sampling phase detector with variable gain in the sampling phase-locked loop can realize higher phase detector gain, is beneficial to better inhibiting phase noise in the bandwidth of the phase-locked loop, and is an excellent solution of the current low-power consumption low-jitter frequency source. The reference sampling phase-discrimination phase-locked loop has small self gain and poor linearity, and the advantages of the sampling phase-discrimination device in suppressing phase noise in the phase-locked loop bandwidth can not be fully exerted. A sub-sampling type phase locked loop is another sampling type phase locked loop, but its extremely narrow phase locking range cannot directly achieve fractional division. In order to solve the problem, the most commonly used method in the work reported at home and abroad at present is to modulate the phase of a reference signal or a frequency division signal by using a digital-to-time converter and change the phase information of a sampled or sampled signal to realize fractional frequency division. However, the noise of the digital-to-time converter modulates the phase of the reference signal, introducing additional phase noise, and this phase noise is not effectively suppressed by the high gain of the sampling phase detector, thereby deteriorating the phase noise characteristics of the sampling phase locked loop. Furthermore, the accuracy and dynamic range of the digital-to-time converter are susceptible to integrated circuit processes, chip supply voltages, ambient temperature, and output signal cycles, requiring real-time calibration to ensure accurate fractional frequency division. Furthermore, the nonlinear nature of the digital-to-time converter can cause noise folding, further degrading the phase noise characteristics of the sampling phase locked loop. The disclosed sampling fractional-n pll has many drawbacks that limit its wide application in today's rf/microwave communication systems and computer systems.
Although the sampling phase-locked loop effectively suppresses phase noise within the system loop bandwidth, for a fractional-n sampling phase-locked loop, phase noise outside the loop bandwidth is still dominated by fractional-n quantization noise. In addition to fractional frequency quantization noise suppression techniques based on digital-to-time converters, researchers at home and abroad have proposed many fractional frequency quantization noise suppression methods in recent twenty years, such as feedforward compensation techniques based on digital-to-analog converters, phase interpolation techniques, filtering preprocessing methods based on finite impulse response filters, space-time average fractional frequency division techniques, and the like. However, these techniques are not fully compatible with sampling phase locked loops and have limitations on the suppression effect of fractional quantization noise.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a fractional frequency division sampling phase-locked loop system architecture based on a voltage space average value, which has the characteristic of low phase noise in the bandwidth of a sampling phase-locked loop and can effectively inhibit the phase noise generated by fractional frequency division.
In order to achieve the above objective, the fractional frequency division sampling phase-locked loop based on voltage space average value of the present invention includes a reference clock input end, a first reference voltage input end, a second reference voltage input end, a common mode voltage input end, a frequency control word input end, a microwave signal output end, a radio frequency signal output end, a voltage average value sampling fractional frequency discriminator, a transconductance amplifier, a low pass loop filter, a voltage controlled oscillator, a differential-single ended converter, a 2/frequency divider, a single ended buffer, a frequency control word input end, a sampling phase generator, a frequency division and sampling control signal generator;
The first clock input end, the second clock input end and the third clock input end of the voltage average sampling fractional frequency phase discriminator are respectively connected with the reference clock input end, the first output end of the sampling phase discriminator generator and the second output end of the sampling phase discriminator generator, the first voltage input end and the second voltage input end of the voltage average sampling fractional frequency phase discriminator are respectively connected with the first reference voltage input end and the second reference voltage input end, the voltage output end of the voltage average sampling fractional frequency phase discriminator is connected with the negative phase voltage input end of the transconductance amplifier, the control pulse output end of the voltage average sampling fractional frequency phase discriminator is connected with the control end of the transconductance amplifier, the positive phase voltage input end of the transconductance amplifier is connected with the common mode voltage input end, the output end of the transconductance amplifier is connected with the input end of the low-pass loop filter, the output end of the low-pass loop filter is connected with the input end of the voltage-controlled oscillator, the differential output end of the voltage-controlled oscillator is connected with the differential input end of the differential-single-ended converter, the differential input end of the 2 frequency divider and the differential input end of the sampling phase generator, the output end of the differential-single-ended converter is connected with the microwave signal output end, the output end of the 2 frequency divider is connected with the radio frequency signal output end through the single-ended buffer, the first vector output end of the frequency dividing and sampling control signal generator and the 5-bit wide digital signal output end of the frequency dividing and sampling control signal generator are respectively connected with the vector input end and the 5-bit wide digital signal input end of the sampling phase generator, the input end of the frequency dividing and sampling control signal generator is connected with the frequency control word input end, the second vector output end of the frequency division and sampling control signal generator is connected with the vector input end of the voltage average sampling decimal frequency phase discriminator. The voltage average sampling decimal frequency phase discriminator comprises a control pulse output end, a sampling and average control clock generator, a double-phase frequency phase discriminator control module and a plurality of sampling and average units;
Each sampling and average unit comprises a first switch, a second switch, a third switch, a fourth switch, a sampling capacitor, a current source and a data selector;
the input end of the sampling and average control clock generator is used as the first clock input end of the voltage average value sampling decimal frequency discrimination phase discriminator, the first clock output end of the sampling and average control clock generator is connected with the control end of the fourth switch in each sampling and average value unit, the second clock output end of the sampling and average value control clock generator is connected with the control end of the second switch in each sampling average value unit, the third clock output end of the sampling and average value control clock generator is connected with the control end of the third switch in each sampling and average value unit, the fourth clock output end of the sampling and average value control clock generator is connected with the first clock input end of the double-phase frequency discrimination phase discriminator control module, and the fifth clock output end of the sampling and average value control clock generator is connected with the control pulse output end;
the second clock input end and the third clock input end of the double-phase frequency discrimination control module are respectively used as the second clock input end and the third clock input end of the voltage average sampling decimal frequency discrimination phase discriminator, the first output end and the second output end of the double-phase frequency discrimination control module are respectively connected with the 0 option input end and the 1 option input end of the data selector in each sampling and average value unit, the vector control end comprises a plurality of sub-input ends, one sub-input end corresponds to one sampling and average value unit, and each sub-input end is respectively connected with the control end of the data selector in the corresponding sampling and average value unit;
In each sampling and average value unit, the output end of the data selector is connected with the control end of a first switch, one end of the first switch is grounded, the other end of the first switch is connected with the output end of a current source and one end of a second switch, the input end of the current source is connected with a power supply, the other end of the second switch is connected with one end of a sampling capacitor and one end of a third switch, the other end of the sampling capacitor is connected with one end of a fourth switch and the negative-phase voltage input end of a transconductance amplifier, the other end of the fourth switch is connected with a first reference voltage input end, and the other end of the third switch is connected with a second reference voltage input end.
The sampling and average control clock generator comprises a transmission gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a third buffer, a fourth buffer, a fifth buffer, a sixth buffer, a seventh buffer, an eighth buffer, a ninth buffer, a first D trigger, a second D trigger, a first delay module and a second delay module;
the input end of the reference clock is connected with the input end of the transmission gate and the input end of the first inverter, the output end of the transmission gate is connected with the input end of the third buffer, the output end of the third buffer is connected with the input end of the second inverter, the output end of the third inverter, the input end of the fifth inverter and the input end of the sixth buffer, the output end of the first inverter is connected with the input end of the fourth buffer, the output end of the fourth buffer is connected with the output end of the second inverter, the input end of the third inverter, the input end of the fourth inverter and the input end of the fifth buffer, the output end of the fourth inverter is suspended, the output end of the fifth inverter is used as the first clock output end of the sampling and average value control clock generator, the output end of the fifth buffer is connected with the input end of the seventh buffer, the output end of the fifth buffer is used as the second clock output end of the sampling and average value control clock generator, the output end of the seventh buffer is connected with the input end of the ninth buffer, the output end of the seventh buffer is used as the third clock output end of the sampling and average value control clock generator, the output end of the ninth buffer is used as the fourth clock output end of the sampling and average value control clock generator, the output end of the sixth buffer is connected with the input end of the eighth buffer, the output end of the eighth buffer is connected with the clock input end of the first D trigger, the data input end of the first D trigger is connected with the high level signal end, the output end of the first D trigger is connected with the input end of the first delay module and the control pulse output end, the output end of the first delay module is connected with the clock input end of the second D trigger, the data input end of the second D trigger is connected with the high level signal end, the output end of the second D trigger is connected with the input end of the second delay module, and the output end of the second delay module is connected with the reset end of the first D trigger and the reset end of the second D trigger.
The double-phase frequency and phase discrimination control module comprises a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a fifth NOR gate, a sixth NOR gate, a seventh NOR gate, an eighth NOR gate, a tenth buffer, an eleventh buffer, a twelfth buffer, a thirteenth buffer, a third delay module and a three-input AND gate;
the first input end of the first NOR gate is used as the second clock input end of the voltage average sampling fractional frequency discriminator, the output end of the first NOR gate is connected with the first input end of the second NOR gate and the first input end of the third NOR gate, the output end of the second NOR gate is connected with the second input end of the first NOR gate and the input end of the tenth buffer, the output end of the third NOR gate is connected with the second input end of the second NOR gate and the first input end of the fourth NOR gate, the output end of the fourth NOR gate is connected with the second input end of the third NOR gate, the output end of the third delay module is connected with the second input end of the fourth NOR gate and the first input end of the fifth NOR gate, the output end of the fifth NOR gate is connected with the first input end of the sixth NOR gate, the output end of the sixth NOR gate is connected with the second input end of the fifth NOR gate and the first input end of the seventh NOR gate, the output end of the seventh NOR gate is connected with the first input end of the eighth NOR gate and the input end of the twelfth buffer, the output end of the eighth NOR gate is connected with the second input end of the sixth NOR gate and the second input end of the seventh NOR gate, the second input end of the eighth NOR gate is used as the third clock input end of the voltage average value sampling decimal frequency phase discriminator, the output end of the tenth buffer is connected with the input end of the eleventh buffer and the first input end of the three-input AND gate, the output end of the eleventh buffer is used as the first output end of the double-phase frequency phase discriminator control module, the second input end of the three-input AND gate is used as the second clock input end of the voltage average value sampling decimal frequency phase discriminator, the output end of the twelfth buffer is connected with the third input end of the three-input AND gate and the input end of the thirteenth buffer, the output end of the thirteenth buffer is used as the second output end of the double-phase frequency discrimination phase discrimination control module, and the output end of the three-input AND gate is connected with the input end of the third delay module.
The sampling phase generator comprises a 5-bit wide digital signal input end, a vector control input end, a quadrature/2 frequency divider, a multi-mode frequency divider, a third D trigger, a fourth D trigger, a fifth D trigger, a sixth D trigger, a seventh D trigger and a multiplexer;
the differential output end of the voltage controlled oscillator is connected with the differential input end of the quadrature/2 frequency divider, the first clock output end of the quadrature/2 frequency divider is connected with the clock input end of the third D trigger and the clock input end of the seventh D trigger, the second clock output end of the quadrature/2 frequency divider is connected with the clock input end of the fourth D trigger, the third clock output end of the quadrature/2 frequency divider is connected with the clock input end of the fifth D trigger, the fourth clock output end of the quadrature/2 frequency divider is connected with the clock input end of the sixth touch D trigger and the clock input end of the multi-mode frequency divider, the clock output end of the multi-mode frequency divider is connected with the data input end of the third D trigger and the first input end of the multi-channel selector, the output end of the fourth D trigger is connected with the data input end of the fifth D trigger and the second input end of the multi-channel selector, the output end of the fifth D trigger is connected with the data input end of the fifth D trigger and the multi-channel selector, the output end of the multi-channel selector is connected with the data input end of the fifth D trigger, the output end of the multi-channel selector is connected with the sampling end of the multi-channel selector, the output end of the multi-channel selector is connected with the output end of the fifth D trigger.
The frequency division and sampling control signal generator comprises a decimal digital delta sigma modulator, an accumulator, a first adder, a second adder and an edge selection logic module;
the input end of the frequency control word is 25-bit wide digital input end, the input end of the fractional digital delta sigma modulator is connected with the input end of the frequency control word, the output end of the fractional digital delta sigma modulator, which is 12 bits wide, is connected with the 5 bits wide input end of the first adder, the highest 2 bits of the fractional digital delta sigma modulator, which is 7 bits wide, are connected with the input end of the accumulator, the lowest 5 bits of the fractional digital delta sigma modulator, which is 7 bits wide, are connected with the input end of the edge selection logic module, the 3 bits wide output end of the accumulator is connected with the 3 bits wide input end of the second adder, the 1 bits wide output end of the edge selection logic module is connected with the 1 bits wide input end of the second adder, the highest 2 bits of the second adder are connected with the 1 bits wide input end of the first adder, the lowest 5 bits of the second adder is the 3 bits wide output end of the second adder is connected with the 2 bits wide input end of the second adder, the second adder is the output end of the sampling vector signal generating vector generating signal generating vector, and the output end of the second adder is the second signal generating vector generating output by the sampling vector generating signal generating the second signal.
The edge selection logic module comprises a data weight average logic module, a plurality of exclusive-OR gates and a plurality of accumulators, wherein one exclusive-OR gate corresponds to one accumulator;
the low 5 bit width in the 7 bit width small number control word of the fractional delta sigma modulator is used as the least significant bit of the small number control word to be connected with the input end of the data weight average value logic module, the vector output end of the data weight average value logic module comprises a plurality of sub-output ends, each sub-output end corresponds to a group of exclusive-OR gates and accumulators, each sub-output end is connected with the first input end of the corresponding exclusive-OR gate, the scalar output end of the data weight average value logic module is connected with the second input end of all the exclusive-OR gates, the output end of each exclusive-OR gate is connected with the input end of the accumulator, and the output end of the accumulator is used as the vector output end of the edge selection logic module.
The invention has the following beneficial effects:
the fractional frequency division sampling phase-locked loop system architecture based on the voltage space average value adopts a sampling fractional phase discriminator structure based on the voltage average value when in specific operation, realizes fractional frequency division without the assistance of a digital-time converter, overcomes the problem that the digital-time converter worsens the phase noise characteristic of a reference clock, is easy to be influenced by the integrated circuit process, the chip power supply voltage and the environment temperature, obviously reduces the phase noise source of the fractional frequency division sampling phase-locked loop, and is beneficial to realizing the fractional frequency division sampling phase-locked loop with lower phase noise. In addition, the invention utilizes the sampling fractional phase discriminator to carry out voltage average, the process does not influence the periodical change of the output signal of the pressure controlled oscillator, the problem that the gain of the digital-time converter needs to be calibrated in real time in the traditional fractional frequency sampling phase-locked loop based on the digital-time converter is solved, the fractional frequency division function can be realized in the sampling phase-locked loop without calibration, the complexity and the power consumption of the system are reduced, and the realization of the low-power consumption fractional frequency division sampling phase-locked loop is facilitated.
Furthermore, the control circuit of the space-time average technology in the invention is mainly realized by a digital circuit, so that the invention has good immunity to errors caused by process, voltage and temperature fluctuation, has good process reconfigurability, is convenient for automatic design, and can further reduce power consumption and hardware cost along with continuous progress of the integrated circuit manufacturing process. In addition, the data weight average module for controlling the space average process can perform first-order high-pass shaping on the mismatch of the sampling capacitors in the sampling decimal phase discriminator unit array, and output strays caused by the mismatch of the sampling capacitors in the sampling decimal phase discriminator are reduced.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of a voltage average sampling fractional phase frequency detector according to the present invention;
FIG. 3 is a schematic diagram of a sample and average control clock generator according to the present invention;
FIG. 4 is a schematic diagram of a dual phase frequency and phase discrimination control module according to the present invention;
FIG. 5 is a schematic diagram of a sampling phase generator according to the present invention;
FIG. 6 is a schematic diagram of a frequency division and sampling control signal generator according to the present invention;
FIG. 7 is a schematic diagram of edge selection logic in accordance with the present invention;
FIG. 8 is a schematic diagram of a multi-modulus divider according to the present invention;
Fig. 9 is a schematic circuit diagram and a time domain waveform diagram of the quadrature/2 divider of the present invention.
Detailed Description
In order to make the present invention better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments, but not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
In the accompanying drawings, there is shown a schematic structural diagram in accordance with a disclosed embodiment of the invention. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and their relative sizes, positional relationships shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
Referring to FIG. 1, the fractional-N sampling phase-locked loop based on voltage space average according to the present invention includes a reference clock input terminal phi ref A first reference voltage input terminal V Ref1 A second reference voltage input terminal V Ref2 A common mode voltage input end, a frequency control word input end, a microwave signal output end phi PLL,mmW Radio frequency signal output terminal phi PLL,RF Voltage-mean sampling fractional phase frequency detector, transconductance amplifier, low-pass loop filter, voltage-controlled oscillator, differential-to-single-ended converter BUF 1 Frequency divider/2, single ended buffer BUF 2 The frequency control word input end N+alpha, the sampling phase generator and the frequency division and sampling control signal generator;
the first clock input end, the second clock input end and the third clock input end of the voltage average sampling decimal phase frequency detector are respectively connected with the reference clock input end phi ref First output terminal phi of sampling phase detector generator Lead Second output terminal phi of sampling phase detector generator Lag A first voltage input end of the voltage average sampling decimal phase frequency detectorThe second voltage input end is respectively connected with the first reference voltage input end V Ref1 A second reference voltage input terminal V Ref2 The voltage output end V of the voltage average sampling decimal phase frequency detector is connected SAMP The control pulse output end PULSER of the voltage average sampling decimal phase frequency discriminator is connected with the control end of the transconductance amplifier, and the positive phase voltage input end of the transconductance amplifier is connected with the common mode voltage input end V CM Output terminal I of transconductance amplifier CP Connected to the input of the low-pass loop filter, the output of the low-pass loop filter is V C_VCO Is connected with the input end of the voltage-controlled oscillator, and the differential output end phi of the voltage-controlled oscillator VCO+ Phi VCO- And a differential-to-single ended converter BUF 1 Is connected to the differential input of the 2/2 frequency divider and the differential input of the sampling phase generator, and is a differential-to-single ended converter BUF 1 Output end phi of the microwave signal output end phi PLL,mmW Is connected with the output end of the 2/2 frequency divider through a single-ended buffer BUF 2 And the radio frequency signal output end phi PLL,RF A first vector output end connected with the frequency division and sampling control signal generatorAnd a 5-bit wide digital signal output end N of the frequency division and sampling control signal generator div The input end of the frequency division and sampling control signal generator is connected with the input end N+alpha of the frequency control word, and the second vector output end of the frequency division and sampling control signal generator is connected with the vector input end and the 5-bit wide digital signal input end of the sampling phase generator respectively >And the vector input end of the voltage average sampling decimal phase frequency detector is connected.
Referring to fig. 2, the voltage average sampling decimal frequency phase discriminator comprises a control pulse output end PULSER, a sampling and average control clock generator, a double-phase frequency phase discriminator control module and a plurality of sampling and average units; wherein each sample isThe mean value units each comprise a first switch SW 1 A second switch SW 2 Third switch SW 3 Fourth switch SW 4 Sampling capacitor C 1 Current source I 1 Data selector MUX 1 ；
The input end of the sampling and average control clock generator is used as the first clock input end of the voltage average sampling decimal phase frequency detector, and the first clock output end phi of the sampling and average control clock generator 1 And a fourth switch SW in each sampling and averaging unit 4 Is connected to the control terminal of the sampling and average control clock generator, the second clock output terminal phi 2 And a second switch SW in each sampling mean unit 2 Is connected to the control terminal of the sampling and average control clock generator, the third clock output terminal phi 3 And a third switch SW in each sampling and averaging unit 3 Is connected to the control terminal of the sampling and average control clock generator, the fourth clock output terminal phi RST,PFD The sampling and average control clock generator is connected with the control pulse output end PULSER.
The second clock input end and the third clock input end of the double-phase frequency and phase discrimination control module are respectively used as the second clock input end and the third clock input end of the voltage average sampling decimal frequency and phase discrimination device, and the first output end phi of the double-phase frequency and phase discrimination control module Lead,PUL A second output terminal phi Lag,PUL Respectively with data selector MUX in each sampling and averaging unit 1 The 0 option input end and the 1 option input end are connected, and the vector control endComprises a plurality of sub-input ends, wherein one sub-input end corresponds to one sampling and average unit, and each sub-input end is respectively connected with a data selector MUX in the corresponding sampling and average unit 1 Is connected with the control end of the control circuit.
In each sampling and averaging unit, a data selector MUX 1 And a first switch SW 1 Is connected with the control end of the firstA switch SW 1 Is grounded at one end of a first switch SW 1 And the other end of the current source I 1 Output terminal of (a) and second switch SW 2 Is connected to one end of a current source I 1 Is connected with a power supply, a second switch SW 2 And the other end of the capacitor C 1 One end of (a) and a third switch SW 3 One end of the sampling capacitor C is connected with 1 And the other end of the fourth switch SW 4 One end of the phase detector is connected and then used as a voltage output end V of the voltage average sampling decimal phase frequency detector SAMP Fourth switch SW 4 The other end of (2) is connected with the first reference voltage input end V Ref1 Is connected with a third switch SW 3 The other end of (2) is connected with the second reference voltage input end V Ref2 Is connected with each other.
When the voltage average sampling decimal phase frequency detector works, the sampling and average control clock generator controls the clock generator according to the input end phi of the reference clock ref The input reference clock signal generates a sampling and average value control signal, a control signal of a transconductance amplifier and a reset signal of a double-phase frequency discrimination phase discrimination control module; the double-phase frequency discrimination phase discrimination control module generates two paths of output pulse signals according to the phase information of two phase discrimination feedback signals output by the sampling phase discriminator generator, and each sampling and average unit controls the vector according to the phase discriminationCorresponding control bits in (a) through a multiplexer MUX 1 Selecting proper pulse signal from the two paths of output pulse signals to control a current source I 1 And a first switch SW 1 To sampling capacitor C 1 Charging and discharging are carried out, and a phase signal is converted into a slope signal; sampling clock control second switch SW 2 And a third switch SW 3 Sampling the ramp signal, and storing the sampled voltage in the form of charge in a sampling capacitor C 1 On the other hand, the fourth switch SW is controlled by the average control clock 4 And finishing the average value of the sampling voltages of the sampling and average value units.
Referring to FIG. 3, the sample and average control clock generator includes a transmission gate TG 1 First, theInverter INV 1 Second inverter INV 2 Third inverter INV 3 Fourth inverter INV 4 Fifth inverter INV 5 Third buffer BUF 3 Fourth buffer BUF 4 Fifth buffer BUF 5 Sixth buffer BUF 6 Seventh buffer BUF 7 Eighth buffer BUF 8 Ninth buffer BUF 9 First D flip-flop DFF 1 Second D flip-flop DFF 2 First Delay module Delay 1 A second Delay module Delay 2 ；
Reference clock input terminal phi ref And transmission gate TG 1 Input end of (a) and first inverter INV 1 Is connected with the input end of the transmission gate TG 1 Output terminal of (c) and third buffer BUF 3 Is connected to the input terminal of the third buffer BUF 3 Output end of (a) and second inverter INV 2 Input end of the third inverter INV 3 Output end of (v) fifth inverter INV 5 Is connected to the input terminal of the sixth buffer BUF 6 Is connected with the input end of the first inverter INV 1 Output terminal of (c) and fourth buffer BUF 4 Is connected to the input terminal of the fourth buffer BUF 4 Output end of (a) and second inverter INV 2 Output end of the third inverter INV 3 Input end of (a) and fourth inverter INV 4 Is connected to the input of the fifth buffer BUF 5 Is connected with the input end of the fourth inverter INV 4 The output end of the fifth inverter INV is suspended 5 Is used as the output end phi of the sampling and average control clock generator 1 Fifth buffer BUF 5 Output terminal of (c) and seventh buffer BUF 7 Is connected to the input terminal of the fifth buffer BUF 5 Is used as the second clock output end phi of the sampling and average control clock generator 2 Seventh buffer BUF 7 Output of (c) and ninth buffer BUF 9 Is connected to the input terminal of the fifth buffer BUF 7 Is used as the third clock output end phi of the sampling and average control clock generator 3 Ninth buffer BUF 9 As output of the sampling deviceFourth clock output terminal phi of average control clock generator RST,PFD Sixth buffer BUF 6 Output of (c) and eighth buffer BUF 8 Is connected to the input terminal of the eighth buffer BUF 8 Is connected with the output end of the first D flip-flop DFF 1 Is connected with the clock input end of the first D flip-flop DFF 1 A first D flip-flop DFF connected to the data input terminal of the high level signal terminal 1 And the first Delay module Delay 1 Is connected with the control pulse output end pulse, and a first Delay module Delay 1 And a second D flip-flop DFF 2 Is connected to the clock input terminal of the second D flip-flop DFF 2 A second D flip-flop DFF connected to the data input terminal of the high level signal terminal 2 And a second Delay module Delay 2 Is connected to the input terminal of the second Delay module Delay 2 Is connected with the output end of the first D flip-flop DFF 1 Is set at the reset terminal of the second D flip-flop DFF 2 Is connected with the reset end of the circuit.
Referring to fig. 4, the dual-phase frequency and phase discrimination control module includes a first NOR gate NOR 1 Second NOR gate NOR 2 Third NOR gate NOR 3 NOR gate NOR 4 Fifth NOR gate NOR 5 NOR gate NOR 6 NOR gate NOR 7 Eighth NOR gate NOR 8 Tenth buffer BUF 10 Eleventh buffer BUF 11 Twelfth buffer BUF 12 Thirteenth buffer BUF 13 A third Delay module Delay 3 Three-input AND gate AND 1 ；
First NOR gate NOR 1 A first NOR gate NOR as a second clock input end of the voltage average sampling decimal phase frequency detector 1 And a second NOR gate NOR 2 Is not equal to the first input terminal of the third NOR gate 3 A second NOR gate NOR is connected with the first input end of 2 And the output end of the first NOR gate NOR 1 Is connected to the second input terminal of the tenth buffer BUF 10 Is connected with the input end of the third NOR gate NOR 3 And a second NOR gate NOR 2 A second input terminal of a fourth NOR gate NOR 4 A fourth NOR gate NOR is connected with the first input end of 4 And a third NOR gate NOR 3 A third Delay module Delay connected to the second input terminal of the first circuit 3 And a fourth NOR gate NOR 4 A fifth NOR gate NOR 5 Is connected to the first input terminal of the fifth NOR gate NOR 5 And a sixth NOR gate NOR 6 A sixth NOR gate NOR is connected with the first input end of 6 And a fifth NOR gate NOR 5 A seventh NOR gate NOR 7 A seventh NOR gate NOR is connected with the first input end of 7 And an eighth NOR gate NOR 8 Is connected to the first input terminal of the twelfth buffer BUF 12 Is connected with the input end of the eighth NOR gate NOR 8 And a sixth NOR gate NOR 6 A seventh NOR gate NOR 7 Is connected to the second input terminal of the eighth NOR gate NOR 8 A tenth buffer BUF as a third clock input of the voltage average sampling decimal phase frequency detector 10 Output terminal of (c) and eleventh buffer BUF 11 Input of (2) AND three-input AND gate AND 1 Is connected to the first input terminal of the eleventh buffer BUF 11 Is used as a first output end phi of the double-phase frequency discrimination phase discrimination control module Lead,PUL Three-input AND gate AND 1 A twelfth buffer BUF serving as a second clock input end of the voltage average sampling decimal phase frequency detector 12 AND of the output of (a) AND of the three-input AND gate 1 Third input terminal of (d) and thirteenth buffer BUF 13 Is connected to the input terminal of the thirteenth buffer BUF 13 Is used as the second output end phi of the double-phase frequency discrimination phase discrimination control module Lag,PUL Three-input AND gate AND 1 And a third Delay module Delay 3 Is connected to the input terminal of the circuit.
Referring to FIG. 5, the sampling phase generator includes a 5-bit wide digital signal input, a vector control inputQuadrature/2 divider QDIV 1 Multimode frequency divider, third D flip-flop DFF 3 Fourth D flip-flop DFF 4 Fifth D flip-flop DFF 5 DFF of sixth D flip-flop 6 Seventh D flip-flop DFF 7 Multiplexer MUX 2 ；
Differential output terminal phi of voltage-controlled oscillator VCO+ Phi VCO- Quadrature/2 divider QDIV 1 Is connected to the differential input of the quadrature/2 frequency divider QDIV 1 Is arranged at the first clock output terminal phi I And a third D flip-flop DFF 3 Seventh D flip-flop DFF 7 Is connected to the clock input of the quadrature/2 frequency divider QDIV 1 Second clock output terminal phi of (2) Q And fourth D flip-flop DFF 4 Is connected to the clock input of the quadrature/2 frequency divider QDIV 1 Third clock output terminal phi of (2) IB And a fifth D flip-flop DFF 5 Is connected to the clock input of the quadrature/2 frequency divider QDIV 1 A fourth clock output terminal phi of (2) QB DFF with sixth trigger D 6 Is connected with the clock input end of the multi-mode frequency divider, and the clock output end phi of the multi-mode frequency divider div And a third D flip-flop DFF 3 Is connected to the data input terminal of the third D flip-flop DFF 3 Output of (D) and fourth D flip-flop DFF 4 Data input terminal of (a) and multiplexer MUX 2 Is arranged at the first input end phi of 0° Connected to a fourth D flip-flop DFF 4 Output of (c) and fifth D flip-flop DFF 5 Data input terminal of (a) and multiplexer MUX 2 Is arranged at the second input end phi of 90° Connected with, fifth D flip-flop DFF 5 Output of (2) and sixth D flip-flop DFF 6 Data input terminal of (a) and multiplexer MUX 2 Is arranged at the third input end phi 180° Connected with, a sixth D flip-flop DFF 6 Output of (c) and seventh D flip-flop DFF 7 Data input terminal of (a) and multiplexer MUX 2 A fourth input terminal phi of (2) 270° Connected with, seventh D flip-flop DFF 7 Output of (2) and multiplexer MUX 2 And (2) a fifth input terminal phi 360° Is connected with 5 bitsWide digital signal input terminal N div Connected to the control terminal of the multimode frequency divider, a multiplexer MUX 2 As a first output terminal phi of a sampling phase detector generator Lead Multiplexer MUX 2 As the second output terminal phi of the sampling phase detector generator Lag First vector output end of frequency division and sampling control signal generatorAnd multiplexer MUX 2 Is connected to the control input of the control circuit.
The sampling phase generator being operative, the quadrature/2 divider QDIV 1 Dividing the differential output clock signal of the voltage-controlled oscillator by two to generate a group of quadrature signals; multimode divider pair quadrature/2 divider QDIV 1 And frequency-dividing the fourth output signal of (c) and synchronizing it with the quadrature signal, and then generating an authentication feedback signal based on the vector control signal.
Referring to fig. 6, the frequency division and sampling control signal generator includes a fractional digital delta-sigma modulator, accumulator ACC 1 A first adder ADD 1 A second adder ADD 2 Edge Selection Logic (ESL);
the frequency control word input end N+alpha is a 25-bit wide digital input end, the input end of the fractional-delta sigma modulator is connected with the frequency control word input end N+alpha, and the high 5-bit wide integer control word d in the 12-bit wide output end of the fractional-delta sigma modulator inte Output end and first adder ADD 1 The 5-bit wide input of the delta sigma modulator is connected, and the high 2 bits in the 7-bit wide small number control word of the delta sigma modulator are used as the most significant bit d of the small number control word frac,MSB And accumulator ACC 1 The lower 5 bits of the 7 bits wide small number control word of the fractional delta sigma modulator are used as the least significant bit d of the small number control word frac,LSB An accumulator ACC connected to the input of the edge selection logic module ESL 1 A 3-bit wide output terminal of (2) and a second adder ADD 2 Is connected to the 3-bit wide input terminal of the Edge Selection Logic (ESL), and the 1-bit wide output terminal N of the ESL ref And second addingFrench ADD 2 A second adder ADD connected to the 1-bit wide input terminal 2 The most significant bit of the 3-bit wide output of (2) is used as the first adder ADD 1 A second adder ADD connected to the 1-bit wide input terminal 2 The lower 2 bits of the 3-bit wide output of (2) are used as the first vector output of the frequency division and sampling control signal generatorFirst adder ADD 1 Is used as the 5-bit wide digital signal output end N of the frequency division and sampling control signal generator div The vector output of the edge selection logic module ESL serves as a second vector output of the frequency dividing and sampling control signal generator +.>
Referring to FIG. 7, the edge selection logic includes a data weight average logic, a plurality of exclusive OR gates, and a plurality of accumulators, wherein one exclusive OR gate XOR 1 Corresponding to an accumulator ACC 2 ；
The lower 5 bits of the 7-bit wide small number control word of the fractional delta sigma modulator are used as the least significant bits d of the small number control word frac,LSB The vector output end of the data weight average value logic module is connected with the input end of the data weight average value logic moduleComprises a plurality of sub-output ends, each sub-output end is respectively connected with a group of exclusive OR gates XOR 1 Accumulator ACC 2 Corresponding to each sub-output end and the corresponding exclusive OR gate XOR 1 Is connected with the first input end of the data weight average logic module, and the scalar output end N of the data weight average logic module DWA,REF Connected to the second input of all exclusive OR gates, each exclusive OR gate XOR 1 Output of (c) and accumulator ACC 2 Is connected to the input of accumulator ACC 2 As vector output of the edge selection logic ESL.
Referring to FIG. 8, the multi-modulus divider includes a first divide-by-2/3 divider DIV 1 Second divide-by-2/3 frequency divider DIV 2 Third divide-by-2/3 frequency divider DIV 3 Fourth divide-by-2/3 frequency divider DIV 4 Fifth divide-by-2/3 frequency divider DIV 5 ；
Quadrature/2 divider QDIV 1 A fourth clock output terminal phi of (2) QB With a first divide-by-2/3 frequency divider DIV 1 Is connected with the clock input end of the first divide-by-2/3 frequency divider DIV 1 A 5-bit wide digital signal output N of the sampling control signal generator div First bit N of (2) div [0]Is connected with a first divide-by-2/3 frequency divider DIV 1 A second divide-by-2/3 frequency divider DIV and a second control input of (2) 2 Is connected with the control output end of the first divide-by-2/3 frequency divider DIV 1 And a second divide-by-2/3 frequency divider DIV 2 Is connected with the clock input end of the first divide-by-2/3 frequency divider DIV 1 Is used as the clock output terminal phi of the multi-mode frequency divider div 。
Second divide-by-2/3 frequency divider DIV 2 A 5-bit wide digital signal output N of the sampling control signal generator div Is the second bit N of (2) div [1]Is connected with a second divide-by-2/3 frequency divider DIV 2 A second control input of (2) and a third divide-by-2/3 frequency divider DIV 3 Is connected with the control output end of the second divide-by-2/3 frequency divider DIV 2 And a third divide-by-2/3 frequency divider DIV 3 Is connected to the clock input terminal of the memory.
Third divide-by-2/3 frequency divider DIV 3 A 5-bit wide digital signal output N of the sampling control signal generator div Third bit N of (2) div [2]Is connected with a third divide-by-2/3 frequency divider DIV 3 A second control input of (2/3) divider DIV 4 Is connected to the control output of the third divide-by-2/3 frequency divider DIV 3 Is divided by a fourth divide-by-2/3 frequency divider DIV 4 Is connected to the clock input terminal of the memory.
Fourth divide-by-2/3 frequency divider DIV 4 A 5-bit wide digital signal output N of the sampling control signal generator div Fourth bit N of (2) div [3]Is connected with a fourth divide-by-2/3 frequency dividerDIV 4 A second control input of (2/3) divider DIV 5 Is connected with the control output end of the fourth divide-by-2/3 frequency divider DIV 4 And a fifth divide-by-2/3 frequency divider DIV 5 Is connected to the clock input terminal of the memory.
Fifth divide-by-2/3 frequency divider DIV 5 A 5-bit wide digital signal output N of the sampling control signal generator div N of the fifth bit of (2) div [4]Is connected with a fifth divide-by-2/3 frequency divider DIV 5 A fifth divide-by-2/3 frequency divider DIV connected to the first control input of the logic high level 5 The clock output terminal of (2) floats.
The multi-mode frequency divider outputs N through a 5-bit wide digital signal div 5 subcontrol bits N of (2) div [0]、N div [1]、N div [2]、N div [3]N div [4]The frequency division ratio is controlled to realize the frequency division of the high-frequency signal output by the voltage-controlled oscillator in different states, and the frequency division ratio DivN of the multi-mode frequency divider and the 5-bit wide digital signal output end N div 5 subcontrol bits N of (2) div [0]、N div [1]、N div [2]、N div [3]N div [4]The correspondence of the input control signals is shown in the following formula.
DivN＝N div [0]×2 0 +N div [1]×2 1 +N div [2]×2 2 +N div [3]×2 3 +N div [4]×2 4 +2 5
Referring to fig. 9, the quadrature/2 frequency divider includes a seventh D flip-flop DFF 7 Eighth D flip-flop DFF 8 ；
First differential output terminal phi of voltage-controlled oscillator VCO+ And seventh D flip-flop DFF 7 Is connected to the clock input terminal of the seventh D flip-flop DFF 7 Is used as the positive output of the quadrature/2 frequency divider QDIV 1 Is arranged at the first clock output terminal phi I Seventh D flip-flop DFF 7 Negative output terminal of (a) and seventh D flip-flop DFF 7 And a seventh D flip-flop DFF 7 Is used as the negative output of the quadrature/2 frequency divider QDIV 1 Third clock output terminal phi of (2) IB Second differential output terminal phi VCO- And eighth D flip-flop DFF 8 Is connected to the clock input terminal of the eighth D flip-flop DFF 8 Is used as the positive output of the quadrature/2 frequency divider QDIV 1 Second clock output terminal phi of (2) Q Eighth D flip-flop DFF 8 Negative output terminal of (a) and eighth D flip-flop DFF 8 Is connected to the data input terminal of the eighth D flip-flop DFF 8 Is used as the negative output of the quadrature/2 frequency divider QDIV 1 A fourth clock output terminal phi of (2) QB 。
Referring to the time domain waveform diagram in FIG. 9, the input signal of the quadrature/2 frequency divider is two clock signals with pi phase difference, the output signal is four clock signals with twice the period of the input signal, and the output signal phi I And phi is phi Q 、Φ Q And phi is phi IB 、Φ IB And phi is phi QB 、Φ QB And phi is phi Q The phase difference between the two signals is pi/2, namely four paths of output signals are quadrature clock signals.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the invention without departing from the spirit and scope of the invention, which is intended to be covered by the claims.

Claims (7)

1. A fractional-n sampling phase-locked loop based on voltage spatial averaging, characterized by comprising a reference clock input (Φ ref ) A first reference voltage input terminal (V Ref1 ) A second reference voltage input terminal (V Ref2 ) A common mode voltage input, a frequency control word input, a microwave signal output (phi) PLL,mmW ) Radio frequency signal output terminal (phi) PLL,RF ) Voltage-average sampled fractional phase frequency detector, transconductance amplifier, low-pass loop filter, voltage-controlled oscillator, differential-to-single-ended converter (BUF) 1 ) Frequency divider/2, single ended Buffer (BUF) 2 ) The frequency control word input end (N+alpha), the sampling phase generator and the frequency division and sampling control signal generator;
the first clock input end, the second clock input end and the third clock input end of the voltage average sampling decimal phase frequency detector are respectively connected with the reference clock input end (phi) ref ) A first output (phi) of a sampling phase detector generator Lead ) And a second output (phi) of the sampling phase detector generator Lag ) Is connected with the first voltage input end and the second voltage input end of the voltage average sampling decimal phase frequency detector respectively and is connected with the first reference voltage input end (V Ref1 ) A second reference voltage input terminal (V Ref2 ) Is connected with the voltage output end (V SAMP ) Is connected with the negative phase voltage input end of the transconductance amplifier, the control pulse output end (PULSER) of the voltage average sampling decimal phase frequency discriminator is connected with the control end of the transconductance amplifier, and the positive phase voltage input end of the transconductance amplifier is connected with the common mode voltage input end (V) CM ) The output of the transconductance amplifier (I CP ) Is connected to the input of the low-pass loop filter, the output of which (V C_VCO ) Is connected to the input of the voltage-controlled oscillator, and the differential output (phi) of the voltage-controlled oscillator VCO+ Phi VCO- ) And differential-to-single ended converter (BUF) 1 ) Is connected to the differential input of the/2 frequency divider and the differential input of the sampling phase generator, and a differential-to-single ended converter (BUF) 1 ) Output terminal of (2) and microwave signal output terminal (phi) PLL,mmW ) Is connected with the output end of the 2/2 frequency divider through a single-ended Buffer (BUF) 2 ) And the radio frequency signal output end (phi) PLL,RF ) A first vector output end connected with the frequency division and sampling control signal generatorAnd a 5-bit wide digital signal output (N div ) Is respectively connected with the vector input end of the sampling phase generator and the 5-bit wide digital signal input end, and the input end of the frequency division and sampling control signal generator and the frequency control The word input end (N+alpha) is connected with the second vector output end of the frequency division and sampling control signal generator>And the vector input end of the voltage average sampling decimal phase frequency detector is connected.
2. The fractional-n sampling phase-locked loop based on voltage spatial averaging of claim 1, wherein the voltage averaging sampling fractional-n-phase discriminator comprises a control pulse output (PULSER), a sampling and averaging control clock generator, a bi-phase frequency discrimination control module, and a plurality of sampling and averaging units;
wherein each sampling and averaging unit comprises a first switch (SW 1 ) A second Switch (SW) 2 ) Third Switch (SW) 3 ) Fourth Switch (SW) 4 ) Sampling capacitor (C) 1 ) Current source (I) 1 ) Data selector (MUX) 1 )；
The input of the sampling and averaging control clock generator is used as the first clock input of the voltage-averaged sampling decimal phase frequency detector, and the first clock output (phi) 1 ) And a fourth Switch (SW) in each sampling and averaging unit 4 ) Is connected to the control terminal of the sampling and average control clock generator, and the second clock output terminal (phi) 2 ) And a second switch (SW 2 ) Is connected to the control terminal of the sampling and average control clock generator, and a third clock output terminal (phi) 3 ) And a third Switch (SW) in each sampling and averaging unit 3 ) Is connected to the control terminal of the sampling and average control clock generator, and a fourth clock output terminal (phi) RST,PFD ) The sampling and average control clock generator is connected with a first clock input end of the double-phase frequency discrimination phase discrimination control module, and a fifth clock output end of the sampling and average control clock generator is connected with a control pulse output end (PULSER);
the second clock input end and the third clock input end of the double-phase frequency and phase discrimination control module are respectively used as the second clock input end of the voltage average sampling decimal frequency and phase discriminatorAn input end and a third clock input end, a first output end (phi) of the double-phase frequency discrimination phase discrimination control module Lead,PUL ) A second output terminal (phi) Lag,PUL ) Respectively and with data selector (MUX) in each sampling and averaging unit 1 ) The 0 option input end and the 1 option input end are connected, and the vector control endComprises a plurality of sub-input ends, wherein one sub-input end corresponds to one sampling and average unit, and each sub-input end is respectively connected with a data selector (MUX) in the corresponding sampling and average unit 1 ) Is connected with the control end of the control circuit;
in each sample and average unit, a data selector (MUX 1 ) And the output end of the first switch (SW 1 ) Is connected to the control terminal of the first switch (SW 1 ) Is grounded, a first switch (SW 1 ) And the other end of the current source (I) 1 ) And a second Switch (SW) 2 ) Is connected to one end of a current source (I 1 ) Is connected to a power supply, a second switch (SW 2 ) And the other end of the capacitor (C) 1 ) One end of (and) a third switch (SW 3 ) Is connected to one end of the sampling capacitor (C 1 ) And the other end of the fourth switch (SW 4 ) One end of the phase detector is connected and then used as a voltage output end (V SAMP ) Fourth Switch (SW) 4 ) And the other end of the first reference voltage input end (V Ref1 ) Is connected to a third switch (SW 3 ) And the other end of the second reference voltage input end (V Ref2 ) Is connected with each other.
3. The fractional-n sampling phase-locked loop based on voltage spatial averaging as claimed in claim 2, wherein the sampling and averaging control clock generator comprises a transmission gate (TG 1 ) First Inverter (INV) 1 ) Second Inverter (INV) 2 ) Third Inverter (INV) 3 ) Fourth Inverter (INV) 4 ) Fifth Inverter (INV) 5 ) Third Buffer (BUF) 3 ) Fourth Buffer (BUF) 4 ) Fifth slowPunch (BUF) 5 ) Sixth Buffer (BUF) 6 ) Seventh Buffer (BUF) 7 ) Eighth Buffer (BUF) 8 ) Ninth Buffer (BUF) 9 ) First D flip-flop (DFF) 1 ) Second D flip-flop (DFF) 2 ) A first Delay module (Delay) 1 ) A second Delay module (Delay) 2 )；
Reference clock input terminal (phi) ref ) AND Transmission Gate (TG) 1 ) Input terminal of (a) and first Inverter (INV) 1 ) Is connected to the input of the Transmission Gate (TG) 1 ) Output of (c) and a third Buffer (BUF) 3 ) Is connected to the input of a third buffer (BUF 3 ) Output end of (a) and a second inverter (INV 2 ) Input end of the third Inverter (INV) 3 ) Output end of fifth Inverter (INV) 5 ) Is connected to the input terminal of the (and) and a sixth Buffer (BUF) 6 ) Is connected to the input end of the first inverter (INV 1 ) Output of (c) and fourth Buffer (BUF) 4 ) Is connected to the input of a fourth buffer (BUF 4 ) Output end of (a) and a second inverter (INV 2 ) Output end of the third Inverter (INV) 3 ) A fourth Inverter (INV) 4 ) Is connected to the input of the fifth Buffer (BUF) 5 ) Is connected to the input of the fourth inverter (INV 4 ) Is suspended at the output end of the fifth Inverter (INV) 5 ) As the first clock output (Φ) of the sample and average controlled clock generator 1 ) Fifth Buffer (BUF) 5 ) Output of (c) and a seventh Buffer (BUF) 7 ) Is connected to the input of the fifth Buffer (BUF) 5 ) As the second clock output (phi) of the sampling and averaging control clock generator 2 ) Seventh Buffer (BUF) 7 ) Output of (c) and a ninth Buffer (BUF) 9 ) Is connected to the input of the first Buffer (BUF) 7 ) As the output of the sampling and averaging control clock generator 3 ) Ninth Buffer (BUF) 9 ) As output of the sampling and averaging clock generator RST,PFD ) Sixth Buffer (BUF) 6 ) Output of (c) and eighth Buffer (BUF) 8 ) Input of (a)The ends are connected, and an eighth Buffer (BUF) 8 ) And the output of the first D flip-flop (DFF) 1 ) Is connected to the clock input of the first D flip-flop (DFF 1 ) Is connected to the high level signal terminal, and a first D flip-flop (DFF 1 ) And the output of the first Delay module (Delay) 1 ) Is connected to the input of the control pulse output (pulse), the first Delay module (Delay 1 ) And a second D flip-flop (DFF) 2 ) Is connected to the clock input of the second D flip-flop (DFF 2 ) Is connected to the high level signal terminal, and a second D flip-flop (DFF 2 ) And a second Delay module (Delay) 2 ) Is connected to the input of the second Delay module (Delay 2 ) And the output of the first D flip-flop (DFF) 1 ) Is connected to the reset terminal of the second D flip-flop (DFF) 2 ) Is connected with the reset end of the circuit.
4. The fractional-n sampling phase-locked loop based on voltage spatial averaging as claimed in claim 1, wherein the bi-phase frequency and phase discrimination control module comprises a first NOR gate (NOR 1 ) Second NOR gate (NOR) 2 ) Third NOR gate (NOR) 3 ) Fourth NOR gate (NOR) 4 ) Fifth NOR gate (NOR) 5 ) Sixth NOR gate (NOR) 6 ) Seventh NOR gate (NOR) 7 ) Eighth NOR gate (NOR) 8 ) Tenth Buffer (BUF) 10 ) Eleventh Buffer (BUF) 11 ) Twelfth Buffer (BUF) 12 ) Thirteenth Buffer (BUF) 13 ) A third Delay module (Delay) 3 ) Three-input AND gate (AND) 1 )；
First NOR gate (NOR) 1 ) As a second clock input of the voltage-averaged sampled fractional phase frequency detector, a first NOR gate (NOR 1 ) And a second NOR gate (NOR) 2 ) Is connected to the first input terminal of the first and third NOR gates (NOR) 3 ) Is connected to the first input of the second NOR gate (NOR 2 ) And the output end of the first NOR gate (NOR) 1 ) Is connected to the second input of the fifth Buffer (BUF) 10 ) Is connected with the input end of the third NOR gate(NOR 3 ) And a second NOR gate (NOR) 2 ) A second input terminal of (a) and a fourth NOR gate (NOR) 4 ) Is connected to the first input of the fourth NOR gate (NOR 4 ) And a third NOR gate (NOR) 3 ) Is connected to the second input of the third Delay module (Delay 3 ) And a fourth NOR gate (NOR) 4 ) And a fifth NOR gate (NOR) 5 ) Is connected to the first input of the fifth NOR gate (NOR 5 ) And a sixth NOR gate (NOR) 6 ) Is connected to the first input of the second NOR gate (NOR 6 ) And a fifth NOR gate (NOR) 5 ) And a seventh NOR gate (NOR) 7 ) Is connected to the first input of the fifth NOR gate (NOR 7 ) And an eighth NOR gate (NOR) 8 ) Is connected to the first input of the (and) twelfth Buffer (BUF) 12 ) Is connected to the input of the eighth NOR gate (NOR 8 ) And a sixth NOR gate (NOR) 6 ) And a seventh NOR gate (NOR) 7 ) Is connected to the second input of the second input unit, and an eighth NOR gate (NOR 8 ) As a third clock input of the voltage-means sampled fractional phase frequency detector, a tenth Buffer (BUF) 10 ) Output of (c) and an eleventh Buffer (BUF) 11 ) Input of (1) AND a three-input AND gate (AND) 1 ) Is connected to the first input of the eleventh buffer (BUF 11 ) Is used as the first output end (phi) of the double-phase frequency discrimination phase discrimination control module Lead,PUL ) Three-input AND gate (AND) 1 ) As a second clock input of the voltage-means sampled fractional phase frequency detector, a twelfth buffer (BUF 12 ) AND the output of (a) AND a three-input AND gate (AND) 1 ) Third input of (d) and thirteenth Buffer (BUF) 13 ) Is connected to the input of the thirteenth Buffer (BUF) 13 ) Is used as the second output end (phi) of the double-phase frequency discrimination phase discrimination control module Lag,PUL ) Three-input AND gate (AND) 1 ) And a third Delay module (Delay) 3 ) Is connected to the input terminal of the circuit.
5. According toThe fractional-n sampling phase-locked loop of claim 1 wherein said sampling phase generator comprises a 5-bit wide digital signal input, a vector control inputQuadrature/2 divider (QDIV) 1 ) Multi-modulus divider, third D flip-flop (DFF) 3 ) Fourth D flip-flop (DFF) 4 ) Fifth D flip-flop (DFF) 5 ) Sixth D flip-flop (DFF) 6 ) Seventh D flip-flop (DFF) 7 ) Multiplexer (MUX) 2 )；
Differential output terminal (phi) of voltage-controlled oscillator VCO+ Phi VCO- ) With quadrature/2 frequency divider (QDIV) 1 ) Is connected to the differential input of the quadrature/2 frequency divider (QDIV 1 ) Is arranged to be connected to the first clock output terminal (phi) I ) And third D flip-flop (DFF) 3 ) Seventh D flip-flop (DFF) 7 ) Is connected to the clock input of the quadrature/2 frequency divider (QDIV 1 ) Is arranged to be connected to the second clock output terminal (phi) Q ) And fourth D flip-flop (DFF) 4 ) Is connected to the clock input of the quadrature/2 frequency divider (QDIV 1 ) Is arranged to be connected to the third clock output terminal (phi) IB ) And fifth D flip-flop (DFF) 5 ) Is connected to the clock input of the quadrature/2 frequency divider (QDIV 1 ) A fourth clock output terminal (phi) QB ) And sixth trigger D (DFF) 6 ) Is connected to the clock input of the multimode frequency divider, the clock output of the multimode frequency divider (phi div ) And third D flip-flop (DFF) 3 ) Is connected to the data input of the third D flip-flop (DFF 3 ) Output of (D) and fourth D flip-flop (DFF) 4 ) Data input of (2) and Multiplexer (MUX) 2 ) Is arranged to be connected to the first input terminal (phi) 0° ) Is connected to, a fourth D flip-flop (DFF) 4 ) Output of (D) and fifth D flip-flop (DFF) 5 ) Data input of (2) and Multiplexer (MUX) 2 ) Is arranged to be connected to the second input terminal (phi) 90° ) Connected, fifth D flip-flop (DFF) 5 ) Output of (D) and a sixth D flip-flop (DFF) 6 ) Data input of (2) and Multiplexer (MUX) 2 ) Third input end of%Φ 180° ) Connected to, a sixth D flip-flop (DFF) 6 ) Output of (c) and seventh D flip-flop (DFF) 7 ) Data input of (2) and Multiplexer (MUX) 2 ) A fourth input terminal (phi) 270° ) Is connected with a seventh D flip-flop (DFF) 7 ) Output of (2) and Multiplexer (MUX) 2 ) Is a fifth input terminal (phi) 360° ) Is connected with the sampling control signal generator, and the 5-bit wide digital signal output end (N div ) Is connected to the control terminal of the multimode frequency divider, and the multiplexer (MUX 2 ) As a first output (phi) of a sampling phase detector generator Lead ) Multiplexer (MUX) 2 ) As a second output (phi) of the sampling phase detector generator Lag ) First vector output end of frequency division and sampling control signal generatorAnd Multiplexer (MUX) 2 ) Is connected to the control input of the control circuit.
6. The fractional-n sampling phase-locked loop of claim 1, wherein said divide-and-sample control signal generator comprises a fractional-n delta-sigma modulator, accumulator (ACC 1 ) A first Adder (ADD) 1 ) A second Adder (ADD) 2 ) Edge Select Logic (ESL);
the frequency control word input (n+α) is a 25-bit wide digital input, the input of the fractional-delta sigma modulator is connected to the frequency control word input (n+α), the high 5-bit wide integer control word (d inte ) The output end is connected with a first adder (ADD 1 ) Is connected to the 5-bit wide input of the delta sigma modulator, the high 2 bits of the 7-bit wide small number control word of the delta sigma modulator are the most significant bits (d frac,MSB ) AND Accumulator (ACC) 1 ) Is connected to the input of the delta sigma modulator, the lower 5 bits of the 7 bits wide small number control word is used as the least significant bit (d frac,LSB ) Connected to an input of an Edge Selection Logic (ESL) Accumulator (ACC) 1 ) And a second Adder (ADD) 2 ) Is connected to the 3-bit wide input terminal of the edge select logic module (ESL), the 1-bit wide output terminal (N ref ) And a second Adder (ADD) 2 ) Is connected to the 1-bit wide input of the second adder (ADD 2 ) The most significant bit of the 3-bit wide output of (a) is added to the first adder (ADD 1 ) Is connected to the 1-bit wide input of the second adder (ADD 2 ) The lower 2 bits of the 3-bit wide output of (2) are used as the first vector output of the frequency division and sampling control signal generatorFirst Adder (ADD) 1 ) Is used as the 5-bit wide digital signal output end (N div ) The vector output of the Edge Selection Logic (ESL) is used as the second vector output of the frequency division and sampling control signal generator>
7. The fractional-n sampling phase-locked loop of claim 6 wherein the edge selection logic comprises a data weight average logic module, a number of exclusive-or gates, and a number of accumulators, wherein one exclusive-or gate (XOR 1 ) Corresponding to an Accumulator (ACC) 2 )；
The lower 5 bits of the 7-bit wide small number control word of the fractional delta sigma modulator are the least significant bits (d frac,LSB ) The vector output end of the data weight average value logic module is connected with the input end of the data weight average value logic moduleComprises a plurality of sub-output ends, each sub-output end is respectively connected with a group of exclusive OR gates (XOR) 1 ) Accumulator (ACC) 2 ) Corresponding to each sub-output end, and corresponding exclusive-OR gate (XOR 1 ) Is connected to the first input terminal of the data rightScalar output of the weight average logic module (N DWA,REF ) Connected to the second inputs of all exclusive-OR gates, each exclusive-OR gate (XOR 1 ) Output of (c) and Accumulator (ACC) 2 ) Is connected to the input of the accumulator (ACC 2 ) As vector outputs of Edge Selection Logic (ESL).
CN202310788093.8A 2023-06-29 2023-06-29 Decimal frequency division sampling phase-locked loop based on voltage space average value Pending CN116827336A (en)

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