CN113938131B - Subsampling phase-locked loop for real-time fractional frequency division - Google Patents

Subsampling phase-locked loop for real-time fractional frequency division Download PDF

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CN113938131B
CN113938131B CN202111153059.0A CN202111153059A CN113938131B CN 113938131 B CN113938131 B CN 113938131B CN 202111153059 A CN202111153059 A CN 202111153059A CN 113938131 B CN113938131 B CN 113938131B
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switch
phase
output end
input end
sampling
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CN113938131A (en
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张岩龙
贾国樑
耿莉
樊超
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Xian Jiaotong University
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Xian Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer

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Abstract

The invention discloses a sub-sampling phase-locked loop for real-time fractional frequency division, which comprises a reference clock input end, a common-mode voltage input end, a frequency division control word input end, a radio frequency signal output end, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator and a frequency locking loop.

Description

Subsampling phase-locked loop for real-time fractional frequency division
Technical Field
The invention belongs to the technical field of electronics, and relates to a sub-sampling phase-locked loop for real-time fractional frequency division.
Background
The phase-locked loop is one of important functional modules in a radio frequency/microwave communication system and a computer system, and is widely applied to the generation of carrier signals, clock signals, frequency modulation signals and phase modulation signals due to the advantages of good frequency tracking characteristic, low phase noise, small spurious component, high system stability and the like.
Compared with the traditional phase-locked loop based on the phase frequency detector-charge pump structure, the sub-sampling phase-locked loop directly utilizes the reference signal to sample the high-frequency signal output by the oscillator, an additional frequency divider is not needed, and noise introduced by the frequency divider and power consumption of the frequency divider are eliminated. In addition, the gain of the sub-sampling phase detector in the sub-sampling phase-locked loop is higher than that of the phase detector with the phase frequency detector-charge pump structure, so that the phase-locked loop can better inhibit phase noise in the loop bandwidth, and the sub-sampling phase-locked loop is a research hot spot of the current phase-locked loop with low power consumption and low phase noise. The sub-sampling phase detector itself lacks a mechanism to distinguish the oscillator periods and is therefore not directly used in a fractional-n pll. To solve this problem, the most commonly used method in the work reported at home and abroad today is to modulate the phase of the reference signal with a digital-to-time converter and change the sampling time to realize fractional frequency division. However, the noise of the digital-to-time converter modulates the phase of the reference signal, introducing additional phase noise, and this phase noise is not effectively suppressed by the sub-sampling phase detector, thereby deteriorating the phase noise characteristics of the sub-sampling phase locked loop. Furthermore, the accuracy and dynamic range of the digital-to-time converter are susceptible to integrated circuit processes, chip supply voltages, ambient temperature, and output signal cycles, requiring real-time calibration to ensure accurate fractional frequency division. Furthermore, the nonlinear nature of the digital-to-time converter can cause noise folding, further degrading the phase noise characteristics of the sub-sampling phase-locked loop. The existing fractional frequency sub-sampling phase-locked loop has many defects, which limit the wide application of the sub-sampling phase-locked loop in the current radio frequency/microwave communication system and computer system.
Although the sub-sampling phase-locked loop effectively suppresses phase noise within the system loop bandwidth, for a fractional-frequency sub-sampling phase-locked loop, phase noise outside the loop bandwidth is still dominated by fractional-frequency quantization noise. Researchers at home and abroad have proposed a plurality of quantization noise suppression methods in the last twenty years, such as feedforward compensation technology based on a digital-to-analog converter and a digital-to-time converter, phase difference value technology, filtering preprocessing method based on a finite impulse response filter, space-time average decimal frequency division technology and the like. However, these techniques have poor compatibility with sub-sampling phase locked loops, cannot be directly combined with sub-sampling phase detectors, and have limitations.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a sub-sampling phase-locked loop system architecture for real-time fractional frequency division, and the phase-locked loop has the advantage of low phase noise in the bandwidth of the sub-sampling phase-locked loop and can effectively inhibit the phase noise generated by fractional frequency division.
In order to achieve the above objective, the real-time fractional frequency sub-sampling phase-locked loop of the present invention includes a reference clock input terminal, a common-mode voltage input terminal, a frequency division control word input terminal, a radio frequency signal output terminal, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator, and a frequency locking loop;
The output end of the transconductance amplifier and the output end of the frequency-locked loop are respectively connected with the input end of a low-pass filter, the output end of the low-pass filter is connected with the input end of a voltage-controlled oscillator, the single-end output end of the voltage-controlled oscillator is connected with the input end of an output buffer and the first input end of the frequency-locked loop, the output end of the output buffer is connected with the output end of a radio-frequency signal, the second input end of the frequency-locked loop is connected with the input end of a reference clock, the differential signal output end of the voltage-controlled oscillator is connected with the first input end and the second input end of a sampling phase generator, the first output end and the second output end of the sampling phase generator are respectively connected with the second input end of the sampling phase generator, the single-end of the sampling phase generator is connected with the second input end of the sampling phase generator and the third input end of the sampling phase generator, the single-end of the sampling phase generator is connected with the input end of a frequency-locked loop, the output end of the sampling phase generator is connected with the frequency-vector of a frequency-locked loop, the output of the sampling phase generator is connected with the frequency-vector of the sampling phase generator is controlled, and the frequency-locked loop is connected with the input end of the frequency-locked vector of the sampling phase generator.
The sub-sampling decimal phase discriminator comprises a mean voltage output end, a slope signal generator, a first bootstrap switch, a second bootstrap switch, a sample-hold signal generator, a mean logic, a fifth switch and a plurality of sub-sampling phase discrimination units;
Each sub-sampling phase discrimination unit comprises a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor and a first inverter;
the first output end and the second output end of the sampling phase generator are respectively connected with the first input end and the second input end of the slope signal generator, the first output end of the slope signal generator is connected with the input end of the first bootstrap switch, the second output end of the slope signal generator is connected with the input end of the second bootstrap switch, the input end of the reference clock is respectively connected with the control end of the first bootstrap switch, the control end of the second bootstrap switch and the input end of the sampling-holding signal generator, the output end of the first bootstrap switch is connected with one end of the first switch in each sub-sampling phase discrimination unit, and the output end of the second bootstrap switch is connected with one end of the second switch in each sub-sampling phase discrimination unit; in each sub-sampling phase discrimination unit, the other end of the first switch is connected with one end of the first capacitor and one end of the third switch, the other end of the second switch is connected with one end of the second capacitor and one end of the fourth switch, the other end of the first capacitor and the other end of the second capacitor are grounded, the other end of the third switch in all sub-sampling phase discrimination units and the other end of the fourth switch in all sub-sampling phase discrimination units are connected with one end of the fifth switch and then serve as average voltage output ends of the sub-sampling fractional phase discriminator, a first clock output end of a sampling-holding signal generator is connected with a control end of the first switch in each sub-sampling phase discrimination unit and a control end of the second switch in each sub-sampling phase discrimination unit, a second clock output end of the sampling-holding signal generator is connected with a scalar input end of an average logic, a holding signal output end of the average logic is connected with a control end of the third switch in the corresponding sub-sampling phase discrimination unit and an input end of a first inverter in the corresponding sub-sampling phase discrimination unit, an output end of the first inverter in each sub-sampling phase discrimination unit is connected with the average voltage vector, and the output end of the sampling-holding signal generator is connected with the fifth clock output end of the sampling phase discriminator.
The slope signal generator comprises a frequency/phase discriminator, a second inverter, a third inverter, a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor and a second resistor;
The first output end and the second output end of the sampling phase generator are respectively connected with the first input end and the second input end of the frequency/phase discriminator, the first output end of the frequency/phase discriminator is connected with the input end of the second inverter, the output end of the second inverter is connected with the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube, the source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the source electrode of the first NMOS tube is grounded, the other end of the first resistor is connected with the drain electrode of the first NMOS tube and then used as a first voltage signal output end, the second output end of the frequency/phase discriminator is connected with the input end of the third inverter, the output end of the third inverter is connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube, the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with one end of the second resistor, the source electrode of the second NMOS tube is grounded, and the other end of the second resistor is connected with the drain electrode of the second NMOS tube and then used as a second voltage signal output end.
The sample-hold signal generator comprises a first delay unit, a fourth inverter, a second delay unit, a first buffer, a third delay unit and a fifth inverter;
The reference clock input end is connected with the input end of the first delay unit, the output end of the first delay unit is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the second delay unit and the input end of the third delay unit, the output end of the fourth inverter is used as a first clock output end, the output end of the second delay unit is connected with the input end of the first buffer, the output end of the first buffer is used as a second clock output end, the output end of the third delay unit is connected with the input end of the fifth inverter, and the output end of the fifth inverter is used as a third clock output end.
The average logic comprises a plurality of holding signal output ends and a plurality of average logic units, wherein each average logic unit comprises a sixth inverter and a first AND gate;
The first vector output end of the sampling and frequency division control signal generator comprises a plurality of sub-input ends, wherein one sub-input end corresponds to an average value logic unit and a sub-sampling phase discrimination unit, each sub-input end is connected with the input end of a sixth inverter in the corresponding average value logic unit, the output end of the sixth inverter in each average value logic unit is connected with the first input end of a first AND gate, the second clock output end of the sampling-holding signal generator is connected with the second input ends of the first AND gates in all the average value logic units, and the output end of each first AND gate is used as a corresponding holding signal output end to be connected with the control end of a third switch in the corresponding sub-sampling phase discrimination unit and the input end of the first inverter.
The sampling phase generator comprises a quadrature/2 frequency divider, a multiplexer, a first phase interpolation unit, a third capacitor, a second phase interpolation unit, a fourth capacitor, a third phase interpolation unit, a fifth capacitor, a fourth phase interpolation unit, a sixth capacitor, a fifth phase interpolation unit, a seventh capacitor, a sixth phase interpolation unit, an eighth capacitor, a seventh phase interpolation unit, a ninth capacitor, an eighth phase interpolation unit, a tenth capacitor, a ninth phase interpolation unit, an eleventh capacitor, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch and an eleventh switch;
The differential input end of the quadrature/2 frequency divider is connected with the differential signal output end of the voltage-controlled oscillator, the first output end, the second output end, the third output end and the fourth output end of the quadrature/2 frequency divider are respectively connected with the first input end, the second input end, the third input end and the fourth input end of the multiplexer, and the first control end and the second control end of the multiplexer are respectively connected with the fourth sub-input end and the fifth sub-input end of the second vector output end of the sampling and frequency division control signal generator;
The first output end of the multiplexer is connected with the first input end of the first phase interpolation unit, the second input end of the first phase interpolation unit and the first input end of the second phase interpolation unit, the second output end of the multiplexer is connected with the second input end of the second phase interpolation unit, the first input end of the third phase interpolation unit and the second input end of the third phase interpolation unit, the output end of the first phase interpolation unit is connected with one end of the third capacitor and the first selection end of the sixth switch, the other end of the third capacitor is grounded, the output end of the second phase interpolation unit is connected with one end of the fourth capacitor, the second selection end of the sixth switch and the first selection end of the seventh switch, the other end of the fourth capacitor is grounded, the other end of the fifth capacitor is grounded, and the third sub-input end of the second vector output end of the sampling and frequency division control signal generator is connected with the control end of the seventh switch;
The fixed end of the sixth switch is connected with the first input end of the fourth phase interpolation unit, the second input end of the fourth phase interpolation unit and the first input end of the fifth phase interpolation unit, the fixed end of the seventh switch is connected with the second input end of the fifth phase interpolation unit, the first input end of the sixth phase interpolation unit and the second input end of the sixth phase interpolation unit, the output end of the fourth phase interpolation unit is connected with one end of a sixth capacitor and the first selection end of an eighth switch, the other end of the sixth capacitor is grounded, the output end of the fifth phase interpolation unit is connected with one end of a seventh capacitor, the second selection end of the eighth switch and the first selection end of the ninth switch, the other end of the seventh capacitor is grounded, the other end of the eighth capacitor is grounded, and the second sub-input end of the second vector output end of the sampling and frequency division control signal generator is connected with the control end of the eighth switch and the control end of the ninth switch;
The fixed end of the eighth switch is connected with the first input end of the seventh phase interpolation unit, the second input end of the seventh phase interpolation unit and the first input end of the eighth phase interpolation unit, the fixed end of the ninth switch is connected with the second input end of the eighth phase interpolation unit, the first input end of the ninth phase interpolation unit and the second input end of the ninth phase interpolation unit, the output end of the seventh phase interpolation unit is connected with one end of a ninth capacitor and the first selection end of the tenth switch, the other end of the ninth capacitor is grounded, the output end of the eighth phase interpolation unit is connected with one end of a tenth capacitor, the second selection end of the tenth switch and the first selection end of the eleventh switch, the other end of the tenth capacitor is grounded, the other end of the eleventh capacitor is grounded, the first input end of the second vector output end of the sampling and frequency division control signal generator is connected with the control end of the tenth switch and the first selection end of the tenth switch, and the other end of the tenth switch is used as the sampling output end of the sampling and the tenth switch.
Each phase interpolation unit comprises a first current source, a second current source, a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube and a second AND gate;
the first input end of the phase interpolation unit is connected with the grid electrode of the third PMOS tube and the first input end of the second AND gate, the source electrode of the third PMOS tube is connected with one end of the first current source, the other end of the first current source is connected with the power supply, the second input end of the phase interpolation unit is connected with the grid electrode of the fourth PMOS tube and the second input end of the second AND gate, the source electrode of the fourth PMOS tube is connected with one end of the second current source, the other end of the second current source is connected with the power supply, the output end of the second AND gate is connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are connected to serve as the output end of the phase interpolation unit.
The sampling and frequency division control signal generator comprises a decimal delta sigma modulator, a first adder, a second adder, an accumulator and a data weight average module;
the number of bits of the input end of the frequency division control word is 25 bits, the input end of the frequency division control word is connected with the input end of the fractional delta sigma modulator, the 5-bit wide first output end of the fractional delta sigma modulator is connected with the input end of the adder, the 5-bit wide second output end of the fractional delta sigma modulator is connected with the input end of the accumulator, the 6-bit wide third output end of the fractional delta sigma modulator is connected with the input end of the data weight average value module, the 5-bit wide output end of the first adder is connected with the scalar output end serving as a sampling and frequency division control signal generator, the 6-bit wide output end of the accumulator is connected with the 6-bit wide input end of the second adder, the highest 1-bit in the 6-bit wide output end of the second adder is connected with the 1-bit wide input end of the first adder, the lower 5-bit in the 6-bit wide output end of the second adder serves as the second vector output end of the sampling and control signal generator, and the 6-bit wide output end of the data weight average value module serves as the vector output of the sampling and frequency division control signal generator, and the output unit 64 serves as the vector of the output vector of the frequency division control signal generator.
The invention has the following beneficial effects:
The sub-sampling phase-locked loop of real-time fractional frequency division adopts a sub-sampling fractional phase discriminator structure based on voltage average value when in specific operation, realizes fractional frequency division without the assistance of a digital-time converter, overcomes the problem that the digital-time converter worsens the phase noise characteristic of a reference clock, is easy to be influenced by the process of an integrated circuit, the power supply voltage of a chip and the environmental temperature, remarkably reduces the phase noise source of the sub-sampling phase-locked loop of fractional frequency division, and is beneficial to realizing the sub-sampling phase-locked loop of fractional frequency division with lower phase noise. In addition, the voltage average is finished by using the sub-sampling fractional phase discriminator, the process is not influenced by the periodical change of the output signal of the pressure-controlled oscillator, the problem that the gain of the digital-to-time converter needs to be calibrated in real time in the traditional sub-sampling phase-locked loop based on the fractional frequency division of the digital-to-time converter is solved, the fractional frequency division function can be realized in the sub-sampling phase-locked loop without calibration, the complexity and the power consumption of the system are reduced, and the low-power-consumption fractional frequency division sub-sampling phase-locked loop is facilitated to be realized. Finally, the control circuit of the space-time average technology in the invention is mainly realized by a digital circuit, so that the invention has good immunity to errors caused by process, voltage and temperature fluctuation, has good process reconfigurability and is convenient for automatic design, and the power consumption and hardware cost can be further reduced along with continuous progress of the integrated circuit manufacturing process. In addition, the data weight average module for controlling the space average process can perform first-order high-pass shaping on the mismatch of the capacitors in the sub-sampling decimal phase discriminator unit array, and output strays caused by the mismatch of the capacitors in the sub-sampling decimal phase discriminator are reduced.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
fig. 2 is a schematic diagram of a sub-sampling fractional phase detector in accordance with the present invention;
FIG. 3 is a schematic diagram of a ramp signal generator according to the present invention;
FIG. 4 is a schematic diagram of a sample-and-hold signal generator according to the present invention;
FIG. 5 is a schematic diagram of mean logic in accordance with the present invention;
FIG. 6 is a block diagram of a sampling phase generator according to the present invention;
FIG. 7 is a schematic diagram of a phase interpolation unit according to the present invention;
FIG. 8 is a block diagram of a sample and divide control signal generator according to the present invention;
FIG. 9 is a schematic diagram and timing diagram of an orthogonal/2 divider of the present invention;
fig. 10 is a block diagram of a frequency locked loop according to the present invention.
Detailed Description
In order to make the present invention better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments, but not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
In the accompanying drawings, there is shown a schematic structural diagram in accordance with a disclosed embodiment of the invention. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and their relative sizes, positional relationships shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
Referring to fig. 1, the sub-sampling phase-locked loop of real-time fractional frequency division according to the present invention includes a reference clock input terminal, a common mode voltage input terminal, a frequency division control word input terminal, a radio frequency signal output terminal, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low pass filter, a voltage controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator, and a frequency locking loop;
The first single-ended input end of the sub-sampling fractional phase discriminator is connected with a reference clock input end phi ref, the fourth single-ended input end of the sub-sampling fractional phase discriminator is connected with a common-mode voltage input end V CM, the positive end and the negative end of the differential input end of the transconductance amplifier are respectively connected with the common-mode voltage input end V CM and the output end V Hold of the sub-sampling fractional phase discriminator, the output end I CP,PLL of the transconductance amplifier and the output end I CP,FLL of the frequency locking loop are respectively connected with the input end I CP of the low-pass filter, the output end V C of the low-pass filter is connected with the input end of the voltage-controlled oscillator, the single-ended output end phi fvco of the voltage-controlled oscillator is connected with the input end of the output buffer and the first input end of the frequency locking loop, the output end of the output buffer is connected with the output end phi PLL of the radio frequency signal, the second input end of the frequency locking loop is connected with the reference clock input end phi ref, the differential signal output end phi VCOP and the frequency locking loop are respectively connected with the first input end of the sampling phase generator and the second input end of the frequency locking loop, the differential signal output end I CP,FLL of the voltage-controlled oscillator is connected with the sampling phase generator and the input end of the sampling frequency-locked loop, the single-ended output end of the voltage-controlled phase generator is connected with the input end of the frequency-locked loop is connected with the input end of the frequency-locked loop, the input end of the frequency signal is connected with the input end of the input signal of the frequency signal A second vector output end/>, connected with the vector control end of the sub-sampling decimal phase discriminator, of the sampling and frequency dividing control signal generatorIs connected with the vector control end of the sampling phase generator.
Referring to fig. 2, the sub-sampling fractional phase discriminator includes a ramp signal generator, a first bootstrap switch BSW 1, a second bootstrap switch BSW 2, a sample-and-hold signal generator, mean logic, a fifth switch SW 5, and several sub-sampling phase discrimination units;
each sub-sampling phase-discrimination unit comprises a first switch SW 1, a second switch SW 2, a third switch SW 3, a fourth switch SW 4, a first capacitor C 1, a second capacitor C 2 and a first inverter INV 1;
the first output end phi LEAD and the second output end phi LAG of the sampling phase generator are respectively connected with the first input end and the second input end of the slope signal generator, the first output end V Lead of the slope signal generator is connected with the input end of the first bootstrap switch BSW 1, the second output end V Lag of the slope signal generator is connected with the input end of the second bootstrap switch BSW 2, the reference clock input end phi ref is respectively connected with the control end of the first bootstrap switch BSW 1, the control end of the second bootstrap switch BSW 2 and the input end of the sampling-holding signal generator, the output end of the first bootstrap switch BSW 1 is connected with one end of the first switch SW 1 in each sub-sampling phase discrimination unit, and the output end of the second bootstrap switch BSW 2 is connected with one end of the second switch SW 2 in each sub-sampling phase discrimination unit; the other end of the first switch SW 1 is connected with one end of a first capacitor C 1 and one end of a third switch SW 3, the other end of the second switch SW 2 is connected with one end of a second capacitor C 2 and one end of a fourth switch SW 4, the other end of the first capacitor C 1 and the other end of the second capacitor C 2 are grounded, the other end of the third switch SW 3 in all sub-sampling phase discrimination units and the other end of the fourth switch SW 4 in all sub-sampling phase discrimination units are connected with one end of a fifth switch SW 5 and then serve as a mean value voltage output end V Hold of a sub-sampling fractional phase discriminator, a first clock output end phi Samp of a sampling-holding signal generator is connected with a control end of the first switch SW 1 in each sub-sampling phase discrimination unit and a control end phi 6293 in each sub-sampling phase discrimination unit, a second clock output end phi Hold of the sampling-holding signal generator is connected with an input end of mean value logic, a holding signal output end Hold i of the mean value logic is connected with a sampling phase discriminator in a control end INV 69 in a sub-sampling phase discriminator, a sampling phase discriminator is connected with a first end 4 in a sub-sampling phase discriminator, and an inverting end of the sampling phase discriminator is connected with a first end of the first switch SW 34943 in a sub-phase discriminator The third clock output Φ CLR of the sample-and-hold signal generator is connected to the control terminal of the fifth switch SW 5, the other terminal of the fifth switch SW 5 is connected to the common mode voltage input V CM.
When the sub-sampling fractional phase discriminator works, a reference clock signal input by a reference clock input end phi ref controls a first bootstrap switch BSW 1 and a second bootstrap switch BSW 2, a first clock output end phi Samp of the sampling-holding signal generator controls a first switch SW 1 and a second switch SW 2 in each sub-sampling phase discriminator unit, two paths of voltage signals V Lead and V Lag output by the ramp signal generator are sampled to a first capacitor C 1 and a second capacitor C 2 respectively, the voltage signals are recorded in a form of electric charges, a second clock output end phi Hold of the sampling-holding signal generator controls a third switch SW 3 and a fourth switch SW 4 in each sub-sampling phase discriminator unit through mean value logic, and real-time fractional frequency division is realized, and a third clock output end phi CLR of the sampling-holding signal generator controls a third switch SW 3 to reset the first capacitor C 1 and the second capacitor C 2.
Referring to fig. 3, the ramp signal generator includes a frequency/phase discriminator, a second inverter INV 2, a third inverter INV 3, a first PMOS transistor MP 1, a second PMOS transistor MP 2, a first NMOS transistor MN 1, a second NMOS transistor MN 2, a first resistor R 1, and a second resistor R 2;
The first output end phi LEAD and the second output end phi LAG of the sampling phase generator are respectively connected with the first input end and the second input end of the frequency/phase discriminator, the first output end of the frequency/phase discriminator is connected with the input end of the second inverter INV 2, the output end of the second inverter INV 2 is connected with the grid electrode of the first PMOS tube MP 1 and the grid electrode of the first NMOS tube MN 1, the source electrode of the first PMOS tube MP 1 is connected with a power supply, the drain electrode of the first PMOS tube MP 1 is connected with one end of the first resistor R 1, the source electrode of the first NMOS tube MN 1 is grounded, the other end of the first resistor R 1 is connected with the drain electrode of the first NMOS tube MN 1 to serve as a first voltage signal output end V Lead, the second output end of the frequency/phase discriminator is connected with the input end of the third inverter INV 3, the output end of the third inverter INV 3 is connected with the grid electrode of the second PMOS tube MP 2 and the grid electrode of the second NMOS tube 2, the drain electrode of the second NMOS tube MN is connected with the drain electrode of the second resistor MN 4638, and the drain electrode of the second NMOS tube is connected with the drain electrode of the second resistor 82348, and the drain electrode of the second resistor is connected with the drain electrode of the second resistor 82343.
Referring to fig. 4, the sample-and-hold signal generator includes a first Delay unit Delay 1, a fourth inverter INV 4, a second Delay unit Delay 2, a first buffer BUFF 1, a third Delay unit Delay 3, and a fifth inverter INV 5;
the reference clock input terminal Φ ref is connected to the input terminal of the first Delay unit Delay 1, the output terminal of the first Delay unit Delay 1 is connected to the input terminal of the fourth inverter INV 4, the output terminal of the fourth inverter INV 4 is connected to the input terminal of the second Delay unit Delay 2 and the input terminal of the third Delay unit Delay 3, the output terminal of the fourth inverter INV 4 is used as the first clock output terminal Φ Samp, the output terminal of the second Delay unit Delay 2 is connected to the input terminal of the first buffer BUFF 1, the output terminal of the first buffer BUFF 1 is used as the second clock output terminal Φ Hold, the output terminal of the third Delay unit Delay 3 is connected to the input terminal of the fifth inverter INV 5, and the output terminal of the fifth inverter INV 5 is used as the third clock output terminal Φ CLR.
Referring to fig. 5, the average logic includes a plurality of Hold signal output ends Hold i AND a plurality of average logic units, wherein each average logic unit includes a sixth inverter INV 6 AND a first AND gate AND 1;
First vector output end of sampling and frequency division control signal generator The sampling-holding circuit comprises a plurality of sub-input ends, wherein one sub-input end corresponds to one average value logic unit AND one sub-sampling phase discrimination unit, each sub-input end is connected with the input end of a sixth inverter INV 6 in the corresponding average value logic unit, the output end of the sixth inverter INV 6 in each average value logic unit is connected with the first input end of a first AND gate AND 1, the second clock output end phi Hold of the sampling-holding signal generator is connected with the second input end of a first AND gate AND 1 in all average value logic units, AND the output end of a first AND gate AND 1 in the ith average value logic unit is used as a control end corresponding to an ith holding signal output end Hold i AND the input end of a first inverter INV 1, AND the control end of a third switch SW 3 in the corresponding ith sub-sampling phase discrimination unit is connected with the output end of the ith sub-sampling phase discrimination unit.
Referring to fig. 6, the sampling phase generator includes a quadrature/2 frequency divider, a multiplexer MUX 1, a first phase interpolation unit Cell 1, a third capacitor C 3, a second phase interpolation unit Cell 2, a fourth capacitor C 4, a third phase interpolation unit Cell 3, a fifth capacitor C 5, a fourth phase interpolation unit Cell 4, a sixth capacitor C 6, a fifth phase interpolation unit Cell 5, a seventh capacitor C 7, a sixth phase interpolation unit Cell 6, an eighth capacitor C 8, a seventh phase interpolation unit Cell 7, a ninth capacitor C 9, an eighth phase interpolation unit Cell 8, a tenth capacitor C 10, a ninth phase interpolation unit Cell 9, an eleventh capacitor C 11, a sixth switch SW 6, a seventh switch SW 7, an eighth switch SW 8, a ninth switch SW 9, a tenth switch SW 10, and an eleventh switch SW 11;
the differential input end of the quadrature/2 frequency divider is connected with the differential signal output end phi VCOP and phi VCON of the voltage-controlled oscillator, the first output end phi I, the second output end phi Q, the third output end phi IB and the fourth output end phi QB of the quadrature/2 frequency divider are respectively connected with the first input end, the second input end, the third input end and the fourth input end of the multiplexer MUX 1, and the first control end and the second control end of the multiplexer MUX 1 are respectively connected with the second vector output end of the sampling and frequency dividing control signal generator The fourth sub-input N PS,3 and the fifth sub-input N PS,4 are connected;
The first output end of the multiplexer MUX 1 is connected with the first input end of the first phase interpolation unit Cell 1, the second input end of the first phase interpolation unit Cell 1 and the first input end of the second phase interpolation unit Cell 2, the second output end of the multiplexer MUX 1 is connected with the second input end of the second phase interpolation unit Cell 2, the first input end of the third phase interpolation unit Cell 3 and the second input end of the third phase interpolation unit Cell 3, the output end of the first phase interpolation unit Cell 1 is connected with one end of the third capacitor C 3 and the first selection end of the sixth switch SW 6, the other end of the third capacitor C 3 is grounded, the output end of the second phase interpolation unit Cell 2 is connected with one end of the fourth capacitor C 4, the second selection end of the sixth switch SW 6 and the first selection end of the seventh switch SW 7, the other end of the fourth capacitor C 4 is grounded, the output end of the third capacitor C69 is connected with the fifth switch SW 34935, the output end of the fifth switch SW 34967 is connected with the fifth switch C9732, and the output end of the fifth switch C signal is connected with the fifth switch C 5 The third sub-input terminal N PS,2 of the sixth switch SW 6 is connected to the control terminal of the seventh switch SW 7;
The fixed end of the sixth switch SW 6 is connected with the first input end of the fourth phase interpolation unit Cell 4, the second input end of the fourth phase interpolation unit Cell 4 and the first input end of the fifth phase interpolation unit Cell 5, the fixed end of the seventh switch SW 7 is connected with the second input end of the fifth phase interpolation unit Cell 5, the first input end of the sixth phase interpolation unit Cell 6 and the second input end of the sixth phase interpolation unit Cell 6, the output end of the fourth phase interpolation unit Cell 4 is connected with one end of the sixth capacitor C 6 and the first selection end of the eighth switch SW 8, the other end of the sixth capacitor C 6 is grounded, the output end of the fifth phase interpolation unit Cell 5 is connected with one end of the seventh capacitor C 7, the second selection end of the eighth switch SW 8 and the first selection end of the ninth switch SW 9, the other end of the seventh capacitor C 7 is grounded, the output end of the sixth capacitor C69 is connected with the eighth switch SW 5297, the output end of the eighth switch SW 8 is connected with the output end of the eighth switch C3732, and the output end of the eighth switch SW 5296 is connected with the output end of the fourth switch C 8 The second sub-input terminal N PS,1 of the eighth switch SW 8 is connected to the control terminal of the ninth switch SW 9;
The fixed end of the eighth switch SW 8 is connected with the first input end of the seventh phase interpolation unit Cell 7, the second input end of the seventh phase interpolation unit Cell 7 and the first input end of the eighth phase interpolation unit Cell 8, the fixed end of the ninth switch SW 9 is connected with the second input end of the eighth phase interpolation unit Cell 8, the first input end of the ninth phase interpolation unit Cell 9 and the second input end of the ninth phase interpolation unit Cell 9, the output end of the seventh phase interpolation unit Cell 7 is connected with one end of a ninth capacitor C 9 and the first selection end of a tenth switch SW 10, the other end of the ninth capacitor C 9 is grounded, the output end of the eighth phase interpolation unit Cell 8 is connected with one end of a tenth capacitor C 10, the second selection end of the tenth switch SW 10 and the first selection end of an eleventh switch SW 11, the other end of the tenth capacitor C659795 is grounded, the output end of the ninth phase interpolation unit Cell 69 is connected with the output end of the eleventh capacitor C34924 and the eleventh switch SW 10, the other end of the eleventh switch C is connected with the output end of the eleventh capacitor C3732, the output end of the frequency divider is connected with the other end of the eleventh capacitor C3732 The first input terminal N PS,0 of the tenth switch SW 10 and the control terminal of the eleventh switch SW 11 are connected, and the fixed terminal of the tenth switch SW 10 and the fixed terminal of the eleventh switch SW 11 are respectively used as the first output terminal Φ LEAD and the second output terminal Φ LAG of the sampling phase generator.
When the sampling phase generator works, the quadrature/2 frequency divider divides the input differential signals phi VCOP and phi VCON into two frequency divisions to generate four-way quadrature signals phi I、ΦIQ、ΦIB、ΦQB, then the phase difference value is realized through the pipeline phase interpolator to generate output signals phi LEAD and phi LAG, namely the sampling phase generator passes through the phase selection control endThe fifth input end N PS,4 and the fourth input end N PS,3 control the multiplexer to perform coarse adjustment interpolation on the output signal, and the coarse adjustment interpolation is performed through the phase selection control end/>The third input N PS,2, the second input N PS,1, and the first input N PS,0 control the pipelined phase interpolator to perform fine-tuning interpolation on the output signal, so that the output sampling signals Φ LEAD and Φ LAG have proper phases.
Referring to fig. 7, each phase interpolation unit includes a first current source CS 1, a second current source CS 2, a third PMOS transistor MP 3, a fourth PMOS transistor MP 4, a third NMOS transistor MN 3, a fourth NMOS transistor MN 4, AND a second AND gate AND 2;
the first input terminal Φ in1 of the phase interpolation unit is connected to the gate of the third PMOS transistor MP 3 AND the first input terminal of the second AND gate AND 2, the source of the third PMOS transistor MP 3 is connected to one end of the first current source CS 1, the other end of the first current source CS 1 is connected to the power supply, the second input terminal Φ in2 of the phase interpolation unit is connected to the gate of the fourth PMOS transistor MP 4 AND the second input terminal of the second AND gate AND 2, the source of the fourth PMOS transistor MP 4 is connected to one end of the second current source CS 2, the other end of the second current source CS 2 is connected to the power supply, the output terminal of the second AND gate AND 2 is connected to the gate of the third NMOS transistor MN 3 AND the gate of the fourth NMOS transistor MN 4, the source of the third NMOS transistor MN 3 is grounded, the source of the fourth NMOS transistor MN 4 is grounded, AND the drain of the third PMOS transistor MP 3, the drain of the fourth PMOS transistor MP 4 is connected to the drain of the third NMOS transistor MN 3 AND the drain of the fourth NMOS transistor MN 4 is connected to the output terminal of the phase interpolation unit Φ out.
Referring to fig. 8, the sampling and frequency-dividing control signal generator includes a fractional delta-sigma modulator, a first adder ADD 1, a second adder ADD 2, an accumulator ACC 1, and a data weight average module;
The number of bits of the input end N+alpha of the frequency division control word is 25 bits, the input end N+alpha of the frequency division control word is connected with the input end of a fractional delta sigma modulator, a 5-bit wide first output end d inte of the fractional delta sigma modulator is connected with the input end of an adder ADD 1, a 5-bit wide second output end d frac,MSB of the fractional delta sigma modulator is connected with the input end of an accumulator ACC 1, a 6-bit wide third output end d frac,LSB of the fractional delta sigma modulator is connected with the input end of a data weight average module, the 5-bit wide output end of a first adder ADD 1 is used as a scalar output end N div of a sampling and frequency division control signal generator, the 6-bit wide output end of the accumulator ACC 1 is connected with the 1-bit wide input end of a second adder ADD 2, the 1-bit output end N ref of the data weight average module is connected with the 1-bit wide input end of the second adder ADD 2, the highest 1-bit wide output end of the second adder ADD 2 is connected with the 1-bit wide output end of the first adder ADD 1 as the output end of the second adder ADD 2, and the output vector of the second adder 2 is used as the output vector of the output end of the sampling and the second adder ADD 3523 is connected with the output end of the bit wide output end of the output vector signal The 64-unit vector output end of the data weight average value module is used as the first vector output end/>, of the sampling and frequency division control signal generator
Referring to the circuit schematic diagram in fig. 9, the quadrature/2 frequency divider includes a first D flip-flop DFF 1 and a second D flip-flop DFF 2;
The first differential signal input terminal Φ VCOP is connected to the clock input terminal of the first D flip-flop DFF 1, the positive output terminal of the first D flip-flop DFF 1 is used as the first clock output terminal Φ I, the negative output terminal of the first D flip-flop DFF 1 is connected to the data input terminal of the first D flip-flop DFF 1 and then used as the second clock output terminal Φ IB, the second differential signal input terminal Φ VCON is connected to the clock input terminal of the second D flip-flop DFF 2, the positive output terminal of the second D flip-flop DFF 2 is used as the third clock output terminal Φ Q, and the negative output terminal of the second D flip-flop DFF 2 is connected to the data input terminal of the second D flip-flop DFF 2 and then used as the fourth clock output terminal Φ QB.
Referring to the schematic diagram of the time domain waveform in fig. 9, the input signal of the quadrature/2 frequency divider is two clock signals with pi phase difference, the output signal is four clock signals with twice the input signal period, and the phase differences between the output signals Φ I and Φ Q、ΦQ and Φ IB、ΦIB and Φ QB、ΦQB and Φ I are pi/2, i.e. the four output signals are quadrature clock signals.
Referring to fig. 10, the frequency-locked loop includes a seventh inverter INV 7, a multi-mode frequency divider, a phase frequency detector with dead zone, and a charge pump;
the reference clock input end phi ref is connected with the input end of the seventh inverter INV 7, the output end phi refn of the seventh inverter INV 7 is connected with the first input end of the phase frequency detector with dead zone, the single-ended output end phi fvco of the voltage-controlled oscillator is connected with the input end of the multi-mode frequency divider, the scalar output end N div of the sampling and frequency division control signal generator is connected with the 5-bit wide control end of the multi-mode frequency divider, the output end phi fdiv of the multi-mode frequency divider is connected with the second input end of the phase frequency detector with dead zone, the first output end UP of the phase frequency detector with dead zone is connected with the first input end of the charge pump, the second output end DN of the phase frequency detector with dead zone is connected with the second input end of the charge pump, and the output end of the charge pump is used as the output end I CP,FLL of the frequency locking loop.
When the phase difference between two paths of input clock signals phi refn and phi fdiv of the phase frequency detector with the dead zone is larger than the dead zone range, the phase frequency detector with the dead zone is in a phase frequency detection state, and two paths of output ends of the phase frequency detector with the dead zone control a charge pump to charge/discharge a low-pass filter, so that the frequency locking of a phase-locked loop is realized; when the phase difference between two input clock signals phi refn and phi fdiv of the phase frequency detector with the dead zone is smaller than the dead zone range, the phase frequency detector with the dead zone stops working, two output ends of the phase frequency detector with the dead zone keep logic low level, a charge pump is turned off, and the phase-locked loop is controlled by the sub-sampling fractional phase detector to complete phase locking.

Claims (7)

1. The sub-sampling phase-locked loop is characterized by comprising a reference clock input end, a common-mode voltage input end, a frequency division control word input end, a radio frequency signal output end, a sub-sampling fractional phase discriminator, a transconductance amplifier, a low-pass filter, a voltage-controlled oscillator, an output buffer, a sampling and frequency division control signal generator, a sampling phase generator and a frequency locking loop;
The first single-ended input end of the sub-sampling fractional phase discriminator is connected with a reference clock input end (phi ref), the fourth single-ended input end of the sub-sampling fractional phase discriminator is connected with a common-mode voltage input end (V CM), the positive end and the negative end of the differential input end of the transconductance amplifier are respectively connected with the common-mode voltage input end (V CM) and the output end (V Hold) of the sub-sampling fractional phase discriminator, the output end (I CP,PLL) of the transconductance amplifier and the output end (I CP,FLL) of the frequency locking loop are connected with the input end (I CP) of the low-pass filter, the output end (V C) of the low-pass filter is connected with the input end of the voltage-controlled oscillator, the single-ended output end (phi fvco) of the voltage-controlled oscillator is connected with the input end of the output buffer and the first input end of the frequency locking loop, the output end of the output buffer is connected with the radio frequency signal output end (phi PLL), the second input end of the frequency locking loop is connected with the reference clock input end (phi ref), the differential signal output ends (phi VCOP) and (phi VCON) of the voltage-controlled oscillator are respectively connected with the first input end and the second input end of the sampling phase generator, the first output end (phi LEAD) and the second output end (phi LAG) of the sampling phase generator are respectively connected with the second single-ended input end and the third single-ended input end of the sub-sampling fractional phase discriminator, the input end of the sampling and frequency dividing control signal generator is connected with the frequency dividing control word input end (N+alpha), the scalar output end (N div) of the sampling and frequency dividing control signal generator is connected with the control end of the frequency locking loop, and the first vector output end of the sampling and frequency dividing control signal generator A second vector output end/>, connected with the vector control end of the sub-sampling decimal phase discriminator, of the sampling and frequency dividing control signal generatorThe vector control end of the sampling phase generator is connected with the vector control end of the sampling phase generator;
The sub-sampling fractional phase discriminator comprises a ramp signal generator, a first bootstrap switch (BSW 1), a second bootstrap switch (BSW 2), a sample-hold signal generator, mean logic, a fifth switch (SW 5) and a plurality of sub-sampling phase discrimination units;
Each sub-sampling phase-discrimination unit comprises a first switch (SW 1), a second switch (SW 2), a third switch (SW 3), a fourth switch (SW 4), a first capacitor (C 1), a second capacitor (C 2) and a first inverter (INV 1);
The first output end (phi LEAD) and the second output end (phi LAG) of the sampling phase generator are respectively connected with the first input end and the second input end of the slope signal generator, the first output end (V Lead) of the slope signal generator is connected with the input end of a first bootstrap switch (BSW 1), the second output end (V Lag) of the slope signal generator is connected with the input end of a second bootstrap switch (BSW 2), the reference clock input end (phi ref) is respectively connected with the control end of the first bootstrap switch (BSW 1), the control end of the second bootstrap switch (BSW 2) and the input end of the sampling-holding signal generator, the output end of the first bootstrap switch (BSW 1) is connected with one end of a first switch (SW 1) in each sub-sampling phase discrimination unit, and the output end of the second bootstrap switch (BSW 2) is connected with one end of a second switch (SW 2) in each sub-sampling phase discrimination unit; in each sub-sampling phase discrimination unit, the other end of the first switch (SW 1) is connected with one end of the first capacitor (C 1) and one end of the third switch (SW 3), the other end of the second switch (SW 2) is connected with one end of the second capacitor (C 2) and one end of the fourth switch (SW 4), the other end of the first capacitor (C 1) and the other end of the second capacitor (C 2) are grounded, the other end of the third switch (SW 3) in all sub-sampling phase discrimination units and the other end of the fourth switch (SW 4) in all sub-sampling phase discrimination units are connected with one end of the fifth switch (SW 5) and then serve as the average voltage output end (V Hold) of the sub-sampling fractional phase discriminator, the first clock output end (phi Samp) of the sample-Hold signal generator is connected with the control end of the first switch (SW 1) in each sub-sampling phase discrimination unit and the control end of the second switch (SW 2) in each sub-sampling phase discrimination unit, the scalar output end (phi Samp) of the sample-Hold signal generator is connected with the average voltage output end (Hold) of the sampling phase discriminator (Tl) of the second switch (Lv 1) in the sub-sampling phase discriminator (Lv) and the logic phase discriminator (Lv) is connected with the average voltage output end (Lv 3) of the sampling phase discriminator (Lv) in the sub-phase discriminator, the output end of the first inverter (INV 1) in the ith sub-sampling phase discrimination unit is connected with the control end of the fourth switch (SW 4) in the ith sub-sampling phase discrimination unit, and the average value control end The third clock output (Φ CLR) of the sample-and-hold signal generator is connected to the control of a fifth switch (SW 5), the other end of which is connected to the common-mode voltage input (V CM).
2. The sub-sampling phase-locked loop of claim 1, wherein the ramp signal generator comprises a frequency/phase discriminator, a second inverter (INV 2), a third inverter (INV 3), a first PMOS transistor (MP 1), a second PMOS transistor (MP 2), a first NMOS transistor (MN 1), a second NMOS transistor (MN 2), a first resistor (R 1), and a second resistor (R 2);
The first output end (phi LEAD) and the second output end (phi LAG) of the sampling phase generator are respectively connected with the first input end and the second input end of the frequency/phase discriminator, the first output end of the frequency/phase discriminator is connected with the input end of the second phase inverter (INV 2), the output end of the second phase inverter (INV 2) is connected with the grid electrode of the first PMOS tube (MP 1) and the grid electrode of the first NMOS tube (MN 1), the source electrode of the first PMOS tube (MP 1) is connected with a power supply, the drain electrode of the first PMOS tube (MP 1) is connected with one end of the first resistor (R 1), the source electrode of the first NMOS tube (MN 1) is grounded, the other end of the first resistor (R 1) is connected with the drain electrode of the first NMOS tube (MN 1) and then used as the first voltage signal output end (V Lead), the second output end of the frequency/phase discriminator is connected with the input end of the third phase inverter (MP 3), the drain electrode of the second PMOS tube (MP 34936) is connected with the second grid electrode of the second PMOS tube (MP 34932), the output end of the second phase inverter (MP 5493) is connected with the second grid electrode of the second PMOS tube (MP 34932) is connected with the second PMOS tube (MP 43932), the other end of the second resistor (R 2) is connected with the drain electrode of the second NMOS tube (MN 2) and then used as a second voltage signal output end (V Lag).
3. The sub-sampling phase-locked loop of real-time fractional frequency division according to claim 1, wherein the sample-hold signal generator comprises a first Delay unit (Delay 1), a fourth inverter (INV 4), a second Delay unit (Delay 2), a first buffer (BUFF 1), a third Delay unit (Delay 3) and a fifth inverter (INV 5);
The reference clock input terminal (Φ ref) is connected with the input terminal of the first Delay unit (Delay 1), the output terminal of the first Delay unit (Delay 1) is connected with the input terminal of the fourth inverter (INV 4), the output terminal of the fourth inverter (INV 4) is connected with the input terminal of the second Delay unit (Delay 2) and the input terminal of the third Delay unit (Delay 3), the output terminal of the fourth inverter (INV 4) is used as the first clock output terminal (Φ Samp), the output terminal of the second Delay unit (Delay 2) is connected with the input terminal of the first buffer (BUFF 1), the output terminal of the first buffer (ff 1) is used as the second clock output terminal (Φ Hold), the output terminal of the third Delay unit (Delay 3) is connected with the input terminal of the fifth inverter (INV 5), and the output terminal of the fifth inverter (INV 5) is used as the third clock output terminal (Φ CLR).
4. The sub-sampling phase-locked loop of real-time fractional division according to claim 1, wherein the average logic comprises a number of Hold signal outputs (Hold i) AND a number of average logic units, wherein each average logic unit comprises a sixth inverter (INV 6) AND a first AND gate (AND 1);
First vector output end of sampling and frequency division control signal generator The sampling-holding circuit comprises a plurality of sub-input ends, wherein one sub-input end corresponds to one average value logic unit AND one sub-sampling phase discrimination unit, each sub-input end is connected with the input end of a sixth inverter (INV 6) in the corresponding average value logic unit, the output end of the sixth inverter (INV 6) in each average value logic unit is connected with the first input end of a first AND gate (AND 1), the second clock output end (phi Hold) of the sampling-holding signal generator is connected with the second input end of a first AND gate (AND 1) in all average value logic units, AND the output end of the first AND gate (AND 1) in the ith average value logic unit is used as a control end corresponding to an ith holding signal output end (Hold i) AND the input end of a first inverter (INV 1) in the corresponding ith sub-sampling phase discrimination unit.
5. The real-time fractional-division sub-sampling phase-locked loop of claim 1, wherein the sampling phase generator comprises a quadrature/2 frequency divider, a multiplexer (MUX 1), a first phase interpolation unit (Cell 1), a third capacitor (C 3), a second phase interpolation unit (Cell 2), a fourth capacitor (Cell 4), a third phase interpolation unit (Cell 3), a fifth capacitor (C 5), a fourth phase interpolation unit (Cell 4), a sixth capacitor (C 6), a fifth phase interpolation unit (Cell 5), a seventh capacitor (C 7), a sixth phase interpolation unit (Cell 6), an eighth capacitor (C 8), a seventh phase interpolation unit (Cell 7), a ninth capacitor (C 9), an eighth phase interpolation unit (Cell 8), a tenth capacitor (C 10), a ninth phase interpolation unit (Cell 9), an eleventh capacitor (C 11), a sixth switch (SW 6), a seventh switch (SW 3775), a tenth switch (SW 3735), and a tenth switch (SW 372);
The differential input end of the quadrature/2 frequency divider is connected with the differential signal output end (phi VCOP) and (phi VCON) of the voltage-controlled oscillator, the first output end (phi I), the second output end (phi Q), the third output end (phi IB) and the fourth output end (phi QB) of the quadrature/2 frequency divider are respectively connected with the first input end, the second input end, the third input end and the fourth input end of the multiplexer (MUX 1), and the first control end and the second control end of the multiplexer (MUX 1) are respectively connected with the second vector output end of the sampling and frequency division control signal generator Is connected to the fourth sub-input (N PS,3) and the fifth sub-input (N PS,4);
The first output end of the multiplexer (MUX 1) is connected with the first input end of the first phase interpolation unit (Cell 1), the second input end of the first phase interpolation unit (Cell 1) and the first input end of the second phase interpolation unit (Cell 2), the second output end of the multiplexer (MUX 1) is connected with the second input end of the second phase interpolation unit (Cell 2), the first input end of the third phase interpolation unit (Cell 3) and the second input end of the third phase interpolation unit (Cell 3), the output end of the first phase interpolation unit (Cell 1) is connected with one end of the third capacitor (C 3) and the first selection end of the sixth switch (SW 6), the other end of the third capacitor (C 3) is grounded, the output end of the second phase interpolation unit (Cell 2) is connected with one end of the fourth capacitor (C 4), the second selection end of the sixth switch (SW 6) and the second input end of the third phase interpolation unit (Cell 5493) are connected with the first selection end of the fourth switch (SW 7), the output end of the third switch (SW 9762) is connected with the other end of the fifth capacitor (C 3) is connected with the other end of the third capacitor (C 3) and the second selection end of the fifth switch (SW 62) is connected with the other end of the third capacitor (C 3) is grounded, the output end of the second switch is connected with the second output end of the third capacitor (C switch (C35) and the output end of the second output end of the third capacitor is connected with the output end Is connected to the third sub-input (N PS,2) of the sixth switch (SW 6) and to the control of the seventh switch (SW 7);
The fixed end of the sixth switch (SW 6) is connected with the first input end of the fourth phase interpolation unit (Cell 4), the second input end of the fourth phase interpolation unit (Cell 4) and the first input end of the fifth phase interpolation unit (Cell 5), the fixed end of the seventh switch (SW 7) is connected with the second input end of the fifth phase interpolation unit (Cell 5), the first input end of the sixth phase interpolation unit (Cell 6) and the second input end of the sixth phase interpolation unit (Cell 6), the output end of the fourth phase interpolation unit (Cell 4) is connected with one end of the sixth capacitor (C 6) and the first selection end of the eighth switch (SW 8), the other end of the sixth capacitor (C 6) is grounded, the output end of the fifth phase interpolation unit (Cell 5) is connected with one end of the seventh capacitor (C 7), the second selection end of the eighth switch (SW 8) and the first selection end of the ninth switch (SW 9), the other end of the seventh capacitor (C 7) is grounded, the output end of the sixth phase interpolation unit (Cell 6) is connected with one end of the eighth capacitor (C 8) and the second selection end of the ninth switch (SW 9), the other end of the eighth capacitor (C 8) is grounded, and the second vector output end of the sampling and frequency division control signal generator Is connected to the second sub-input (N PS,1) of the eighth switch (SW 8) and to the control of the ninth switch (SW 9);
The fixed end of the eighth switch (SW 8) is connected to the first input end of the seventh phase interpolation unit (Cell 7), the second input end of the seventh phase interpolation unit (Cell 7) and the first input end of the eighth phase interpolation unit (Cell 8), the fixed end of the ninth switch (SW 9) is connected to the second input end of the eighth phase interpolation unit (Cell 8), the first input end of the ninth phase interpolation unit (Cell 9) and the second input end of the ninth phase interpolation unit (Cell 9), the output end of the seventh phase interpolation unit (Cell 7) is connected to one end of the ninth capacitor (C 9) and the first selection end of the tenth switch (SW 10), the other end of the ninth capacitor (C 9) is grounded, the output end of the eighth phase interpolation unit (Cell 8) is connected to one end of the tenth capacitor (C 10), the second selection end of the tenth switch (SW 10) and the second input end of the ninth phase interpolation unit (Cell 9) are connected to the first selection end of the eleventh switch (SW 11), the output end of the eleventh capacitor (C 9) is connected to the other end of the ninth capacitor (C 9), the output end of the eighth capacitor (C 9) is connected to the other end of the eighth capacitor (C 10), and the output end of the eleventh capacitor (C end of the eighth capacitor (C3754) is connected to the other end of the eighth capacitor (C3769) is connected to the input end of the eighth capacitor (C 10) and the output end of the output signal is connected to the output end of the output signal The first input terminal (N PS,0) of the tenth switch (SW 10) and the control terminal of the eleventh switch (SW 11) are connected, and the fixed terminal of the tenth switch (SW 10) and the fixed terminal of the eleventh switch (SW 11) are respectively used as a first output terminal (phi LEAD) and a second output terminal (phi LAG) of the sampling phase generator.
6. The sub-sampling pll according to claim 1, wherein each phase interpolation unit comprises a first current source (CS 1), a second current source (CS 2), a third PMOS transistor (MP 3), a fourth PMOS transistor (MP 4), a third NMOS transistor (MN 3), a fourth NMOS transistor (MN 4) AND a second AND gate (AND 2);
The first input end (Φ in1) of the phase interpolation unit is connected with the grid electrode of the third PMOS tube (MP 3) AND the first input end of the second AND gate (CS 2), the source electrode of the third PMOS tube (MP 3) is connected with one end of the first current source (CS 1), the other end of the first current source (CS 1) is connected with a power supply, the second input end (Φ in2) of the phase interpolation unit is connected with the grid electrode of the fourth PMOS tube (MP 4) AND the second input end of the second AND gate (AND 2), the source electrode of the fourth PMOS tube (MP 4) is connected with one end of the second current source (CS 2), the other end of the second current source (CS 2) is connected with the power supply, the output end of the second AND gate (AND 2) is connected with the grid electrode of the third NMOS tube (MN 3) AND the grid electrode of the fourth NMOS tube (MN 3), the source electrode of the fourth NMOS tube (4) is grounded, AND the source electrode of the fourth NMOS tube (MP 34962) is connected with the drain electrode of the fourth NMOS tube (MN 3752) AND the drain electrode (MN 3752) of the fourth NMOS tube (MN 3732) is connected with the drain electrode of the fourth NMOS tube (MN).
7. The real-time fractional-n sub-sampling phase-locked loop of claim 1 wherein the sampling and divide control signal generator comprises a fractional delta-sigma modulator, a first adder (ADD 1), a second adder (ADD 2), an accumulator (ACC 1) and a data weight average module;
The number of bits of the input end N+alpha of the frequency division control word is 25 bits, the input end N+alpha of the frequency division control word is connected with the input end of a fractional delta sigma modulator, a first output end d inte of the 5 bit width of the fractional delta sigma modulator is connected with the input end of an adder (ADD 1), a second output end (d frac,MSB) of the 5 bit width of the fractional delta sigma modulator is connected with the input end of an adder (ACC 1), a third output end (d frac,LSB) of the 6 bit width of the fractional delta sigma modulator is connected with the input end of a data weight average module, the 5 bit width output end of the first adder (ADD 1) is used as a scalar output end (N div) of a sampling and frequency division control signal generator, the 6 bit width output end of the adder (ACC 1) is connected with the 6 bit width input end of a second adder (ADD 2), the 1 bit width output end (N ref) of the data weight average module is connected with the 1 bit width input end of the second adder (ACD 1), the 6 bit width output end of the second adder (ADD 2) is connected with the 1 bit width output end of the second adder (ADD 2), and the output end of the output of the digital delta sigma modulator is used as a vector signal of the output of the 1 bit of the second adder (ADD 2) is connected with the output end of the input end of the digital delta sigma modulator The 64-unit vector output end of the data weight average value module is used as the first vector output end/>, of the sampling and frequency division control signal generator
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