CN102185473A - Charge pump circuit for low current mismatching and low current change - Google Patents
Charge pump circuit for low current mismatching and low current change Download PDFInfo
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- CN102185473A CN102185473A CN2011100747853A CN201110074785A CN102185473A CN 102185473 A CN102185473 A CN 102185473A CN 2011100747853 A CN2011100747853 A CN 2011100747853A CN 201110074785 A CN201110074785 A CN 201110074785A CN 102185473 A CN102185473 A CN 102185473A
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Abstract
The invention belongs to the technical field of clocks and in particular discloses a charge pump circuit structure which is based on a standard complementary metal oxide semiconductor (CMOS) process, has low current mismatching and low current change and is applicable to a charge pump type phase locked loop. The charge pump circuit consists of a current biasing circuit, a reference current circuit, an output current circuit and an amplifier. A negative feedback loop is formed by utilizing the amplifier so as to reduce mismatching of charging current and discharging current due to the voltage change at an output end; and when the voltage at the output end changes, the total change of the charging current and the discharging current is reduced by adding current with a positive output voltage coefficient and current with a negative output voltage coefficient. The charge pump circuit can effectively reduce the mismatching of the charging current and the discharging current and the current change. Meanwhile, the circuit has high speed, low power consumption and low noise.
Description
Technical field
The invention belongs to the clock technology field, be specifically related to a kind of charge pump circuit that is applicable to based on the charge pump type phaselocked loop circuit of standard CMOS process.
Background technology
Clock is as one of module that is most widely used, and its performance can directly have influence on the final properties index of system, and High Performance Charge Pumps type clock circuit all is the focus of studying in the integrated circuit all the time.The mismatch of charge pump circuit electric current directly has influence on the phase noise of clock circuit and spuious size, do not have at pll lock under the situation of locking, its major function is exactly to change the phase difference in the system into electric current output, thereby produces the effect that output voltage reaches the output frequency of adjusting voltage controlled oscillator through low pass filter again; Under the situation of pll lock, its major function is the voltage-controlled voltage effect of stablizing voltage controlled oscillator, thereby makes voltage controlled oscillator be in stable frequency output state.
Conventional charge pump circuit mainly is by increasing output impedance, reduces because output voltage changes the mismatch of dashing of causing, discharging current thereby reach, and main method has: the 1) channel length of increase efferent duct; 2) utilize cascodes; 3) utilize operational amplifier to form negative feedback loop; 4) gain bootstrap.More than the utilization of these technology reduced the mismatch that changes dashing of causing, discharging current owing to output voltage effectively, but these structures have only solved the mismatch of quiescent current, and have ignored the dynamic mismatch of electric current and the variation of electric current.
Summary of the invention
It is a kind of based on CMOS technology that main purpose of the present invention is to provide, be applicable to the charge pump circuit structure that charge pump type phaselocked loop circuit low current mismatch, low current change, dash to solve in the circuit, the mismatch of discharging current, the variation of the electric current that causes by output voltage and the dynamic mismatch of electric current.
Provided by the invention a kind of based on CMOS technology, be suitable for the charge pump construction of charge pump type phaselocked loop circuit, comprise that one has the current branch of positive output voltage coefficient and has the current branch of negative output voltage coefficient, two circuit have been formed a charge pump construction that low current mismatch, low current change, as shown in Figure 1.Two current branch link to each other by output, output is total dash electric current by
I Up1 +
I Up2 Form, total discharging current by
I Dn1 +
I Dn2 Form;
I Up1 ,
I Up2 The charging current of the charging current of first negative feedback loop and second negative feedback loop,
I Dn1 ,
I Dn2 The discharging current of the discharging current of first negative feedback loop and second negative feedback loop.
In the such scheme, by biasing circuit
I Bias Provide the most basic bias current, operational amplifier
A V1 Form first negative feedback loop with pMOS transistor MP1+ and MP2+ pipe, be used to guarantee amplifier
A V1 Positive input terminal voltage
V N1 With amplifier
A V1 Negative input end voltage
V Out Equate, to reduce its charging current
I Up1 With its discharging current
I Dn1 Between mismatch; By operational amplifier
A V2 Form second negative feedback loop with nMOS transistor MN1-and MN3-pipe, be used to guarantee amplifier
A V2 Positive input terminal voltage
V N2 With amplifier
A V2 Negative input end voltage
V Out Equate, to reduce its charging current
I Up2 With its discharging current
I Dn2 Between mismatch.
In the such scheme, since transistorized raceway groove mudulation effect, charging current
I Up1 And discharging current
I Dn1 Have positive output voltage coefficient, and charging current
I Up2 And discharging current
I Dn2 Have negative output voltage coefficient, utilize positive voltage coefficient to form total charging current towards electric current summation, thereby reduced total output towards electric current towards electric current and negative voltage coefficient
I Up1 +
I Up2 The raceway groove index of modulation; In like manner utilize positive voltage coefficient discharge stream and the addition of negative voltage coefficient discharging current to form total charging current, thereby reduced total output discharging current
I Dn1 +
I Dn2 The raceway groove index of modulation.
In the such scheme, nMOS transistor MN7+ is used for accelerating the velocity of discharge and the clock feed-through effect that reduces by transistor MP4+ of transistor MP4+ drain terminal node P+; NMOS transistor MN7-is used for accelerating the velocity of discharge and the clock feed-through effect that reduces by transistor MP4-of transistor MP4-drain terminal node P-; PMOS transistor MP7+ is used for accelerating the velocity of discharge and the clock feed-through effect that reduces by transistor MN4+ of transistor MN4+ drain terminal node N+; PMOS transistor MP7-is used for accelerating the velocity of discharge and the clock feed-through effect that reduces by transistor MN4-of transistor MN4-drain terminal node N-.
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilize the present invention, can effectively reduce dash, the mismatch of discharging current is when output end voltage changes;
2, utilize the present invention, can effectively reduce dash, the variation of discharging current is when output end voltage changes;
3, utilize the present invention, can effectively reduce the non-linear of phase difference and output current;
4, utilize the present invention, can between performances such as power consumption, noise, broadband, speed, well be compromised.
Description of drawings
Fig. 1 is the charge pump circuit with little current mismatch, electric current variation provided by the invention.
Fig. 2 is the charge pump reference current biasing circuit with positive output voltage coefficient of the present invention.
Fig. 3 has positive output voltage coefficient current circuit for charge pump provided by the invention.
Fig. 4 is the charge pump reference current biasing circuit with negative output voltage coefficient of the present invention.
Fig. 5 has negative output voltage coefficient current circuit for charge pump provided by the invention.
Embodiment
The present invention is described in more detail below in conjunction with accompanying drawing.
Fig. 1 is novel charge pump circuit figure with low current mismatch, electric current variation provided by the invention.This structure comprises two operational amplifiers
A V1 With
A V2 , generation and output voltage
V Out The charge pump current branch road, generation and the output voltage that are directly proportional
V Out The charge pump current branch road that is inversely proportional to.
V Out The charge pump current branch road that is directly proportional with
V Out The charge pump current branch road that is inversely proportional to links to each other by output, output is total dash electric current by
I Up1 +
I Up2 Form, total discharging current by
I Dn1 +
I Dn2 Form.
Fig. 2 has the charge pump reference current biasing circuit of positive output voltage coefficient for novel charge pump provided by the invention.Comprised an input current in this structure
I Bias , form by transistor MN1 and MN2.The source end of MN1 and the drain terminal of MN2 are connected, and grid are connected with drain terminal, gate voltage
V 1 For late-class circuit provides biasing; The grid of MN2 pipe link to each other with supply voltage, and the source end links to each other with ground VSS.
Fig. 3 has the charge pump Key Circuit of positive output voltage coefficient for novel charge pump provided by the invention.Comprised an operational amplifier in this structure
A V1 , reference current circuit and charge pump output current branch road.Transistor MN1+, MN2+, MP1+, MP3+ form the reference current branch road, and MN2+ pipe source end links to each other with ground VSS, and drain terminal links to each other with MN1+ source end, and the grid end links to each other with supply voltage; MN1+ drain terminal and MP1+ drain terminal and operational amplifier positive input terminal
V N1 Link to each other grid end and bias voltage
V 1 Link to each other; MP1+ source end links to each other with the MP3+ drain terminal, grid end and amplifier
A V1 Output links to each other; MP3+ source end links to each other with supply voltage VDD, and grid link to each other with ground VSS.Transistor MN3+, MN4+, MP2+, MP4+ form the output current branch road, and MN4+ pipe source end links to each other with ground VSS, and drain terminal links to each other with MN3+ source end and MP7+ drain terminal, and the grid end links to each other with control signal DN; MN3+ drain terminal and MP2+ drain terminal and operational amplifier negative input end
V Out Link to each other grid end and bias voltage
V 1 Link to each other; MP2+ source end links to each other with MP4+ drain terminal and MN7+ drain terminal, grid end and amplifier
A V1 Output links to each other; MP4+ source end links to each other with supply voltage VDD, and grid link to each other with control signal UP; MN7+ and MP7+ are the repid discharge transistor, and the MN7+ drain terminal links to each other with the MP4+ drain terminal, and grid link to each other with control voltage U P, and the source end links to each other with ground VSS; The MP7+ drain terminal links to each other with the MN4+ drain terminal, and grid link to each other with control voltage DN, and the source end links to each other with supply voltage VDD.
Fig. 4 has the charge pump reference current biasing circuit of negative output voltage coefficient for novel charge pump provided by the invention.Transistor MN5, MN6, MP5 and MP6 have been comprised in this structure.MN6 source end links to each other with ground VSS, and drain terminal links to each other with MN5 source end, and grid link to each other with supply voltage VDD; MN5 grid end and voltage
V 1 Link to each other, drain terminal links to each other with the drain terminal of MP5; The grid of MP5 pipe are connected with drain terminal, gate source voltage
V 2 For late-class circuit provides biasing; The grid of MP6 pipe link to each other with ground VSS, and the source end links to each other with supply voltage VDD.
Fig. 5 has the charge pump Key Circuit of negative output voltage coefficient for novel charge pump provided by the invention.Comprised an operational amplifier in this structure
A V2 , reference current circuit and charge pump output current branch road.Transistor MN1-, MN2-, MP1-, MP3-form the reference current branch road, and MN2-pipe source end links to each other with ground VSS, and drain terminal links to each other with MN1-source end, and the grid end links to each other with supply voltage; MN1-drain terminal and MP1-drain terminal and operational amplifier
A V2 Positive input terminal
V N2 Link to each other grid end and operational amplifier
A V2 Output links to each other; MP1-source end links to each other with the MP3-drain terminal, grid end and bias voltage
V 2 Link to each other; MP3-source end links to each other with supply voltage VDD, and grid link to each other with ground VSS.Transistor MN3-, MN4-, MP2-, MP4-form the output current branch road, and MN4-pipe source end links to each other with ground VSS, and drain terminal links to each other with MN3-source end and MP7-drain terminal, and the grid end links to each other with control signal DN; MN3-drain terminal and MP2-drain terminal and operational amplifier
A V2 Negative input end
V Out Link to each other grid end and operational amplifier
A V2 Output links to each other; MP2-source end links to each other with MP4-drain terminal and MN7-drain terminal, grid end and bias voltage
V 2 Link to each other; MP4-source end links to each other with supply voltage VDD, and grid link to each other with control signal UP; MN7-and MP7-are the repid discharge transistor, and the MN7-drain terminal links to each other with the MP4-drain terminal, and grid link to each other with control voltage U P, and the source end links to each other with ground VSS; The MP7-drain terminal links to each other with the MN4-drain terminal, and grid link to each other with control voltage DN, and the source end links to each other with supply voltage VDD.
Claims (5)
1. the charge pump circuit that changes of the low current mismatch of a suitable charge pump type phaselocked loop circuit, low current, it is characterized in that, this circuit structure comprises a current circuit that has the current circuit of positive output voltage coefficient and have the negative output voltage coefficient, and two current circuits are formed the charge pump construction of a low current mismatch, low current variation; Two current branch link to each other by output, output is total dash electric current by
I Up1 +
I Up2 Form, total discharging current by
I Dn1 +
I Dn2 Form; Wherein,
I Up1 ,
I Up2 Be respectively the charging current of first negative feedback loop and the charging current of second negative feedback loop,
I Dn1 ,
I Dn2 Be respectively the discharging current of first negative feedback loop and the discharging current of second negative feedback loop;
Provide the most basic bias current by biasing circuit; By first operational amplifier
A V1 Form first negative feedback loop with a pMOS transistor MP1+ and the 2nd MP2+ pipe, be used to guarantee first operational amplifier
A V1 Positive input terminal voltage
V N1 With first operational amplifier
A V1 Negative input end voltage
V Out Equate, to reduce its charging current
I Up1 With its discharging current
I Dn1 Between mismatch; By second operational amplifier
A V2 Form second negative feedback loop with a nMOS transistor MN1-and the 2nd nMOS transistor MN3-pipe, be used to guarantee second operational amplifier
A V2 Positive input terminal voltage
V N2 With second operational amplifier
A V2 Negative input end voltage
V Out Equate, to reduce its charging current
I Up2 With its discharging current
I Dn2 Between mismatch;
Charging current with positive output voltage coefficient
I Up1 With charging current with negative output voltage coefficient
I Up2 Total output current is formed in addition, thereby always reduces the output voltage coefficient towards the electric current electric current;
Discharging current with positive output voltage coefficient
I Dn1 With discharging current with negative output voltage coefficient
I Dn2 Total output current is formed in addition, thereby reduces the output voltage coefficient of total discharging current.
2. charge pump circuit according to claim 1 is characterized in that having the charge pump reference current biasing circuit of negative output voltage coefficient; This biasing circuit comprises an input current
I Bias , form by the first transistor MN1 and transistor seconds MN2; The source end of the first transistor MN1 is connected with the drain terminal of transistor seconds MN2, and the grid of the first transistor MN1 are connected with drain terminal, the first transistor MN1 gate voltage
V 1 For late-class circuit provides biasing; The grid of transistor seconds MN2 link to each other with supply voltage, and the source end links to each other with ground VSS.
3. charge pump circuit according to claim 2 is characterized in that described current circuit with positive output voltage coefficient, comprises one first operational amplifier
A V1 , first reference current circuit and the charge pump first output current branch road; Transistor MN1+, transistor MN2+, transistor MP1+, transistor MP3+ form first reference current circuit; Transistor MN2+ pipe source end links to each other with ground VSS, and transistor MN2+ pipe drain terminal links to each other with transistor MN1+ source end, and transistor MN2+ pipe grid end links to each other with supply voltage; Transistor MN1+ drain terminal and transistor MP1+ drain terminal and the first operational amplifier positive input terminal
V N1 Link to each other transistor MN1+ grid end and bias voltage
V 1 Link to each other; Transistor MP1+ source end links to each other with transistor MP3+ drain terminal, transistor MP1+ grid end and amplifier
A V1 Output links to each other; Transistor MP3+ source end links to each other with supply voltage VDD, and transistor MP3+ grid link to each other with ground VSS; Transistor MN3+, transistor MN4+, transistor MP2+, transistor MP4+ form the first output current branch road; Transistor MN4+ pipe source end links to each other with ground VSS, and transistor MN4+ drain terminal links to each other with transistor MN3+ source end and transistor MP7+ drain terminal, and transistor MN4+ grid end links to each other with control signal DN; Transistor MN3+ drain terminal and transistor MP2+ drain terminal and the first operational amplifier negative input end
V Out Link to each other transistor MN3+ grid end and bias voltage
V 1 Link to each other; Transistor MP2+ source end links to each other with transistor MP4+ drain terminal and transistor MN7+ drain terminal, the transistor MP2+ grid end and first operational amplifier
A V1 Output links to each other; Transistor MP4+ source end links to each other with supply voltage VDD, and transistor MP4+ grid link to each other with control signal UP; Transistor MN7+ and transistor MP7+ are the repid discharge transistor, and transistor MN7+ drain terminal links to each other with transistor MP4+ drain terminal, and transistor MN7+ grid link to each other with control voltage U P, and transistor MN7+ source end links to each other with ground VSS; Transistor MP7+ drain terminal links to each other with transistor MN4+ drain terminal, and transistor MP7+ grid link to each other with control voltage DN, and transistor MP7+ source end links to each other with supply voltage VDD.
4. charge pump circuit according to claim 3 is characterized in that having the charge pump reference current biasing circuit of negative output voltage coefficient, and this circuit comprises transistor MN5, transistor MN6 transistor, MP5 and transistor MP6; Transistor MN6 source end links to each other with ground VSS, and transistor MN6 drain terminal links to each other with transistor MN5 source end, and transistor MN6 grid link to each other with supply voltage VDD; Transistor MN5 grid end and voltage
V 1 Link to each other, transistor MN5 drain terminal links to each other with the drain terminal of transistor MP5; The grid of transistor MP5 are connected with drain terminal, transistor MP5 gate source voltage
V 2 For late-class circuit provides biasing; The grid of transistor MP6 link to each other with ground VSS, and transistor MP6 source end links to each other with supply voltage VDD.
5. charge pump circuit according to claim 4 is characterized in that described current circuit with negative output voltage coefficient, comprises one second operational amplifier
A V2 , second reference current circuit and the charge pump second output current branch road; Wherein, transistor MN1-, transistor MN2-, transistor MP1-, transistor MP3-form second reference current circuit, transistor MN2-pipe source end links to each other with ground VSS, and transistor MN2-drain terminal links to each other with transistor MN1-source end, and transistor MN2-grid end links to each other with supply voltage; Transistor MN1-drain terminal and transistor MP1-drain terminal and second operational amplifier
A V2 Positive input terminal
V N2 Link to each other the transistor MN1-grid end and second operational amplifier
A V2 Output links to each other; Transistor MP1-source end links to each other with transistor MP3-drain terminal, transistor MP1-grid end and bias voltage
V 2 Link to each other; Transistor MP3-source end links to each other with supply voltage VDD, and transistor MP3-grid link to each other with ground VSS; Transistor MN3-, transistor MN4-, transistor MP2-, transistor MP4-form the second output current branch road; Transistor MN4-pipe source end links to each other with ground VSS, and transistor MN4-drain terminal links to each other with transistor MN3-source end and transistor MP7-drain terminal, and transistor MN4-grid end links to each other with control signal DN; Transistor MN3-drain terminal and transistor MP2-drain terminal and second operational amplifier
A V2 Negative input end
V Out Link to each other the transistor MN3-grid end and second operational amplifier
A V2 Output links to each other; Transistor MP2-source end links to each other with transistor MP4-drain terminal and transistor MN7-drain terminal, transistor MP2-grid end and bias voltage
V 2 Link to each other; Transistor MP4-source end links to each other with supply voltage VDD, and transistor MP4-grid link to each other with control signal UP; Transistor MP4-and transistor MP7-are the repid discharge transistor, and transistor MN7-drain terminal links to each other with transistor MP4-drain terminal, and transistor MN7-grid link to each other with control voltage U P, and transistor MN7-source end links to each other with ground VSS; Transistor MP7-drain terminal links to each other with transistor MN4-drain terminal, and transistor MP7-grid link to each other with control voltage DN, and transistor MP7-source end links to each other with supply voltage VDD.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100747853A CN102185473A (en) | 2011-03-28 | 2011-03-28 | Charge pump circuit for low current mismatching and low current change |
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| CN2011100747853A CN102185473A (en) | 2011-03-28 | 2011-03-28 | Charge pump circuit for low current mismatching and low current change |
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| CN2011100747853A Pending CN102185473A (en) | 2011-03-28 | 2011-03-28 | Charge pump circuit for low current mismatching and low current change |
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Cited By (11)
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| CN102710124A (en) * | 2012-06-19 | 2012-10-03 | 电子科技大学 | Charge pump circuit |
| CN102739043A (en) * | 2012-06-19 | 2012-10-17 | 电子科技大学 | Charge pump circuit |
| CN103036423A (en) * | 2012-12-12 | 2013-04-10 | 电子科技大学 | Charge pump circuit used for phase-locked loop |
| CN103490626A (en) * | 2013-09-30 | 2014-01-01 | 中国科学技术大学 | Charge pump based on shunt feedback |
| WO2014090136A1 (en) * | 2012-12-12 | 2014-06-19 | 电子科技大学 | Charge pump circuit used for charge pump phase-locked loop |
| CN104201880A (en) * | 2014-07-15 | 2014-12-10 | 浙江大学 | Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop |
| CN105144558A (en) * | 2013-04-25 | 2015-12-09 | 三菱电机株式会社 | Charge pump circuit |
| CN106100321A (en) * | 2016-07-18 | 2016-11-09 | 东南大学 | A kind of complementary feedback formula gate switch charge pump circuit |
| WO2018223622A1 (en) * | 2017-06-08 | 2018-12-13 | 尚睿微电子（上海）有限公司 | Control circuit, bias circuit, and control method |
| CN112504494A (en) * | 2020-12-02 | 2021-03-16 | 中国科学院上海高等研究院 | Ultra-low power consumption CMOS temperature sensing circuit |
| CN112910255A (en) * | 2021-01-29 | 2021-06-04 | 西安交通大学 | Charge pump circuit with low current mismatch |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710124B (en) * | 2012-06-19 | 2015-06-17 | 电子科技大学 | Charge pump circuit |
| CN102739043A (en) * | 2012-06-19 | 2012-10-17 | 电子科技大学 | Charge pump circuit |
| CN102739043B (en) * | 2012-06-19 | 2014-10-15 | 电子科技大学 | Charge pump circuit |
| CN102710124A (en) * | 2012-06-19 | 2012-10-03 | 电子科技大学 | Charge pump circuit |
| CN103036423A (en) * | 2012-12-12 | 2013-04-10 | 电子科技大学 | Charge pump circuit used for phase-locked loop |
| US9419631B2 (en) | 2012-12-12 | 2016-08-16 | University Of Electronic Science And Technology Of China | Charge pump circuit used for charge pump phase-locked loop |
| WO2014090136A1 (en) * | 2012-12-12 | 2014-06-19 | 电子科技大学 | Charge pump circuit used for charge pump phase-locked loop |
| CN105144558A (en) * | 2013-04-25 | 2015-12-09 | 三菱电机株式会社 | Charge pump circuit |
| CN105144558B (en) * | 2013-04-25 | 2018-06-15 | 三菱电机株式会社 | Charge pump circuit |
| CN103490626A (en) * | 2013-09-30 | 2014-01-01 | 中国科学技术大学 | Charge pump based on shunt feedback |
| CN104201880A (en) * | 2014-07-15 | 2014-12-10 | 浙江大学 | Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop |
| CN104201880B (en) * | 2014-07-15 | 2016-08-24 | 浙江大学 | The low current mismatch charge pump circuit of anti-process fluctuation under phaselocked loop low-voltage |
| CN106100321A (en) * | 2016-07-18 | 2016-11-09 | 东南大学 | A kind of complementary feedback formula gate switch charge pump circuit |
| CN106100321B (en) * | 2016-07-18 | 2018-06-15 | 东南大学 | A kind of complementary feedback formula gate switch charge pump circuit |
| WO2018223622A1 (en) * | 2017-06-08 | 2018-12-13 | 尚睿微电子（上海）有限公司 | Control circuit, bias circuit, and control method |
| CN112504494A (en) * | 2020-12-02 | 2021-03-16 | 中国科学院上海高等研究院 | Ultra-low power consumption CMOS temperature sensing circuit |
| CN112910255A (en) * | 2021-01-29 | 2021-06-04 | 西安交通大学 | Charge pump circuit with low current mismatch |
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Application publication date: 20110914 |