CN110176927A - The digital pulse-width modulator being made of segmented speed delay chain and single delay phase-locked loop - Google Patents
The digital pulse-width modulator being made of segmented speed delay chain and single delay phase-locked loop Download PDFInfo
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- CN110176927A CN110176927A CN201910408469.1A CN201910408469A CN110176927A CN 110176927 A CN110176927 A CN 110176927A CN 201910408469 A CN201910408469 A CN 201910408469A CN 110176927 A CN110176927 A CN 110176927A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of digital pulse-width modulators being made of segmented speed delay chain and single delay phase-locked loop, for solving the low technical problem of existing digital pulse-width modulator conversion accuracy.Technical solution is can to reduce the frequency of external input clock while improving DPWM resolution ratio using the bulk delay chain of fast, slow two sections of delay chain built-up circuits, and reduce the power consumption and area overhead of circuit.The single delay phase-locked loop comprising bulk delay chain is added, form closed loop feedback control mechanism, inhibit the delay time of each delay cell with the drift of manufacturing process, supply voltage and operating temperature, to improve the delay time precision of delay cell in fast, slow delay chain, and then the conversion accuracy of DPWM is improved, while reducing circuit complexity.The present invention has the characteristics that external input clock frequency is low, circuit structure is simple, resolution ratio and conversion accuracy are high, power consumption and area are small, is particularly suitable in digital control DC-DC switch converters.
Description
Technical field
The present invention relates to a kind of digital pulse-width modulator, more particularly to one kind by segmented speed delay chain with individually prolong
The digital pulse-width modulator that slow phaselocked loop is constituted.
Background technique
Referring to Fig. 6.The analog output voltage v of digital control DC-DC switch converters load end0(t) number is converted to through ADC
Word output quantity v0[n], then by v0[n] and reference voltage vrefError signal e [n] between [n] is sent into digital voltage compensator.
In digital voltage compensator, number duty cycle signals d [n] is generated using specific digital control algorithm (such as pid algorithm),
Then number duty cycle signals d [n] simulation is converted to through DPWM (Digital Pulse Width Modulation) to account for
Sky is than signal d (t), most afterwards through driving the on and off of buffer (Buffer) control switch pipe G, to adjust output voltage v0
(t) stablize it in reference voltage value.
For digital control DC-DC switch converters, in order to reduce the steady-state error of output voltage, to improve output electricity
The control precision of pressure needs to realize the sampling and digitlization to output voltage using high-resolution ADC.Meanwhile in order to avoid
Limit Cycle Phenomena occurs in control loop, it is desirable that the digit of digital pulse-width modulator (DPWM) is greater than the digit of ADC.Therefore,
When designing digital control DC-DC switch converters, need using high-resolution DPWM.
The conventional circuit structure for realizing DPWM includes counter-comparator mixed structure, delay-line structure, sigma-delta modulation
Device structure etc..When counter-comparator mixed structure realizes high-resolution DPWM, the external input clock using high frequency is needed
Signal, this will lead to the rising of system overall power.When delay-line structure realizes high-resolution DPWM, it is desirable that high-precision delay
Unit and large-scale delay chain circuits, so that the power consumption of circuit and area significantly increase.DPWM based on sigma-delta modulator,
Due to circuit structure complexity, again such that the power consumption of circuit and area increase.
Document " Digitally Controlled Single-inductor Multiple-output Synchronous
DC-DC Boost Converter with Smooth Loop Handover Using 55nm Process, Journal of
One kind is proposed in Power Electronics, Vol.17, No.3, pp.821-834, May 2017 " only to be postponed by segmented
The DPWM structure of chain composition, has the advantages that circuit structure is simple, working frequency is lower.But due to the segmentation in the structure
Formula delay chain is in open loop situations, and no feed-back regulatory mechanism, the delay time of delay cell is with manufacturing process, supply voltage
It drifts about with operating temperature, the conversion accuracy of DPWM is caused to reduce.
Summary of the invention
In order to overcome the shortcomings of that existing digital pulse-width modulator conversion accuracy is low, the present invention provides one kind by segmented speed
The digital pulse-width modulator that delay chain and single delay phase-locked loop are constituted.The modulator forms electricity using fast, slow two sections of delay chains
The bulk delay chain on road can reduce the frequency of external input clock, and reduce the function of circuit while improving DPWM resolution ratio
Consumption and area overhead.The single delay phase-locked loop (DLL:Delay locked Loop) comprising bulk delay chain is added, formation is closed
Ring feedback control mechanism inhibits the delay time of each delay cell with the drift of manufacturing process, supply voltage and operating temperature, with
The delay time precision of delay cell in fast, slow delay chain is improved, and then improves the conversion accuracy of DPWM, while it is multiple to reduce circuit
Miscellaneous degree.Therefore, compared with prior art, DPWM circuit structure of the present invention is low with external input clock frequency, circuit structure is simple
Single, resolution ratio and the feature that conversion accuracy is high, power consumption and area are small, are particularly suitable in digital control DC-DC switch converters.
The technical solution adopted by the present invention to solve the technical problems is: it is a kind of by segmented speed delay chain with individually prolong
The digital pulse-width modulator that slow phaselocked loop is constituted, its main feature is that being selected by delay phase-locked loop DLL, fast delay chain, slow delay chain, multichannel
Device MUX1, multiple selector MUX2, impulse generator PGT1, impulse generator PGT2 and rest-set flip-flop is selected to constitute.The ginseng of input
It examines after clock signal clk_ref passes sequentially through fast delay chain and slow delay chain, output clock signal clk_out is connected to delay locking phase
One of input terminal of ring DLL.Reference clock signal clk_ref is connected to another input terminal of delay phase-locked loop DLL simultaneously.
In the inside of delay phase-locked loop DLL, after phase discriminator PD, charge pump CP and low-pass filter LP, control voltage V is generatedc, Vc
It is connected to the control terminal of fast delay chain and slow delay chain simultaneously, as two clock signal clk_out for being input to delay phase-locked loop DLL
When identical with the phase of clk_ref, delay phase-locked loop DLL is in the lock state.Each fast delay cell and slow delay cell
Output one tap of termination, generates multi-phase delay clock signal, and each tap is respectively connected to multiple selector MUX1 and multichannel choosing
Select the input terminal of device MUX2.The n-bit number duty cycle signals D [n-1:0] of input be divided into high power and position data DH [n-1:n/2] and
Low power and position data DL [n/2-1:0] two parts.DH [n-1:n/2] and DL [n/2-1:0] controls slow delay chain and fast delay respectively
The output of the multiple selector MUX1 and multiple selector MUX2 of chain, multiple selector MUX1 and multiple selector MUX2 are produced respectively
Raw output signal MUX1_out and MUX2_out, are respectively outputted to impulse generator PGT1 and impulse generator PGT2.Pulse hair
Raw device PGT1 and impulse generator PGT2 generates output signal PGT1_out and PGT2_out respectively, resets to rest-set flip-flop
And set operation, the output signal of rest-set flip-flop is the output signal of DPWM.
The beneficial effects of the present invention are: the modulator utilizes the bulk delay chain of fast, slow two sections of delay chain built-up circuits,
While improving DPWM resolution ratio, the frequency of external input clock can be reduced, and reduce the power consumption and area overhead of circuit.It is added
Single delay phase-locked loop (DLL:Delay locked Loop) comprising bulk delay chain forms closed loop feedback control mechanism, suppression
The delay time of each delay cell is made with the drift of manufacturing process, supply voltage and operating temperature, to improve in fast, slow delay chain
The delay time precision of delay cell, and then the conversion accuracy of DPWM is improved, while reducing circuit complexity.Therefore, with it is existing
Technology is compared, and DPWM circuit structure of the present invention is low with external input clock frequency, circuit structure is simple, resolution ratio and conversion are smart
The feature that degree is high, power consumption and area are small, is particularly suitable in digital control DC-DC switch converters.
It elaborates with reference to the accompanying drawings and detailed description to the present invention.
Detailed description of the invention
Fig. 1 is the electricity for the digital pulse-width modulator that the present invention is made of segmented speed delay chain and single delay phase-locked loop
Line structure figure.
Fig. 2 is the particular circuit configurations figure for the impulse generator that the present invention uses.
Fig. 3 is the timing diagram example of digital pulse-width modulator circuit of the present invention.
Fig. 4 is the simulation result of relationship between digital pulse-width modulator input data of the present invention and output pulse duty factor.
When Fig. 5 is no DLL the input data of digital pulse-width modulator and output pulse duty factor between relationship emulation knot
Fruit.
Fig. 6 is the structure principle chart of the digital control DC-DC switch converters of background technique.
Specific embodiment
Following embodiment is referring to Fig.1~5.
The digital pulse-width modulator that the present invention is made of segmented speed delay chain and single delay phase-locked loop is postponed by 1
Phaselocked loop (DLL), 1 fast delay chain, 1 slow delay chain, 2 multiple selector (MUX1, MUX2), 2 impulse generators
(PGT1, PGT2) and 1 rest-set flip-flop are constituted.The reference clock signal clk_ref of input passes sequentially through fast delay chain and prolongs slowly
After slow chain, the output clock signal clk_out finally obtained is connected to one of input terminal of DLL.Reference clock signal clk_
Ref is connected to another input terminal of DLL simultaneously.In the inside of DLL, by phase discriminator (PD), charge pump (CP) and low-pass filtering
After device (LP), control voltage V is generatedc, VcIt is connected to the control terminal of fast delay chain and slow delay chain simultaneously, it is single to adjust each delay
The delay time of member, finally when be input to the phase of two clock signal clk_out and clk_ref of DLL it is identical when, at DLL
In lock state.The output of each fast delay cell and slow delay cell terminates a tap, generates multi-phase delay clock signal, often
A tap is respectively connected to the input terminal of two multiple selector MUX1 and MUX2.The n-bit number duty cycle signals D of input
[n-1:0] is divided into high power and position data DH [n-1:n/2] and low power and position data DL [n/2-1:0] two parts.DH [n-1:n/2] and DL
[n/2-1:0] controls the output of the multiple selector MUX1 and MUX2 of slow delay chain and fast delay chain, multiple selector respectively
MUX1 and MUX2 generates output signal MUX1_out and MUX2_out respectively, is respectively outputted to impulse generator PGT1 and PGT2.
Impulse generator PGT1 and PGT2 generate output signal PGT1_out and PGT2_out respectively, are resetted and are set to rest-set flip-flop
Bit manipulation.The output signal of rest-set flip-flop is the output signal of DPWM.
In order to improve the resolution ratio and conversion accuracy of DPWM, the bulk delay of fast, slow two sections of delay chain built-up circuits is utilized
Chain, and the single delay phase-locked loop (DLL) comprising the bulk delay chain is utilized, closed loop feedback control mechanism is formed, inhibition is respectively prolonged
The delay time of slow unit with the drift of manufacturing process, supply voltage and operating temperature, postpones list to improve in fast, slow delay chain
The delay time precision of member, and then improve the conversion accuracy of DPWM.Therefore, the present invention has external input clock frequency low, electric
Line structure is simple, resolution ratio and conversion accuracy is high, power consumption and area are small feature, is particularly suitable for digital control DC-DC switch
In converter.
The working principle of DPWM of the present invention.Assuming that the switch periods of digital control DC-DC switch converters are Tsw, switch frequency
Rate fsw=1/Tsw, the digital duty cycle signals of input are n-bit, and n is even number.It is assumed that slow delay chain is by (2n/2- 1) a to prolong slowly
The delay time of slow unit composition, each slow delay cell is Δ t1, fast delay chain is by 2n/2A fast delay cell composition, each
The delay time of fast delay cell is Δ t0。Δt0With Δ t1Between meet following relationship:
Δt1=2n/2×Δt0 (1)
Switch periods TswRelationship between the delay time of delay cell are as follows:
Tsw=2n/2×Δt0+(2n/2-1)×Δt1=2n/2×Δt1 (2)
In addition, in DLL, since fast delay cell and slow delay cell use the same control voltage Vc, fast, slow delay
The delay of unit/voltage control coefrficient Δ t0/ΔVc、Δt1Following relationship (in linear region) should be met between/Δ Vc:
The clock signal clk_ref being input from the outside is successively through too fast delay chain and slow delay chain, each fast delay cell
Output with slow delay cell terminates a tap, generates multi-phase delay clock signal, and each tap is respectively connected to two multichannels
The input terminal of selector MUX1 and MUX2.
For the sake of easy analysis, it is assumed here that DH_code and DL_code is high power and position data DH [n-1:n/2] respectively
The corresponding decimal value with low power and position data DL [n/2-1:0].For DPWM output analog pulse signal, high level
Duration ThighIt can be calculated by following formula:
Thigh=(DH_code+1) × Δ t1-(2n/2-DL_code)×Δt0 (4)
By formula (4) it is found that the delay chain tap direction that MUX1 and MUX2 chooses is precisely opposite.That is, fast delay chain
First output tap be connected to the 2nd of multiple selector MUX2n/2- No. 1 input, second output tap of fast delay chain connect
To the 2nd of multiple selector MUX2 then/2- No. 2 inputs, the connection and so on of remaining output tap.And first of slow delay chain
Output tap is connected in No. 0 input of multiple selector MUX1, and second output tap is connected to the 1st of multiple selector MUX1
Number input on, remaining output tap connection and so on.
In order to improve the precision of DPWM output signal duty ratio, the entire delay that will be made of fast delay chain and slow delay chain
It is linked in the closed feedback loop of delay phase-locked loop (DLL), when delay phase-locked loop is in the lock state, fast delay chain and slow
The delay of each delay cell in delay chain is equal, and the delay size between fast delay cell and slow delay cell meets
Relationship shown in formula (1).
The output end of multiple selector MUX1 and MUX2 meet impulse generator a PGT1 and PGT2 respectively.Impulse generator
Under the rising edge excitation of multiple selector output signal, the relatively narrow pulse signal of pulsewidth is generated, it is therefore intended that prevent more
The waveform of road selector output enters rest-set flip-flop dead zone.The particular circuit configurations of impulse generator are as shown in Fig. 2.Pulse hair
The output signal of raw device PGT1 and PGT2 are connected respectively to the reset terminal and set end of rest-set flip-flop, to realize to rest-set flip-flop
Reset and set.The output signal of rest-set flip-flop is the output signal of DPWM, the digital duty ratio of duty ratio and input at
Proportionate relationship.
Attached drawing 3 gives the timing diagram example of DPWM circuit proposed by the present invention.Attached drawing 4 gives proposed by the present invention
Simulation result (the simulated conditions: switch frequency of relationship between input data D [n-1:0] and DPWM the output pulse duty factor of DPWM
Rate fsw=2MHz, resolution ratio n=8, duty cycle range are limited to 10%~90%), in Fig. 4, " linear line " indicates DPWM
Input data and output pulse duty factor between ideal relationship, " typical ", " worst ", " best " respectively indicate manufacture
Technique, the representative value of supply voltage and operating temperature, worst-case value, best values.It can be acquired by Fig. 4, export the reality of pulse duty factor
Maximum deviation between actual value and ideal value is 0.5%.In order to be compared with the prior art, when giving no DLL in attached drawing 5
The simulation result of relationship, simulated conditions are same as above between input data D [n-1:0] and DPWM the output pulse duty factor of DPWM.From
Attached drawing 5 can acquire, and exporting the maximum deviation between the actual value of pulse duty factor and ideal value is 21%.Obviously, with existing skill
Art is compared, and the conversion accuracy of DPWM circuit proposed by the present invention is significantly improved.
Claims (1)
1. a kind of digital pulse-width modulator being made of segmented speed delay chain and single delay phase-locked loop, it is characterised in that:
By delay phase-locked loop DLL, fast delay chain, slow delay chain, multiple selector MUX1, multiple selector MUX2, impulse generator
PGT1, impulse generator PGT2 and rest-set flip-flop are constituted；The reference clock signal clk_ref of input pass sequentially through fast delay chain and
After slow delay chain, output clock signal clk_out is connected to one of input terminal of delay phase-locked loop DLL；Reference clock signal
Clk_ref is connected to another input terminal of delay phase-locked loop DLL simultaneously；In the inside of delay phase-locked loop DLL, by phase discriminator
After PD, charge pump CP and low-pass filter LP, control voltage V is generatedc, VcIt is connected to the control of fast delay chain and slow delay chain simultaneously
End, when be input to the phase of two clock signal clk_out and clk_ref of delay phase-locked loop DLL it is identical when, delay phase-locked loop
DLL is in the lock state；The output of each fast delay cell and slow delay cell terminates a tap, generates multi-phase delay clock letter
Number, each tap is respectively connected to the input terminal of multiple selector MUX1 and multiple selector MUX2；The n-bit number of input accounts for
Sky is divided into high power and position data DH [n-1:n/2] and low power and position data DL [n/2-1:0] two parts than signal D [n-1:0]；DH[n-
1:n/2] and DL [n/2-1:0] control the multiple selector MUX1 and multiple selector MUX2 of slow delay chain and fast delay chain respectively
Output, multiple selector MUX1 and multiple selector MUX2 generate output signal MUX1_out and MUX2_out respectively, respectively
It is output to impulse generator PGT1 and impulse generator PGT2；Impulse generator PGT1 and impulse generator PGT2 generates defeated respectively
Signal PGT1_out and PGT2_out out reset to rest-set flip-flop and set operation, the output signal of rest-set flip-flop is
The output signal of DPWM.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111865300A (en) * | 2020-07-08 | 2020-10-30 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
| CN112104342A (en) * | 2020-09-01 | 2020-12-18 | 西北工业大学 | High-precision digital pulse width modulator composed of counter and fast and slow delay chain |
| JP2023515232A (en) * | 2020-03-12 | 2023-04-12 | 湖南轂梁微電子有限公司 | ULTRA-HIGH PRECISION DIGITAL PULSE SIGNAL GENERATION CIRCUIT AND METHOD |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1636904A1 (en) * | 2003-06-11 | 2006-03-22 | Koninklijke Philips Electronics N.V. | High resolution pwm generator or digitally controlled oscillator |
| US7439787B2 (en) * | 2006-07-27 | 2008-10-21 | Freescale Semiconductor, Inc. | Methods and apparatus for a digital pulse width modulator using multiple delay locked loops |
| US20090009224A1 (en) * | 2007-07-06 | 2009-01-08 | Gyh-Bin Wang | Multiphase DLL using 3-edge phase detector for wide-range operation |
| CN101657959A (en) * | 2007-03-16 | 2010-02-24 | 爱萨有限公司 | Digital pulse width modulator based on asymmetric self-oscillation circuit |
| CN101711457A (en) * | 2007-02-28 | 2010-05-19 | 爱萨有限公司 | Universal and fault tolerant multi-phase digital PWM controller for high frequency DC-DC converters |
| CN102197597A (en) * | 2008-10-31 | 2011-09-21 | 爱萨有限公司 | Multi-channel digital pulse width modulator (DPWM) |
| CN102832914A (en) * | 2012-09-17 | 2012-12-19 | 电子科技大学 | Digital pulse width modulator circuit |
| CN104242921A (en) * | 2014-09-30 | 2014-12-24 | 山东华芯半导体有限公司 | High-frequency delay-locked loop (DLL) and clock processing method thereof |
| CN207720116U (en) * | 2018-02-09 | 2018-08-10 | 南华大学 | A kind of digital delay phase-locked loop of quick lock in |
-
2019
- 2019-05-16 CN CN201910408469.1A patent/CN110176927A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1636904A1 (en) * | 2003-06-11 | 2006-03-22 | Koninklijke Philips Electronics N.V. | High resolution pwm generator or digitally controlled oscillator |
| US7439787B2 (en) * | 2006-07-27 | 2008-10-21 | Freescale Semiconductor, Inc. | Methods and apparatus for a digital pulse width modulator using multiple delay locked loops |
| CN101711457A (en) * | 2007-02-28 | 2010-05-19 | 爱萨有限公司 | Universal and fault tolerant multi-phase digital PWM controller for high frequency DC-DC converters |
| CN101657959A (en) * | 2007-03-16 | 2010-02-24 | 爱萨有限公司 | Digital pulse width modulator based on asymmetric self-oscillation circuit |
| US20090009224A1 (en) * | 2007-07-06 | 2009-01-08 | Gyh-Bin Wang | Multiphase DLL using 3-edge phase detector for wide-range operation |
| CN102197597A (en) * | 2008-10-31 | 2011-09-21 | 爱萨有限公司 | Multi-channel digital pulse width modulator (DPWM) |
| CN102832914A (en) * | 2012-09-17 | 2012-12-19 | 电子科技大学 | Digital pulse width modulator circuit |
| CN104242921A (en) * | 2014-09-30 | 2014-12-24 | 山东华芯半导体有限公司 | High-frequency delay-locked loop (DLL) and clock processing method thereof |
| CN207720116U (en) * | 2018-02-09 | 2018-08-10 | 南华大学 | A kind of digital delay phase-locked loop of quick lock in |
Non-Patent Citations (3)
| Title |
|---|
| HOU SIJIAN: "A Monolithic High Frequency Digitally Controlled Buck Converter in", 《2010 10TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY》 * |
| HUEY CHIAN FOONG: "A Supply and Process-Insensitive 12-Bit DPWM for Digital DC-DC Converters", 《 2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS》 * |
| 宋慧滨: "基于延迟锁定环技术的数字脉宽调制器的设计与实现", 《电子器件》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023515232A (en) * | 2020-03-12 | 2023-04-12 | 湖南轂梁微電子有限公司 | ULTRA-HIGH PRECISION DIGITAL PULSE SIGNAL GENERATION CIRCUIT AND METHOD |
| JP7362169B2 (en) | 2020-03-12 | 2023-10-17 | 湖南轂梁微電子有限公司 | Ultra-high precision digital pulse signal generation circuit and method |
| CN111865300A (en) * | 2020-07-08 | 2020-10-30 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
| CN111865300B (en) * | 2020-07-08 | 2022-05-17 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
| CN112104342A (en) * | 2020-09-01 | 2020-12-18 | 西北工业大学 | High-precision digital pulse width modulator composed of counter and fast and slow delay chain |
| CN112104342B (en) * | 2020-09-01 | 2023-06-23 | 西北工业大学 | High-precision digital pulse width modulator composed of counter and fast and slow delay chain |
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