CN113626356B

CN113626356B - Circuit structure of host chip for realizing serial interface full duplex communication

Info

Publication number: CN113626356B
Application number: CN202010371706.4A
Authority: CN
Inventors: 刘欣洁; 华纯; 华晶; 李亚菲; 徐佰新
Original assignee: CRM ICBG Wuxi Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2020-05-06
Filing date: 2020-05-06
Publication date: 2023-07-21
Anticipated expiration: 2040-05-06
Also published as: CN113626356A

Abstract

The invention relates to a circuit structure of a host chip for realizing full duplex communication of a serial interface, wherein the circuit decodes an external-to-internal serial data input signal SDI_I generated through a serial data input PAD port through an input clock signal SCK_I generated through a bidirectional clock signal input and output PAD port, and ensures that the phase of the communication clock signal SCK is consistent with the phase of a serial data output signal SDO output by the serial data output PAD port so as to ensure that the problem of sampling/shifting errors caused by time delay of the bidirectional PAD port is avoided. The host chip adopting the structure has the characteristics of high information transmission accuracy, excellent performance and low cost, and has wide adaptability.

Description

Circuit structure of host chip for realizing serial interface full duplex communication

Technical Field

The invention relates to the field of communication, in particular to the field of synchronous transmission of serial interfaces, in particular to a circuit structure of a host chip for realizing full duplex communication of the serial interfaces.

Background

Serial communication is one of the communication modes of a computer, and mainly plays a role in data transmission between a host or a slave and a peripheral. Serial communication has the characteristics of few transmission lines and low cost.

If the serial interface is to achieve high-speed transmission rate and transmission efficiency, full duplex and clock synchronous communication modes are adopted, and master and slave modes are supported to work. The chip pins only occupy serial data lines and synchronous clock lines, are connected with an external device through 3 pins, and the 3 pins are respectively used for transmitting serial data input signals SDI, serial data output signals SDO and communication clock signals SCK, and in some cases, one pin for transmitting a chip selection signal CS is added.

The interface of the host chip can provide a communication clock signal SCK for the external slave device; the chip select signal CS is used to control whether the corresponding interface of the external slave device is selected. The communication timing synchronized with the communication clock signal SCK is very simple, that is, under the control of the host communication clock signal SCK, the serial data input signal SDI and the serial data output signal SDO on the two bidirectional shift data lines exchange synchronous data, and the rising edge of the communication clock signal SCK corresponds to data sampling and the falling edge corresponds to data shifting, or the rising edge of the communication clock signal SCK corresponds to data shifting and the falling edge corresponds to data sampling. The communication clock signal SCK is generated by the host chip itself and used directly in the master mode.

The actual logic circuit inside the chip needs to be connected with each pin through the PAD port of the chip, wherein the PAD port is formed by a metal block. Because the logic circuit inside the chip needs to be connected with each pin through the PAD port of the chip, delay problems exist in some signal transmission processes. The problem of the time delay of a two-way PAD port input/output to the full duplex high-speed serial interface is not considered in the design of the existing full duplex high-speed serial interface, but under high-frequency transmission (the general transmission speed is nanosecond), the time delay of the input and output of the two-way PAD port is not negligible, especially the time delay of the output of the PAD port is long, the serial input data signal SDI on a sampling data line and the serial output data signal SDO on a shift data line are easy to be asynchronous, and a larger phase difference exists between the serial input data signal SDI and the communication clock signal SCK used for sampling/shifting, which has a great challenge for the correct receiving of the data of the other party, and is shown by combining with figures 1 and 2, and is specifically as follows:

the signals which are supposed by the user and are connected with the external pin interface connected with the host chip through the PAD port should comprise a communication clock signal SCK, a serial data input signal SDI and a serial data output signal SDO; however, based on the structural characteristics of the digital circuit logic design of the host chip, that is, the delay effect caused by the PAD port, the signals actually participating in the operation of the host chip include an internal clock signal sck_o, an input clock signal sck_i, an external-to-internal serial data input signal sdi_i and an internal serial data output signal sdo_o, and the relationship between these signals and the effect caused by them are further described below:

In the prior art, all signals adopt a synchronous design mode, but because the input/output delay of the PAD port of the chip usually reaches nanosecond level, the delay of the PAD port of the chip is not negligible for serial data transmission of which the high-frequency transmission communication clock signal SCK reaches tens of megabits.

It is assumed that the own host is a non-ideal host (i.e., there is input/output delay at the bi-directional PAD port of the host), while the other slave is an ideal slave (i.e., there is no delay at the bi-directional PAD port of the slave).

When the serial data input signal SDI transmitted from the signal line of the slave is generated from the clock signal SCK received by the signal line of the slave and transmitted to the master, as shown in fig. 1 (fig. 1 only illustrates the delay problem, therefore, only some relevant components and ports are drawn, but not all functional modules in the host chip are drawn), the internal clock signal sck_o of the host chip is output to the PAD port to generate the communication clock signal SCK, and the delay experienced by the communication clock signal SCK is the delay (at least 10ns delay) caused by the output of the PAD port. The serial data input signal SDI is generated by the communication clock signal SCK, and the serial data input signal SDI is in phase with the communication clock signal SCK, the signal input into the serial communication interface to generate the external-to-internal serial data input signal sdi_i also needs to undergo a PAD port input delay (at least 3ns delay), and the phase difference between the internal clock signal sck_o and the external-to-internal serial data input signal sdi_i is a bidirectional PAD port output delay+a bidirectional PAD port input delay (at least 13ns delay), because the phase of correlation may cause the host to sample errors.

As can be more clearly seen from the timing chart in fig. 2 (the timing chart in fig. 2 is a timing chart when the serial port communication is sampled at the rising edge of the communication clock signal SCK and the falling edge is shifted), the timing relationship among the internal clock signal sck_o, the communication clock signal SCK, the serial input data signal SDI and the external-to-internal serial data input signal sdi_i is plotted in fig. 2, and if the input data (i.e., the external-to-internal serial data input signal sdi_i) is sampled at the rising edge of the internal clock signal sck_o in the manner in the prior art, the sampling is very prone to error when the external-to-internal serial data input signal sdi_i data is just unstable.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a circuit structure of a host chip which can realize serial interface full duplex communication, and has the advantages of accurate sampling, no time delay and wide application range.

In order to achieve the above object, the circuit structure of the host chip for realizing serial interface full duplex communication of the present invention is as follows:

the circuit structure of the host chip for realizing the full duplex communication of the serial interface is mainly characterized in that the host chip comprises a serial data input PAD port, a serial data output PAD port, a bidirectional clock signal input/output PAD port and a clock generating module;

After the external serial data input signal SDI is input through the serial data input PAD port, an external-to-internal serial data input signal SDI_I is generated;

the clock generation module is used for generating an internal clock signal SCK_O, and is connected with the first end of the internal connection end of the two-way clock signal input/output PAD port;

after the internal clock signal sck_o is output through the first end of the internal connection end of the bidirectional clock signal input/output PAD port, a communication clock signal SCK is generated and output from the external connection end of the bidirectional clock signal input/output PAD port, and an input clock signal sck_i is generated and output through the second end of the internal connection end of the bidirectional clock signal input/output PAD port, wherein the input clock signal sck_i is used for decoding the external-to-internal serial data input signal sdi_i;

the phase of the communication clock signal SCK is identical to the phase of the serial data output signal SDO output from the serial data output PAD port.

Preferably, the bidirectional clock signal input/output PAD port includes an output buffer and an input buffer;

the input end of the output buffer forms the first end of the internal connection end of the two-way clock signal input/output PAD port; the output end of the input buffer forms the second end of the internal connection end of the two-way clock signal input/output PAD port; the output end of the output buffer is connected with the input end of the input buffer;

And the output end of the output buffer forms an external end of the two-way clock signal input/output PAD port.

Preferably, the host chip further comprises an auxiliary clock generation module;

the first end of the auxiliary clock generation module is connected with the clock generation module and receives the internal clock signal SCK_O; the second end of the auxiliary clock generation module is connected with the second end of the bidirectional clock signal input/output PAD port and receives the input clock signal SCK_I;

the auxiliary clock generation module generates a shift clock signal sck_shift according to the internal clock signal sck_o;

the auxiliary clock generation module generates a sampling clock signal sck_sample according to the input clock signal sck_i.

More preferably, when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the auxiliary clock generating module inputs the received input clock signal sck_i into the first inverter to perform inversion, so as to obtain the sampling clock signal sck_sample for output, and the auxiliary clock generating module outputs the received internal clock signal sck_o as the shift clock signal sck_shift;

When the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the auxiliary clock generating module outputs the received input clock signal sck_i as the sampling clock signal sck_sample, and the auxiliary clock generating module inputs the received internal clock signal sck_o into the second inverter for inversion, so as to obtain the shift clock signal sck_shift for output.

Further, the host chip also comprises a shift module and a sampling module;

the first input end of the sampling module is connected with the external-to-internal serial data input signal SDI_I;

the shift clock signal sck_shift and the sampling clock signal sck_sample are not synchronous with the main frequency clock signal CLK;

triggering the sampling module to sample the external-to-internal serial data input signal SDI_I by the sampling clock signal sck_sample to generate a serial sampling data signal SDI_I_S;

the shift clock signal sck_shift triggers the shift module to shift the data in the output parallel data packet to be transmitted, so as to generate a corresponding internal serial data output signal sdo_o, and the internal serial data output signal sdo_o is output through the serial data output PAD port to generate the serial data output signal SDO.

Further, the host chip also comprises a synchronous cache module, a data sending cache module and a data receiving cache module;

the synchronous buffer module acquires the serial sampling data signal SDI_I_S and synchronizes the serial sampling data signal SDI_I_S with the main frequency clock signal CLK;

the first input end of the shifting module is connected with the sending data caching module;

the load trigger signal load_time and the shift clock signal sck_shift trigger the data transmission buffer module to transmit the output parallel data packet to the shift module; the trigger time of the load trigger signal load_time is as follows: avoiding the moment when the shift module shifts the data in the output parallel data packet;

triggering the received data buffer module to receive a serial sampled data signal SDI_I_S synchronized with the main frequency clock signal CLK from the synchronous buffer module by a load trigger signal send_time; the trigger time of the send_time of the load trigger signal is as follows: the received data buffer module receives any two adjacent serial sampled data signals sdi_i_s synchronized with the main clock signal CLK, and after the last bit of the serial sampled data signals sdi_i_s synchronized with the main clock signal CLK in the previous frame is completely sampled, the first bit of the serial sampled data signals sdi_i_s synchronized with the main clock signal CLK in the previous frame is not completely sampled, but is not shifted;

And the load_time and the send_time are synchronized with the clock signal CLK.

Further, the load trigger signal load_time is generated by the load trigger module,

when the auxiliary clock generation module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o,

the loading trigger module comprises a first sampling clock synchronization and edge taking unit, a first counter generating unit, a first NAND gate, a second NAND gate, a first comparator, a second comparator and a first D trigger;

the first sampling clock synchronization and edge taking unit is connected with the sampling clock signal sck_sample at a first input end, the second input end of the first sampling clock synchronization and edge taking unit is connected with the main frequency clock signal CLK, the first sampling clock synchronization and edge taking unit synchronizes the sampling clock signal sck_sample under the main frequency clock signal CLK and takes the falling edge, a sampling clock synchronization falling edge signal sck_sample_syn_neg is generated, and the sampling clock synchronization falling edge signal sck_sample_syn_neg is output by an output end of the first sampling clock synchronization and edge taking unit;

The output end of the first sampling clock synchronization and edge taking unit is respectively connected with the first end of the first counter generating unit, the first end of the first NAND gate and the first end of the second NAND gate;

the second end of the first counter generating unit is connected with the main frequency clock signal CLK, the output end of the first counter generating unit outputs a counter signal cnt, and the output end of the first counter generating unit is respectively connected with the first input end of the first comparator, the first input end of the second comparator and the feedback end of the first counter generating unit;

the second input end of the first comparator is connected with zero, the output end of the first comparator is connected with the second end of the first NAND gate, and the output end of the first NAND gate is connected with the setting end of the first D trigger;

the second input end of the second comparator is connected with a preset constant, the value of the preset constant corresponds to the data bit width of the output parallel data packet sent by the sending data buffer module, the output end of the second comparator is connected with the second end of the second NAND gate, and the output end of the second NAND gate is connected with the reset end of the first D trigger;

The clock input end of the first D trigger is connected with the main frequency clock signal CLK, the Q output end of the first D trigger is connected with the input end of the first D trigger, and the Q non-output end of the first D trigger outputs the load trigger signal load_time;

when the auxiliary clock generation module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o,

the host chip further comprises a chip selection signal generating module and a first OR gate, wherein the chip selection signal generating module is used for generating a chip selection signal CS, a first input end of the first OR gate is connected with the sampling clock signal sck_sample, a second input end of the first OR gate is connected with the chip selection signal CS, and an output end of the first OR gate outputs the chip selection sampling clock signal sck_sample';

the loading triggering module comprises a second sampling clock synchronization and edge taking unit, a chip selection signal synchronization and edge taking unit, a second counter generating unit, a third NAND gate, a fourth NAND gate, a third comparator, a fourth comparator, a first AND gate, a third inverter and a second D trigger;

The second sampling clock synchronization and edge taking unit is connected with the chip selection sampling clock signal sck_sample 'at a first input end, the second sampling clock synchronization and edge taking unit is connected with the main frequency clock signal CLK at a second input end, the second sampling clock synchronization and edge taking unit synchronizes the chip selection sampling clock signal sck_sample' under the main frequency clock signal CLK and takes a falling edge, a sampling clock synchronization falling edge signal sck_sample_syn_neg is generated, and the sampling clock synchronization falling edge signal sck_sample_syn_neg is output by an output end of the second sampling clock synchronization and edge taking unit;

the output end of the second sampling clock synchronization and edge taking unit is respectively connected with the first end of the second counter generating unit, the first end of the third NAND gate and the first end of the fourth NAND gate;

the first input end of the chip selection signal synchronizing and edge taking unit is connected with the chip selection signal CS, and the second input end of the chip selection signal synchronizing and edge taking unit is connected with the main frequency clock signal CLK; the chip selection signal synchronizing and edge taking unit synchronizes the chip selection signal CS under the main frequency clock signal CLK to generate a chip selection synchronizing signal CS_syn, and the chip selection synchronizing signal CS_syn is output by the first output end of the chip selection signal synchronizing and edge taking unit; the chip selection signal synchronizing and edge taking unit synchronizes the chip selection signal CS under the main frequency clock signal CLK and takes the rising edge to generate a chip selection synchronous rising edge signal CS_syn_pos, and the chip selection signal synchronizing and edge taking unit outputs the chip selection synchronous rising edge signal CS_syn_pos through a second output end of the chip selection signal synchronizing and edge taking unit;

The second end of the second counter generating unit is connected with the main frequency clock signal CLK, the third end of the second counter generating unit is connected with the chip selection synchronous signal CS_syn, the output end of the second counter generating unit outputs a counter signal cnt, and the output end of the second counter generating unit is respectively connected with the first input end of the third comparator, the first input end of the fourth comparator and the feedback end of the second counter generating unit;

the second input end of the third comparator is connected with zero, the output end of the third comparator is connected with the second end of the third NAND gate, and the output end of the third NAND gate is connected with the setting end of the second D trigger;

the second input end of the fourth comparator is connected with a preset constant, the value of the preset constant corresponds to the data bit width of the output parallel data packet sent by the sending data buffer module, the output end of the fourth comparator is connected with the second end of the fourth NAND gate, and the output end of the fourth NAND gate is connected with the first input end of the first AND gate;

The input end of the third inverter is connected with the chip selection synchronous rising edge signal CS_syn_pos, the output end of the third inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate is connected with the reset end of the second D trigger;

the clock input end of the second D trigger is connected with the main frequency clock signal CLK, the Q output end of the second D trigger is connected with the input end of the second D trigger, and the Q non-output end of the second D trigger outputs the load trigger signal load_time.

Further, the send_time is generated by an send trigger module, which includes a fifth comparator, a third sampling clock synchronization and edge taking unit, a third D trigger and a second and gate;

the first input end of the fifth comparator is connected with zero, the second input end of the fifth comparator is connected with the counter signal cnt, and the output end of the fifth comparator is connected with the first input end of the second AND gate;

when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the third sampling clock synchronizes and takes the first input end of the edge unit to terminate the sampling clock signal sck_sample; the second input end of the third sampling clock synchronization and edge taking unit is connected with the main frequency clock signal CLK, and the third sampling clock synchronization and edge taking unit synchronizes the sampling clock signal sck_sample under the main frequency clock signal CLK and takes the rising edge to generate a sampling clock synchronization rising edge signal sck_sample_syn_pos; when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the first input end of the third sampling clock synchronizing and sampling unit is connected with the chip selection sampling clock signal sck_sample ', the second input end of the third sampling clock synchronizing and sampling unit is connected with the main frequency clock signal CLK, and the third sampling clock synchronizing and sampling unit synchronizes the chip selection sampling clock signal sck_sample' under the main frequency clock signal CLK and takes the rising edge to generate a sampling clock synchronizing rising edge signal sck_sample_syn_pos;

The third sampling clock synchronizes and takes the output end of the edge unit to output the sampling clock synchronization rising edge signal sck_sample_syn_pos;

the clock input end of the third D trigger is connected with the main frequency clock signal CLK, the input end of the third D trigger is synchronous with the third sampling clock and is connected with the output end of the edge taking unit, and the Q output end of the third D trigger is connected with the second input end of the second AND gate;

the output end of the second AND gate outputs the load trigger signal send_time.

Furthermore, the first sampling clock synchronization and edge taking unit and the second sampling clock synchronization and edge taking unit may be composed of a synchronization and edge taking unit, and the synchronization and edge taking unit includes: a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a fourth inverter, and a third AND gate;

the input end of the fourth D trigger forms the first input end of the first sampling clock synchronization and edge taking unit or the second sampling clock synchronization and edge taking unit; the clock input end of the fourth D trigger, the clock input end of the fifth D trigger and the clock input end of the sixth D trigger jointly form the second input end of the first sampling clock synchronous and edge taking unit or the second input end of the second sampling clock synchronous and edge taking unit;

The Q output end of the fourth D trigger is connected with the input end of the fifth D trigger; the Q output end of the fifth D trigger is respectively connected with the input end of the sixth D trigger and the input end of the fourth inverter;

the output end of the fourth inverter is connected with the first output end of the third AND gate; the Q output end of the sixth D trigger is connected with the second output end of the third AND gate; the output end of the third AND gate forms the output end of the first sampling clock synchronization and edge taking unit or the output end of the second sampling clock synchronization and edge taking unit;

the chip selection signal synchronizing and edge taking unit and the third sampling clock synchronizing and edge taking unit can be composed of a synchronizing and rising edge taking unit, and the synchronizing and rising edge taking unit comprises: seventh D flip-flop, eighth D flip-flop, ninth D flip-flop, fifth inverter and fourth AND gate;

the input end of the seventh D trigger forms the first input end of the chip selection signal synchronization and edge taking unit or the third sampling clock synchronization and edge taking unit; the clock input end of the seventh D trigger, the clock input end of the eighth D trigger and the clock input end of the ninth D trigger jointly form the second input end of the chip selection signal synchronizing and edge taking unit or the second input end of the third sampling clock synchronizing and edge taking unit;

The Q output end of the seventh D trigger is connected with the input end of the eighth D trigger; the Q output end of the eighth D trigger is respectively connected with the input end of the ninth D trigger and the first input end of the fourth AND gate; the Q output end of the eighth D trigger forms a first output end of the chip selection signal synchronization and edge taking unit;

the Q output end of the ninth D trigger is connected with the second input end of the fourth AND gate through the fifth inverter;

the output end of the fourth AND gate forms the second output end of the chip selection signal synchronization and edge taking unit or the output end of the third sampling clock synchronization and edge taking unit.

Further, the sampling module includes a tenth D flip-flop, and an input terminal of the tenth D flip-flop forms a first input terminal of the sampling module;

when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the clock input end of the tenth D flip-flop is connected with the sampling clock signal sck_sample; when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the clock input end of the tenth D flip-flop is connected with the chip selection sampling clock signal sck_sample';

The Q output of the tenth D flip-flop outputs the serial sampled data signal sdi_i_s.

Further, the shift module comprises a shift register unit;

the first input end of the shift register unit forms the first input end of the shift module, and the second input end of the shift register unit is connected with the load trigger signal load_time;

when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the clock input end of the shift register unit is connected with the shift clock signal sck_shift; when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the host chip further comprises a sixth inverter and a fifth and gate, the chip select signal CS is input to the first input end of the fifth and gate through the sixth inverter, the second input end of the fifth and gate is connected with the shift clock signal sck_shift, the output end of the fifth and gate outputs the chip select shift clock signal sck_shift ', and the clock input end of the shift register unit is connected with the chip select shift clock signal sck_shift';

The first output terminal of the shift register unit outputs the internal serial data output signal sdo_o.

Still further, the synchronous buffer module includes: a serial sampling signal synchronization unit, a shift register synchronization unit, and an eleventh D trigger;

the first input end of the serial sampling signal synchronization unit is connected with the Q output end of the tenth D trigger, the second input end of the serial sampling signal synchronization unit is connected with the main frequency clock signal CLK, and the output end of the serial sampling signal synchronization unit is connected with the first input end of the received data buffer module;

the Q output end of the tenth D trigger is connected with the third input end of the shift register unit, the second output end of the shift register unit is connected with the first input end of the shift register synchronization unit, the second input end of the shift register synchronization unit is connected with the main frequency clock signal CLK, the output end of the shift register synchronization unit is connected with the input end of the eleventh D trigger, the clock input end of the eleventh D trigger is connected with the main frequency clock signal CLK, and the Q output end of the eleventh D trigger is connected with the second input end of the received data buffer module;

The third input end of the receiving data buffer module is connected with the main frequency clock signal CLK, and the fourth input end of the receiving data buffer module is connected with the load trigger signal send_time;

the signal output by the output end of the serial sampling signal synchronizing unit is spliced with the signal output by the Q output end of the eleventh D trigger to form the serial sampling data signal SDI_I_S synchronized with the main frequency clock signal CLK.

Furthermore, the serial sampling signal synchronization unit and the shift register synchronization unit may each be composed of a synchronization unit, where the synchronization unit includes a twelfth D trigger and a thirteenth D trigger;

the input end of the twelfth D trigger forms the first input end of the serial sampling signal synchronization unit or the first input end of the shift register synchronization unit; the clock input end of the twelfth D trigger and the clock input end of the thirteenth D trigger jointly form a second input end of the serial sampling signal synchronization unit or a second input end of the shift register synchronization unit; the Q output end of the twelfth D trigger is connected with the input end of the thirteenth D trigger; the Q output end of the thirteenth D trigger forms the output end of the serial sampling signal synchronizing unit or the output end of the shift register synchronizing unit.

By adopting the circuit structure of the host chip for realizing the full duplex communication of the serial interface, the data received by the serial data input PAD port is decoded by the input clock signal SCK_I generated by the bidirectional clock signal input/output PAD port, and the phase of the communication clock signal SCK is consistent with the phase of the serial data output signal SDO output by the serial data output PAD port, so that the problem of sampling/shifting errors caused by the delay of the bidirectional PAD port is avoided. The circuit structure of the host chip for realizing the full duplex communication of the serial interface has the characteristics of high information transmission accuracy, excellent performance and low cost, and has wide adaptability.

Drawings

Fig. 1 is a schematic diagram of a signal transmission state of a serial interface full duplex communication circuit in the prior art.

Fig. 2 is a timing diagram of the signals in fig. 1.

Fig. 3 is a schematic diagram of the circuit structure of a host chip implementing serial interface full duplex communication according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a bidirectional clock signal input/output PAD port according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of a signal transmission state of a circuit structure of a host chip for implementing full duplex communication of a serial interface according to an embodiment of the present invention.

FIG. 6a is a logic diagram of the auxiliary clock generation module of the present invention for generating sampling signals and shifting signals according to an embodiment.

Fig. 6b is a logic diagram of generating a sampling signal and a shift signal of the auxiliary clock generating module according to another embodiment of the present invention.

Fig. 7 is a schematic diagram of a module relationship of a host chip in a circuit structure of a host chip implementing serial interface full duplex communication according to an embodiment of the invention.

Fig. 8a is a schematic structural diagram of a load trigger module according to an embodiment of the invention.

Fig. 8b is a schematic structural diagram of a load trigger module according to another embodiment of the present invention.

Fig. 9 is a schematic structural diagram of an out-trigger module according to an embodiment of the invention.

FIG. 10 is a schematic diagram of a synchronous and falling edge unit according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of a synchronous and rising edge cell according to an embodiment of the present invention.

Fig. 12 is a schematic structural diagram of a synchronization unit according to an embodiment of the invention.

Fig. 13 is a schematic diagram illustrating an operation principle of the shift module according to an embodiment of the invention.

Fig. 14 is a timing diagram of generating the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generating the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o.

Fig. 15 is a timing diagram of generating the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generating the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o.

Fig. 16 is a timing chart showing the phase relationship between the load trigger signal send_time and other signals when the sampling clock signal sck_sample is generated according to the falling edge of the input clock signal sck_i and the shift clock signal sck_shift is generated according to the rising edge of the internal clock signal sck_o.

Fig. 17 is a timing chart showing the phase relationship between the load trigger signal send_time and other signals when the sampling clock signal sck_sample is generated according to the rising edge of the input clock signal sck_i and the shift clock signal sck_shift is generated according to the falling edge of the internal clock signal sck_o.

Detailed Description

In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.

As shown in fig. 3 to 12, the main functional modules of the circuit structure of the host chip for implementing serial interface full duplex communication of the present invention include a clock generation module, an auxiliary clock generation module, a sampling module, a shift module and a synchronous buffer module, when the auxiliary clock generation module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i, and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the circuit structure further includes a chip selection signal generation module, and the specific circuit is as follows:

as shown in fig. 3, the host chip includes a serial data input PAD port, a serial data output PAD port, a bidirectional clock signal input output PAD port, and a clock generation module;

With the circuit structure of the host chip for realizing the full duplex communication of the serial interface in this embodiment, the internal clock signal sck_o is not directly used for processing serial input/output data, but is input to the input clock signal sck_i after being output and delayed through the bidirectional clock signal input/output PAD port. The sampling and shifting operations of the data are implemented by two different clocks, a sampling clock signal sck_sample and a shifting clock signal sck_shift.

The method can effectively solve the problem of sampling or shift dislocation of signals caused by the time delay of the bidirectional PAD port in communication in a main mode (namely, the problem that PAD output time delay exists when clock signals generated by a host pass through the bidirectional PAD port in the main mode), and keep the phase of a serial data output signal SDO consistent with the phase of a communication clock signal SCK on the premise of the reliability design of a digital circuit, and simultaneously ensure that host sampling cannot be influenced by the time delay of the bidirectional PAD port to cause sampling errors.

As shown in fig. 4, in this embodiment, the bidirectional clock signal input/output PAD port includes an output buffer and an input buffer;

As shown in fig. 4, the bidirectional clock signal input/output PAD port may be understood as a bidirectional I/O buffer structure, where a pad_o port inputs an internal clock signal sck_o, a pad_i port outputs an input clock signal sck_i, a port outputting a communication clock signal SCK is a Bonding PAD (i.e., a binding port to an external pin), the internal clock signal sck_o is generated by a host chip, a pad_oe may be configured by a circuit main CPU, and is an output enable signal of the bidirectional I/O buffer, and is used for setting whether the bidirectional clock signal input/output PAD port is in an output mode or an input mode, and in the main mode, the pad_oe is set as an output mode, but its setting does not hinder input of signals at the pad_i port, and a signal at the pad_i port is an input delay signal generated by accumulating output delay time of the bidirectional clock signal input/output PAD port and output delay time of the pad_o port, i.e., an input delay time signal sck_i generated by the internal clock signal sck_o after output delay time of the bidirectional clock signal input/output port and input delay time of the PAD port.

In this embodiment, the host chip further includes an auxiliary clock generation module;

That is, in the circuit structure of the host chip for realizing full duplex communication of the serial interface in this embodiment, for re-inputting the internal clock signal sck_o generated in the circuit after the internal clock signal sck_o is delayed by the bidirectional clock signal input/output PAD port from the bidirectional clock signal input/output PAD port, the input clock signal sck_i is obtained, and the external serial data input signal sdi_i is sampled by the input clock signal sck_i, that is, the sampling accuracy is ensured by the process of outputting the sampling clock through the bidirectional clock signal input/output PAD port and then returning. In the main mode, the selected shift clock sck_shift is not transmitted back through the PAD port, but is shifted by the internal clock sck_o, and the processing of the shift clock sck_shift is completed in the auxiliary clock generating unit.

The relationship between signals in the circuit structure of the host chip for implementing serial interface full duplex communication in the present invention is further described below with reference to fig. 5, where the bidirectional clock signal input/output PAD port corresponds to the combination of the serial data input PAD port and the serial data output PAD port.

Taking the case that the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o as an example:

in the main mode, an internal clock signal sck_o is generated, the internal clock signal sck_o is output and delayed through a bidirectional clock signal input/output PAD port, a delayed signal, namely a communication clock signal SCK, is generated, a shift clock signal sck_shift is generated by the internal clock signal sck_o through a combinational logic as shown in fig. 6a in an auxiliary clock generating unit, parallel data are shifted on each rising edge of the shift clock signal sck_shift in a shift module to generate an internal serial data output signal sdo_o, and the internal serial data output signal sdo_o is output and delayed through a serial data output PAD port, so that a delayed signal, namely a serial data output signal SDO, is generated. The internal clock signal sck_o and the internal serial data output signal sdo_o are always aligned along the edges, and after the output delay of the bidirectional clock signal input/output PAD port with the same characteristics, the communication clock signal SCK and the serial data output signal SDO are always aligned along the edges, which means that no phase difference exists between the communication clock signal SCK and the serial data output signal SDO.

There is no phase difference between the serial data input signal SDI and the communication clock signal SCK (on the basis that the other slave is an ideal slave), the serial data input signal SDI is input delayed through the serial data input PAD port, a delayed signal, i.e., an external-to-internal serial data input signal sdi_i, is generated, the communication clock signal SCK is input delayed through the bidirectional clock signal input/output PAD port, a delayed signal, i.e., an input clock signal sck_i, is generated, and there is no phase difference between the input clock signal sck_i and the external-to-internal serial data input signal sdi_i after the PAD port input delay with the same characteristics. The input clock signal sck_i generates a sampling clock signal sck_sample in the auxiliary clock generating module shown in fig. 6a, and under the combined action of the sampling module and the synchronous buffer module, the sampling clock signal sck_sample performs in-phase sampling on the external serial data input signal sdi_i to generate parallel sampling data, so that the sampling accuracy can be ensured.

In the case that the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the working principle is similar to that of the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i, and the situation of generating the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o is similar to that of the chip select clock signal sck_shift formed by the combining logic in fig. 6b, except that the shift clock signal sck_shift generated by the combining logic in fig. 6b is replaced by the chip select shift clock signal sck_shift 'formed by the combining logic in fig. 6b, and the sampling clock signal sck_sample generated by the combining logic in fig. 6b is replaced by the chip select clock signal sck_shift' formed by the chip select signal CS, so that the auxiliary clock generating module does not work in the same way.

As shown in fig. 6a, in this embodiment, when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the auxiliary clock generating module inputs the received input clock signal sck_i into the first inverter to perform inversion, so as to obtain the sampling clock signal sck_sample for output, and the auxiliary clock generating module outputs the received internal clock signal sck_o as the shift clock signal sck_shift;

as shown in fig. 6b, when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the auxiliary clock generating module outputs the received input clock signal sck_i as the sampling clock signal sck_sample, and the auxiliary clock generating module inputs the received internal clock signal sck_o into the second inverter for inversion, so as to obtain the shift clock signal sck_shift for output.

As shown in fig. 3, in this embodiment, the host chip further includes a shift module and a sampling module;

In this embodiment, the host chip further includes a synchronization buffer module, a transmission data buffer module, and a reception data buffer module;

that is, the load_time of the load trigger signal is valid at a high level, and the high level is selected as a time for avoiding shifting the internal data by the shift register unit, and the high level is also understood as a trigger time for filtering and transmitting parallel data in the data buffer unit to load into the shift register unit.

The trigger time of the send_time of the load trigger signal is the rising edge of the 8 th sampling clock signal for 8-bit data of a frame, that is, the current moment when the 8 th data just completes sampling.

And the load_time and the send_time are synchronized with the clock signal CLK.

The module relationship of the host chip in the circuit structure of the host chip for implementing serial interface full duplex communication according to this embodiment is shown in fig. 7, where fig. 7 shows a schematic diagram in the case where the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o; when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i AND generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the chip select signal generating module, the first or gate, the fifth AND gate AND5 AND the corresponding inverter in fig. 7 are omitted, AND the sampling clock signal sck_sample 'AND the shift clock signal sck_shift' are directly used to trigger the corresponding sampling module, the load triggering module AND the shift module to operate, so that the corresponding pictures are not drawn.

When the auxiliary clock generation module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the chip select sampling clock signal sck_sample 'formed by the sampling clock signal sck_sample and the chip select signal CS replaces the sampling clock signal sck_sample, and the chip select shift clock signal sck_shift' formed by the shift clock signal sck_shift and the chip select signal CS replaces the shift clock signal sck_shift, because in this case, if the shift operation is triggered by the shift clock signal sck_shift only, the first rising edge of the shift clock signal sck_shift is staggered with the enabled part of the load trigger signal load_time, the function of triggering the transmission data buffer module to transmit the output data packet to the shift module cannot be realized, so that the function of the transmission data packet is parallel to the shift module can be realized.

In this embodiment, the load_time is generated by the load trigger module,

As shown in fig. 8a, when the auxiliary clock generation module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o,

the loading trigger module comprises a first sampling clock synchronization and edge taking unit, a first counter generating unit, a first NAND gate NAND1, a second NAND gate NAND2, a first comparator EQU1, a second comparator EQU2 and a first D trigger DFF1;

the output end of the first sampling clock synchronization and edge taking unit is respectively connected with the first end of the first counter generating unit, the first end of the first NAND gate NAND1 and the first end of the second NAND gate NAND 2;

The second end of the first counter generating unit is connected with the main frequency clock signal CLK, the output end of the first counter generating unit outputs a counter signal cnt, and the output end of the first counter generating unit is respectively connected with the first input end of the first comparator EQU1, the first input end of the second comparator EQU2 and the feedback end of the first counter generating unit;

the second input end of the first comparator EQU1 is connected with zero, the output end of the first comparator EQU1 is connected with the second end of the first NAND gate NAND1, and the output end of the first NAND gate NAND1 is connected with the set end of the first D trigger DFF 1;

the second input end of the second comparator EQU2 is connected with a preset constant, the value of the preset constant corresponds to the data bit width of the output parallel data packet sent by the sending data buffer module, the output end of the second comparator EQU2 is connected with the second end of the second NAND gate NAND2, and the output end of the second NAND gate NAND2 is connected with the reset end of the first D trigger DFF 1;

the clock input end of the first D trigger DFF1 is connected with the main frequency clock signal CLK, the Q output end of the first D trigger DFF1 is connected with the input end of the first D trigger DFF1, and the Q non-output end of the first D trigger DFF1 outputs the load trigger signal load_time;

the chip select sampling clock signal sck_sample' in this embodiment is actually generated by combining logic of the sampling clock signal sck_sample obtained by processing the input clock signal sck_i by the auxiliary clock generation module and the chip select signal CS.

As shown in fig. 8b, the load trigger module includes a second sampling clock synchronization AND edge taking unit, a chip selection signal synchronization AND edge taking unit, a second counter generating unit, a third NAND gate NAND3, a fourth NAND gate NAND4, a third comparator EQU3, a fourth comparator EQU4, a first AND gate AND1, a third inverter AND a second D flip-flop DFF2;

the output end of the second sampling clock synchronization and edge taking unit is respectively connected with the first end of the second counter generating unit, the first end of the third NAND gate NAND3 and the first end of the fourth NAND gate NAND 4;

The second end of the second counter generating unit is connected with the main frequency clock signal CLK, the third end of the second counter generating unit is connected with the chip selection synchronous signal CS_syn, the output end of the second counter generating unit outputs a counter signal cnt, and the output end of the second counter generating unit is respectively connected with the first input end of the third comparator EQU3, the first input end of the fourth comparator EQU4 and the feedback end of the second counter generating unit;

the second input end of the third comparator EQU3 is connected with zero, the output end of the third comparator EQU3 is connected with the second end of the third NAND gate NAND3, and the output end of the third NAND gate NAND3 is connected with the set end of the second D trigger DFF 2;

the second input end of the fourth comparator EQU4 is connected with a preset constant, the value of the preset constant corresponds to the data bit width of the output parallel data packet sent by the sending data buffer module, the output end of the fourth comparator EQU4 is connected with the second end of the fourth NAND gate NAND4, AND the output end of the fourth NAND gate NAND4 is connected with the first input end of the first AND gate AND 1;

The input end of the third inverter is connected with the chip selection synchronous rising edge signal CS_syn_pos, the output end of the third inverter is connected with the second input end of the first AND gate AND1, AND the output end of the first AND gate AND1 is connected with the reset end of the second D trigger DFF 2;

the clock input end of the second D trigger DFF2 is connected with the main frequency clock signal CLK, the Q output end of the second D trigger DFF2 is connected with the input end of the second D trigger DFF2, and the Q non-output end of the second D trigger DFF2 outputs the load trigger signal load_time.

Under any precondition (whether the sampling clock sck_sample is generated based on the rising edge of the input clock sck_i or the sampling clock sck_sample is generated based on the falling edge of the input clock sck_i), the load trigger signal load_time must return to the reset state (high state) after one frame data transmission is completed.

The auxiliary clock generation module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i, and resets the load trigger signal load_time by using the chip select synchronous rising edge signal cs_syn_pos in the scheme of generating the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o. In fig. 8b, the generated falling edge rn is reset through the reset terminal clr of the second D flip-flop DFF2, and a rising edge of the load trigger signal load_time is generated, so that the load trigger signal load_time returns to the reset state, i.e. the high level state, after the transmission of one frame of data is completed.

Meanwhile, in this scheme, a necessary condition for the counter generating unit counter to clear 0 is that the chip selection synchronizing signal cs_syn is high, the data transmission is finished, the counter signal cnt is cleared, if the chip selection synchronizing signal cs_syn is not high, the counter signal cnt is finally stopped at 1 and returns to the initial value 0. As shown in fig. 15, there are 9 sampling clock synchronous falling edge signals sck_sample_syn_neg, each sampling clock synchronous falling edge signal sck_sample_syn_neg is valid at high level, the counter signal cnt is added with 1, the counter signal cnt can count only 0-7 and is added with 1 finally, after one frame of 8-bit data transmission is finished, the counter signal cnt is cleared again to 0 under the condition that the chip selection synchronization signal cs_syn is valid at high level, so that the counter signal cnt is returned to an initial state.

The first counter generating unit and the second counter generating unit have the functions of: the number of the serial data of a frame which is currently transmitted and received is recorded, and a counter signal cnt is 0 in a reset state, so that the first data is not sampled, and meanwhile, the first data is not transmitted; when the counter signal cnt is 1, the first serial data to be received is sampled, but the data is not shifted into the shift register, and the first serial data to be transmitted is transmitted at the same time; when the counter signal cnt is 2, the second serial data to be received is sampled, the first sampled serial data to be received is shifted into the shift register, and meanwhile, the second serial data to be transmitted is transmitted; when the counter signal cnt is 3, the third serial data to be received is sampled, the second sampled serial data to be received is shifted into the shift register, and meanwhile, the third serial data to be transmitted is transmitted; similarly, when the counter signal cnt is 7, the seventh serial data to be received is sampled, the sixth serial data to be received is shifted into the shift register, and the seventh serial data to be transmitted is transmitted at the same time; when the counter signal cnt returns to 0 again, it is explained that the eighth serial data to be received is sampled, the seventh serial data to be received sampled is shifted into the shift register, and the eighth serial data to be transmitted is transmitted at the same time.

The above description is given by taking transmission of 8-bit data as an example, one frame of 8-bit data is incremented from 0 to 7 and then returned to 0, if 16-bit data is described by incrementing from 0 to 15 and then returned to 0 in the same manner, the first counter generating unit and the second counter generating unit adopted in the embodiment are both loop counters, and the input back counter generating unit is the description that it will loop count. The counter cnt clears 0 after a frame of data is full (7 or 15, etc.) as the data is transmitted continuously frame by frame.

The following describes the operation of the load trigger module when the auxiliary clock generation module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o:

the sampling clock signal sck_sample is synchronized with the main frequency clock signal CLK and subjected to an edge taking operation to generate a sampling clock synchronized falling edge signal sck_sample_syn_neg signal. The chip select signal CS generates a chip select sync signal cs_syn and a chip select sync rising edge signal cs_syn_pos signal through synchronization with the main frequency clock signal CLK and an edge taking operation. The counter signal cnt counts the data frame bits, the counter signal cnt is generated by the counter generating unit, and the size of the counter signal cnt is determined by the serial data frame bits. data_len is a constant indicating the number of bits of the data frame. When the counter signal cnt extracts cnt= 0 after passing through the third comparator EQU3, when the counter signal cnt extracts cnt= data_len after passing through the fourth comparator EQU4, signals generated by the two-input NAND gate (the third NAND gate NAND 3) AND the two-input AND gate (the first AND gate AND 1) are input into the SET end SET AND the reset end CLR of the second D flip-flop DFF2, the SET end AND the reset end of the second D flip-flop DFF2 are the asynchronous falling edge SET end SET AND the asynchronous falling edge reset end CLR, AND signals output by the Q non-output end are the load trigger signal load_time.

As shown in fig. 9, in this embodiment, the send_time is generated by an send trigger module, which includes a fifth comparator EQU5, a third sampling clock synchronization and edge taking unit, a third D trigger DFF3, and a second and gate;

the first input end of the fifth comparator EQU5 is connected with zero, the second input end of the fifth comparator EQU5 is connected with the counter signal cnt, and the output end of the fifth comparator EQU5 is connected with the first input end of the second AND gate;

the clock input end of the third D trigger DFF3 is connected with the main frequency clock signal CLK, the input end of the third D trigger DFF3 is synchronous with the third sampling clock and is connected with the output end of the edge taking unit, and the Q output end of the third D trigger DFF3 is connected with the second input end of the second AND gate;

The load trigger signal load_time and the load trigger signal send_time correspond to the trigger time of the output parallel data packet in the sending data buffer module to be loaded in the shift module and the trigger time of the parallel data in the synchronous buffer module to be loaded out to the receiving data buffer module respectively.

The load trigger signal send_time is an active high signal, after comparing the counter signal cnt with zero through a comparator, a moment of cnt= 0 is provided, the sampling clock signal sck_sample (or the chip selection sampling clock signal sck_sample ') is synchronized through a third sampling clock AND the sampling unit generates a sampling clock sampling rising edge signal sck_sample_syn_pos, the sampling clock sampling rising edge signal sck_sample_syn_pos is delayed by one beat through a third D trigger DFF3, a sampling clock sampling rising edge delay signal sck_sample_syn_pos_d is generated, AND a moment of ' cnt= 0 ' is generated after passing through a second AND gate AND 2. The rising edge time of the main frequency clock signal CLK corresponding to the high effective time of the loading trigger signal send_time completes the operation of splicing the serial sampling data synchronous signal SDI_I_S_syn and the shift register synchronous delay signal shift_reg_syn_d [ data_len:1] and simultaneously sending the spliced signals into the receiving data buffer module.

In this embodiment, the first sampling clock synchronizing and taking unit and the second sampling clock synchronizing and taking unit may be configured by a synchronizing and taking falling edge unit, as shown in fig. 10, where the synchronizing and taking falling edge unit includes: a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a fourth inverter, and a third and gate;

the input end of the fourth D trigger DFF4 forms the first input end of the first sampling clock synchronous and edge taking unit or the first input end of the second sampling clock synchronous and edge taking unit; the clock input end of the fourth D flip-flop DFF4, the clock input end of the fifth D flip-flop DFF5 and the clock input end of the sixth D flip-flop DFF6 together form the first sampling clock synchronization and take the second input end of the edge unit or the second sampling clock synchronization and take the second input end of the edge unit;

the Q output end of the fourth D trigger DFF4 is connected with the input end of the fifth D trigger DFF 5; the Q output end of the fifth D trigger DFF5 is respectively connected with the input end of the sixth D trigger DFF6 and the input end of the fourth inverter;

The output end of the fourth inverter is connected with the first output end of the third AND gate; the Q output end of the sixth D trigger DFF6 is connected with the second output end of the third AND gate; the output end of the third AND gate forms the output end of the first sampling clock synchronization and edge taking unit or the output end of the second sampling clock synchronization and edge taking unit;

the chip select signal synchronizing and edge taking unit and the third sampling clock synchronizing and edge taking unit may be composed of a synchronizing and edge taking unit, as shown in fig. 11, where the synchronizing and edge taking unit includes: seventh D flip-flop DFF7, eighth D flip-flop DFF8, ninth D flip-flop DFF9, fifth inverter, and fourth and gate;

the input end of the seventh D trigger DFF7 forms the first input end of the chip selection signal synchronous and edge taking unit or the third sampling clock synchronous and edge taking unit; the clock input end of the seventh D flip-flop DFF7, the clock input end of the eighth D flip-flop DFF8, and the clock input end of the ninth D flip-flop DFF9 together form the second input end of the chip select signal synchronizing and edge taking unit or the third sampling clock synchronizing and edge taking unit;

The Q output end of the seventh D trigger DFF7 is connected with the input end of the eighth D trigger DFF 8; the Q output end of the eighth D trigger DFF8 is respectively connected with the input end of the ninth D trigger DFF9 and the first input end of the fourth AND gate; the Q output end of the eighth D trigger DFF8 forms a first output end of the chip selection signal synchronization and edge taking unit;

the Q output end of the ninth D trigger DFF9 is connected with the second input end of the fourth AND gate through the fifth inverter;

As shown in fig. 10, the synchronous AND falling edge taking unit is used to make the asynchronous signal data pass through two stages of flip-flops (the fourth D flip-flop DFF4 AND the fifth D flip-flop DFF 5) AND generate a synchronous data signal data_syn, wherein the synchronous data signal data_syn is synchronous with the main frequency clock signal CLK, AND the synchronous data falling edge taking signal data_syn_neg, which is the output signal of the second AND gate AND3, is a signal obtained by taking the falling edge after the synchronous signal data AND the main frequency clock signal CLK are synchronous.

As shown in fig. 11, the structure of the synchronous and rising edge taking unit is basically similar to that of the synchronous and falling edge taking unit, except that the positions of the used inverters are different, and the synchronous and rising edge taking unit takes the synchronous data output by the output end of the two-input fourth and gate used in the structure of the synchronous and rising edge taking unit as a rising edge signal data_syn_pos; the signal is a rising edge signal after the asynchronous signal data is synchronous with the main frequency CLK.

In this embodiment, the sampling module includes a tenth D flip-flop DFF10, and an input terminal of the tenth D flip-flop DFF10 forms a first input terminal of the sampling module;

when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the clock input end of the tenth D flip-flop DFF10 is connected with the sampling clock signal sck_sample; when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the clock input end of the tenth D flip-flop DFF10 is connected with the chip selection sampling clock signal sck_sample';

The Q output terminal of the tenth D flip-flop DFF10 outputs the serial sampling data signal sdi_i_s.

That is, in this embodiment, the sampling module samples the external-to-internal serial data input signal sdi_i under the triggering of the sampling clock signal sck_sample (or the chip-select sampling clock signal sck_sample '), specifically, samples the external-to-internal serial data input signal sdi_i by the tenth D flip-flop DFF10 under the triggering of the sampling clock signal sck_sample (or the chip-select sampling clock signal sck_sample'), and then obtains the sampled serial sampling data signal sdi_i_s.

In this embodiment, the shift module includes a shift register unit;

when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the clock input end of the shift register unit is connected with the shift clock signal sck_shift; when the auxiliary clock generating module generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i AND generates the shift clock signal sck_shift according to the falling edge of the internal clock signal sck_o, the host chip further includes a sixth inverter AND a fifth AND gate AND5, the chip select signal CS is input to the first input terminal of the fifth AND gate AND5 through the sixth inverter, the second input terminal of the fifth AND gate AND5 is connected to the shift clock signal sck_shift, the output terminal of the fifth AND gate AND5 outputs the chip select shift clock signal sck_shift ', AND the clock input terminal of the shift register unit is connected to the chip select shift clock signal sck_shift';

The chip select shift clock sck_shift' may be considered as a result of combining the internal clock sck_o and the chip select signal CS.

The main function of the load trigger module is to generate a load trigger signal load_time. The shift register unit in the shift module corresponds to two functions: (1) shifting the serial sampled data signal sdi_i_s into the shift register at the rising edge of the shift clock signal sck_shift to generate a shift register signal shift_reg while generating an internal serial data output signal sdo_o; (2) after the data shift is completed, new data in the data transmission buffer module needs to be loaded into the shift register again to generate a shift register signal shift_reg.

In this embodiment, the synchronous buffer module includes: a serial sampling signal synchronization unit, a shift register synchronization unit, and an eleventh D flip-flop DFF11;

the first input end of the serial sampling signal synchronization unit is connected with the Q output end of the tenth D trigger DFF10, the second input end of the serial sampling signal synchronization unit is connected with the main frequency clock signal CLK, and the output end of the serial sampling signal synchronization unit is connected with the first input end of the received data buffer module;

The Q output end of the tenth D flip-flop DFF10 is connected to the third input end of the shift register unit, the second output end of the shift register unit is connected to the first input end of the shift register synchronization unit, the second input end of the shift register synchronization unit is connected to the main frequency clock signal CLK, the output end of the shift register synchronization unit is connected to the input end of the eleventh D flip-flop DFF11, the clock input end of the eleventh D flip-flop DFF11 is connected to the main frequency clock signal CLK, and the Q output end of the eleventh D flip-flop DFF11 is connected to the second input end of the received data buffer module;

the signal output by the output end of the serial sampling signal synchronizing unit is spliced with the signal output by the Q output end of the eleventh D flip-flop DFF11 to form the serial sampling data signal sdi_i_s synchronized with the main frequency clock signal CLK.

In this embodiment, the shift register unit is a multiplexed modular device that is used to implement 2 functions:

first: shifting the serial sampled data signal SDI I reg into the shift register unit at a rising edge of the shift clock signal sck_shift (or chip select shift clock signal sck_shift') to generate a shift register signal shift reg, which is output from the second output terminal of the shift register unit;

second,: performing shift operation on the output parallel data packet to generate a corresponding internal serial data output signal SDO_O, and outputting the signal;

after the shift register unit completes outputting the internal serial data output signal sdo_o, new data in the transmit data buffer module needs to be loaded into the shift register unit again to generate a shift register signal shift_reg.

In this embodiment, the serial sampling signal synchronization unit and the shift register synchronization unit may be both composed of synchronization units, and the synchronization units include a twelfth D flip-flop DFF12 and a thirteenth D flip-flop DFF13, and the structures thereof may be shown in fig. 12;

the input end of the twelfth D trigger DFF12 forms a first input end of the serial sampling signal synchronization unit or a first input end of the shift register synchronization unit; the clock input end of the twelfth D flip-flop DFF12 and the clock input end of the thirteenth D flip-flop DFF13 together form the second input end of the serial sampling signal synchronization unit or the second input end of the shift register synchronization unit; the Q output end of the twelfth D trigger DFF12 is connected with the input end of the thirteenth D trigger DFF 13; the Q output terminal of the thirteenth D flip-flop DFF13 forms the output terminal of the serial sampling signal synchronizing unit or the output terminal of the shift register synchronizing unit.

The synchronization unit can synchronize signals through two stages of flip-flops under the main frequency clock signal CLK, and as shown in fig. 12, signals of asynchronous signals data after passing through twelfth D flip-flop DFF12 and thirteenth D flip-flop DFF13 of the two stages of flip-flops are signals data' synchronized with the main frequency.

In the above embodiment, the clock used by the shift module is the shift clock signal sck_shift, and the shift module may perform data loading and shift on the output parallel data packet in the transmit data buffer module, and the shift module directly generates and outputs the internal serial data output signal sdo_o, where the internal serial data output signal sdo_o is delayed through the serial data output PAD port, and generates and outputs the serial data output signal SDO synchronized with the communication clock signal SCK. The sampling module performs sampling operation on the external-to-internal serial data input signal SDI_I through the sampling clock signal sck_sample to obtain a serial sampling data signal SDI_I_S and an input parallel data packet which is shifted into the shifting module and contains the serial sampling data signal SDI_I_S information, the input parallel data packet enters the synchronous buffer module after being synchronized under the main frequency clock CLK, the serial sampling data signal SDI_I_S synchronized with the main frequency clock signal CLK is generated, and finally the serial sampling data signal SDI_I_S synchronized with the main frequency clock signal CLK in the synchronous buffer module is sent into the receiving data buffer module. The operation process of converting the external serial data input signal SDI into parallel data under the communication clock signal SCK and storing the parallel data into the received data buffer module is realized; and the operation process of finally converting the output parallel data packet in the sending data buffer module into the serial data output signal SDO under the communication clock signal SCK and outputting the serial data output signal SDO is realized. In this embodiment, the sampling module and the synchronous buffer module cooperate together to complete the operation of converting the serial data input signal SDI having a frequency synchronous with the communication clock signal SCK into parallel received data packets input into the received data buffer module; the shift module completes the operation of converting the output parallel transmission data packet output from the transmission data buffer module into the serial data output signal SDO having the frequency synchronized with the communication clock signal SCK. The sending data buffer module and the receiving data buffer module are equivalent to two RAMs or two FIFO memories and are used for storing parallel data packets with fixed bits.

Fig. 13 is a schematic diagram of an operation principle of a shift module in an embodiment, where the shift module is configured to load and generate a shift register signal shift_reg on an output parallel data packet in the transmit data buffer module when a load trigger signal load_time is valid at a rising edge of each shift clock signal sck_shift, shift the shift register signal shift_reg at other moments, shift a head of the shift register signal shift_reg out of the internal serial data output signal sdo_o, and shift a tail of the shift register signal shift_reg into the serial sampling data signal sdi_i_s, which is input data sampled by the sampling clock signal sck_sample.

Specifically, the workflow of the shift register unit in the shift module is:

on the rising edge of each shift clock signal sck_shift (or chip select shift clock signal sck_shift'), when the load trigger signal load_time is active, the output parallel data packet in the transmit data buffer module is loaded into the shift register unit and generates the shift register signal shift_reg. And shifting the shift register signal shift_reg at other moments, shifting the shift register signal shift_reg out of the head of the register, outputting an internal serial data output signal SDO_O, and shifting the tail of the shift register signal shift_reg into the serial sampling data signal SDI_I_S which is input data after sampling is triggered by a sampling clock signal sck_sample.

Referring to fig. 13, taking a shift register unit as an example of an 8-bit shift register, the data in the output parallel data packet output by the transmit data buffer module is 8 bits, the external-to-internal serial data input signal sdi_i input to the serial communication interface is also 8 bits, the 8-bit output parallel data packet is triggered by the load trigger signal load_time and the shift clock signal sck_shift together to be loaded into the shift register unit, then the shift clock signal sck_shift (or the chip select shift clock signal sck_shift') triggers the shift register unit to shift the data in the shift register, when the most significant bit of the data in the output parallel data packet is shifted out, the first bit of the serial sampling data signal sdi_i_s is input to the least significant bit of the shift register unit, and each shifting out one bit of the data in the output parallel data packet is input to the data of one bit of the serial sampling data signal sdi_i_s. I.e. the first 7 serial data have been sampled at 1-7 rising edges of the sampling clock signal sck_sample (or chip select sampling clock signal sck_sample '), shifted at the first 2-8 rising edges of the shift clock signal sck_shift (or chip select shift clock signal sck_shift'), and stored in the first seven bits of the shift register unit, i.e. the first 7 serial data correspond to shift_reg [7:1] in order, are synchronized with the main frequency clock signal CLK, the 8 th data are being sampled at this current point in time, are synchronized with the main frequency clock signal CLK, become the corresponding 8 th sampling clock synchronized rising edge signal sck_sample_syn_pos, the 8 th data just after finishing sampling the current time point and synchronizing under the main frequency clock correspondingly takes a rising edge delay signal sck_sample_syn_pos_d for the 8 th sampling clock, the rising edge delay signal sck_sample_syn_pos_d is extracted by an AND gate and an upper cnt to be equal to 0 "(the eighth serial data is sampled, the seventh serial data is shifted into a shift register), and the generated corresponding signal is a carrying trigger signal send_time, and the carrying trigger signal send_time is effectively triggered at the moment, and the time length is the period of the main frequency clock CLK.

In this embodiment, the counter signal cnt corresponds to the number of serial data received by the shift register unit, and is 0 in the initial state, which indicates that one data is not sampled; when the counter signal cnt is 1, the first serial data is sampled, and the data is only sampled in the state, but the data is not shifted into the shift register unit, and when the counter signal cnt is 2, the second serial data is sampled, and the first serial data is shifted into the shift register unit; when the counter signal cnt is 3, the third serial data is sampled, and the second serial data is shifted into the shift register; similarly, when the counter signal cnt is 7, the seventh serial data is sampled, and the sixth serial data is shifted into the shift register; when the counter signal cnt returns to 0 again, the sampling is described to the eighth serial data, which is shifted into the shift register.

At this time, the eighth data is not required to be shifted into the shift register unit (meanwhile, the eighth sampling data sdi_s_syn is spliced together with the first seven data shift_reg_syn_d [ data_len:1] shifted into the shift register unit by performing the shift operation on the condition that the sampling clock signal sck_sample is generated according to the falling edge of the input clock signal sck_i and the 9 th shift clock signal sck_shift is also not generated according to the rising edge of the internal clock signal sck_o.

During signal processing, at this point in time when the 8 th sampling clock synchronizes the rising edge signal sck_sample_syn_pos, the eighth data is being sampled, and the eighth sampling data sdi_s_syn is still in an unstable state. The shift register synchronous signal shift_reg_syn generates a shift register synchronous delay signal shift_reg_syn_d after passing through the D trigger, the sampling clock synchronous rising edge signal sck_sample_syn_pos generates a sampling clock rising edge delay signal sck_sample_syn_pos_d after passing through the D trigger, which is commonly referred to as the time of each delay of one main frequency clock signal CLK cycle, and the eighth sampling data SDI_S_syn sample is spliced with the eighth sampling data SDI_S_syn after the sampling is stabilized at the effective time point of the output trigger signal sendtime and then sent into the received data buffer unit.

The synchronous buffer module has the main functions of:

when the last bit of one frame of data is sampled by the sampling clock signal sck_sample, the last bit of the shift register signal shift_reg and the serial sampling data signal SDI_S are required to be synchronized with the main frequency clock signal CLK and then sent into the receiving data buffer module; namely, the shift register signal shift_reg output by the shift register unit splices other bit data except the last bit in the serial sampling data signal SDI_S and the serial sampling data signal SDI_I_S which is currently sampled into a receiving data buffer module;

The synchronous buffer module specifically comprises the following operations:

the serial sampling data signal SDI_I_S becomes a serial sampling data synchronizing signal SDI_I_S_syn through a serial sampling signal synchronizing unit under the synchronization of the main frequency clock signal CLK; the shift register signal shift_reg output by the shift register unit is converted into a shift register synchronizing signal shift_reg_syn through a shift register synchronizing unit under the synchronization of a main frequency clock signal CLK, and the shift register synchronizing signal shift_reg_syn is delayed by one beat through an eleventh D trigger DFF11 to generate a delay signal, namely a shift register synchronizing delay signal shift_reg_syn_d; the generated serial sampling data synchronous signal SDI_I_S_syn and the shift register synchronous delay signal shift_reg_syn_d [ data_len:1] are spliced (wherein data_len is a constant indicating the number of data frame bits), and the serial sampling data synchronous signal SDI_I_S synchronized with the main frequency clock signal CLK is sent into the receiving data buffer unit together at the time point when the output trigger signal send_time is high.

As can be seen from fig. 14 to 17, the auxiliary clock generating module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i, generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, and generates the sampling clock signal sck_sample according to the rising edge of the input clock signal sck_i, and generates the phase relationship between the corresponding signals according to the falling edge of the internal clock signal sck_o. Fig. 14 is a timing diagram of generating the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i, and generating the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o; FIG. 15 is a timing diagram of generating the sampling clock signal sck_sample according to the rising edge of the input clock signal SCK_I and generating the shift clock signal sck_shift according to the falling edge of the internal clock signal SCK_O; FIG. 16 is a timing chart showing the phase relationship between the load trigger signal send_time and other signals when the sampling clock signal sck_sample is generated according to the falling edge of the input clock signal SCK_I and the shift clock signal sck_shift is generated according to the rising edge of the internal clock signal SCK_O; fig. 17 is a timing chart showing the phase relationship between the load trigger signal send_time and other signals when the sampling clock signal sck_sample is generated according to the rising edge of the input clock signal sck_i and the shift clock signal sck_shift is generated according to the falling edge of the internal clock signal sck_o.

In the operation of the circuit configuration, before the trigger timing of the trigger signal send_time is carried out, the communication clock signal SCK, the chip select signal CS, the sampling clock signal sck_sample, the shift clock signal sck_shift, the shift register signal shift_reg, the external-to-internal serial data input signal sdi_i and the serial sampling data signal sdi_i_s are synchronized, and belong to the same clock domain, which is asynchronous with the main frequency clock signal CLK.

The clock signal CLK, the synchronized sampling clock signal sck_sample_syn, the counter signal cnt, the sampling clock synchronized falling edge signal sck_sample_syn_neg, the sampling clock synchronized rising edge signal sck_sample_syn_pos, the sampling clock sampling rising edge delay signal sck_sample_syn_pos_d, the serial sampling data synchronizing signal sdi_i_s_syn, the shift register synchronizing signal shift_reg_syn, the shift register synchronizing delay signal shift_reg_syn_d are synchronized in the same clock domain, the operation of the "receive data buffer module" for storing data must be completed under the clock signal CLK, so that the shift data in the shift register signal shift_reg must be synchronized under the clock signal CLK to the shift register synchronizing signal shift_reg_syn_signal sdi_syn, and the shift register synchronizing signal sdi_reg_syn must be operated under the clock signal sdi_signal.

The load_time and the send_time are synchronized with the clock signal CLK.

As can be seen from fig. 14 to 17, in the load trigger module generating the load trigger signal load_time, the output signal shift_reg of the shift register unit is synchronized with the clock phase of the shift clock signal sck_shift, and other signals are synchronized with the main frequency clock signal CLK to ensure the reliability of the digital circuit design.

As can be seen from fig. 9, 16 AND 17, the generation of the send_time is a high-efficiency signal, in the send trigger module, after comparing the counter signal cnt with 0 through the fifth comparator EQU5, the moment of cnt= 0 is extracted, the sampling clock signal sck_sample generates the sampling clock synchronous rising edge signal sck_sample_syn_pos through synchronization with the main frequency clock signal CLK AND edge taking operation, AND the signal is delayed by one beat through the third D flip-flop DFF3 to generate the sampling clock synchronous rising edge delay signal sck_sample_syn_pos_d, AND finally generates the send trigger signal send_time through the second AND gate AND 2.

In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. The circuit structure of the host chip for realizing the full duplex communication of the serial interface is characterized in that the host chip comprises a serial data input PAD port, a serial data output PAD port, a bidirectional clock signal input/output PAD port and a clock generating module;

2. The circuit structure of the host chip for realizing full duplex communication of a serial interface according to claim 1, wherein the bidirectional clock signal input/output PAD port comprises an output buffer and an input buffer;

3. The circuit structure of a host chip for implementing serial interface full duplex communication according to claim 1, wherein said host chip further comprises an auxiliary clock generation module;

4. The circuit structure of a host chip for realizing full duplex communication of a serial interface as claimed in claim 3, wherein,

when the auxiliary clock generation module generates the sampling clock signal sck_sample according to the falling edge of the input clock signal sck_i and generates the shift clock signal sck_shift according to the rising edge of the internal clock signal sck_o, the auxiliary clock generation module inputs the received input clock signal sck_i into a first inverter to perform inversion, so as to obtain the sampling clock signal sck_sample for output, and the auxiliary clock generation module outputs the received internal clock signal sck_o as the shift clock signal sck_shift;

5. The circuit structure of the host chip for realizing serial interface full duplex communication according to claim 4, wherein the host chip further comprises a shift module and a sampling module;

6. The circuit structure of the host chip for realizing full duplex communication of a serial interface according to claim 5, wherein the host chip further comprises a synchronous buffer module, a transmission data buffer module and a reception data buffer module;

And the load_time and the send_time are synchronized with the clock signal CLK.

7. The circuit structure of the host chip for realizing full duplex communication of a serial interface as claimed in claim 6, wherein said load trigger signal load_time is generated by a load trigger module,

8. The circuit structure of the host chip for implementing full duplex communication of serial interface according to claim 7, wherein the send_time of the send trigger signal is generated by a send trigger module, the send trigger module comprises a fifth comparator, a third sampling clock synchronization and edge taking unit, a third D trigger and a second and gate;

9. The circuit structure of a host chip for implementing serial interface full duplex communication according to claim 8, wherein,

the first sampling clock synchronization and edge taking unit and the second sampling clock synchronization and edge taking unit can be composed of a synchronization and edge taking unit, and the synchronization and edge taking unit comprises: a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a fourth inverter, and a third AND gate;

10. The circuit structure of a host chip for realizing serial interface full duplex communication according to claim 7, wherein,

the sampling module comprises a tenth D trigger, and the input end of the tenth D trigger forms a first input end of the sampling module;

11. The circuit structure of the host chip for realizing full duplex communication of a serial interface according to claim 10, wherein the shift module comprises a shift register unit;

12. The circuit structure of the host chip for implementing serial interface full duplex communication according to claim 11, wherein said synchronous buffer module comprises: a serial sampling signal synchronization unit, a shift register synchronization unit, and an eleventh D trigger;

13. The circuit structure of the host chip for realizing full duplex communication of a serial interface according to claim 12, wherein the serial sampling signal synchronization unit and the shift register synchronization unit are both constituted by synchronization units, and the synchronization units include a twelfth D flip-flop and a thirteenth D flip-flop;