CN113626356A

CN113626356A - Circuit structure of host chip for realizing serial interface full duplex communication

Info

Publication number: CN113626356A
Application number: CN202010371706.4A
Authority: CN
Inventors: 刘欣洁; 华纯; 华晶; 李亚菲; 徐佰新
Original assignee: CRM ICBG Wuxi Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2020-05-06
Filing date: 2020-05-06
Publication date: 2021-11-09
Anticipated expiration: 2040-05-06
Also published as: CN113626356B

Abstract

The invention relates to a circuit structure of a host chip for realizing serial interface full duplex communication, wherein the circuit decodes an external-to-internal serial data input signal SDI _ I generated by a serial data input PAD port through an input clock signal SCK _ I generated by a bidirectional clock signal input and output PAD port, and enables the phase of the communication clock signal SCK to be consistent with the phase of a serial data output signal SDO output by the serial data output PAD port so as to ensure that the problem of sampling/shifting errors caused by the time delay of the bidirectional PAD port is avoided. The host chip adopting the structure has the characteristics of high information transmission accuracy, superior performance and low cost, and has wide adaptability.

Description

Circuit structure of host chip for realizing serial interface full duplex communication

Technical Field

The invention relates to the field of communication, in particular to the field of synchronous transmission of serial interfaces, and particularly relates to a circuit structure of a host chip for realizing full-duplex communication of the serial interfaces.

Background

Serial communication is one of computer communication modes, and mainly plays a role in data transmission between a host or a slave and a peripheral. The serial communication has the characteristics of few transmission lines and low cost.

For achieving high-speed transmission rate and transmission efficiency, the serial interface mostly adopts a full-duplex and clock-synchronous communication mode and supports master and slave modes. The chip pin only occupies a serial data line and a synchronous clock line and is connected with an external device through 3 pins, the 3 pins are respectively used for transmitting a serial data input signal SDI, a serial data output signal SDO and a communication clock signal SCK, and a pin for transmitting a chip selection signal CS is required to be added under some conditions.

The interface of the host chip can provide a communication clock signal SCK for an external slave device; the chip select signal CS is used to control whether a corresponding interface of the external slave device is selected. The communication timing sequence synchronous with the communication clock signal SCK is simple, that is, under the control of the host communication clock signal SCK, the serial data input signal SDI and the serial data output signal SDO on the two bidirectional shift data lines perform synchronous data exchange, and the rising edge of the communication clock signal SCK corresponds to data sampling and the falling edge corresponds to data shifting, or the rising edge of the communication clock signal SCK corresponds to data shifting and the falling edge corresponds to data sampling. The communication clock signal SCK in the master mode is generated by the host chip itself and is used directly.

The actual logic circuit inside the chip needs to be connected with each pin through a PAD port of the chip, wherein the PAD port is formed by a metal block. Because the logic circuit inside the chip needs to be connected with each pin through the PAD port of the chip, some signal transmission processes have a delay problem. In the design of the existing full-duplex high-speed serial interface, the problem of the bidirectional PAD port delay from the input/output of the communication interface to the full-duplex high-speed serial interface is not considered, and under high-frequency transmission (the general transmission speed is nanosecond), the input and output delays of the bidirectional PAD port are not negligible, especially the delay time of the PAD port output port easily causes that the serial input data signal SDI on the sampling data line and the serial output data signal SDO on the shifting data line are not synchronous, and have a large phase difference with the communication clock signal SCK used for sampling/shifting, which has a huge challenge to the receivers of both parties to correctly receive the data of the other party, as shown in fig. 1 and2, the problem is specifically as follows:

the signal which is supposed by the user and connected with the external pin interface connected with the host chip through the PAD port comprises a communication clock signal SCK, a serial data input signal SDI and a serial data output signal SDO; however, based on the structural characteristics of the digital circuit logic design of the host chip, i.e. the delay effect caused by the PAD port thereon, the signals actually participating in the operation of the host chip include the internal clock signal SCK _ O, the input clock signal SCK _ I, the external-to-internal serial data input signal SDI _ I, and the internal serial data output signal SDO _ O, and the relationship between these signals and the effect thereof will be further described below:

in the prior art, all signals adopt a synchronous design mode, but because the input/output delay of a PAD port of a chip usually reaches a nanosecond level, the time delay of the PAD port of the chip cannot be ignored for serial data transmission when the high-frequency transmission communication clock signal SCK reaches dozens of megabytes.

It is assumed that the host of the host is a non-ideal host (i.e. there is input/output delay in the bidirectional PAD port of the host), and the slave of the opposite side is an ideal slave (i.e. there is no delay in the bidirectional PAD port of the slave).

When the serial data input signal SDI transmitted by the signal line of the slave of the other party is generated by the clock signal SCK received by the serial data input signal SDI and transmitted to the host of the other party as shown in fig. 1 (fig. 1 is only used for explaining the delay problem, and therefore, only some relevant parts and ports are drawn, and not all functional modules in the host chip), the internal clock signal SCK _ O of the host chip is output to the PAD port to generate the communication clock signal SCK, and the delay experienced by the internal clock signal SCK _ O is the delay (at least 10ns delay) caused by the output of the PAD port. The serial data input signal SDI is generated by the communication clock signal SCK and is in phase with the communication clock signal SCK, the signal input into the serial communication interface to generate the out-to-in serial data input signal SDI _ I also needs to experience PAD input delay (delay of at least 3 ns), and the phase difference between the internal clock signal SCK _ O and the out-to-in serial data input signal SDI _ I is bidirectional PAD output delay + bidirectional PAD input delay (delay of at least 13 ns), which may cause sampling errors due to the relative phases.

It can be seen more clearly by combining the timing diagram in fig. 2 (the timing diagram in fig. 2 is a timing diagram when serial port communication samples at the rising edge of the communication clock signal SCK and shifts at the falling edge, and fig. 2 plots a timing relationship among the internal clock signal SCK _ O, the communication clock signal SCK, the serial input data signal SDI, and the external-to-internal serial data input signal SDI _ I), that, when the input data (i.e., the external-to-internal serial data input signal SDI _ I) is sampled at the rising edge of the internal clock signal SCK _ O in the manner in the prior art, the sampling is very prone to error when the data of the external-to-internal serial data input signal SDI _ I is not stable.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a circuit structure of a host chip for realizing serial interface full-duplex communication, which has the advantages of accurate sampling, no time delay and wide application range.

In order to achieve the above object, the circuit structure of the host chip for realizing serial interface full duplex communication according to the present invention is as follows:

the circuit structure of the host chip for realizing the serial interface full duplex communication is mainly characterized in that the host chip comprises a serial data input PAD port, a serial data output PAD port, a bidirectional clock signal input and output PAD port and a clock generation module;

an external serial data input signal SDI is input through the serial data input PAD port, and then an external-to-internal serial data input signal SDI _ I is generated;

the clock generation module is used for generating an internal clock signal SCK _ O and is connected with the first end of the internal connection end of the bidirectional clock signal input and output PAD port;

after the internal clock signal SCK _ O is output through the first end of the internal connection end of the bidirectional clock signal input and output PAD port, a communication clock signal SCK is generated and output from the external connection end of the bidirectional clock signal input and output PAD port, and an input clock signal SCK _ I is generated and output through the second end of the internal connection end of the bidirectional clock signal input and output PAD port, wherein the input clock signal SCK _ I is used for decoding the external-to-internal serial data input signal SDI _ I;

the phase of the communication clock signal SCK is consistent with the phase of the serial data output signal SDO output by the serial data output PAD port.

Preferably, the bidirectional clock signal input/output PAD port includes an output buffer and an input buffer;

the input end of the output buffer forms the first end of the internal connection end of the bidirectional clock signal input and output PAD port; the output end of the input buffer forms the second end of the internal connection end of the bidirectional clock signal input and output PAD port; the output end of the output buffer is connected with the input end of the input buffer;

and the output end of the output buffer forms the external end of the bidirectional clock signal input and output PAD port.

Preferably, the host chip further comprises an auxiliary clock generating module;

the first end of the auxiliary clock generation module is connected with the clock generation module and receives the internal clock signal SCK _ O; the second end of the auxiliary clock generation module is connected with the second end of the bidirectional clock signal input and output PAD port and receives the input clock signal SCK _ I;

the auxiliary clock generation module generates a shift clock signal SCK _ shift according to the internal clock signal SCK _ O;

the auxiliary clock generating module generates a sampling clock signal SCK _ sample according to the input clock signal SCK _ I.

Preferably, when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to a falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to a rising edge of the internal clock signal SCK _ O, the auxiliary clock generating module inputs the received input clock signal SCK _ I into the first inverter for inversion to obtain the sampling clock signal SCK _ sample output, and the auxiliary clock generating module outputs the received internal clock signal SCK _ O as the shift clock signal SCK _ shift;

when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the auxiliary clock generation module outputs the received input clock signal SCK _ I as the sampling clock signal SCK _ sample, and inputs the received internal clock signal SCK _ O into the second inverter for inversion to obtain the shift clock signal SCK _ shift output.

Furthermore, the host chip also comprises a shifting module and a sampling module;

a first input end of the sampling module is connected with the external-to-internal serial data input signal SDI _ I;

the shift clock signal sck _ shift and the sampling clock signal sck _ sample are not synchronous with the main frequency clock signal CLK;

triggering the sampling module by the sampling clock signal sck _ sample to perform sampling operation on the external-to-internal serial data input signal SDI _ I to generate a serial sampling data signal SDI _ I _ S;

and triggering the shifting module to shift data in an output parallel data packet to be sent by the shifting clock signal sck _ shift to generate a corresponding internal serial data output signal SDO _ O, and generating the serial data output signal SDO after the internal serial data output signal SDO _ O is output through the serial data output PAD port.

Furthermore, the host chip also comprises a synchronous cache module, a sending data cache module and a receiving data cache module;

the synchronous cache module acquires the serial sampling data signal SDI _ I _ S and synchronizes the serial sampling data signal SDI _ I _ S with the main frequency clock signal CLK;

the first input end of the shifting module is connected with the sending data caching module;

the sending data buffer module is triggered by a loading trigger signal load _ time and the shifting clock signal sck _ shift together to send the output parallel data packet to the shifting module; wherein, the trigger time of the loading trigger signal load _ time is as follows: avoiding the moment when the shifting module shifts the data in the output parallel data packet;

triggering the receiving data buffer module by a load trigger signal send _ time to receive a serial sampling data signal SDI _ I _ S which is synchronized with the main frequency clock signal CLK from the synchronous buffer module; wherein, the trigger time of the loading trigger signal send _ time is as follows: when any two adjacent serial sampling data signals SDI _ I _ S synchronized with the main frequency clock signal CLK are received by the received data caching module, after sampling of the last bit data bit in the received serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK in the previous frame is completed, the received serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK in the next frame is sampled at the time before shifting is not started after the sampling of the first bit data bit in the received serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK is completed;

and the load trigger signal load _ time and the load trigger signal send _ time are both synchronous with the main frequency clock signal CLK.

Furthermore, the load trigger signal load _ time is generated by the load trigger module,

when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O,

the loading trigger module comprises a first sampling clock synchronous edge taking unit, a first counter generating unit, a first NAND gate, a second NAND gate, a first comparator, a second comparator and a first D trigger;

the first sampling clock synchronization and edge-taking unit has a first input end connected with the sampling clock signal sck _ sample, a second input end connected with the main frequency clock signal CLK, a second sampling clock synchronization and edge-taking unit synchronizes the sampling clock signal sck _ sample under the main frequency clock signal CLK and takes down the falling edge to generate a sampling clock synchronization falling edge signal sck _ sample _ syn _ neg, and an output end of the first sampling clock synchronization and edge-taking unit outputs the sampling clock synchronization falling edge signal sck _ sample _ syn _ neg;

the output end of the first sampling clock synchronization and edge-taking unit is respectively connected with the first end of the first counter generation unit, the first end of the first NAND gate and the first end of the second NAND gate;

the second end of the first counter generating unit is connected with the main frequency clock signal CLK, the output end of the first counter generating unit outputs a counter signal cnt, and the output end of the first counter generating unit is respectively connected with the first input end of the first comparator, the first input end of the second comparator and the feedback end of the first counter generating unit;

the second input end of the first comparator is connected with zero, the output end of the first comparator is connected with the second end of the first NAND gate, and the output end of the first NAND gate is connected with the set end of the first D flip-flop;

a second input end of the second comparator is connected with a preset constant, a value of the preset constant corresponds to a data bit width of the output parallel data packet sent by the sending data cache module, an output end of the second comparator is connected with a second end of the second nand gate, and an output end of the second nand gate is connected with a reset end of the first D flip-flop;

the clock input end of the first D flip-flop is connected with the main frequency clock signal CLK, the Q output end of the first D flip-flop is connected with the input end of the first D flip-flop, and the Q non-output end of the first D flip-flop outputs the load trigger signal load _ time;

when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O,

the host chip further comprises a chip selection signal generation module and a first OR gate, wherein the chip selection signal generation module is used for generating a chip selection signal CS, a first input end of the first OR gate is connected with the sampling clock signal sck _ sample, a second input end of the first OR gate is connected with the chip selection signal CS, and an output end of the first OR gate outputs a chip selection sampling clock signal sck _ sample';

the loading trigger module comprises a second sampling clock synchronization and edge taking unit, a chip selection signal synchronization and edge taking unit, a second counter generation unit, a third NAND gate, a fourth NAND gate, a third comparator, a fourth comparator, a first AND gate, a third inverter and a second D trigger;

the first input end of the second sampling clock synchronization and edge-taking unit is connected with the chip selection sampling clock signal sck _ sample ', the second input end of the second sampling clock synchronization and edge-taking unit is connected with the main frequency clock signal CLK, the second sampling clock synchronization and edge-taking unit synchronizes and takes down the falling edge of the chip selection sampling clock signal sck _ sample' under the main frequency clock signal CLK to generate a sampling clock synchronization falling edge signal sck _ sample _ syn _ neg, and the output end of the second sampling clock synchronization and edge-taking unit outputs the sampling clock synchronization falling edge signal sck _ sample _ syn _ neg;

the output end of the second sampling clock synchronization and edge-taking unit is respectively connected with the first end of the second counter generation unit, the first end of the third NAND gate and the first end of the fourth NAND gate;

the first input end of the chip selection signal synchronization and edge taking unit is connected with the chip selection signal CS, and the second input end of the chip selection signal synchronization and edge taking unit is connected with the main frequency clock signal CLK; the chip selection signal synchronization and edge-taking unit synchronizes the chip selection signal CS under the main frequency clock signal CLK to generate a chip selection synchronous signal CS _ syn, and the first output end of the chip selection signal synchronization and edge-taking unit outputs the chip selection synchronous signal CS _ syn; the chip selection signal synchronization and edge-taking unit synchronizes the chip selection signal CS under the main frequency clock signal CLK and takes a rising edge to generate a chip selection synchronization rising edge signal CS _ syn _ pos, and a second output end of the chip selection signal synchronization and edge-taking unit outputs the chip selection synchronization rising edge signal CS _ syn _ pos;

the second end of the second counter generating unit is connected with the main frequency clock signal CLK, the third end of the second counter generating unit is connected with the chip selection synchronizing signal CS _ syn, the output end of the second counter generating unit outputs a counter signal cnt, and the output end of the second counter generating unit is respectively connected with the first input end of the third comparator, the first input end of the fourth comparator and the feedback end of the second counter generating unit;

the second input end of the third comparator is connected with zero, the output end of the third comparator is connected with the second end of the third NAND gate, and the output end of the third NAND gate is connected with the set end of the second D flip-flop;

a second input end of the fourth comparator is connected with a preset constant, a value of the preset constant corresponds to a data bit width of the output parallel data packet sent by the sending data cache module, an output end of the fourth comparator is connected with a second end of the fourth nand gate, and an output end of the fourth nand gate is connected with a first input end of the first and gate;

the input end of the third inverter is connected with the chip selection synchronous rising edge signal CS _ syn _ pos, the output end of the third inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate is connected with the reset end of the second D trigger;

the clock input end of the second D flip-flop is connected with the main frequency clock signal CLK, the Q output end of the second D flip-flop is connected with the input end of the second D flip-flop, and the Q non-output end of the second D flip-flop outputs the load trigger signal load _ time.

Furthermore, the load-out trigger signal send _ time is generated by a load-out trigger module, and the load-out trigger module comprises a fifth comparator, a third sampling clock synchronization and edge-taking unit, a third D flip-flop and a second and gate;

the first input end of the fifth comparator is connected with zero, the second input end of the fifth comparator is connected with the counter signal cnt, and the output end of the fifth comparator is connected with the first input end of the second AND gate;

when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the third sampling clock is synchronous, and the first input end of the edge taking unit is connected with the sampling clock signal SCK _ sample; the second input end of the third sampling clock synchronization and edge taking unit is connected with the main frequency clock signal CLK, and the third sampling clock synchronization and edge taking unit synchronizes the sampling clock signal sck _ sample under the main frequency clock signal CLK and takes a rising edge to generate a sampling clock synchronization rising edge signal sck _ sample _ syn _ pos; when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the first input end of the third sampling clock synchronization and edge taking unit is connected with the chip selection sampling clock signal SCK _ sample ', the second input end of the third sampling clock synchronization and edge taking unit is connected with the main clock signal CLK, and the third sampling clock synchronization and edge taking unit synchronizes the chip selection sampling clock signal SCK _ sample' under the main clock signal CLK and takes the rising edge to generate a sampling clock synchronization rising edge signal SCK _ sample _ syn _ pos;

the output end of the third sampling clock synchronization and edge taking unit outputs the sampling clock synchronization rising edge signal sck _ sample _ syn _ pos;

the clock input end of the third D flip-flop is connected with the main frequency clock signal CLK, the input end of the third D flip-flop is synchronous with the third sampling clock and is connected with the output end of the edge taking unit, and the Q output end of the third D flip-flop is connected with the second input end of the second AND gate;

and the output end of the second AND gate outputs the load trigger signal send _ time.

Furthermore, the first sampling clock synchronization and edge taking unit and the second sampling clock synchronization and edge taking unit can be both composed of a synchronization and edge taking-down unit, and the synchronization and edge taking-down unit includes: a fourth D trigger, a fifth D trigger, a sixth D trigger, a fourth inverter and a third AND gate;

the input end of the fourth D flip-flop forms the first input end of the first sampling clock synchronization and edge taking unit or the first input end of the second sampling clock synchronization and edge taking unit; the clock input end of the fourth D flip-flop, the clock input end of the fifth D flip-flop and the clock input end of the sixth D flip-flop form the first sampling clock synchronization and edge taking unit or the second sampling clock synchronization and edge taking unit;

the Q output end of the fourth D trigger is connected with the input end of the fifth D trigger; the Q output end of the fifth D trigger is respectively connected with the input end of the sixth D trigger and the input end of the fourth inverter;

the output end of the fourth inverter is connected with the first output end of the third AND gate; the Q output end of the sixth D trigger is connected with the second output end of the third AND gate; the output end of the third AND gate forms the output end of the first sampling clock synchronization and edge taking unit or the output end of the second sampling clock synchronization and edge taking unit;

the chip selection signal synchronization and edge taking unit and the third sampling clock synchronization and edge taking unit can be composed of a synchronization and rising edge taking unit, and the synchronization and rising edge taking unit comprises: a seventh D flip-flop, an eighth D flip-flop, a ninth D flip-flop, a fifth inverter, and a fourth AND gate;

the input end of the seventh D flip-flop forms the first input end of the edge unit or the first input end of the edge unit; the clock input end of the seventh D flip-flop, the clock input end of the eighth D flip-flop and the clock input end of the ninth D flip-flop form the second input end of the chip selection signal synchronization and edge taking unit or the second input end of the third sampling clock synchronization and edge taking unit together;

the Q output end of the seventh D trigger is connected with the input end of the eighth D trigger; the Q output end of the eighth D trigger is respectively connected with the input end of the ninth D trigger and the first input end of the fourth AND gate; the Q output end of the eighth D trigger forms a first output end of the chip selection signal synchronization and edge taking unit;

the Q output end of the ninth D trigger is connected with the second input end of the fourth AND gate through the fifth inverter;

and the output end of the fourth AND gate forms the second output end of the edge unit or the output end of the edge unit.

Furthermore, the sampling module comprises a tenth D flip-flop, and an input terminal of the tenth D flip-flop constitutes the first input terminal of the sampling module;

when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the clock input end of the tenth D flip-flop is connected with the sampling clock signal SCK _ sample; when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the clock input end of the tenth D flip-flop is connected with the chip selection sampling clock signal SCK _ sample';

and the Q output end of the tenth D flip-flop outputs the serial sampling data signal SDI _ I _ S.

Furthermore, the shift module comprises a shift register unit;

the first input end of the shift register unit forms the first input end of the shift module, and the second input end of the shift register unit is connected with the load trigger signal load _ time;

when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the clock input end of the shift register unit is connected with the shift clock signal SCK _ shift; when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the host chip further includes a sixth inverter and a fifth and gate, the chip select signal CS is input to the first input end of the fifth and gate through the sixth inverter, the second input end of the fifth and gate is connected to the shift clock signal SCK _ shift, the output end of the fifth and gate outputs a chip select shift clock signal SCK _ shift ', and the clock input end of the shift register unit is connected to the chip select shift clock signal SCK _ shift';

the first output terminal of the shift register unit outputs the internal serial data output signal SDO _ O.

Furthermore, the synchronous cache module comprises: the device comprises a serial sampling signal synchronization unit, a shift register synchronization unit and an eleventh D trigger;

a first input end of the serial sampling signal synchronization unit is connected with a Q output end of the tenth D flip-flop, a second input end of the serial sampling signal synchronization unit is connected with the main frequency clock signal CLK, and an output end of the serial sampling signal synchronization unit is connected with a first input end of the received data caching module;

a Q output end of the tenth D flip-flop is connected to the third input end of the shift register unit, a second output end of the shift register unit is connected to the first input end of the shift register synchronizing unit, a second input end of the shift register synchronizing unit is connected to the master clock signal CLK, an output end of the shift register synchronizing unit is connected to an input end of the eleventh D flip-flop, a clock input end of the eleventh D flip-flop is connected to the master clock signal CLK, and a Q output end of the eleventh D flip-flop is connected to the second input end of the received data buffer module;

the third input end of the received data buffer module is connected with the main frequency clock signal CLK, and the fourth input end of the received data buffer module is connected with the load-out trigger signal send _ time;

and the serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK is formed by splicing the signal output by the output end of the serial sampling signal synchronization unit and the signal output by the Q output end of the eleventh D trigger.

Furthermore, the serial sampling signal synchronization unit and the shift register synchronization unit can both be composed of synchronization units, and each synchronization unit comprises a twelfth D trigger and a thirteenth D trigger;

the input end of the twelfth D trigger forms the first input end of the serial sampling signal synchronization unit or the first input end of the shift register synchronization unit; the clock input end of the twelfth D flip-flop and the clock input end of the thirteenth D flip-flop jointly form a second input end of the serial sampling signal synchronization unit or a second input end of the shift register synchronization unit; the Q output end of the twelfth D trigger is connected with the input end of the thirteenth D trigger; the Q output terminal of the thirteenth D flip-flop constitutes the output terminal of the serial sampling signal synchronization unit or the output terminal of the shift register synchronization unit.

By adopting the circuit structure of the host chip for realizing the serial interface full duplex communication, the input clock signal SCK _ I generated by the bidirectional clock signal input and output PAD port is used for decoding the data received by the serial data input signal SDI _ I serial data input PAD port generated by the serial data input PAD port, and the phase of the communication clock signal SCK is consistent with the phase of the serial data output signal SDO output by the serial data output PAD port, so that the problem of sampling/shifting error caused by the time delay of the bidirectional PAD port is solved. The circuit structure of the host chip for realizing the serial interface full duplex communication has the characteristics of high information transmission accuracy, superior performance and low cost, and has wide adaptability.

Drawings

Fig. 1 is a schematic diagram illustrating a signal transmission state of a serial interface full-duplex communication circuit in the prior art.

Fig. 2 is a timing diagram of signals in fig. 1.

Fig. 3 is a schematic diagram of a circuit configuration of a host chip for implementing serial interface full duplex communication according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a bidirectional clock input/output PAD port according to an embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating a signal transmission state of a circuit structure of a host chip for implementing serial interface full duplex communication according to an embodiment of the present invention.

Fig. 6a is a logic diagram of an auxiliary clock generation module according to an embodiment of the present invention for generating a sampling signal and a shift signal.

Fig. 6b is a logic diagram of an auxiliary clock generation module according to another embodiment of the present invention for generating a sampling signal and a shift signal.

Fig. 7 is a schematic diagram illustrating a module relationship of a host chip in a circuit structure of the host chip for implementing serial interface full duplex communication according to an embodiment of the present invention.

Fig. 8a is a schematic structural diagram of a load trigger module according to an embodiment of the present invention.

Fig. 8b is a schematic structural diagram of a load trigger module according to another embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a load-out trigger module according to an embodiment of the invention.

FIG. 10 is a schematic diagram of a synchronization and falling edge unit according to an embodiment of the present invention.

FIG. 11 is a block diagram of a synchronization and rising edge fetch unit according to an embodiment of the present invention.

Fig. 12 is a schematic structural diagram of a synchronization unit according to an embodiment of the invention.

Fig. 13 is a schematic diagram illustrating an operation principle of the shift module according to an embodiment of the present invention.

Fig. 14 is a timing diagram of generating the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generating the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O.

Fig. 15 is a timing diagram of generating the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generating the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O.

Fig. 16 is a timing diagram showing the phase relationship between the output trigger signal send _ time and other signals when the sampling clock signal SCK _ sample is generated according to the falling edge of the input clock signal SCK _ I and the shift clock signal SCK _ shift is generated according to the rising edge of the internal clock signal SCK _ O.

Fig. 17 is a timing diagram showing the phase relationship between the output trigger signal send _ time and other signals when the sampling clock signal SCK _ sample is generated according to the rising edge of the input clock signal SCK _ I and the shift clock signal SCK _ shift is generated according to the falling edge of the internal clock signal SCK _ O.

Detailed Description

In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.

As shown in fig. 3 to 12, the circuit structure of the host chip for implementing serial interface full duplex communication according to the present invention includes a clock generation module, an auxiliary clock generation module, a sampling module, a shift module, and a synchronous buffer module, and further includes a chip select signal generation module when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, and the specific circuit is as follows:

as shown in fig. 3, the host chip includes a serial data input PAD port, a serial data output PAD port, a bidirectional clock signal input/output PAD port, and a clock generation module;

By adopting the circuit structure of the host chip for realizing the serial interface full duplex communication in the embodiment, the internal clock signal SCK _ O is not directly used for processing serial input/output data, but the internal clock signal SCK _ O is output and delayed through the bidirectional clock signal input/output PAD port, then is input and delayed through the bidirectional clock signal input/output PAD port, and then is taken as the input clock signal SCK _ I. The sampling and shifting operations of the data are realized by two different clocks, a sampling clock signal sck _ sample and a shifting clock signal sck _ shift.

The method can effectively solve the problem of wrong sampling or shifting of signals caused by the time delay of the bidirectional PAD port in the main mode (namely, the problem that the PAD output time delay exists when clock signals generated by the own party pass through the bidirectional PAD port in the main mode), keeps the phase consistency of the serial data output signal SDO and the communication clock signal SCK on the premise of the reliability design of a digital circuit, and simultaneously ensures that the sampling of the own party cannot be influenced by the time delay of the bidirectional PAD port to cause sampling errors.

As shown in fig. 4, in this embodiment, the bi-directional clock input/output PAD port includes an output buffer and an input buffer;

As shown in FIG. 4, the bidirectional clock input/output PAD port can be understood as a structure of a bidirectional I/O buffer, wherein an internal clock signal SCK _ O is input from a PAD _ O port, an input clock signal SCK _ I is output from the PAD _ I port, a port for outputting a communication clock signal SCK is Bonding PAD (i.e. an external pin Bonding port), the internal clock signal SCK _ O is generated by a host chip, a PAD _ OE can be configured by a circuit host CPU, an enable signal is output for the bidirectional I/O buffer for setting the bidirectional clock input/output PAD port to be in an output mode or an input mode, in the main mode, the PAD _ OE is set to be in the output mode but not set to block the input of the signals at the PAD _ I port, the signals at the PAD _ I port are accumulated signals input and output from the PAD _ O port after the output delay and the input delay of the bidirectional clock signal input/output PAD port are delayed, namely, the internal clock signal SCK _ O is the input clock signal SCK _ I generated after the output delay + the input delay of the bidirectional PAD port.

In this embodiment, the host chip further includes an auxiliary clock generation module;

In other words, in the circuit structure of the host chip for implementing serial interface full duplex communication in this embodiment, in order to re-input the communication clock signal SCK obtained after delaying the internal clock signal SCK _ O generated inside the circuit through the bidirectional clock signal input/output PAD port from the bidirectional clock signal input/output PAD port to obtain the input clock signal SCK _ I, the input clock signal SCK _ I is used to sample the external serial data input signal SDI _ I to the internal serial data input signal SDI _ I, that is, the sampling accuracy is ensured by the process of outputting and returning the sampling clock through the bidirectional clock signal input/output PAD port. In the master mode, the selected shift clock signal SCK _ shift is not returned through the PAD port, but is shifted by the internal clock signal SCK _ O, and the processing of the internal clock signal SCK _ O is completed in the auxiliary clock generation unit.

The relationship between signals in the circuit structure of the host chip for implementing serial interface full duplex communication according to the present invention will be further described with reference to fig. 5, where the bidirectional clock input/output PAD port is equivalent to the combination of the serial data input PAD port and the serial data output PAD port.

Taking the case that the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I, and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O as an example:

an internal clock signal SCK _ O is generated in a master mode, the internal clock signal SCK _ O is delayed through a bidirectional clock signal input/output PAD port to output a delayed signal, namely a communication clock signal SCK, the internal clock signal SCK _ O generates a shift clock signal SCK _ shift through combinational logic shown in fig. 6a in an auxiliary clock generation unit, in a shift module, parallel data are shifted on each rising edge of the shift clock signal SCK _ shift to generate an internal serial data output signal SDO _ O, the internal serial data output signal SDO _ O is delayed through a serial data output PAD port to output a delayed signal, namely a serial data output signal SDO. The internal clock signal SCK _ O and the internal serial data output signal SDO _ O are always aligned, and similarly, after the bidirectional clock signal input/output PAD port with the same characteristics is delayed, the communication clock signal SCK and the serial data output signal SDO are always aligned, that is, no phase difference exists between the communication clock signal SCK and the serial data output signal SDO.

The serial data input signal SDI and the communication clock signal SCK have no phase difference (on the basis that the opposite slave is an ideal slave), the serial data input signal SDI is subjected to input delay through a serial data input PAD port to generate a delayed signal, namely an external-to-internal serial data input signal SDI, the communication clock signal SCK is subjected to input delay through a bidirectional clock signal input and output PAD port to generate a delayed signal, namely an input clock signal SCK _ I, and after input delay through the PAD port with the same characteristics, no phase difference exists between the input clock signal SCK _ I and the external-to-internal serial data input signal SDI _ I. The input clock signal SCK _ I generates a sampling clock signal SCK _ sample in the auxiliary clock generating module shown in fig. 6a, and under the combined action of the sampling module and the synchronous buffer module, the sampling clock signal SCK _ sample performs in-phase sampling on the external-to-internal serial data input signal SDI _ I to generate parallel sampling data, so that the sampling is correct.

Under the condition that the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I, generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the working principle of the auxiliary clock generating module is similar to the condition that the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I, and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, except that the shift clock signal SCK _ shift is replaced by a chip shift clock signal SCK _ shift 'formed by the shift clock signal SCK _ shift generated by the combinational logic in fig. 6b and a chip select signal CS, and the sampling clock signal SCK _ shift is replaced by a sampling clock signal SCK _ sample' formed by the sampling clock signal SCK _ sample generated by the combinational logic in fig. 6b and the chip select signal CS Therefore, the working principle thereof will not be described again.

As shown in fig. 6a, in this embodiment, when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the auxiliary clock generation module inputs the received input clock signal SCK _ I into the first inverter for inversion to obtain the sampling clock signal SCK _ sample output, and the auxiliary clock generation module outputs the received internal clock signal SCK _ O as the shift clock signal SCK _ shift;

as shown in fig. 6b, when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the auxiliary clock generation module outputs the received input clock signal SCK _ I as the sampling clock signal SCK _ sample, and the auxiliary clock generation module inputs the received internal clock signal SCK _ O into the second inverter for inversion, so as to obtain the shift clock signal SCK _ shift output.

As shown in fig. 3, in this embodiment, the host chip further includes a shift module and a sampling module;

In this embodiment, the host chip further includes a synchronization buffer module, a transmission data buffer module, and a reception data buffer module;

namely, the load trigger signal load _ time is active at a high level, and the timing of the high level is selected to avoid the timing of shifting the internal data by the shift register unit, and the timing of the high level is also understood to be the trigger timing of screening the parallel data in the sending data buffer unit to be loaded into the shift register unit.

that is, the trigger time of the loading trigger signal send _ time is between the sampling of the last bit of the first frame of sampled data and the shifting of the first bit of the second frame of data, and for a frame of 8-bit data, the trigger time of the loading trigger signal send _ time is the rising edge of the 8 th sampling clock signal, that is, the current time point at which the 8 th data just completes sampling.

Fig. 7 shows a module relationship of a host chip in a circuit structure of the host chip for implementing serial interface full duplex communication according to this embodiment, where fig. 7 shows a schematic diagram of a case where the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to a rising edge of the input clock signal SCK _ I, and generates the shift clock signal SCK _ shift according to a falling edge of the internal clock signal SCK _ O; when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I AND generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the chip select signal generating module, the first or gate, the fifth AND gate AND5 AND the corresponding inverters in fig. 7 are only needed to be omitted, AND the sampling clock signal SCK _ sample AND the shift clock signal SCK _ shift directly replace the chip select sampling clock signal SCK _ sample 'AND the chip select shift clock signal SCK _ shift' to trigger the corresponding sampling module, the loading trigger module AND the shift module to work, so that the corresponding picture is not drawn.

When the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I, and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the chip-select sampling clock signal SCK _ sample 'formed by the sampling clock signal SCK _ sample and the chip-select signal CS replaces the sampling clock signal SCK _ sample to trigger sampling, and the chip-select shift clock signal SCK _ shift' formed by the shift clock signal SCK _ shift and the chip-select signal CS replaces the shift clock signal SCK _ shift to trigger shifting, because in this case, if the shift operation is triggered only by the shift clock signal SCK _ shift, the first rising edge of the shift clock signal SCK _ shift is staggered with the enabled portion of the load trigger signal load _ time, the function of sending the data buffer module to send the output parallel data packet to the shift module cannot be triggered, therefore, the chip select sampling clock signal sck _ sample 'and the chip select shift clock signal sck _ shift' are adopted.

In this embodiment, the load trigger signal load _ time is generated by a load trigger module,

as shown in fig. 8a, when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O,

the load trigger module comprises a first sampling clock synchronization and edge taking unit, a first counter generation unit, a first NAND gate NAND1, a second NAND gate NAND2, a first comparator EQU1, a second comparator EQU2 and a first D flip-flop DFF 1;

the output end of the first sampling clock synchronization and edge-taking unit is respectively connected with the first end of the first counter generation unit, the first end of the first NAND gate NAND1 and the first end of the second NAND gate NAND 2;

a second end of the first counter generating unit is connected to the main frequency clock signal CLK, an output end of the first counter generating unit outputs a counter signal cnt, and output ends of the first counter generating unit are respectively connected to a first input end of the first comparator EQU1, a first input end of the second comparator EQU2, and a feedback end of the first counter generating unit;

a second input end of the first comparator EQU1 is connected to zero, an output end of the first comparator EQU1 is connected to a second end of the first NAND gate NAND1, and an output end of the first NAND gate NAND1 is connected to a set end of the first D flip-flop DFF 1;

a second input end of the second comparator EQU2 is connected to a preset constant, a value of the preset constant corresponds to a data bit width of the output parallel data packet sent by the send data buffer module, an output end of the second comparator EQU2 is connected to a second end of the second NAND gate NAND2, and an output end of the second NAND gate NAND2 is connected to a reset end of the first D flip-flop DFF 1;

a clock input terminal of the first D flip-flop DFF1 is connected to the main frequency clock signal CLK, a Q output terminal of the first D flip-flop DFF1 is connected to an input terminal of the first D flip-flop DFF1, and a Q non-output terminal of the first D flip-flop DFF1 outputs the load trigger signal load _ time;

the chip select sampling clock signal SCK _ sample' in this embodiment is actually generated by the sampling clock signal SCK _ sample obtained by processing the input clock signal SCK _ I by the auxiliary clock generation module and the chip select signal CS after the combination logic.

As shown in fig. 8b, the load trigger module includes a second sampling clock synchronization AND edge fetching unit, a chip select signal synchronization AND edge fetching unit, a second counter generation unit, a third NAND gate NAND3, a fourth NAND gate NAND4, a third comparator EQU3, a fourth comparator EQU4, a first AND gate AND1, a third inverter, AND a second D flip-flop DFF 2;

the output end of the second sampling clock synchronization and edge-taking unit is respectively connected with the first end of the second counter generation unit, the first end of the third NAND gate NAND3 and the first end of the fourth NAND gate NAND 4;

a second end of the second counter generating unit is connected to the main frequency clock signal CLK, a third end of the second counter generating unit is connected to the chip selection synchronizing signal CS _ syn, an output end of the second counter generating unit outputs a counter signal cnt, and output ends of the second counter generating unit are respectively connected to a first input end of the third comparator EQU3, a first input end of the fourth comparator EQU4, and a feedback end of the second counter generating unit;

a second input end of the third comparator EQU3 is connected to zero, an output end of the third comparator EQU3 is connected to a second end of the third NAND gate NAND3, and an output end of the third NAND gate NAND3 is connected to a set end of the second D flip-flop DFF 2;

a second input end of the fourth comparator EQU4 is connected to a preset constant, a value of the preset constant corresponds to a data bit width of the output parallel data packet sent by the send data buffer module, an output end of the fourth comparator EQU4 is connected to a second end of the fourth NAND gate NAND4, AND an output end of the fourth NAND gate NAND4 is connected to a first input end of the first AND gate AND 1;

the input end of the third inverter is connected with the chip selection synchronous rising edge signal CS _ syn _ pos, the output end of the third inverter is connected with the second input end of the first AND gate AND1, AND the output end of the first AND gate AND1 is connected with the reset end of the second D flip-flop DFF 2;

a clock input terminal of the second D flip-flop DFF2 is connected to the main frequency clock signal CLK, a Q output terminal of the second D flip-flop DFF2 is connected to an input terminal of the second D flip-flop DFF2, and a Q non-output terminal of the second D flip-flop DFF2 outputs the load trigger signal load _ time.

Under any precondition (no matter the sampling clock signal SCK _ sample is generated according to the rising edge of the input clock signal SCK _ I or the sampling clock signal SCK _ sample is generated according to the falling edge of the input clock signal SCK _ I), the load trigger signal load _ time must return to the reset state (high level state) after the transmission of one frame of data is finished.

In the scheme that the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the chip selection synchronous rising edge signal CS _ syn _ pos is used for resetting the load trigger signal load _ time. In fig. 8b, the generated falling edge rn is reset by the reset terminal clr of the second D flip-flop DFF2, and a rising edge of the load trigger signal load _ time is generated, so that the load trigger signal load _ time returns to a reset state, i.e., a high level state, after the transmission of one frame of data is finished.

Meanwhile, in the scheme, one necessary condition for the counter generation unit to clear 0 is that the chip selection synchronization signal CS _ syn is high, data transmission is finished, and if the counter signal cnt is cleared to zero and the counter signal cnt is not high, the counter signal cnt will stop at 1 and not reach the initial value 0 at last. As shown in fig. 15, there are 9 sampling clock synchronous falling edge signals sck _ sample _ syn _ neg in total, when the high level of each sampling clock synchronous falling edge signal sck _ sample _ syn _ neg is active, the counter signal cnt is increased by 1, the count of the counter signal cnt can only count 0-7 and is finally increased to 1, and after the 8-bit data transmission of one frame is finished, the counter signal cnt is cleared again by 0 under the condition that the high level of the chip selection synchronous signal cs _ syn is active, so that the counter signal cnt returns to the initial state.

The first counter generation unit and the second counter generation unit have the functions of: recording the number of the currently sent and received frame of serial data, wherein a counter signal cnt is 0 in a reset state, which indicates that the first data is not sampled and is not sent at the same time; when the counter signal cnt is 1, the first serial data to be received is sampled, and only the first serial data to be received is sampled currently, but the data is not shifted into the shift register, and the first serial data to be transmitted is transmitted at the same time; when the counter signal cnt is 2, the serial data to be received sampled to the second time is indicated, the serial data to be received sampled to the first time is shifted into the shift register, and the serial data to be transmitted to the second time is transmitted; when the counter signal cnt is 3, the third serial data to be received is sampled, the second sampled serial data to be received is shifted into the shift register, and the third serial data to be transmitted is transmitted at the same time; by analogy, when the counter signal cnt is 7, it indicates that the seventh serial data to be received is sampled, the sixth sampled serial data to be received is shifted into the shift register, and the seventh serial data to be transmitted is transmitted at the same time; when the counter signal cnt returns to 0 again, the eighth serial data to be received is sampled, the seventh serial data to be received is shifted into the shift register, and the eighth serial data to be transmitted is transmitted at the same time.

In the above description, the 8-bit data is transmitted as an example, the 8-bit data is incremented from 0 to 7 and then returned to 0 in one frame, and if the data is 16-bit data, the data is incremented from 0 to 15 and then returned to 0 in the same manner. When data is transmitted continuously frame by frame, the counter cnt is cleared to 0 after it is counted that one frame of data is full (7 or 15, etc.).

The following describes the working process of the load trigger module when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O:

after the sampling clock signal sck _ sample is synchronized with the main frequency clock signal CLK and the edge is taken, a sampling clock synchronous falling edge signal sck _ sample _ syn _ neg signal is generated. The chip select signal CS generates a chip select synchronization signal CS _ syn and a chip select synchronization rising edge signal CS _ syn _ pos signal through synchronization and edge fetch operations with the master frequency clock signal CLK. The counter signal cnt is the data frame bit count, the counter signal cnt is generated by the counter generating unit, and the size of the counter signal cnt is determined by the serial data frame bit number. data _ len is a constant indicating the number of data frame bits. The time when the cnt is 0 is extracted after the counter signal cnt passes through the third comparator EQU3, the time when the cnt is data _ len is extracted after the counter signal cnt passes through the fourth comparator EQU4, signals generated by a two-input NAND gate (the third NAND gate 3) AND a two-input AND gate (the first AND gate 1) are input to the SET terminal SET AND the reset terminal CLR of the second D flip-flop DFF2, the SET terminal AND the reset terminal of the second D flip-flop DFF2 are an asynchronous falling edge SET terminal SET AND an asynchronous falling edge reset terminal CLR, AND the signal output by a Q non-output terminal is the load trigger signal load _ time.

As shown in fig. 9, in this embodiment, the load trigger signal send _ time is generated by a load trigger module, where the load trigger module includes a fifth comparator EQU5, a third sampling clock synchronization edge fetching unit, a third D flip-flop DFF3, and a second and gate;

a first input end of the fifth comparator EQU5 is connected to zero, a second input end of the fifth comparator EQU5 is connected to the counter signal cnt, and an output end of the fifth comparator EQU5 is connected to a first input end of the second and gate;

the clock input end of the third D flip-flop DFF3 is connected to the main frequency clock signal CLK, the input end of the third D flip-flop DFF3 is connected to the output end of the edge taking unit in synchronization with the third sampling clock, and the Q output end of the third D flip-flop DFF3 is connected to the second input end of the second and gate;

The loading trigger signal load _ time and the loading trigger signal send _ time respectively correspond to the trigger time for loading the output parallel data packet in the sending data cache module into the shifting module and the trigger time for loading the parallel data in the synchronous cache module to the receiving data cache module.

The carried-out trigger signal send _ time is a high-effective signal, AND after the counter signal cnt is compared with zero by the comparator, the time when cnt is equal to 0 is provided, the sampling clock signal sck _ sample (or chip selection sampling clock signal sck _ sample') is synchronized by the third sampling clock AND the edge taking unit generates the sampling clock taking rising edge signal sck _ sample _ syn _ pos, the sampling clock taking rising edge signal sck _ sample _ syn _ pos is delayed for one beat by the third D flip-flop DFF3, AND the sampling clock taking rising edge delay signal sck _ sample _ syn _ pos _ D is generated, AND the time when cnt is equal to 0 passes through the second AND gate 2, AND the carried-out trigger signal send _ time is generated. And finishing the operation of splicing the serial sampling data synchronous signal SDI _ I _ S _ syn and the shift register synchronous delay signal shift _ reg _ syn _ d [ data _ len:1] and simultaneously sending the spliced signals into the receiving data cache module at the rising edge moment of the main frequency clock signal CLK corresponding to the high effective moment of the loading trigger signal send _ time.

In this embodiment, the first sampling clock synchronization and edge taking unit and the second sampling clock synchronization and edge taking unit may each be formed by a synchronization and edge taking-down unit, as shown in fig. 10, where the synchronization and edge taking-down unit includes: a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a fourth inverter, and a third and gate;

the input end of the fourth D flip-flop DFF4 constitutes the first sampling clock synchronization and takes the first input end of the edge unit or the second sampling clock synchronization and takes the first input end of the edge unit; the clock input terminal of the fourth D flip-flop DFF4, the clock input terminal of the fifth D flip-flop DFF5 and the clock input terminal of the sixth D flip-flop DFF6 together form the first sampling clock synchronization and edge unit second input terminal or the second sampling clock synchronization and edge unit second input terminal;

the Q output terminal of the fourth D flip-flop DFF4 is connected to the input terminal of the fifth D flip-flop DFF 5; the Q output terminal of the fifth D flip-flop DFF5 is connected to the input terminal of the sixth D flip-flop DFF6 and the input terminal of the fourth inverter, respectively;

the output end of the fourth inverter is connected with the first output end of the third AND gate; the Q output end of the sixth D flip-flop DFF6 is connected to the second output end of the third and gate; the output end of the third AND gate forms the output end of the first sampling clock synchronization and edge taking unit or the output end of the second sampling clock synchronization and edge taking unit;

the chip selection signal synchronization and edge-taking unit and the third sampling clock synchronization and edge-taking unit may be formed by a synchronization and edge-taking unit, as shown in fig. 11, where the synchronization and edge-taking unit includes: a seventh D flip-flop DFF7, an eighth D flip-flop DFF8, a ninth D flip-flop DFF9, a fifth inverter, and a fourth and gate;

the input end of the seventh D flip-flop DFF7 constitutes the first input end of the edge unit or the first input end of the edge unit; the clock input terminal of the seventh D flip-flop DFF7, the clock input terminal of the eighth D flip-flop DFF8 and the clock input terminal of the ninth D flip-flop DFF9 together form the chip select signal synchronization and edge unit second input terminal or the third sampling clock synchronization and edge unit second input terminal;

the Q output terminal of the seventh D flip-flop DFF7 is connected to the input terminal of the eighth D flip-flop DFF 8; the Q output end of the eighth D flip-flop DFF8 is connected to the input end of the ninth D flip-flop DFF9 and the first input end of the fourth and gate, respectively; the Q output terminal of the eighth D flip-flop DFF8 constitutes the first output terminal of the chip select signal synchronization and edge fetching unit;

the Q output end of the ninth D flip-flop DFF9 is connected to the second input end of the fourth and gate through the fifth inverter;

As shown in fig. 10, by using the synchronous AND edge-taken-down unit, the asynchronous signal data passes through two stages of flip-flops (the fourth D flip-flop DFF4 AND the fifth D flip-flop DFF5) to generate a synchronous data signal data _ syn, which is synchronous with the main frequency clock signal CLK, AND the two-input output signal of the third AND gate AND3, i.e., the synchronous data edge-taking signal data _ syn _ neg, is a signal obtained by taking down the asynchronous signal data AND the main frequency clock signal CLK synchronously.

As shown in fig. 11, the structure of the synchronization and taking rising edge unit is substantially similar to that of the synchronization and taking falling edge unit, except that the position of the inverter used is different, and the synchronization and taking rising edge signal data _ syn _ pos is taken from the synchronization data output from the output terminal of the fourth and gate of the two inputs used in the structure of the rising edge unit; the signal is a rising edge signal obtained after an asynchronous signal data is synchronous with a main frequency CLK.

In this embodiment, the sampling module comprises a tenth D flip-flop DFF10, an input of the tenth D flip-flop DFF10 constituting a first input of the sampling module;

when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the clock input terminal of the tenth D flip-flop DFF10 is connected to the sampling clock signal SCK _ sample; when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the clock input terminal of the tenth D flip-flop DFF10 is connected with the chip selection sampling clock signal SCK _ sample';

the Q output terminal of the tenth D flip-flop DFF10 outputs the serial sampled data signal SDI _ I _ S.

That is, in this embodiment, the sampling module samples the external-to-internal serial data input signal SDI _ I under the trigger of the sampling clock signal sck _ sample (or the chip select sampling clock signal sck _ sample '), specifically, the sampling module samples the external-to-internal serial data input signal SDI _ I by the tenth D flip-flop DFF10 under the trigger of the sampling clock signal sck _ sample (or the chip select sampling clock signal sck _ sample'), and then obtains the sampled serial sampling data signal SDI _ I _ S.

In this embodiment, the shift module includes a shift register unit;

when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the clock input end of the shift register unit is connected with the shift clock signal SCK _ shift; when the auxiliary clock generating module generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I AND generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, the host chip further includes a sixth inverter AND a fifth AND gate AND5, the chip select signal CS is input to the first input end of the fifth AND gate AND5 through the sixth inverter, the second input end of the fifth AND gate AND5 is connected to the shift clock signal SCK _ shift, the output end of the fifth AND gate AND5 outputs a chip select shift clock signal SCK _ shift ', AND the clock input end of the shift register unit is connected to the chip select shift clock signal SCK _ shift';

The chip select shift clock signal SCK _ shift' may be generated by performing combinational logic on the internal clock signal SCK _ O and the chip select signal CS.

The main function of the load trigger module is to generate a load _ time trigger signal. The shift register unit in the shift module corresponds to two functions: firstly, at the rising edge of a shift clock signal sck _ shift, a serial sampling data signal SDI _ I _ S is shifted into a shift register to generate a shift register signal shift _ reg, and an internal serial data output signal SDO _ O is generated at the same time; and secondly, after the data shifting is finished, new data in the sending data cache module is required to be loaded into the shift register again to generate a shift register signal shift _ reg.

In this embodiment, the synchronous cache module includes: a serial sampling signal synchronization unit, a shift register synchronization unit, and an eleventh D flip-flop DFF 11;

a first input end of the serial sampling signal synchronization unit is connected with a Q output end of the tenth D flip-flop DFF10, a second input end of the serial sampling signal synchronization unit is connected with the main frequency clock signal CLK, and an output end of the serial sampling signal synchronization unit is connected with a first input end of the received data buffer module;

a Q output terminal of the tenth D flip-flop DFF10 is connected to the third input terminal of the shift register unit, a second output terminal of the shift register unit is connected to the first input terminal of the shift register synchronizing unit, a second input terminal of the shift register synchronizing unit is connected to the main frequency clock signal CLK, an output terminal of the shift register synchronizing unit is connected to an input terminal of the eleventh D flip-flop DFF11, a clock input terminal of the eleventh D flip-flop DFF11 is connected to the main frequency clock signal CLK, and a Q output terminal of the eleventh D flip-flop DFF11 is connected to the second input terminal of the received data buffer module;

and the signal output by the output end of the serial sampling signal synchronization unit is spliced with the signal output by the Q output end of the eleventh D flip-flop DFF11 to form the serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK.

In this embodiment, the shift register unit is a device of a multiplexing module, and is used to implement 2 functions:

firstly, the method comprises the following steps: at the rising edge of the shift clock signal sck _ shift (or chip select shift clock signal sck _ shift'), shifting the serial sampling data signal SDI _ I _ S into the shift register unit to generate a shift register signal shift _ reg, wherein the shift register signal shift _ reg is output by a second output end of the shift register unit;

secondly, the method comprises the following steps: shifting the output parallel data packet to generate and output a corresponding internal serial data output signal SDO _ O;

after the shift register unit finishes outputting the internal serial data output signal SDO _ O, new data in the sending data buffer module needs to be loaded into the shift register unit again to generate a shift register signal shift _ reg.

In this embodiment, the serial sampling signal synchronizing unit and the shift register synchronizing unit may be formed by synchronizing units, and the synchronizing units include a twelfth D flip-flop DFF12 and a thirteenth D flip-flop DFF13, the structure of which can be seen in fig. 12;

an input end of the twelfth D flip-flop DFF12 constitutes a first input end of the serial sampling signal synchronization unit or a first input end of the shift register synchronization unit; the clock input terminal of the twelfth D flip-flop DFF12 and the clock input terminal of the thirteenth D flip-flop DFF13 together form a second input terminal of the serial sampling signal synchronization unit or a second input terminal of the shift register synchronization unit; a Q output terminal of the twelfth D flip-flop DFF12 is connected to an input terminal of the thirteenth D flip-flop DFF 13; the Q output terminal of the thirteenth D flip-flop DFF13 constitutes the output terminal of the serial sampling signal synchronizing unit or the output terminal of the shift register synchronizing unit.

The synchronization unit can synchronize the signals passing through the two-stage flip-flop under the main frequency clock signal CLK, and as shown in FIG. 12, the signals of the asynchronous signal data passing through the twelfth flip-flop DFF12 and the thirteenth flip-flop DFF13 of the two-stage flip-flop are the signals data' synchronized with the main frequency.

In the above embodiment, the clock used by the shift module is the shift clock signal SCK _ shift, the shift module can perform data loading and shifting on the output parallel data packet in the transmission data buffer module, and the shift module directly generates the internal serial data output signal SDO _ O for output, where the internal serial data output signal SDO _ O is delayed by the serial data output PAD port, and generates the serial data output signal SDO synchronized with the communication clock signal SCK after output. Through the sampling clock signal sck _ sample, the sampling module samples an external-to-internal serial data input signal SDI _ I to obtain a serial sampling data signal SDI _ I _ S and an input parallel data packet which is moved into the shift module and contains serial sampling data signal SDI _ I _ S information, the serial sampling data signal SDI _ I _ S and the input parallel data packet enter the synchronous cache module after being synchronized under a main frequency clock CLK to generate a serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK, and finally the serial sampling data signal SDI _ I _ S synchronized with the main frequency clock signal CLK in the synchronous cache module is sent to the receiving data cache module. The operation process that an external serial data input signal SDI is converted into parallel data under a communication clock signal SCK and the parallel data are stored in a receiving data cache module is realized; and the operation process that the output parallel data packet in the sending data cache module is finally converted into a serial data output signal SDO under the communication clock signal SCK and is output is realized. In the embodiment, the sampling module and the synchronous buffer module cooperate to complete the operation of converting the serial data input signal SDI with the synchronous frequency with the communication clock signal SCK into parallel received data packets input into the received data buffer module; the shift module performs an operation of converting the output parallel transmission data packet output from the transmission data buffer module into a serial data output signal SDO having a frequency synchronized with the communication clock signal SCK. The sending data buffer module and the receiving data buffer module are equivalent to two RAMs or two FIFO memories and are used for storing parallel data packets with fixed bit positions.

Fig. 13 is a schematic diagram of an operating principle of a shift module in an embodiment, and a function of the shift module in the embodiment is that at a rising edge of each shift clock signal sck _ shift, when a load trigger signal load _ time is valid, an output parallel data packet in a sending data buffer module is loaded to generate a shift register signal shift _ reg, the shift register signal shift _ reg is shifted at other moments, a head of the shift register signal shift _ reg is shifted out of an internal serial data output signal SDO _ O, and a tail of the shift register signal shift _ reg is shifted into an input data sampled by a sampling clock signal sck _ sample, i.e., a serial sampling data signal SDI _ I _ S.

Specifically, the work flow of the shift register unit in the shift module is as follows:

at the rising edge of each shift clock signal sck _ shift (or chip select shift clock signal sck _ shift'), when the load trigger signal load _ time is valid, the output parallel data packet in the transmission data buffer module is loaded into the shift register unit, and a shift register signal shift _ reg is generated. And shifting the shift register signal shift _ reg at other moments, shifting out the shift register signal shift _ reg at the head of the register, outputting an internal serial data output signal SDO _ O, and shifting in the tail of the shift register signal shift _ reg into the serial sampling data signal SDI _ I _ S which is input data subjected to trigger sampling by the sampling clock signal sck _ sample.

Referring to fig. 13, taking an example that the shift register unit is an 8-bit shift register, the data in the output parallel data packet output by the sending data buffer module is 8 bits, the external-to-internal serial data input signal SDI _ I input to the serial communication interface is also 8 bits, the 8-bit output parallel data packet is loaded into the shift register unit under the common trigger of the load trigger signal load _ time and the shift clock signal sck _ shift, and then the shift register unit is triggered by the shift clock signal sck _ shift (or the chip select shift clock signal sck _ shift') to shift the data in the shift register, when the most significant data of the data in the output parallel data packet is shifted out, the first bit of the serial sampling data signal SDI _ I _ S is input to the lowest bit of the shift register unit, and each bit of the data in the output parallel data packet is shifted out, the data of the one-bit serial sample data signal SDI _ I _ S is input. That is, the first 7 serial data have been sampled at 1-7 rising edges of the sampling clock signal sck _ sample (or chip selection sampling clock signal sck _ sample '), shifted at the first 2-8 rising edges of the shift clock signal sck _ shift (or chip selection shift clock signal sck _ shift'), and have been stored in the first seven bits of the shift register unit, that is, the first 7 serial data correspond to shift _ reg [7:1] in sequence, and are synchronized with the master clock signal CLK, the current time point of sampling the 8 th data is being performed, and after being synchronized with the master clock signal CLK, the current time point of sampling the 8 th data just completed sampling becomes the corresponding 8 th sampling clock synchronous rising edge signal sck _ sample _ syn _ pos, the sampling clock rising edge signal sck _ sample _ sync _ pos is extracted as the 8 th sampling clock rising edge delay signal sck _ sample _ sync _ pos after being synchronized with the master clock, and the sampling clock rising edge signal sync _ sample _ pos is extracted to be equal to the sampling clock delay time point of the 8 th sampling clock (the sampling clock signal sck _ sample _ sync _ sample _ pos) (after the sampling clock signal is synchronized with the sampling clock _ sync _ pos and the sampling clock signal sync _ pos '0' is extracted up 'the sampling clock' th time delay _ sync 'and' clock 'the sampling clock' is extracted Eight serial data and a seventh serial data are shifted into the shift register), the generated corresponding signal is the send-out trigger signal send _ time, the send-out trigger signal send _ time is triggered effectively, and the time length is one cycle of the main frequency clock CLK.

In this embodiment, the counter signal cnt corresponds to the number of serial data received by the shift register unit, and is 0 in the initial state, which indicates that one data is not sampled; when the counter signal cnt is 1, the first serial data is sampled, only the data is sampled in the state, but the data is not shifted into the shift register unit, and when the counter signal cnt is 2, the second serial data is sampled, and the first serial data is shifted into the shift register unit; when the counter signal cnt is 3, the third serial data is sampled, and the second serial data is shifted into the shift register; by analogy, when the counter signal cnt is 7, the seventh serial data is sampled, and the sixth serial data is shifted into the shift register; when the counter signal cnt returns to 0 again, it is illustrated that the eighth serial data is sampled and the seventh serial data is shifted into the shift register.

At this time, the eighth data does not need to be shifted into the shift register unit to be shifted to the right (meanwhile, in the scheme under the precondition that the sampling clock signal SCK _ sample is generated according to the falling edge of the input clock signal SCK _ I, and the shift clock signal SCK _ shift is generated according to the rising edge of the internal clock signal SCK _ O, the rising edge of the 9 th shift clock signal SCK _ shift is not available for shift operation, and the circuit sends the eighth sampling data SDI _ S _ syn spliced by the first seven data shift _ reg _ syn [ data _ len:1] shifted into the shift register unit into the receiving data buffer unit together.

In the signal processing process, at the time point of the 8 th sampling clock synchronous rising edge signal sck _ sample _ syn _ pos, the eighth data is being sampled, and the eighth sampling data SDI _ S _ syn is still in an unstable state. The shift register synchronizing signal shift _ reg _ syn passes through a D trigger to generate a shift register synchronizing delay signal shift _ reg _ syn _ D, a sampling clock synchronizing rising edge signal sck _ sample _ syn _ pos passes through the D trigger to generate a sampling clock taking rising edge delay signal sck _ sample _ syn _ pos _ D, which is generally a time for delaying one main frequency clock signal CLK period, and after the eighth sampling data SDI _ S _ syn is completely stabilized, the eighth sampling data SDI _ S _ syn spliced by the shift register synchronizing delay signal shift _ reg _ syn _ D [ data _ len:1] is sent to a receiving data buffer unit together at the time point when the trigger signal send _ time is high-effective.

The main functions of the synchronous cache module are as follows:

when the last bit of a frame of data is sampled by the sampling clock signal sck _ sample, the shift register signal shift _ reg and the last bit of the serial sampling data signal SDI _ S need to be synchronized with the main frequency clock signal CLK and then sent to the received data buffer module; the shift register signal shift _ reg output by the shift register unit splices other bit data except the last bit in the serial sampling data signal SDI _ S and the serial sampling data signal SDI _ I _ S which finishes sampling currently into the receiving data buffer module;

the specific operation of the synchronous cache module is as follows:

the serial sampling data signal SDI _ I _ S passes through the serial sampling signal synchronization unit and becomes a serial sampling data synchronization signal SDI _ I _ S _ syn under the synchronization of a main frequency clock signal CLK; a shift register signal shift _ reg output by the shift register unit passes through the shift register synchronization unit and becomes a shift register synchronization signal shift _ reg _ syn under the synchronization of a main frequency clock signal CLK, and the shift register synchronization signal shift _ reg _ syn is delayed for one beat by an eleventh D trigger DFF11 to generate a delay signal, namely a shift register synchronization delay signal shift _ reg _ syn _ D; the generated serial sampling data synchronous signal SDI _ I _ S _ syn and the shift register synchronous delay signal shift _ reg _ syn _ d [ data _ len:1] are spliced (wherein data _ len is a constant and indicates the number of data frame bits), and the serial sampling data synchronous signal SDI _ S and the shift register synchronous delay signal shift _ reg _ syn are jointly sent to a receiving data buffer unit at the time point when the send _ time of the trigger signal is loaded out to be effective, namely the serial sampling data synchronous with the main frequency clock signal CLK is sent to the receiving data buffer unit.

As can be seen from fig. 14 to 17, the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I, generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, generates the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I, and generates the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O, respectively, and the auxiliary clock generation module generates the phase relationship between the corresponding signals. Fig. 14 is a timing diagram of generating the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I, and generating the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O; fig. 15 is a timing diagram of generating the sampling clock signal SCK _ sample according to the rising edge of the input clock signal SCK _ I and generating the shift clock signal SCK _ shift according to the falling edge of the internal clock signal SCK _ O; fig. 16 is a timing diagram showing the phase relationship between the carry-out trigger signal send _ time and other signals when the sampling clock signal SCK _ sample is generated according to the falling edge of the input clock signal SCK _ I and the shift clock signal SCK _ shift is generated according to the rising edge of the internal clock signal SCK _ O; fig. 17 is a timing diagram showing the phase relationship between the output trigger signal send _ time and other signals when the sampling clock signal SCK _ sample is generated according to the rising edge of the input clock signal SCK _ I and the shift clock signal SCK _ shift is generated according to the falling edge of the internal clock signal SCK _ O.

In the working process of the circuit structure, before the trigger time of the trigger signal send _ time is carried out, the communication clock signal SCK, the chip select signal CS, the sampling clock signal SCK _ sample, the shift clock signal SCK _ shift, the shift register signal shift _ reg, the external-to-internal serial data input signal SDI _ I and the serial sampling data signal SDI _ I _ S are synchronous and belong to a clock domain, and the clock domain is asynchronous with the main frequency clock signal CLK.

The main clock signal CLK, the synchronized sampling clock signal sck _ sample _ syn, the counter signal cnt, the sampling clock synchronous falling edge signal sck _ sample _ syn _ neg, the sampling clock synchronous rising edge signal sck _ sample _ syn _ pos, the sampling clock synchronous rising edge delay signal sck _ sample _ syn _ pos _ d, the serial sampling data synchronization signal SDI _ S _ syn, the shift register synchronization signal shift _ reg _ syn, the shift register synchronous delay signal shift _ reg _ syn _ d, and the like are synchronized, and belong to a clock domain, the receiving data buffer module for storing data is in the main clock signal CLK time domain, the operation of the receiving data buffer module must be completed under the main clock signal CLK, so the shift data in the shift register signal shift _ reg must be synchronized to the shift register synchronization signal CLK under the main clock signal CLK time domain before the operation can continue, similarly, the serial sampled data signal SDI _ I _ S must be synchronized with the serial sampled data synchronization signal SDI _ I _ S _ syn by the master clock signal CLK before the following operation can be continued.

The load trigger signal load _ time and the load trigger signal send _ time are both synchronous with the main frequency clock signal CLK.

As can be seen from fig. 14 to 17, in the load trigger module for generating the load trigger signal load _ time, except for the clock phase synchronization between the shift register signal shift _ reg, which is the output signal of the shift register unit, and the shift clock signal sck _ shift, other signals are synchronized with the main frequency clock signal CLK, so as to ensure the reliability of the digital circuit design.

It can be seen from fig. 9, 16 AND 17 that the generated load trigger signal send _ time is a high-activity signal, in the load trigger module, after the counter signal cnt is compared with 0 by the fifth comparator EQU5, a time when cnt is equal to 0 is extracted, the sampling clock signal sck _ sample generates a sampling clock synchronous rising edge signal sck _ sample _ syn _ pos through synchronization AND edge fetching with the main frequency clock signal CLK, the signal is delayed for one beat by the third D flip-flop DFF3 to generate a sampling clock synchronous rising edge delay signal sck _ sample _ syn _ pos _ D, AND finally, the load trigger signal send _ time is generated after passing through the second AND gate 2.

In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A circuit structure of a host chip for realizing serial interface full duplex communication is characterized in that the host chip comprises a serial data input PAD port, a serial data output PAD port, a bidirectional clock signal input and output PAD port and a clock generation module;

2. The circuit structure of a host chip for implementing serial interface full duplex communication of claim 1, wherein the bi-directional clock signal input/output PAD port comprises an output buffer and an input buffer;

3. The circuit structure of a host chip for implementing serial interface full duplex communication of claim 1, wherein the host chip further comprises an auxiliary clock generating module;

4. The circuit structure of host chip for implementing serial interface full duplex communication according to claim 3,

when the auxiliary clock generation module generates the sampling clock signal SCK _ sample according to the falling edge of the input clock signal SCK _ I and generates the shift clock signal SCK _ shift according to the rising edge of the internal clock signal SCK _ O, the auxiliary clock generation module inputs the received input clock signal SCK _ I into the first inverter for inversion to obtain the sampling clock signal SCK _ sample output, and the auxiliary clock generation module outputs the received internal clock signal SCK _ O as the shift clock signal SCK _ shift;

5. The circuit structure of the host chip for implementing serial interface full duplex communication according to claim 4, wherein the host chip further comprises a shift module and a sampling module;

6. The circuit structure of the host chip for realizing serial interface full duplex communication according to claim 5, wherein the host chip further comprises a synchronization buffer module, a transmission data buffer module and a reception data buffer module;

7. The circuit structure of the host chip for implementing serial interface full duplex communication of claim 6, wherein the load trigger signal load _ time is generated by a load trigger module,

8. The circuit structure of the host chip for realizing serial interface full-duplex communication according to claim 7, wherein the load-out trigger signal send _ time is generated by a load-out trigger module, and the load-out trigger module includes a fifth comparator, a third sampling clock synchronization edge-taking unit, a third D flip-flop, and a second and gate;

9. The circuit structure of host chip for implementing serial interface full duplex communication according to claim 8,

the first sampling clock synchronization and edge taking unit and the second sampling clock synchronization and edge taking unit can be composed of a synchronization and edge taking-down unit, and the synchronization and edge taking-down unit comprises: a fourth D trigger, a fifth D trigger, a sixth D trigger, a fourth inverter and a third AND gate;

10. The circuit structure of host chip for implementing serial interface full duplex communication according to claim 7,

the sampling module comprises a tenth D trigger, and the input end of the tenth D trigger forms the first input end of the sampling module;

11. The circuit structure of a host chip for implementing serial interface full duplex communication of claim 10, wherein the shift module comprises a shift register unit;

12. The circuit structure of a host chip for implementing serial interface full duplex communication of claim 11, wherein the synchronization buffer module comprises: the device comprises a serial sampling signal synchronization unit, a shift register synchronization unit and an eleventh D trigger;

13. The circuit structure of a host chip for implementing serial interface full duplex communication according to claim 12, wherein the serial sampling signal synchronizing unit and the shift register synchronizing unit are both constituted by synchronizing units, and the synchronizing units include a twelfth D flip-flop and a thirteenth D flip-flop;