JP2008148078A - Low pressure differential signal receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low pressure differential signal receiving device which improves a transmission rate and a quality of a pixel. <P>SOLUTION: A low pressure differential signal receiving device is composed of two differential receivers, two over-sampling devices, a phase lock loop device, and a clock data boundary detection logical module, wherein a clock signal and a data signal are transmitted through a path of the same circuit arrangement, the clock signal is made another data signal and a frequency for an input clock and data by an asynchronous clock, clock conversion is detected through a specific clock data boundary detection logical module, and a data bit is analyzed by a clock and data sampling. Thus, delay times of the clock and the data signal become coincident, an over-sampling error state due to a time difference between the clock and data is avoided, an over-sampling frequency is accurately improved, and a pixel transmission efficiency and quality can be improved without an influence of a voltage change. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a low-voltage differential signal receiver that improves the transmission speed and quality of pixels, and more particularly, to a low-voltage differential signal receiver that improves the quality and efficiency of low-voltage differential signal (LVDS) transmission.

  In recent years, the processing speed of processors has been increasing more and more, the amount of data processed per unit time has been increasing day by day, and it has been applied to data transmission of personal computer peripheral devices and various types of integrated circuit products. These are all due to the completion of an interface that can send and receive large amounts of data. For long-distance transmission of several tens of kilometers or even several hundred kilometers or more, it can be used as a means of transmission using an optical fiber, but transmission of each chip bus data on a circuit board is several tens of centimeters. Cannot be used, it is necessary to exchange data through a copper wire or a transmission line on a circuit board. In the prior art, the number of transmission lines is increased to meet the demand for high frequency and high speed, but the area of the device circuit board is limited, energy saving, low cost, simplified production and assembly, etc. Due to the demand, a more efficient interface design is needed.

  Low voltage differential signaling (LVDS) is widely used in visual information interfaces between liquid crystal display surface plates and image control ICs. LVDS was originally developed to replace high efficiency ECL transmission line drive technology. By reducing the efficiency, it is possible to improve the finite characteristics of the ECL, such as the supply of ordinary power, the high degree of matching, and the compatibility of low-cost IC packages.

LVDS is a data layer standard for a substance layer defined in the ANSI / TIA / EIA-644 and IEEE1596.3 standards, and is widely referred to as RS-644. This standard only defines the electrical characteristics of the driver output and receiver input and does not include application-related definitions such as function, cable characteristics, etc. LVDS is often used for communication with display interfaces and replaces prior art interfaces such as RS-422, PECL (positive reference emitter coupling logic), and LV-PECL. The differential characteristics of LVDS have strong noise suppression and do not require any restriction on the power supply voltage of the driver and receiver. Compared to other interfaces, LVDS includes the following advantages:
(1) Environment where low voltage power supply can be used,
(2) The generated signal is low noise.
(3) High noise resistance,
(4) Robust signal transmission capability,
(5) Easy to match in the system chip.

  As various electronic devices develop in the direction of lighter and thinner, the bus from the circuit board to the display becomes narrower, but the transmission rate is required to be higher. By adopting the LVDS chip, this contradiction can be solved. For the circuit board, previously required electrical resistance and capacitance can be eliminated, and cost and space can be reduced. it can.

LVDS has the above advantages, but there are problems that are difficult to solve during conventional design. One LVDS connection port consists of one clock (Clock) differential pair and multiple data (DATA) differential pairs. Each data path transmits 7-bit data for each clock period, and the receiver is accurate. In each data path, the clock edges need to be well synchronized with the data bit stream.
The time chart of the LVDS clock / data is as shown in FIG.

  During the design of a conventional low-voltage differential signal (LVDS) receiver, a common approach is to use a phase-locked loop (PLL) or a delay-locked loop (DLL) to generate a seven-period clock signal, with each period The data bits corresponding to each other in the data stream are taken, and the edges of the clock signals of the seven periods need to be well synchronized with the corresponding data bits. A conventional low voltage differential signal (LVDS) receiver structure is as shown in FIG.

  Problems with current low voltage differential signal (LVDS) receivers vary depending on the delay time of each clock and data signal path due to a number of factors, including the number, type and manufacturing process of each electronic component, voltage All the elements such as changes generate different time differences between each corresponding clock and data, these are likely to cause errors during oversampling, affect the signal transmission quality, and improve the pixel transmission rate, It is even clearer.

  In order to overcome the occurrence of many oversampling errors with the improvement of the pixel transmission rate, the number and types of electronic components differing with respect to the clock and data paths in the current low voltage differential signal (LVDS) receiver structure. It is only after adjusting the arrangement of elements such as manufacturing process and voltage change on the circuit that the pixel transmission rate can be improved and the transmission quality can be improved, but it takes much time and process for the producer Let me.

  Therefore, it is very difficult to combine the improvement of the pixel transmission rate and the quality of signal transmission in the conventional low-voltage differential signal (LVDS) receiver structure.

JP 2005-33571 A

An object of the present invention is to provide a low-voltage differential signal receiver that can smoothly improve the transmission speed and quality of pixels.
It is another object of the present invention to provide a low-voltage differential signal receiver that can be applied to various display products.
It is another object of the present invention to provide a low-voltage differential signal receiver having advantages such as a wide range of application, stable transmission, low cost and long service life.

To achieve the above object, the low-voltage differential signal receiver provided by the present invention includes two differential receivers, two oversamplers, a phase locked loop (PLL), and clock data boundary detection. It is composed of logic modules (Clock Edge Data Boundary Detection & Data Extraction).
In the present invention, the clock signal and the data signal are transmitted through the same circuit arrangement path (the same circuit module), and the clock signal is viewed as one other data signal so that both signals have the same delay time. An asynchronous clock improves the oversampling frequency for the input clock and data and analyzes the data bits through clock conversion and clock and data sampling through a specific clock data boundary detection logic module.

That is, the invention of claim 1 is a low-voltage differential signal receiving apparatus including a first differential receiver, a second differential receiver, a phase-locked loop unit, and a clock data boundary detection logic module. The dynamic receiver receives the data signal input from the data signal input terminal, outputs the data signal to the first oversampler, and then outputs the data signal to the clock data boundary detection logic module, The second differential receiver receives a clock signal, outputs the clock signal to a second oversampler, and then outputs the clock signal to the clock data boundary detection logic module. The loop unit receives the clock signal output from the second differential receiver, and sets the oversampling clock respectively. The clock data boundary detection logic module receives the signals output from the first oversampler and the second oversampler and passes through the oversampling process. Later, the data signal and the clock signal can be output, and the clock signal is viewed as one other data signal, and the asynchronous clock increases the frequency for the input clock and data, thereby passing through the specific clock data boundary detection logic module. A low-voltage differential signal receiver that detects clock conversion and analyzes data bits from clock and data sampling.
A second aspect of the present invention is the low-voltage differential signal receiving apparatus according to the first aspect, wherein the number of the data signal input terminals is one or more.
A third aspect of the present invention is the low-voltage differential signal receiving apparatus according to the second aspect, wherein the first differential receiver and the number of data signal input terminals are the same.

  According to the low-voltage differential signal receiving apparatus for pixel transmission of the present invention, the delay time of the clock and the data signal coincides, thereby avoiding the situation where the time difference between the clock and the data causes an oversampling error, By reliably improving the oversampling frequency, the data signal effectively improves the pixel transmission efficiency and quality without being affected by factors such as the number, type, manufacturing process, and voltage change of the electronic members.

  FIG. 3 is an implementation structure diagram of the low-voltage differential induction receiver according to the present invention. As can be seen from the figure, the low-voltage differential signal (LVDS) receiver 1 according to the present invention includes a first differential signal. A receiver (Differential Receiver) 11, a second differential receiver 12, a phase locked loop (PLL) 15, and a clock data boundary detection logic module (Clock Edge Data Boundary Detection & Data Extraction) 16 are included.

The first differential receiver 11 receives the data signal input from the data signal input terminal, outputs the data signal to the first oversampler 13, and then outputs the data signal to the clock data boundary detection logic module 16. When the number of data signal input terminals is one or more, the first differential receiver 11 and the first oversampling 13 are provided with the same number of circuits as the number of data signal input terminals, and a plurality of data signals Are transmitted simultaneously.
Since the DC voltage level range of the LVDS input signal to the first differential receiver 11 can be from 0 to 24V, the differential receiver accurately converts the operation input signal within this range into a logic signal. This first differential receiver uses the conventional PMOS / NMOS differential input level (MP1, MP2, MN1, MN2) to expand the input signal, and the second level (MP3 to MP7, MN3) To MN7), the differential signal is converted into a single-ended output to be input to the first oversampler 13.
The first oversampler is usually composed of 12 sets of flip-flops, and each of the 3 sets of flip-flops performs oversampling 3 times for each data bit. Is. The 12 sets of flip-flop outputs are sent to the next level clock data boundary detection logic module 16. The 12 sets of flip-flops are used to sample with 12 different phase clocks generated by the PLL.

On the other hand, the second differential receiver 12 receives the clock signal, outputs the clock signal to the second oversampler 14, and then outputs the clock signal to the clock data boundary detection logic module 16. The operation is the same as that of the first differential receiver 11 and the first oversampler 13.
This clock data boundary detection logic module is used to detect the bit stream of the clock and data after oversampling, and further to determine the correspondence between the position of the clock edge in the clock signal stream and the data signal stream. Based on these information and logical operations, a data boundary is further determined.

  A phase locked loop unit (Phase Locked Loop = PLL) 15 receives a clock signal output from the second differential receiver 12 and sends oversampling clocks to the first oversampler 13 and the second oversampler 14, respectively. Output.

The clock data boundary detection logic module 16 can receive the signals output from the first oversampler 12 and the second oversampler 14, and can output the data signal and the clock signal after passing through the oversampling process. .
The clock edge needs to be well synchronized with the data bitstream, but for example, it employs asynchronous oversampling with a 3x rate oversampling scheme, and the data bitstream and clock bitstream in the example are completely If the synchronization is not performed, a data bit stream and a clock bit stream closer to the data boundary of the data waveform can be obtained even if the clock edges of the data waveform do not match. However, this does not affect the determination result of the logic module.
Therefore, the sampling frequency is three times the data bit rate, so that the clock edge is well synchronized with the data bit stream with a precision of 3 times and the sampling clock and the signal to be sampled using an oversampler Can avoid synchronization problems.

  In the present invention, a clock signal and a data signal are transmitted through a path of the same circuit arrangement, that is, transmitted through a module of the same circuit, the clock signal is set as another data signal, the outputs of both signals are set as the same delay time, and the asynchronous clock Improves clock and data oversampling frequency, detects clock conversion and analyzes data bids from clock and data sampling through a specific clock data boundary detection logic module. Embodiments of the present invention improve the oversampling frequency probable by the clock and data signal by avoiding the situation of oversampling errors that cause the clock and data signal delay times to coincide, resulting in a time difference between the clock and data In addition, the pixel transmission efficiency and quality are effectively improved without being affected by factors such as the number, type, manufacturing process, and voltage change of the electronic members.

  In the present invention, the preferred embodiments have been disclosed as described above, but these are not intended to limit the present invention in any way, and any person who is familiar with the technology will not depart from the spirit and scope of the present invention. It goes without saying that various variations and hydration colors can be added within the range.

It is a time chart of the clock data of the low voltage | pressure differential signal of a prior art. It is the implementation structural drawing of the low voltage | pressure differential signal receiver of a prior art. It is the implementation structural drawing of the low voltage | pressure differential induction | guidance | derivation receiving apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Low voltage | pressure differential signal receiver 11 1st differential receiver
12 Second differential receiver
13 First Oversampler 14 Second Oversampler 15 Phase Lock Loop Unit 16 Clock Data Boundary Detection Logic Module

Claims (3)

A low-voltage differential signal receiving apparatus comprising a first differential receiver, a second differential receiver, a phase-locked loop unit, and a clock data boundary detection logic module;
The first differential receiver receives the data signal input from the data signal input terminal, outputs the data signal to the first oversampler, and then outputs the data signal to the clock data boundary detection logic module. And
The second differential receiver receives a clock signal, outputs the clock signal to a second oversampler, and then outputs the clock signal to the clock data boundary detection logic module.
The phase-locked loop device receives a clock signal output from the second differential receiver and outputs oversampling clocks to the first oversampler and the second oversampler, respectively.
The clock data boundary detection logic module can receive the signals output from the first oversampler and the second oversampler, and can output the data signal and the clock signal after passing through the oversampling process,
By looking at the clock signal as one other data signal, the asynchronous clock increases the frequency for the input clock and data, thereby detecting the clock conversion through a specific clock data boundary detection logic module and data bits from the clock and data sampling. Analyzing low voltage differential signal receiver.   2. The low-voltage differential signal receiving apparatus according to claim 1, wherein the number of the data signal input terminals is one or more.   3. The low-voltage differential signal receiving apparatus according to claim 2, wherein the first differential receiver and the number of data signal input terminals are the same.

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