CN114325196A - Signal test system - Google Patents
Signal test system Download PDFInfo
- Publication number
- CN114325196A CN114325196A CN202111675904.0A CN202111675904A CN114325196A CN 114325196 A CN114325196 A CN 114325196A CN 202111675904 A CN202111675904 A CN 202111675904A CN 114325196 A CN114325196 A CN 114325196A
- Authority
- CN
- China
- Prior art keywords
- signal
- module
- eom
- value
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 40
- 238000010586 diagram Methods 0.000 claims abstract description 37
- 238000005070 sampling Methods 0.000 claims abstract description 31
- 238000012545 processing Methods 0.000 claims description 16
- 230000000630 rising effect Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Images
Abstract
The application provides a signal testing system, which comprises a PI module, an ALGO module and an EOM module, wherein the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and clock phase control signals sent by the ALGO module and outputting target clock signals, the EOM module is used for receiving signals to be tested, target clock signals and threshold voltage control signals sent by the ALGO module and outputting statistical results of sampling the signals to be tested, the ALGO module is used for receiving the statistical results and determining eye width values and eye height values of eye diagrams of the signals to be tested, the target clock signals input by the phase interpolation PI module and the threshold voltage control signals sent by the ALGO module are used for sampling and counting the signals to be tested, the ALGO module determines eye width values and eye height values of the eye diagrams of the signals to be tested by using the obtained statistical results, and automatic storage and reading of the eye height and eye width of high-speed signals are realized, the power consumption of the signal testing system is low.
Description
Technical Field
The invention relates to the field of signal testing, in particular to a signal testing system.
Background
Currently, with the advancement of technology, there is an increasing demand for high-speed transmission of signals. However, as the transmission rate of the signal increases, the attenuation of the signal during transmission increases accordingly. Therefore, in a system for transmitting signals at high speed, the loss of a high-frequency channel is compensated by using an equalization technology. And then testing the equalized signal to obtain the parameters of the current signal, and continuously optimizing the signal by using the equalization technology.
When a signal is tested, the eye pattern can reflect the quality of the signal, and how to acquire information related to the eye pattern of the signal is an urgent problem to be solved.
Disclosure of Invention
In view of the above, the present application aims to provide a signal testing system capable of automatically acquiring information related to an eye pattern of a signal, such as eye height and eye width.
An embodiment of the present application provides a signal testing system, the system includes: the device comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module;
the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and a clock phase control signal sent by the ALGO module and outputting a target clock signal;
the EOM module is used for receiving a signal to be tested, the target clock signal and a threshold voltage control signal sent by the ALGO module and outputting a statistical result of sampling the signal to be tested;
and the ALGO module is used for receiving the statistical result and determining the eye width value and the eye height value of the eye pattern of the signal to be detected.
Optionally, the EOM module includes a threshold voltage setting module and a signal processing module;
the threshold voltage setting module is used for traversing threshold voltage values according to the threshold voltage control signal, and the threshold voltage values comprise eye height values of the eye diagram after traversing;
and the signal processing module is used for sampling the signal to be tested according to the rising edge and the falling edge of the target clock signal when traversing the threshold voltage value according to the threshold voltage control signal, and obtaining and storing a statistical result.
Optionally, the statistical result comprises a first statistical result and a second statistical result;
the signal processing module is specifically configured to, when traversing the threshold voltage value according to the threshold voltage control signal, sample the signal to be measured according to a rising edge of the target clock signal to obtain and store a first statistical result, and sample the signal to be measured according to a falling edge of the target clock signal to obtain and store a second statistical result;
and the ALGO module is used for receiving the first statistical result and the second statistical result and determining an eye width value and an eye height value of an eye pattern of the signal to be detected according to the sum of the first statistical result and the second statistical result.
Optionally, the EOM module is further configured to send a statistical end flag signal to the ALGO module, so as to send a statistical result of the signal to be detected to the ALGO module.
Optionally, the ALGO module is further configured to send a reset signal to the EOM module after receiving the statistics end flag signal sent by the EOM module, so that the EOM module is reset according to the reset signal.
Optionally, the ALGO module is configured to maintain the threshold voltage control signal as an initial voltage value, traverse the clock phase control signal, and obtain a plurality of statistical results of the signal to be detected.
Optionally, the plurality of statistical results include a first critical result and a second critical result, a distance between clock phase values corresponding to adjacent first critical results and second critical results is an eye width value of an eye diagram of the signal to be measured, a value of the first critical result is not 0 to 0, and a value of the second critical result is 0 to not 0.
Optionally, the ALGO module is configured to maintain the clock phase control signal as a phase initial value, traverse the threshold voltage control signal, and obtain a plurality of statistical results of the signal to be detected.
Optionally, the initial phase value is a middle value between clock phase values corresponding to the first critical result and the second critical result, the plurality of statistical results include a third critical result, a threshold voltage value corresponding to the third critical result is an eye height value of the signal to be measured, and a value of the third critical result is 0 to non-0.
Optionally, the initial clock signal includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, where the frequency of the first clock signal is one half of the frequency of the signal to be measured, the second clock signal is an inverted signal of the first clock signal, the third clock signal has the same frequency as the first clock signal, a phase difference is 90 °, and the fourth clock signal is an inverted signal of the third clock signal.
The signal testing system provided by the embodiment of the application comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module, wherein the PI module is used for receiving a plurality of initial clock signals orthogonal in pairs and clock phase control signals sent by the ALGO module and outputting target clock signals, the EOM module is used for receiving signals to be tested, the target clock signals and threshold voltage control signals sent by the ALGO module and outputting statistical results of sampling the signals to be tested, the ALGO module is used for receiving the statistical results and determining eye width values and eye height values of eye diagrams of the signals to be tested, namely, the EOM module carries out sampling statistics on the signals to be tested by using the target clock signals input by the phase interpolation PI module and the threshold voltage control signals sent by the ALGO module, and then the ALGO module determines the eye width values and the eye height values of the eye diagrams of the signals to be tested by using the obtained statistical results, the automatic storage and reading of the eye height and the eye width of the high-speed signal are realized, the design flow of signal testing is simplified, the design and testing cost of the signal testing is reduced, the power consumption of a signal testing system is low, and the requirement on the difficulty of realization is also low.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram illustrating a signal testing system according to an embodiment of the present disclosure;
FIG. 2 is a block diagram of another signal testing system provided in an embodiment of the present application;
FIG. 3 is a waveform diagram illustrating an initial clock signal provided by an embodiment of the present application;
fig. 4 shows an eye diagram provided by an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Currently, with the advancement of technology, there is an increasing demand for high-speed transmission of signals. However, as the transmission rate of the signal increases, the attenuation of the signal during transmission increases accordingly. Therefore, in a system for transmitting signals at high speed, the loss of a high-frequency channel is compensated by using an equalization technology. And then testing the equalized signal to obtain the parameters of the current signal, and continuously optimizing the signal by using the equalization technology.
When a signal is tested specifically, an Eye Diagram can reflect the quality of the signal, and the Eye Diagram (Eye Diagram) is a graph displayed after a series of code elements of the signal are accumulated on an oscilloscope according to a certain rule, and is often used for analyzing the signal integrity of a high-speed interconnection system, wherein the signal integrity refers to the quality of the signal on a transmission path and is a standard for measuring the signal quality.
One of the more important information of the Eye diagram is Eye Height (Eye Height), which is the distance of the blank area on the Eye diagram on the vertical axis, and Eye Width (Eye Width), which reflects the noise margin of the signal on the transmission path when the signal data superimposed on the Eye diagram is sufficient. The eye width refers to a distance of a blank area on the eye pattern on the horizontal axis, and when the signal data superimposed on the eye pattern is sufficient, the eye width can reflect a settling time of the signal on the transmission path.
The current system for acquiring the relevant information of the eye pattern is high in implementation difficulty and cost, the frequency of a clock signal used for sampling is the same as that of a signal to be detected, the sampling difficulty is high, and the power consumption of the system is high.
How to acquire the high-speed signal efficiently and acquire the relevant information of the eye pattern of the high-speed signal at low cost is an urgent problem to be solved.
Based on this, the signal testing system provided in the embodiment of the present application includes a phase interpolation PI module, a logic control algorithm ALGO module, and a data sampling and processing EOM module, where the PI module is configured to receive a plurality of initial clock signals orthogonal to each other and a clock phase control signal sent by the ALGO module, and output a target clock signal, the EOM module is configured to receive a signal to be tested, the target clock signal, and a threshold voltage control signal sent by the ALGO module, and output a statistical result of sampling the signal to be tested, the ALGO module is configured to receive the statistical result, and determine an eye width value and an eye height value of an eye diagram of the signal to be tested, that is, the eye width value and the eye height value of the eye diagram of the signal to be tested are sampled and counted by the EOM module using the target clock signal input by the phase interpolation PI module and the threshold voltage control signal sent by the ALGO module, and then the ALGO module determines the eye width value and the eye height value of the eye diagram of the signal to be tested by using the obtained statistical result, the automatic storage and reading of the eye height and the eye width of the high-speed signal are realized, the design flow of signal testing is simplified, the design and testing cost of the signal testing is reduced, the power consumption of a signal testing system is low, and the requirement on the difficulty of realization is also low.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a signal testing system according to an embodiment of the present disclosure. The signal testing system in the embodiment of the application can be applied to testing signals transmitted at a high speed and automatically acquiring relevant information of an eye pattern of the signals transmitted at the high speed. The signal testing system may be integrated in a chip.
The signal testing system 100 provided by the embodiment of the present application includes: a Phase Interpolation (PI) module 110, an algorithm (algogo) module 120, and a data sampling and processing module 130, namely, an Eye Opening Monitor (EOM) module 130 for implementing Eye Opening of an Eye diagram of a signal to be detected.
In the embodiment of the present application, the PI module 110 is configured to receive a plurality of initial clock signals orthogonal to each other and a clock phase control signal PI _ phsel _ code <5:0> sent by the ALGO module 120, and output a target clock signal PI _ CLK to the EOM module 130.
The plurality of initial clock signals include a first clock signal CLKI, a second clock signal CLKIB, a third clock signal CLKQ, and a fourth clock signal CLKQB, where the frequency of the first clock signal CLKI is one half of the frequency of the signal to be measured Vin, the second clock signal CLKIB is an inverted signal of the first clock signal CLKI, the frequency of the third clock signal CLKQ is the same as that of the first clock signal CLKI, and the phase difference is 90 °, and the fourth clock signal CLKQB is an inverted signal of the third clock signal CLKQ, as shown in fig. 3, which is a waveform diagram of an initial clock signal provided in the embodiment of the present application.
The four initial clock signals CLKI, CLKIB, CLKQ, and CLKQB have a strict phase relationship and must be orthogonal two by two, so that the target clock signal PI _ CLK generated by the PI module 110 is uniformly distributed over the entire clock period after one cycle traversal of the clock phase control signal PI _ phsel _ code <5:0>, and complete eye diagram information can be obtained.
That is, the PI module 110 receives the initial clock signals of four phases and outputs the target clock signal PI _ CLK of a phase between the four initial clock signals according to the clock phase control signal PI _ phsel _ code <5:0> of a 6-bit (bit) code value provided by the ALGO module 120. After the ALGO module 120 traverses all the clock phase control signals PI _ phsel _ code <5:0> of the 6-bit code value for controlling the phase of the target clock signal PI _ CLK once, the phase of the target clock signal PI _ CLK output by the PI module 110 is exactly and uniformly distributed for two clock cycles of the high-speed signal Vin, that is, the horizontal axis information of the eye diagram in two Unit Intervals (UI) is covered, as shown in fig. 4, which is an eye diagram provided by the embodiment of the present application.
In the embodiment of the present application, the EOM module 130 is configured to receive a signal to be measured Vin, a target clock signal PI _ CLK, and a threshold voltage control signal EOM _ vref _ code <5:0> sent by the ALGO module 120, and output a statistical result of sampling the signal to be measured Vin.
The EOM module 130 includes a threshold voltage setting module 131 and a signal processing module 132, as shown in fig. 2, the threshold voltage setting module 131 is configured to traverse threshold voltage values according to a threshold voltage control signal EOM _ vref _ code <5:0>, and the threshold voltage values are traversed to include eye height values of an eye diagram. That is, the threshold voltage control signal eom _ vref _ code <5:0> of the 6bit code value provided by the ALGO module 120 can control the threshold voltage setting module 131 to set the threshold voltage value.
As an example, when the code value of the threshold voltage control signal eom _ vref _ code <5:0> is 00, which indicates that the threshold voltage is V1+/V1-, i.e., the common mode voltage corresponding to the high-speed signal Vin, shown in fig. 4 at this time, when the code value of the threshold voltage control signal eom _ vref _ code <5:0> is increased correspondingly, the threshold voltage becomes V2+/V2-, V3+/V3-, so that the threshold voltage control signal eom _ vref _ code <5:0> controlling the threshold voltage 6-bit code value is traversed once, the threshold voltage just distributes the swing of the high-speed signal Vin uniformly, i.e., covers the information of the vertical axis direction of the eye diagram, and the threshold voltage value traversal is completed to include the eye height value of the eye diagram.
The signal processing module 132 is configured to sample the signal to be measured Vin according to the rising edge and the falling edge of the target clock signal PI _ CLK when traversing the threshold voltage value according to the threshold voltage control signal eom _ vref _ code <5:0>, and obtain and store a statistical result.
The target clock signal PI _ CLK provides sampling clocks with different phases for the EOM module 130, and the frequency of the sampling clocks is half of the frequency of the high-speed signal Vin, that is, the rising edge and the falling edge of the target clock signal PI _ CLK are used for sampling simultaneously, so that the requirement on the sampling speed of the EOM module 130 is relatively low, and the power consumption of the whole signal testing system is also reduced.
In practical applications, the EOM module 130 is mainly used to count the number of signal edges passing through the positive and negative threshold voltages of the corresponding signal edge for a period of time, and obtain a statistical result.
The statistical result includes a first statistical result eom _ value _ p <5:0> and a second statistical result eom _ value _ n <5:0>, and the signal processing module 132 is specifically configured to sample the signal to be measured Vin according to a rising edge of the target clock signal PI _ CLK when the threshold voltage is traversed according to the threshold voltage control signal eom _ vref _ code <5:0>, obtain and store the first statistical result eom _ value _ p <5:0>, sample the signal to be measured Vin according to a falling edge of the target clock signal PI _ CLK, and obtain and store the second statistical result eom _ value _ n <5:0 >.
In practical applications, the EOM module 130 is further configured to send a statistical end flag signal EOM _ done to the ALGO module 120, so as to send a statistical result of the signal to be measured Vin to the ALGO module 120, specifically, send a first statistical result EOM _ value _ p <5:0> and a second statistical result EOM _ value _ n <5:0> of the signal to be measured Vin to the ALGO module 120.
When the level of the end-of-statistics flag signal EOM _ done changes from low to high, which means that the EOM module 130 obtains the statistical result, the counting of a certain clock phase or a certain voltage threshold of the signal Vin to be measured is ended.
In an embodiment of the present application, the ALGO module 120 is configured to receive the statistical result, and determine an eye width value and an eye height value of an eye pattern of the signal Vin to be measured.
Specifically, ALGO module 120 outputs clock phase control signals PI _ phsel _ code <5:0> to PI module 110, controls the phase of the target clock signal PI _ CLK output by PI module 110, meanwhile, a threshold voltage control signal EOM _ vref _ code <5:0> is output to the EOM module 130, the threshold voltage set by the EOM module 130 is controlled, a first statistical result EOM _ value _ p <5:0> and a second statistical result EOM _ value _ n <5:0> sent by the EOM module 130 are received, and determines the eye width value and the eye height value of the eye pattern of the signal Vin to be measured according to the sum of the first statistical result EOM _ value _ p <5:0> and the second statistical result EOM _ value _ n <5:0>, and also receives the statistical end flag signal EOM _ done sent by the EOM module 130, sends a reset signal EOM _ rst _ n to the EOM module 130, so that the EOM module 130 is reset according to the reset signal EOM _ rst _ n.
That is, the ALGO module 120 sends a reset signal EOM _ rst _ n to the EOM module 130, and resets the EOM module 130 before the EOM module 130 starts to operate and after the counting end flag signal EOM _ done changes from low to high, so as to ensure that the counting result of the EOM module 130 starts to be counted from zero each time.
In the embodiment of the present application, when the PI module 110, the EOM module 130, and the ALGO module 120 are specifically used to test the high-speed signal Vin, the method may include the following steps: initializing the system, traversing the phase code value, determining the eye width, traversing the threshold voltage code value, and determining the eye height.
Prior to testing, the system may be initialized, i.e., the ALGO module 120 pulls the reset signal EOM _ rst _ n signal low to the reset EOM module 130, and sets the code value of the threshold voltage control signal EOM _ vref _ code <5:0> to 00, and sets the code value of the clock phase control signal pi _ phsel _ code <5:0> to 00.
The phase code values are then traversed to determine the eye width. After the PI module 110 and the EOM module 130 are stabilized, the threshold voltage control signal EOM _ vref _ code <5:0> is kept as the voltage initial value 00, and the code values of the clock phase control signals PI _ phsel _ code <5:0> are traversed to obtain a plurality of statistical results of the signal Vin to be measured.
Specifically, the reset signal EOM _ rst _ n is released, and at this time, the EOM module 130 operates normally, and the ALGO module 120 starts to traverse the code values of the clock phase control signals pi _ phsel _ code <5:0> from 00 to 3F.
The traversal process is as follows: firstly, setting the code value of the threshold voltage control signal EOM _ vref _ code <5:0> to be a voltage initial value 00, and keeping the voltage initial value 00 unchanged, setting the threshold voltage corresponding to the voltage initial value to be V1+/V1-, namely, transversely crossing the threshold voltage at the middle of the eye diagram, as shown in FIG. 4, the PI module 110 outputs a corresponding target clock signal PI _ CLK at an initial phase where the code value of the clock phase control signal PI _ phsel _ code <5:0> is 00, the EOM module 130 uses the target clock signal PI _ CLK to sample and process the high-speed signal to be tested Vin, the sampling frequency is half of the frequency of the signal to be tested, and obtains a sampling result of the rising edge of the target clock signal PI _ CLK, namely, a first statistical result EOM _ value _ p <5:0> and a falling edge sampling result, namely, a second statistical result eoM _ value _ n <5:0>, and the EOM module 130 sends a statistical end flag EOM _ done, waiting until the rising edge of the end-of-statistics flag signal EOM _ done comes, the count values of the first statistical result EOM _ value _ p <5:0> and the second statistical result EOM _ value _ n <5:0> are locked, the ALGO module 120 records the sum of the two locked statistical results, then pulls down the reset signal EOM _ rst _ n, resets the EOM module 130, then keeps the code value of the threshold voltage control signal EOM _ vref _ code <5:0> unchanged at the initial voltage value 00, changes the code value of the clock phase control signal pi _ phsel _ code <5:0> to 01, releases the reset signal EOM _ rst _ n after the EOM module 130 is stabilized, continues the operation of the EOM module 130 until the rising edge of the end-of-statistics flag signal EOM _ done comes, continues to record the sum of the two locked statistical results until the clock phase control signal pi _ phsel _ code <5:0> is traversed from 00 to 3, ending the process of traversing the phase.
After obtaining a plurality of statistical results corresponding to code values of a plurality of clock phase control signals pi _ phsel _ code <5:0>, the statistical results include a first critical result and a second critical result, a distance between clock phase values corresponding to adjacent first critical results and second critical results is an eye width value of an eye diagram of the signal Vin to be measured, a value of the first critical result is not 0 to 0, and a value of the second critical result is 0 to not 0.
When determining the eye width of the eye diagram of the signal Vin to be tested, first determining a first critical result from a plurality of statistical results, the value of the first critical result being non-0 to 0, where non-0 indicates that a signal edge passes through positive and negative threshold voltages at the phase, 0 indicates that no signal edge passes through the positive and negative threshold voltages at the phase, then determining a second critical result, the value of the second critical result being 0 to non-0, determining the code values of clock phase control signals pi _ phsel _ code <5:0> respectively corresponding to the adjacent first critical result and second critical result, where the distance between the adjacent two clock phase control signals pi _ phsel _ code <5:0> is the blank space appearing on the horizontal axis in the eye diagram, and jitter appears on each critical result due to the limited accuracy of the signal testing system, as shown in fig. 4, that a short-term shift appears on a signal at a certain time relative to its ideal position, this results in multiple blank spaces being calculated, but not the actual eye width value of the eye pattern, so the ALGO module 120 automatically finds the maximum blank space, which is the actual eye width, i.e., determines the eye width value of the eye pattern.
After traversing the phase code values to determine the eye width of the eye diagram, the threshold voltage code values may also be traversed to determine the eye height. And keeping the clock phase control signal pi _ phsel _ code <5:0> as a phase initial value, traversing the code value of the threshold voltage control signal eom _ vref _ code <5:0> and obtaining a plurality of statistical results of the signal Vin to be measured.
Specifically, the EOM module 130 is reset, the initial phase value is set to be the middle value between the clock phase values corresponding to the first critical result and the second critical result, that is, the code value of the clock phase control signal PI _ phsel _ code <5:0> corresponding to the middle point of the two critical results of the eye width is used as the initial phase value of the PI module 110, then the threshold voltage control signal EOM _ vref _ code <5:0> is traversed from the code value 00, and the code value of the clock phase control signal PI _ phsel _ code <5:0> is kept unchanged as the initial phase value in the traversing process, so as to obtain a plurality of statistical results.
The traversal process is as follows: firstly, setting the code value of a clock phase control signal PI _ phsel _ code <5:0> as a phase initial value, keeping the phase initial value unchanged, outputting a corresponding target clock signal PI _ CLK by the PI module 110 when the code value of the clock phase control signal PI _ phsel _ code <5:0> is the phase initial value, sampling and processing the high-speed signal to be detected Vin by the EOM module 130 by using the target clock signal PI _ CLK, wherein the sampling frequency is half of the frequency of the signal to be detected Vin, and obtaining a rising edge sampling result of the target clock signal PI _ CLK, namely a first statistical result EOM _ value _ p <5:0> and a falling edge sampling result, namely a second statistical result eValue _ n <5:0>, at the moment, sending a statistical end mark signal eOM _ done by the EOM module 130, and locking a count value of the first statistical result eOM _ value _ p <5:0> and the second statistical end mark signal eOM _ done < 0>, the ALGO module 120 records the sum of the two locked statistics, then pulls down the reset signal EOM _ rst _ n to reset the EOM module 130, then keeps keeping the code value of the clock phase control signal pi _ phsel _ code <5:0> unchanged as the initial phase value, changes the code value of the threshold voltage control signal EOM _ vref _ code <5:0> to 01, and after the EOM module 130 is stabilized, releases the reset signal EOM _ rst _ n, and the EOM module 130 continues to operate until the rising edge of the count end flag signal EOM _ done arrives, and continues to record the sum of the two locked statistics until the code value of the threshold voltage control signal EOM _ vse _ code <5:0> is traversed from 00 to 3F, and then ends the process of traversing the threshold voltage.
And determining a third critical result in the plurality of statistical results, wherein the value of the third critical result is 0 to non-0, and the threshold voltage value corresponding to the code value of the threshold voltage control signal eom _ vref _ code <5:0> corresponding to the third critical result is the eye height value of the signal to be detected.
In practical applications, instead of traversing the code values of the threshold voltage control signals EOM _ vref _ code <5:0> from 00 to 3F, the code values of the threshold voltage control signals EOM _ vref _ code <5:0> are traversed from 0 to non-0 of the sum of the first statistical result EOM _ value _ p <5:0> and the second statistical result EOM _ value _ n <5:0> of the EOM module 130, so as to obtain a third critical result, the code values of the threshold voltage control signals EOM _ vref _ code <5:0> are recorded at this time, the traversal of the threshold voltage control signals EOM _ vref _ code <5:0> is ended, and the threshold voltage values corresponding to the code values of the threshold voltage control signals EOM _ vref _ code <5:0> at this time are approximately equivalent to the maximum eye height value of the eye diagram.
In practical application, when the signal to be detected Vin is not input, the signal detection system is in a turn-off state, so that the power consumption of the signal detection system can be saved. When the high-speed signal Vin to be measured is input, the signal detection system will normally work.
Therefore, the signal testing system provided by the embodiment of the application comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module, wherein the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and clock phase control signals sent by the ALGO module and outputting target clock signals, the EOM module is used for receiving signals to be tested, the target clock signals and threshold voltage control signals sent by the ALGO module and outputting statistical results of sampling the signals to be tested, the ALGO module is used for receiving the statistical results and determining eye width values and eye height values of eye diagrams of the signals to be tested, namely, the EOM module carries out sampling statistics on the signals to be tested by using the target clock signals input by the phase interpolation PI module and the threshold voltage control signals sent by the ALGO module, and then the ALGO module determines the eye width values and the eye height values of the eye diagrams of the signals to be tested by using the obtained statistical results, the automatic storage and reading of the eye height and the eye width of the high-speed signal are realized, the design flow of signal testing is simplified, the design and testing cost of the signal testing is reduced, the power consumption of a signal testing system is low, and the requirement on the difficulty of realization is also low.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A signal testing system, the system comprising: the device comprises a phase interpolation PI module, a logic control algorithm ALGO module and a data sampling and processing EOM module;
the PI module is used for receiving a plurality of initial clock signals which are orthogonal in pairs and a clock phase control signal sent by the ALGO module and outputting a target clock signal;
the EOM module is used for receiving a signal to be tested, the target clock signal and a threshold voltage control signal sent by the ALGO module and outputting a statistical result of sampling the signal to be tested;
and the ALGO module is used for receiving the statistical result and determining the eye width value and the eye height value of the eye pattern of the signal to be detected.
2. The system of claim 1, wherein the EOM module comprises a threshold voltage setting module and a signal processing module;
the threshold voltage setting module is used for traversing threshold voltage values according to the threshold voltage control signal, and the threshold voltage values comprise eye height values of the eye diagram after traversing;
and the signal processing module is used for sampling the signal to be tested according to the rising edge and the falling edge of the target clock signal when traversing the threshold voltage value according to the threshold voltage control signal, and obtaining and storing a statistical result.
3. The system of claim 2, wherein the statistical result comprises a first statistical result and a second statistical result;
the signal processing module is specifically configured to, when traversing the threshold voltage value according to the threshold voltage control signal, sample the signal to be measured according to a rising edge of the target clock signal to obtain and store a first statistical result, and sample the signal to be measured according to a falling edge of the target clock signal to obtain and store a second statistical result;
and the ALGO module is used for receiving the first statistical result and the second statistical result and determining an eye width value and an eye height value of an eye pattern of the signal to be detected according to the sum of the first statistical result and the second statistical result.
4. The system of claim 1, wherein the EOM module is further configured to send a statistics end flag signal to the ALGO module, so as to send a statistics result of the signal to be tested to the ALGO module.
5. The system of claim 4, wherein the ALGO module is further configured to send a reset signal to the EOM module after receiving the end of statistics flag signal sent by the EOM module, so that the EOM module is reset according to the reset signal.
6. The system of claim 1, wherein the ALGO module is configured to maintain the threshold voltage control signal at an initial voltage value, and traverse the clock phase control signal to obtain a plurality of statistical results for the signal under test.
7. The system of claim 6, wherein the plurality of statistical results includes a first critical result and a second critical result, and a distance between clock phase values corresponding to adjacent first critical result and second critical result is an eye width value of an eye pattern of the signal to be measured, the value of the first critical result is not 0 to 0, and the value of the second critical result is 0 to not 0.
8. The system of claim 6, wherein the ALGO module is configured to maintain the clock phase control signal as an initial phase value, and traverse the threshold voltage control signal to obtain a plurality of statistical results for the signal under test.
9. The system of claim 8, wherein the initial phase value is an intermediate value between the clock phase values corresponding to the first and second critical results, the plurality of statistical results includes a third critical result, a threshold voltage value corresponding to the third critical result is an eye height value of the signal under test, and a value of the third critical result is 0 to non-0.
10. The system according to any one of claims 1 to 9, wherein the initial clock signal comprises a first clock signal, a second clock signal, a third clock signal and a fourth clock signal, the frequency of the first clock signal is one half of the frequency of the signal to be measured, the second clock signal is an inverted signal of the first clock signal, the third clock signal has the same frequency as the first clock signal and is 90 ° out of phase, and the fourth clock signal is an inverted signal of the third clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111675904.0A CN114325196A (en) | 2021-12-31 | 2021-12-31 | Signal test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111675904.0A CN114325196A (en) | 2021-12-31 | 2021-12-31 | Signal test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114325196A true CN114325196A (en) | 2022-04-12 |
Family
ID=81022291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111675904.0A Pending CN114325196A (en) | 2021-12-31 | 2021-12-31 | Signal test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114325196A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116148643A (en) * | 2023-04-21 | 2023-05-23 | 长鑫存储技术有限公司 | Eye pattern analysis method |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060109896A1 (en) * | 2004-11-23 | 2006-05-25 | Gunter Steinbach | Characterizing eye diagrams |
| US8451883B1 (en) * | 2009-12-03 | 2013-05-28 | Altera Corporation | On-chip full eye viewer architecture |
| CN103926471A (en) * | 2014-04-25 | 2014-07-16 | 浙江大学 | Eye-open monitor device for high-speed serializer/deserializer and testing method |
| US20140270030A1 (en) * | 2013-03-15 | 2014-09-18 | Dima Hammad | Eye width measurement and margining in communication systems |
| CN104378321A (en) * | 2014-11-26 | 2015-02-25 | 英特格灵芯片(天津)有限公司 | Method and circuit for integrating adaptive equalization parameter adjusting and transmission performance testing |
| KR20160089922A (en) * | 2015-01-20 | 2016-07-29 | 삼성전자주식회사 | Integrated circuit and serdes device having eye opening monitor |
| US20170031436A1 (en) * | 2015-07-28 | 2017-02-02 | Phison Electronics Corp. | Eye-width detector, memory storage device and eye-width detection method of data signal |
| CN109194460A (en) * | 2018-10-26 | 2019-01-11 | 光梓信息科技（上海）有限公司 | Clock data recovery circuit, adaptive adjustment module and method |
| CN111713029A (en) * | 2017-12-07 | 2020-09-25 | 康杜实验室公司 | Decision feedback equalization correction of eye pattern measurements |
| CN112462121A (en) * | 2020-10-13 | 2021-03-09 | 中国科学院微电子研究所 | Eye pattern wave filter system and eye pattern testing method |
-
2021
- 2021-12-31 CN CN202111675904.0A patent/CN114325196A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060109896A1 (en) * | 2004-11-23 | 2006-05-25 | Gunter Steinbach | Characterizing eye diagrams |
| US8451883B1 (en) * | 2009-12-03 | 2013-05-28 | Altera Corporation | On-chip full eye viewer architecture |
| US20140270030A1 (en) * | 2013-03-15 | 2014-09-18 | Dima Hammad | Eye width measurement and margining in communication systems |
| CN103926471A (en) * | 2014-04-25 | 2014-07-16 | 浙江大学 | Eye-open monitor device for high-speed serializer/deserializer and testing method |
| CN104378321A (en) * | 2014-11-26 | 2015-02-25 | 英特格灵芯片(天津)有限公司 | Method and circuit for integrating adaptive equalization parameter adjusting and transmission performance testing |
| KR20160089922A (en) * | 2015-01-20 | 2016-07-29 | 삼성전자주식회사 | Integrated circuit and serdes device having eye opening monitor |
| US20170031436A1 (en) * | 2015-07-28 | 2017-02-02 | Phison Electronics Corp. | Eye-width detector, memory storage device and eye-width detection method of data signal |
| CN111713029A (en) * | 2017-12-07 | 2020-09-25 | 康杜实验室公司 | Decision feedback equalization correction of eye pattern measurements |
| CN109194460A (en) * | 2018-10-26 | 2019-01-11 | 光梓信息科技（上海）有限公司 | Clock data recovery circuit, adaptive adjustment module and method |
| CN112462121A (en) * | 2020-10-13 | 2021-03-09 | 中国科学院微电子研究所 | Eye pattern wave filter system and eye pattern testing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116148643A (en) * | 2023-04-21 | 2023-05-23 | 长鑫存储技术有限公司 | Eye pattern analysis method |
| CN116148643B (en) * | 2023-04-21 | 2023-09-15 | 长鑫存储技术有限公司 | Eye pattern analysis method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6728311B1 (en) | Apparatus and method for creating eye diagram | |
| US7467336B2 (en) | Method and apparatus to measure and display data dependent eye diagrams | |
| US7606297B2 (en) | Method and system for creating an eye diagram using a binary data bit decision mechanism | |
| JP2007519005A (en) | Method and apparatus for measuring jitter | |
| US7573957B2 (en) | Strobe technique for recovering a clock in a digital signal | |
| US8779952B1 (en) | Background calibration of threshold errors in analog to digital converters | |
| US7876873B2 (en) | Asynchronous ping-pong counter and thereof method | |
| US20070118316A1 (en) | Determining frequency components of jitter | |
| US7668235B2 (en) | Jitter measurement algorithm using locally in-order strobes | |
| CN115667945A (en) | System and method for separating and classifying signals using a circulating loop image | |
| CN114325196A (en) | Signal test system | |
| US10797984B1 (en) | Systems and methods for timestamping a data event | |
| EP3388844B1 (en) | Analog transitional storage | |
| CN109283833A (en) | A kind of time statistical system and method | |
| US8054907B2 (en) | Waveform analyzer | |
| US11178036B2 (en) | Systems and methods for measuring latency in a network device | |
| CN107707258B (en) | Eye diagram generator | |
| US10680792B1 (en) | Systems and methods for timing a signal | |
| CN111863114B (en) | Chip sampling quasi-position determining method and device | |
| US20060149492A1 (en) | System and method for testing differential signal crossover using undersampling | |
| US20230006903A1 (en) | Systems and methods for timing a signal | |
| Zhang et al. | 48-channel coincidence counting system for multiphoton experiment | |
| CN111371453A (en) | Signal period measuring circuit and method | |
| US11626934B1 (en) | Probability-based capture of an eye diagram on a high-speed digital interface | |
| JP2002015523A (en) | Method for measuring timing jitter and reproducing method using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |