JP2002015523A - Method for measuring timing jitter and reproducing method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally methods for measuring the timing jitter of a signal after an A/D conversion requires a measuring device such as a TIA, and that it is difficult to improve accuracy of measurement due to the speed-up of signals. SOLUTION: The method for measuring timing jitters includes an A/D conversion means for converting an inputted analog signal into a digital value, a polarity discriminating means 3 for discriminating the polarity of an output signal sequence of the A/D conversion means 1 when the sequence crosses the zero level, a sampled data holding means 2 for holding the value of one or more sampling points before or after the output timing of a polarity discriminating means 3, a supplementary means 4 for supplementing the zero cross timing which is the timing when the signal sequence crosses the zero level from the value of the sampled data holding means 2, and a statistical processing means 5 for performing the statistical processing of an output of the supplementary means 4 for obtaining variance and standard deviation. Thereby, a superior method for measuring timing jitters adaptive to a high-speed operation and the reproduction method using the same are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus or a communication apparatus for reproducing a signal from an optical disk apparatus or the like.

[0002]

2. Description of the Related Art In recent years, this kind of information reproducing apparatus or communication apparatus has been rapidly changing to large capacity (high speed) and small size, and the technology thereof has shown remarkable progress.

FIG. 15 is a block diagram showing an example of a conventional timing jitter measuring method. FIG. 16 is a waveform illustrating an example of a timing jitter measurement method, FIG. 17 is a diagram illustrating an ideal statistical distribution, and FIG. 18 is a diagram illustrating a statistical distribution according to a conventional timing jitter measurement method. In FIG. 15, the analog signal 100 input to the binarizing means 14 is generated as a binarized signal 103. This binary signal 1
From 03, a synchronous clock 102 synchronized with the binary signal 103 is generated by the synchronous clock generating means 3. The timing shift is measured by the timing measuring means 2 for measuring the time shift between the binary signal 103 and the synchronous clock 102, and the amount of the shift is statistically processed by the statistical processing means 5 to determine the timing jitter σ. Ask. The binary signal 103 and the synchronous clock 10 obtained by the timing measuring means
The deviation amount 104 of 2 is input to the statistical processing means 5 and subjected to calculations such as an average value, a square addition, and a root mean square to calculate a standard deviation and a variance σ 105. The statistical distribution is ideally the distribution shown in FIG. The variance σ 105 shown in FIG. 17 is a very important parameter for communication and a data storage device such as an optical disk as timing jitter. Conventionally, the statistical processing means shown here generally uses a dedicated measuring device such as a time interval analyzer (hereinafter referred to as TIA) to sample and measure at a frequency much higher than the signal frequency of the signal under measurement.

[0004]

In such a timing jitter measuring method, both a binary signal obtained by binarizing an analog signal and a synchronous clock synchronized with the binary data are required for timing jitter measurement. Was. However, due to the speeding up of communication devices and the densification of storage devices, the frequency of signals has increased, and high-frequency signals have wrapped around the input analog signals in measurements with conventional timing jitter measurement devices, etc. It has become difficult to measure accurate timing jitter. In addition, as the speed and the density have been increased, the conventional analog technology has reached the limit of performance improvement, and a signal processing technology using a digital technology has become necessary. In signal processing technology using digital technology, A /
Using a D converter, an analog signal is converted into a digital signal to perform signal processing. However, there is no method for measuring the timing jitter of the signal that has been subjected to the A / D conversion in this manner, so that it has been very difficult to measure the timing jitter. Also, if the frequency of the signal to be measured increases, it becomes difficult to directly measure the timing jitter between the data and the clock. Therefore, the timing jitter between the data is measured. At this time, a statistical distribution as shown in FIG. 17 was obtained, and it was very difficult to accurately measure the timing jitter of a signal having various frequency components.

The present invention utilizes a characteristic of a digital signal processing method and has an excellent timing jitter capable of supporting a high-speed operation with a maximum frequency of about the same frequency as a channel clock without using a measuring device such as a TIA. The purpose of the present invention is to provide a measuring method and a reproducing method using the measuring method.

[0006]

Means for Solving the Problems To solve this problem, a timing jitter measuring method and a reproducing method using the same according to the present invention include an A / D converter for converting an input analog signal into a digital value, Polarity discriminating means for discriminating the polarity when the output signal sequence of the A / D converter crosses the zero level, and 1 before and after the output timing of the polarity discriminating means.
Sample value holding means for holding values of one or a plurality of sampling points; complementation means for complementing a zero-cross timing at which a signal sequence crosses zero level from the value of the sample value retention means; and cumulative output of the complementation means And a cumulative addition means for obtaining the amount of timing jitter.

A / D conversion means for converting an input analog signal into a digital value, polarity determination means for determining the polarity when the output signal sequence of the A / D converter crosses zero level, and polarity determination. Sample value holding means for holding the values of one or more sampling points before and after the output timing of the means, and complement means for complementing the zero-cross timing, which is the timing at which the signal sequence crosses the zero level from the value of the sample value holding means And statistical processing means for statistically processing the output of the complementing means to obtain the variance and the standard deviation.

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after a timing when an output signal sequence of the A / D converter crosses a zero level are held. It has a sample value holding means, and an adding means for adding a set of sampling values held in the sample value holding means, and the output of the adding means is cumulatively added to obtain a timing jitter amount. .

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after a timing when an output signal sequence of the A / D converter crosses a zero level. Sample value holding means, zero point detection means for detecting a sample point closest to the zero level in the signal sequence held in the sample value holding means, and zero cross detection means for detecting a zero cross timing when crossing the zero level And cumulative addition means for cumulatively adding the value of the zero level detected by the zero point detection means immediately before or immediately after the zero cross timing detected by the zero cross detection means to obtain the amount of timing jitter. It is.

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after a timing when an output signal sequence of the A / D converter crosses a zero level. Sample value holding means, zero point detection means for detecting a sample point closest to the zero level in the signal sequence held in the sample value holding means, and zero cross detection means for detecting a zero cross timing when crossing the zero level And statistical processing means for statistically processing the output of the zero point detecting means to obtain a variance and a standard deviation.

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after a timing when an output signal sequence of the A / D converter crosses a zero level. A sample value holding unit, a complementing unit that complements a zero cross timing, which is a timing at which the signal sequence crosses the zero level from the value of the sample value holding unit, and a zero level among the signal sequences held in the sample value holding unit. Complementary to the present invention is a zero point detecting means for detecting a near sample point, and a sampling timing control means for controlling a sampling timing of an A / D converter so that a sample value obtained by the zero point detecting means is close to a zero level. The output of the means is cumulatively added to obtain the amount of timing jitter.

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after the timing when the output signal sequence of the A / D converter crosses zero level. The sampling value holding means and a sampling value of a rising edge or a falling edge in an output signal sequence of the sample value holding means are selectively held, and a timing jitter amount is obtained from a sampling value of an arbitrary edge. .

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after a timing when an output signal sequence of the A / D converter crosses a zero level. Sample value holding means, and statistics for selectively holding a sampling value of a rising edge or a falling edge in an output signal sequence of the sample value holding means and statistically processing the variance and standard deviation from a sampling value of an arbitrary edge. And processing means.

A / D conversion means for converting an input analog signal into a digital value, and a set of sampling values before and after the timing when the output signal sequence of the A / D converter crosses zero level. Holding both the rising edge or the falling edge of the sampled signal sequence,
And statistical processing means for statistically processing the two zero-crossing signals by mixing the zero-crossing signal and the falling edge to obtain a variance and a standard deviation.

A / D conversion means for converting an input analog signal into a digital value, polarity determination means for determining the polarity when the output signal sequence of the A / D conversion means crosses zero level, Sample value holding means for holding a set of sampling values before and after the timing when the output signal sequence of the D converter crosses the zero level, and complements the timing corresponding to zero crossing from the sample sequence held in the sample value holding means. And a statistical processing means for statistically processing the output of the complementing means to obtain a variance and a standard deviation.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram of a timing jitter measuring system for measuring timing jitter from a signal sequence converted into a digital value and a reproducing system using the same according to a first embodiment of the present invention. FIG. 1 shows an A / D converter 1 for converting an input analog signal into a digital value, a sample value holding unit 2 for holding a series of output values of the A / D converter, and a reference numeral 3 for an input signal. A polarity discriminating means for discriminating the positive and negative polarities of the signal, a complementing means for complementing and generating desired data from a signal sequence output from the sample value holding means, and a cumulative adding means for accumulating and adding outputs of the complementing means. Make up. FIG. 10 is a waveform diagram showing an embodiment of the present invention, and FIG. 11 is a diagram for explaining a method of generating complementary data P.

The operation of the timing jitter measuring method for determining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, an analog reproduction signal 100 is input to the A / D conversion means 1. The A / D converter 1 continuously samples the input analog signal 100 at a desired cycle and converts it into a digital signal 101. The sampling clock is a synchronous clock 10
2 is used. The digital signal 101 is inputted to the polarity discriminating means 3 and is compared with a reference level (reference level). The polarity of the polarity discriminating signal 112 is changed by the digital signal 101 inputted at a timing crossing the reference level. A / D conversion means 1
Digital signal 101 and polarity discrimination signal 11
2 is input, and the values of one or more sample points before and after the change point of the polarity determination signal 112 are held. The complementing means 4 includes, as shown in FIG.
At the point corresponding to the timing of crossing the zero level from the sequence of the sample signal 113 which is the output of
Generate First, a signal a1 which is a set of signals before and after the point where the digital signal 101 crosses the zero level signal 110
06 and the signal b107. Next, based on the level a of the signal a106 and the level b of the signal b107, a point that intersects a zero level between the pair of signals is complemented on the time axis. Regardless of whether the sampling period Tw109 is known or unknown, complementary data P108 of the zero level signal 110 is obtained from the levels of the signal a106 and the signal b107 by the following equation.

P = ax100 / (ab) -50 The supplementary data P108 is input to the subsequent cumulative addition means 6. The accumulating means 6 accumulatively adds the complementary data generated by the complementing means 4 to generate and provide timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Embodiment 2) FIG. 2 is a block diagram showing a timing jitter measuring system and a reproducing system using the same according to a second embodiment. In FIG. 2, reference numeral 1 denotes an input analog signal. A / D conversion means for converting into a digital value, 2 is a sample value holding means for holding a series of output values of the A / D conversion means, 3 is polarity discrimination means for discriminating between positive and negative polarities of an input signal, and 4 is a sample value. Complementing means for complementing and generating desired data from the signal sequence output from the holding means, and statistical processing means for statistically processing the output of the complementing means and generating variance or standard deviation and a similar statistic. .

The operation of the timing jitter measuring method for obtaining the timing jitter configured as described above will be described below.

First, as in the first embodiment, at the time of signal reproduction, the analog reproduction signal 100 is input, and the complementing means 4 generates complementary data P108. This complementary data P108 is used as an input to the statistical processing means 5 at the subsequent stage. The statistic processing unit 5 generates variance or standard deviation and a statistic similar thereto from the complementary data generated by the complementing unit 4 to generate and provide timing jitter information. By using such a method, the timing jitter of the digital signal can be accurately measured.

As described above, according to this embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Embodiment 3) FIG. 3 is a block diagram showing a timing jitter measuring system and a reproducing system using the same according to a third embodiment. In FIG. 3, reference numeral 1 denotes an input analog signal. A / D conversion means for converting to a digital value, 2 a sample value holding means for holding a series of output values of the A / D conversion means, and 7 an addition means for adding the output of the sample value holding means and the output of the addition means. Make up.

The operation of the timing jitter measuring method for determining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, an analog reproduction signal 100 is input to the A / D conversion means 1. The A / D converter 1 continuously samples the input analog signal 100 at a desired cycle and converts it into a digital signal 101. The sampling clock is a synchronous clock 10
2 is used. The digital signal 101 is input to the sample value holding means 2. The sample value holding means 2 receives the digital signal 101 output from the A / D conversion means 1 as an input,
Values close to the zero level 110, that is, the signals a and b shown in FIG. 10 are held and output. This output is accumulated and added by the adding means 7, and the result is provided as timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Embodiment 4) FIG. 4 is a block diagram of a timing jitter measuring method for measuring timing jitter from a signal sequence converted into a digital value and a reproducing method using the same according to a fourth embodiment. In FIG. 4, reference numeral 1 denotes A / D conversion means for converting an input analog signal into a digital value, reference numeral 2 denotes a sample value holding means for holding a series of output values of the A / D conversion means, and reference numeral 9 denotes an input signal. Zero cross detecting means for detecting zero crossing, zero point detecting means for detecting a zero level from the output of the sample value holding means 2, and accumulating means for accumulating and adding outputs of the zero point detecting means. .

The operation of the timing jitter measuring method for determining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, the analog reproduction signal 100 is input to the A / D conversion means 1. The synchronous clock 102 is used as a clock for sampling. A /
The D conversion means 1 continuously samples the input analog signal 100 at a desired cycle, and
Convert to Digital signal 1
01 is input and the reference zero level (reference level)
Each signal of the digital signal 101 is compared with 110, and a zero-cross signal 111 is generated from the input digital signal 101 at a timing crossing the reference level. In the zero point detecting means 8, the sample value holding means 2
From the output of the zero-cross detection means 9 and the zero-cross signal 111 of the signal sequence held by the sample value holding means,
The digital value having the value closest to the zero level in the digital value immediately before or immediately after the change point is detected as the zero point. The digital value detected by the zero point detecting means 8 is input to the accumulating means 6. The accumulative adding means 6 accumulatively adds the zero point data generated by the zero point detecting means 8 to generate and provide timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Embodiment 5) FIG. 5 is a block diagram of a timing jitter measuring method for measuring timing jitter from a signal sequence converted into a digital value and a reproducing method using the same according to a fifth embodiment. In FIG. 5, reference numeral 1 denotes A / D conversion means for converting an input analog signal into a digital value, reference numeral 2 denotes a sample value holding means for holding a series of output values of the A / D conversion means, and reference numeral 9 denotes an input signal. Zero cross detecting means for detecting zero crossing, zero point detecting means for detecting zero level from the output of the sample value holding means, and statistical processing of the output of the complementing means for generating variance or standard deviation and similar statistics. This constitutes statistical processing means.

The operation of the timing jitter measuring method for obtaining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, the operation is the same as that of the fourth embodiment until the analog reproduction signal 100 is input and the digital value detected by the zero point detection means 8 is generated. The statistical processing means 5 generates a variance or a standard deviation and a similar statistic from the digital value detected by the zero point detecting means 8 to generate and provide timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Embodiment 6) FIG. 6 is a block diagram of a timing jitter measuring system for measuring timing jitter from a signal sequence converted into a digital value and a reproducing system using the same according to the sixth embodiment. 6, reference numeral 1 denotes A / D conversion means for converting an input analog signal into a digital value, reference numeral 2 denotes a sample value holding means for holding a series of output values of the A / D conversion means, and reference numeral 3 denotes an input signal. Polarity discriminating means for discriminating positive and negative polarities, 4 is a complementing means for complementing and generating desired data from a signal sequence output from the sample value holding means, 6 is a cumulative adding means for accumulating and adding outputs of the complementing means, 8 Is a zero point detecting means for detecting a zero point;
Constitutes sampling timing control means for controlling the cycle of the sampling clock.

The operation of the timing jitter measuring method for determining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, an analog reproduction signal 100 is input to the A / D conversion means 1. The A / D converter 1 continuously samples the input analog signal 100 at a desired cycle and converts it into a digital signal 101. The zero point detecting means 8 detects, from the A / D output signal 101, one or both of the digital values immediately before or immediately after crossing the zero level among the digital values immediately before or immediately after crossing the zero level. The sample timing control means 12 generates a synchronous clock 102 for controlling the sampling timing from the signal detected by the zero point detection means 8 and uses it as a sampling clock for the A / D conversion means 1. The method of controlling the synchronous clock including the zero point detecting means 8 and the sample timing control means 12 is also called PLL. The digital signal 101 is inputted to the polarity discriminating means 3 and is compared with a reference level (reference level). The polarity of the polarity discriminating signal 112 is changed by the digital signal 101 inputted at a timing crossing the reference level. The sample value holding means 2 is A
The digital signal 101 and the polarity discrimination signal 112 output from the / D conversion means 1 are input, and the values of one or a plurality of sample points before and after the change point of the polarity discrimination signal 112 are held. The complementing means 4 generates the complementary data P108 from the sequence of the sample signal 113 output from the sample value holding means 2 at a point corresponding to the timing crossing the zero level shown in FIG. 11, as described in the first embodiment. I do. This complementary data P108 is used as an input to the subsequent cumulative addition means 6. The accumulating means 6 accumulatively adds the complementary data generated by the complementing means 4 to generate and provide timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured.

(Embodiment 7) FIG. 7 is a block diagram of a timing jitter measuring method for measuring timing jitter from a signal sequence converted into a digital value and a reproducing method using the same according to a seventh embodiment. In FIG. 7, reference numeral 1 denotes A / D conversion means for converting an input analog signal into a digital value, reference numeral 2 denotes a sample value holding means for holding a series of output values of the A / D conversion means, and reference numeral 3 denotes an input signal. Polarity discriminating means for discriminating positive and negative polarities, 10 is an edge selecting means for selectively outputting the rising or falling edge of the output signal of the sample value holding means, and 4 is complementing desired data from the signal sequence of the output of the edge selecting means. The complementary means 6 generated by the above constitutes a cumulative addition means for accumulating and adding outputs of the complementary means. FIG. 12 is a diagram for explaining signals of respective sections when the sample value holding means of the embodiment of the present invention selects a sample having both positive and negative polarities.

The operation of the timing jitter measuring method for obtaining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, the analog reproduction signal 100 is input to the A / D conversion means 1. The A / D converter 1 continuously samples the input analog signal 100 at a desired cycle and converts it into a digital signal 101. The sampling clock is a synchronous clock 10
2 is used. The digital signal 101 is inputted to the polarity discriminating means 3 and is compared with a reference level (reference level). The polarity of the polarity discriminating signal 112 is changed by the digital signal 101 inputted at a timing crossing the reference level. A / D conversion means 1
Digital signal 101 and polarity discrimination signal 11
2 is input, and the values of one or a plurality of sample points before and after the change point of the polarity determination signal 112 are held as shown by the waveform 115 in FIG. The edge selector 10 determines the polarity of the signal from the output of the polarity determiner 3 and selectively outputs only the rising or falling output of the input digital signal sequence (A / D output signal 101). It is possible to output to the complementing means 4.
The complementing means 4 generates complementary data P108 from the sequence of the selected sample signal 113 output from the edge selecting means 10 at a point corresponding to the timing crossing the zero level as shown in FIG. The method of generating the complementary data P108 is as described in the first embodiment. This complementary data P108 is used as an input to the subsequent cumulative addition means 6. The accumulative addition means 6 accumulatively adds the complementary data generated by the complementing means 4 to generate and provide timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Eighth Embodiment) FIG. 8 is a block diagram of a timing jitter measuring system for measuring timing jitter from a signal sequence converted into a digital value and a reproducing system using the same according to the eighth embodiment. In FIG. 8, reference numeral 1 denotes A / D conversion means for converting an input analog signal into a digital value, reference numeral 2 denotes a sample value holding means for holding a series of output values of the A / D conversion means, and reference numeral 3 denotes an input signal. Polarity discriminating means for discriminating positive and negative polarities, 10 is an edge selecting means for selectively outputting the rising or falling edge of the output signal of the sample value holding means, and 4 is complementing desired data from the signal sequence of the output of the edge selecting means. Complementing means 5 generate statistical data on the output of the complementing means, and constitute statistical processing means for generating variance or standard deviation and similar statistics.

The operation of the timing jitter measuring method for determining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, the analog reproduction signal 100 is input, and the complementary data
8 is the same as that of the seventh embodiment. This complementary data P108 is used as an input to the statistical processing means 5 at the subsequent stage. The statistical processing unit 5 generates variance or standard deviation and a similar statistic from the complementary data generated by the complementary unit 4 to generate and provide timing jitter information.

As described above, according to the present embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

(Embodiment 9) FIG. 9 is a block diagram of a timing jitter measuring system and a reproducing system using the same according to the ninth embodiment. In FIG. 9, reference numeral 1 denotes an input analog signal. A / D conversion means for converting into a digital value, 2 is a sample value holding means for holding a series of output values of the A / D conversion means, 3 is polarity discrimination means for discriminating between positive and negative polarities of an input signal, and 11 is a sample value. Timing synchronization means for synchronizing the output of the holding means with the polarity determination signal 112,
10 is an edge selecting means for selecting an edge of the output signal, 4 is a complementing means for complementing and generating desired data from the signal sequence of the timing synchronizing means 11, 5 is a statistical processing of the output of the complementing means, and variance or standard It constitutes a statistical processing means for generating a deviation and a similar statistic. FIG. 13 is a diagram for explaining signals of respective parts when the positive polarity is selected by the polarity discriminating means of the embodiment of the present invention. FIG. 14 is a diagram for explaining respective signals when the negative polarity is selected by the polarity discriminating means of the embodiment of the present invention. It is a figure explaining a signal. The waveform 114 is the polarity discriminating means 3 corresponding to the edge selected by the edge selecting means 10.
Is a waveform obtained by extracting the sample value A immediately before the rising edge and the sample value B immediately after the rising edge from the output waveform 112 of FIG. The waveform 116 is the output waveform 11 of the polarity discriminating means 3 corresponding to the edge selected by the edge selecting means 10.
2, the sample value A immediately before the selected edge
And a waveform obtained by extracting a sample value B located immediately after.

The operation of the timing jitter measuring method for determining the timing jitter configured as described above will be described below.

First, at the time of signal reproduction, the analog reproduction signal 100 is input to the A / D conversion means 1. The A / D converter 1 continuously samples the input analog signal 100 at a desired cycle and converts it into a digital signal 101. The sampling clock is a synchronous clock 10
2 is used. The digital signal 101 is inputted to the polarity discriminating means 3 and is compared with a reference level (reference level). The polarity of the polarity discriminating signal 112 is changed by the digital signal 101 inputted at a timing crossing the reference level. A signal for selecting an edge to be measured is generated by the edge selecting means 10, and a sample value corresponding to the selected edge is selected by the polarity determination signal 112. As a result,
Output signal 11 of polarity discrimination signal according to the edge to be measured
2 is inverted, and the states of waveforms 114 and 116 change. The sample value holding means 2 receives the digital signal 101 and the polarity discrimination signal 112, which are the outputs of the A / D conversion means 1, and holds the values of one or more sample points before and after the change point of the polarity discrimination signal 112. I do. The output of the sample value holding means 2 is synchronized by the timing synchronizing means 11 so as to be synchronized with the polarity discrimination signal 112. When the rising edge is selected, the waveform A follows the rising edge of the polarity discrimination signal 112 as shown in FIG. The waveform B is output, and the waveform C is output at the falling edge in the order of the waveform C followed by the waveform D. When the falling edge is selected, as shown in FIG. 14, the waveform A follows the waveform A at the falling edge of the polarity determination signal 112, and the waveform C follows the waveform C at the falling edge. Is done. The complementing means 4 includes, as shown in FIG.
At the point corresponding to the timing of crossing the zero level from the sequence of the sample signal 113 which is the output of
Generate The method of generating the complementary data P108 is as described above. This complementary data P108 is used as an input to the statistical processing means 5 at the subsequent stage. The statistical processing unit 5 generates variance or standard deviation and a similar statistic from the complementary data generated by the complementary unit 4 to generate and provide timing jitter information.

As described above, according to this embodiment, the timing jitter of a digital signal can be accurately measured. At this time, the sampling clock need not be the synchronous clock 102.

[0054]

As described above, according to the present invention, the timing jitter of a digital signal obtained by A / D conversion of an analog signal of a storage device such as an optical disk or a hard disk or a communication device is accurately and low, and is as low as a channel clock. The timing jitter can be measured with the sampling clock of the frequency, and the advantageous effect that the reliability is dramatically improved by a relatively simple method with respect to the high-density recording and the high transfer rate of the storage device and the communication device is obtained. can get.

[Brief description of the drawings]

FIG. 1 is a block diagram of a timing jitter measuring method and a reproducing method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a block embodiment of a timing jitter measurement system and a reproduction system according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a timing jitter measuring method and a reproducing method according to a third embodiment of the present invention;

FIG. 4 is a block diagram of a timing jitter measuring method and a reproducing method according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a timing jitter measuring method and a reproducing method according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a timing jitter measuring method and a reproducing method according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram of a timing jitter measuring method and a reproducing method according to a seventh embodiment of the present invention;

FIG. 8 is a block diagram of a timing jitter measuring method and a reproducing method according to an eighth embodiment of the present invention.

FIG. 9 is a block diagram of a timing jitter measuring method and a reproducing method according to a ninth embodiment of the present invention.

FIG. 10 is a waveform chart showing an example of a timing jitter measuring method and a reproducing method according to an embodiment of the present invention.

FIG. 11 is a diagram illustrating a method for generating complementary data P according to the embodiment of the present invention.

FIG. 12 is a view for explaining signals of respective parts when positive and negative bipolar samples are selected by the sample value holding means of the embodiment of the present invention;

FIG. 13 is a view for explaining signals of respective parts when positive polarity is selected by the polarity discriminating means of the embodiment of the present invention.

FIG. 14 is a diagram for explaining signals of respective parts when negative polarity is selected by the polarity discriminating means according to the embodiment of the present invention;

FIG. 15 is a block diagram of a conventional timing jitter measuring method and a reproducing method.

FIG. 16 is a waveform diagram showing an example of a conventional timing jitter measuring method and a reproducing method.

FIG. 17 is a diagram showing an ideal statistical distribution;

FIG. 18 is a diagram showing a statistical distribution according to a conventional timing jitter measuring method and a reproducing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion means 2 Sample value holding means 3 Polarity discrimination means 4 Complementary means 5 Statistical processing means 6 Cumulative addition means 7 Addition means 8 Zero point detection means 9 Zero cross detection means 10 Edge selection means 11 Timing synchronization means 12 Sampling timing control Means 13 Synchronous clock generating means 14 Binarizing means 100 Analog signal 101 A / D output signal 102 Synchronous clock 103 Binary signal 104 Timing error 105 Variance σ 106 Signal a 107 Signal b 108 Complementary data P 109 Period Tw 110 Zero level Signal 111 Zero-cross signal 112 Polarity discrimination signal 113-116 Selected sample signal

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Ken Nakajima 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. F term (reference) 5D044 BC02 CC04 FG11 GM15 GM40 5K029 AA11 CC07 KK23

Claims (11)

[Claims] 1. An information reproducing apparatus or a communication apparatus, comprising:
An A / D converter for digitizing an analog signal with a constant or variable sampling clock; and a polarity discrimination for discriminating a polarity when the signal sequence crosses a zero level from a signal sequence sampled by the A / D converter. Means before and after the output timing of the polarity discriminating means.
A sample value holding unit for holding a value of one or a plurality of sampling points; and a complementing unit for complementing a zero cross timing, which is a timing at which a signal sequence crosses a zero level, based on the value of the sample value holding unit. A timing jitter measuring method and a reproducing method using the same, wherein the timing jitter amount is obtained by cumulatively adding the data given in (1). 2. In an information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock; and a polarity discrimination for discriminating a polarity when the signal sequence crosses a zero level from a signal sequence sampled by the A / D converter. Means before and after the output timing of the polarity discriminating means.
A sample value holding unit for holding a value of one or a plurality of sampling points; and a complementing unit for complementing a zero cross timing, which is a timing at which a signal sequence crosses a zero level, based on the value of the sample value holding unit. 2. A timing jitter measuring method and a reproducing method using the same, wherein the data given in (2) are squared and cumulatively added, and a standard deviation is obtained from information in a time domain. 3. An information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock; and a set of signals before and after the timing when the signal sequence crosses zero level from a signal sequence sampled by the A / D converter. A sampling value holding unit for holding a sampling value; and an adding unit for adding a set of sampling values held in the sample value holding unit. The output of the adding unit is cumulatively added to reduce a timing jitter amount. A timing jitter measuring method and a reproducing method using the same. 4. An information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock, sample value holding means for holding a plurality of sampling values from a signal sequence sampled by the A / D converter, Zero point detecting means for detecting a sample point closest to zero level in the signal sequence held in the holding means,
Zero cross detection means for detecting a zero cross timing when crossing the zero level, and accumulatively adding the value of the zero level detected by the zero point detection means immediately before or immediately after the zero cross timing detected by the zero cross detection means. A timing jitter measuring method for obtaining a timing jitter amount by using the method, and a reproducing method using the same. 5. An information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock, sample value holding means for holding a plurality of sampling values from a signal sequence sampled by the A / D converter, Zero point detecting means for detecting a sample point closest to zero level in the signal sequence held in the holding means,
A zero-crossing detecting means for detecting a zero-crossing timing when the zero-level crossing is detected, and immediately before or immediately after the zero-crossing timing detected by the zero-crossing detecting means, the value of the zero-level detected by the zero-point detecting means is set to 2
A timing jitter measuring method and a reproducing method using the same, wherein the standard jitter is obtained by multiplying by a power and accumulating and adding. 6. An information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock, sample value holding means for holding a plurality of sampling values from a signal sequence sampled by the A / D converter, Supplementing means for complementing a zero-cross timing, which is a timing at which the signal sequence crosses the zero level from the value of the holding means, and zero for detecting a sample point closest to the zero level in the signal sequence held in the sample value holding means. And a sampling timing control means for controlling a sampling timing of the A / D converter so that a sample value obtained by the zero point detection means is close to a zero level. The timing jitter by determining the amount of timing jitter by accumulating the outputs of Measurement method and reproducing method using the same. 7. An information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock, sample value holding means for holding a plurality of sampling values from a signal sequence sampled by the A / D converter, A timing jitter measurement method characterized by selectively holding a sampling value of a rising edge or a falling edge in an output signal sequence of a holding means and obtaining a timing jitter amount from a sampling value of an arbitrary edge, and using the same. Playback method. 8. In an information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock, sample value holding means for holding a plurality of sampling values from a signal sequence sampled by the A / D converter, A timing jitter measurement method characterized by selectively holding a sampling value of a rising edge or a falling edge in an output signal sequence of a holding unit and obtaining a standard deviation from a sampling value of an arbitrary edge, and reproduction using the timing jitter measurement method. method. 9. An information reproducing apparatus or a communication apparatus,
An A / D converter for digitizing an analog signal with a constant or variable sampling clock; a sample value holding unit for holding a plurality of sampled values from a signal sequence sampled by the A / D converter; A timing jitter measurement method and a reproduction method using the same, wherein both a rising edge and a falling edge in a signal sequence are held and a standard deviation is obtained from sampling values of both edges. 10. An information reproducing apparatus or a communication apparatus, comprising: an A / D converter for digitizing an analog signal with a constant or variable sampling clock; and a signal sequence sampled by the A / D converter. A polarity discriminating means for discriminating a polarity when the signal crosses a zero level; a sample value holding means for holding a value of one or more sampling points before and after an output timing of the polarity discriminating means; And complementing the zero-cross timing, which is the timing at which the signal series crosses the zero level from the value of, holds the sampling signal immediately before the polarity inversion at the timing synchronized with the rising edge of the output of the polarity discrimination means, A timer synchronized with the falling edge of the polarity clock signal output from the polarity determination means. A timing jitter measurement method and a timing jitter measurement method, wherein a phase relationship is maintained such that a sampling signal immediately after polarity reversal is maintained by inputting, and a timing jitter amount is determined by inputting the signal sequence to a circuit for determining a standard deviation. The playback method used. 11. An information reproducing apparatus or a communication apparatus, wherein: an A / D converter for digitizing an analog signal with a constant or variable sampling clock; and a signal sequence sampled by the A / D converter. A polarity discriminating means for discriminating a polarity when the signal crosses a zero level; a sample value holding means for holding a value of one or more sampling points before and after an output timing of the polarity discriminating means; And complementing the zero-cross timing, which is the timing at which the signal series crosses the zero level from the value of, holds the sampling signal immediately before the polarity inversion at the timing synchronized with the rising edge of the output of the polarity discrimination means, A timer synchronized with the falling edge of the polarity clock signal output from the polarity determination means. The phase relationship is maintained such that the sampling signal immediately after the polarity inversion is maintained in the timing, and the rising edge of the polarity clock signal always means the first data of a set of signal series.
It means the next data of the set of signal series, or always means the first data of one set of signal series at the fall of the polarity clock signal, and the next data of one set of signal series at the rise of the polarity clock signal. A timing jitter measuring method and a reproducing method using the same, wherein a timing jitter amount is obtained by inputting the timing jitter to a circuit for obtaining a standard deviation.