CN101452712B - Optical disk reproducing device and phase-locked loop circuit - Google Patents
Optical disk reproducing device and phase-locked loop circuit Download PDFInfo
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- CN101452712B CN101452712B CN2008101816098A CN200810181609A CN101452712B CN 101452712 B CN101452712 B CN 101452712B CN 2008101816098 A CN2008101816098 A CN 2008101816098A CN 200810181609 A CN200810181609 A CN 200810181609A CN 101452712 B CN101452712 B CN 101452712B
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Abstract
The invention provides an optical disk reproducing device for controlling false detection of synchronization signals due to inter-symbol interference, and stably improving accuracy of frequency acquisition of a PLL even when offset and so on occur. A signal width close to an original mark length is obtained to use for frequency acquisition of the PLL by, for example, using two different slice thresholds and taking a width between a rising of a result of slicing at one threshold and a falling of a result of slicing at the other threshold as a synchronization signal width. When asymmetric properties due to offset, asymmetry, etc. occur, an amount of corrections on the slice threshold is calculated, and it is reflected on a threshold previously set to always obtain a correct synchronization signal width.
Description
Technical field
The present invention relates to relate in particular to phase-locked loop circuit from the sync detection circuit of the optical disc reproducing apparatus of optical disc replay data.
Background technology
CDs such as CD (Compact Disc below is called CD) and DVD are general as being used to store the storage medium of lot of data.In recent years, more jumbo BlueRay Disc (registered trademark, Blu-ray disc), the so jumbo optical disc apparatus of high density of HD DVD (registered trademark) also begin to popularize gradually.
When reproducing CD,, need in the capture range (capture range) of PLL (phaselocked loop), introduce clock frequency in order to generate and the reproducing signal clock synchronized.As this concrete method, just like inferior method: method 1, behind the binaryzation reproducing signal, measure reversal interval, detect its maximal value, the rotational speed of console panel is so that detected maximal value becomes specified length; Method 2, the reversal interval of mensuration reproducing signal detects its maximal value or minimum value, according to the cycle of detected synchronizing signal, makes the rotational speed of dish become set value.
But, when in reproducing waveform signal, producing intersymbol and interfering, might produce the such problem during the synchronizing signal that can't correctly detect.That is, detect the deration of signal wideer, thereby might produce as situation about detecting during the synchronizing signal during original unexpected than the deration of signal that should show originally through zero amplitude limit (zero slice).
As its solution; Open in the flat 8-138328 communique (following patent documentation 1) the spy and to have proposed following technology: in synchronization signal detection circuit; Even with zero level various signals level in also can carry out amplitude limit to signal waveform, and with reference to this moment the deration of signal detect synchronizing signal.
In addition, the spy open disclose in the 2006-252640 communique (following patent documentation 2) with zero level various signals level in, the technology of detection reference synchronizing signal width.And, also disclose according to the skew of reproducing signal waveform and the state of asymmetric (asymmetry) and come the suitably technology of setting benchmark synchronizing signal width.
Patent documentation 1: japanese kokai publication hei 8-138328 communique
Patent documentation 2: TOHKEMY 2006-252640 communique
Summary of the invention
But, as the invention of patent documentation 1, become shorter than original synchronizing signal width with the deration of signal in the zero level various signals level.When being introduced into PLL, might wrong pull-in frequency.
In addition, such like the invention of patent documentation 2 record, when producing skew on the reproducing signal waveform, benchmark synchronizing signal width changes according to the state that squints etc.Therefore, more different when producing asymmetry with original synchronous width.
The objective of the invention is to realize a kind of optical disc reproducing apparatus, can suppress intersymbol and interfere the synchronizing signal erroneous detection that causes, introduce precision even when generation is squinted or be asymmetric, also can stably improve the PLL frequency.
Above-mentioned and other purpose and new characteristic of the present invention, record and accompanying drawing through this instructions will be able to clearly.
The summary that representational technical scheme in the application's invention disclosed is described is following.
The optical disc reproducing apparatus of representative embodiments of the present invention comprises: AFE(analog front end) (below be called AFE:Analog Front End), carry out simulation process to the output of pick-up; AD converter (below be called ADC) uses by the reference frequency of voltage-controlled oscillator (below become VCO:Voltage Controlled Oscillator) output the analog signal conversion of above-mentioned AFE output is become digital signal; The frequency error detection circuit detects the frequency error that ADC exports; Low-pass filter circuit (below be called LPF) is removed the radio-frequency component of frequency error detection circuit output; DA converter (below be called DAC) converts the output of LPF to simulating signal; And VOC, coming the output reference frequency according to the output of DAC, this optical disc reproducing apparatus is characterised in that the frequency error detection circuit comprises: first amplitude limiter circuit, with above-mentioned first threshold amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is carried out amplitude limit with second threshold value to the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of above-mentioned first amplitude limiter circuit and second amplitude limiter circuit; Peak signal width detection circuit, the deration of signal that the deration of signal from the output of deration of signal testing circuit is kept with itself compares, the deration of signal of record and output broad; And error-detector circuit, the output and the predefined object synchronization deration of signal of peak signal width detection circuit compared, and export its difference.
Another optical disc reproducing apparatus of representative embodiments of the present invention comprises: the AFE that the output of pick-up is carried out simulation process; Use is become the analog signal conversion of AFE output by the reference frequency of VCO output the ADC of digital signal; Detect the frequency error detection circuit of the frequency error of ADC output; Detect the phase error detection circuit of the phase error of ADC output; Switch is selected the output of output frequency error-detector circuit and the output of phase error detection circuit; Remove the LPF of the radio-frequency component of the output of opening the light; The output of LPF is converted to the DAC of simulating signal; And export the VCO of said reference frequency according to the output of this DAC, and this optical disc reproducing apparatus is characterised in that the frequency error detection circuit comprises: first amplitude limiter circuit, with first threshold amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is carried out amplitude limit with second threshold value to the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of first amplitude limiter circuit and second amplitude limiter circuit; Peak signal width detection circuit, the deration of signal that the deration of signal from the output of deration of signal testing circuit is kept with itself compares, the deration of signal of record and output broad; And error-detector circuit, the output and the predefined object synchronization deration of signal of peak signal width detection circuit compared, and export its difference.
The characteristic of the deration of signal testing circuit of these optical disc reproducing apparatus can for: make up the output of first amplitude limiter circuit and the output of second amplitude limiter circuit and detect a deration of signal.
The deration of signal testing circuit of these optical disc reproducing apparatus detects first deration of signal that obtains from the combination of the marginal information of the marginal information of first amplitude limiter circuit output and the output of second amplitude limiter circuit; And detect marginal information from the output of first amplitude limiter circuit, or the combination of the marginal information of second amplitude limiter circuit output and the secondary signal width that obtains; When the difference of first deration of signal and secondary signal width is the tolerance of in the register initialization circuit, setting in advance when following; First deration of signal is outputed to peak signal width detection circuit; When the difference of first deration of signal and secondary signal width surpasses tolerance, the secondary signal width is outputed to peak signal width detection circuit.
The characteristic of the deration of signal testing circuit of these optical disc reproducing apparatus can for: the marginal information according to first amplitude limiter circuit output detects first deration of signal; Marginal information according to the output of second amplitude limiter circuit detects the secondary signal width; Detect the 3rd deration of signal of a plurality of marks according to the combination of the marginal information of the marginal information of first amplitude limiter circuit output and the output of second amplitude limiter circuit; When first deration of signal and secondary signal width sum, be the allowable value of in the register initialization circuit, setting in advance when following, export the 3rd deration of signal with the difference of the 3rd deration of signal.
Another optical disc reproducing apparatus of representative embodiments of the present invention comprises: the AFE that the output of pick-up is carried out simulation process; Utilization is become the analog signal conversion of AFE output by the reference frequency of VCO output the ADC of digital signal; Detect the frequency error detection circuit of the frequency error of ADC output; Remove the LPF of the radio-frequency component of frequency error detection circuit output; The output of LPF is converted to the DAC of simulating signal; And come the VCO of output reference frequency according to the output of DAC, the characteristic of this optical disc reproducing apparatus can for, the said frequencies error-detector circuit comprises: asymmetric quantitative determination circuit, calculate and output violent change threshold value correcting value according to the output of ADC; First amplitude limiter circuit is used by the correction of first behind the output calibration of asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is used by the correction of second behind the output calibration of asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of first amplitude limiter circuit and second amplitude limiter circuit; Peak signal width detection circuit, the deration of signal that the deration of signal from the output of deration of signal testing circuit is kept with itself compares, the deration of signal of record and output broad; And error-detector circuit, the output and the predefined object synchronization deration of signal of peak signal width detection circuit compared, and export its difference.
Another optical disc reproducing apparatus of representative embodiments of the present invention comprises: the AFE that the output of pick-up is carried out simulation process; Utilization is become the analog signal conversion of AFE output by the reference frequency of VCO output the ADC of digital signal; Detect the frequency error detection circuit of the frequency error of ADC output; Remove the LPF of the radio-frequency component of frequency error detection circuit output; The output of LPF is converted to the DAC of simulating signal; And export the VCO of said reference frequency according to the output of DAC, the characteristic of this optical disc reproducing apparatus can for, the frequency error detection circuit comprises: first amplitude limiter circuit, with first threshold amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is carried out amplitude limit with second threshold value to the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of first amplitude limiter circuit and second amplitude limiter circuit; Synchronization signal detection circuit compares the output of predefined synchronizing signal width and deration of signal testing circuit, and judges whether to be synchronizing signal; Synchronous signal cycle is measured circuit, from the output of synchronization signal detection circuit, measures synchronous signal cycle; Error-detector circuit, the output of predefined synchronous signal cycle and synchronous signal cycle being measured circuit compares, and output error.
The phase-locked loop circuit of representative embodiments of the present invention comprises: utilize the ADC that is converted to digital signal by the reference frequency of VCO output; And the frequency error detection circuit that detects the frequency error of above-mentioned ADC output, this phase-locked loop circuit is characterised in that the frequency error detection circuit comprises: first amplitude limiter circuit, with first threshold amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is carried out amplitude limit with second threshold value to the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of first amplitude limiter circuit and second amplitude limiter circuit; Peak signal width detection circuit, the deration of signal that the deration of signal from the output of deration of signal testing circuit is kept with itself compares, the deration of signal of record and output broad; And error-detector circuit, the output and the predefined object synchronization deration of signal of peak signal width detection circuit compared, and export its difference.
Another phase-locked loop circuit of representative embodiments of the present invention comprises: utilize the ADC that input signal is converted to digital signal by the reference frequency of VCO output; And the frequency error detection circuit that detects the frequency error of ADC output, this phase-locked loop circuit is characterised in that the frequency error detection circuit comprises: asymmetric quantitative determination circuit, calculate and output violent change threshold value correcting value according to the output of ADC; First amplitude limiter circuit is used by the correction of first behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is used by the correction of second behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of first amplitude limiter circuit and second amplitude limiter circuit; Peak signal width detection circuit, the deration of signal that the deration of signal from the output of deration of signal testing circuit is kept with itself compares, the deration of signal of record and output broad; And error-detector circuit, the output and the predefined object synchronization deration of signal of peak signal width detection circuit compared, and export its difference.
Another phase-locked loop circuit of representative embodiments of the present invention comprises: utilize by the reference frequency of voltage-controlled oscillator output and come input signal is carried out the ADC of analog-digital conversion; And the frequency error detection circuit that detects the frequency error of ADC output, this phase-locked loop circuit is characterised in that the frequency error detection circuit comprises: asymmetric quantitative determination circuit, calculate and output violent change threshold value correcting value according to the output of ADC; First amplitude limiter circuit is used by the correction of first behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of ADC; Second amplitude limiter circuit is used by the correction of second behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of ADC; Deration of signal testing circuit, detection signal width from the output of the output of first amplitude limiter circuit and second amplitude limiter circuit; Synchronization signal detection circuit compares the output of predefined synchronizing signal width and deration of signal testing circuit, and judges whether to be synchronizing signal; Synchronous signal cycle is measured circuit, measures synchronous signal cycle according to the output of synchronization signal detection circuit; And error-detector circuit, the output of predefined synchronous signal cycle and synchronous signal cycle being measured circuit compares, and output error.
In these phase-locked loop circuits, its characteristic can be the phase difference detecting circuit that also comprises the phase error that detects ADC output; And the switch of the output of the output of selection output frequency error-detector circuit and phase error detection circuit.
In these phase-locked loop circuits, its characteristic can for: deration of signal testing circuit makes up the output of first amplitude limiter circuit and the output of second amplitude limiter circuit, exports a deration of signal.
The characteristic of the deration of signal testing circuit of these phase-locked loop circuits can for: detect first deration of signal that the combination according to the marginal information of the marginal information of first amplitude limiter circuit output and the output of above-mentioned second amplitude limiter circuit obtains; And detect marginal information according to the output of first amplitude limiter circuit, or the secondary signal width that obtains of the combination of the marginal information of second amplitude limiter circuit output; When the difference of first deration of signal and secondary signal width is the allowable value of in the register initialization circuit, setting in advance when following; Export first deration of signal to peak signal width detection circuit; When the difference of first deration of signal and secondary signal width surpasses allowable value, to peak signal width detection circuit output secondary signal width.
The characteristic of the deration of signal testing circuit of these phase-locked loop circuits can for: the marginal information according to first amplitude limiter circuit output detects first deration of signal; Combination according to the marginal information of second amplitude limiter circuit output detects the secondary signal width; Detect the 3rd deration of signal of a plurality of marks according to the combination of the marginal information of the margin signal of first amplitude limiter circuit output and the output of second amplitude limiter circuit; When first deration of signal and secondary signal width sum, be the allowable value of in the register initialization circuit, setting in advance when following, export the 3rd deration of signal with the difference of the 3rd deration of signal.
To use these phase-locked loop circuits also to fall within the scope of the present invention as the optical disc reproducing apparatus of characteristic.
The resulting effect of representative solution is following among simple declaration the application invention disclosed.
Optical disc reproducing apparatus according to representative embodiments of the present invention; Even when the reproduction of high-density medium etc. under the situation; Mistake is carried out under the situation of synchronization signal detection easily because intersymbol interferes the amplitude of big, short marking signal to reduce; Also can correctly detect synchronizing signal, thereby the frequency that can improve PLL is introduced precision.In addition, even when skew or asymmetric such asymmetry take place, also can stably detect synchronizing signal on the reproducing signal waveform.
Description of drawings
Fig. 1 is the block diagram of the optical disc reproducing apparatus structure of expression first embodiment of the invention.
Fig. 2 is the block diagram of the first frequency error-detector circuit structure of expression first embodiment of the invention.
Fig. 3 is the figure that schematically shows the synchronization signal detection of optical disc reproducing apparatus of the present invention.
Fig. 4 is (b) figure of (c) of the figure (a) that uses in the sychronizing signal detecting method of expression signal width detection circuit.
Fig. 5 is the figure of first frequency error-detector circuit structure in the optical disc reproducing apparatus of expression four embodiment of the invention.
Fig. 6 is the waveform concept map of work of asymmetric quantitative determination circuit that is used for explaining the frequency error detection circuit working of four embodiment of the invention.
Fig. 7 is the block diagram of the asymmetric quantitative determination circuit structure of expression four embodiment of the invention.
Fig. 8 is the block diagram of frequency error detection circuit structure in the optical disc reproducing apparatus of expression fifth embodiment of the invention.
Fig. 9 is the figure of first frequency error-detector circuit structure in the optical disc reproducing apparatus of expression sixth embodiment of the invention.
Figure 10 is the figure of first frequency error-detector circuit structure in the optical disc reproducing apparatus of expression seventh embodiment of the invention.
Figure 11 is the figure of deration of signal testing circuit structure of the optical disc reproducing apparatus of expression second embodiment of the invention and the 3rd embodiment.
Embodiment
Below, use description of drawings embodiment of the present invention.
(first embodiment)
Fig. 1 is the block diagram of the optical disc reproducing apparatus structure of expression first embodiment of the invention.
The optical disc reproducing apparatus of Fig. 1 comprises: CD 101, light picker 102, spindle motor 103, AFE104, ADC105, phase error detection circuit 106, first frequency error-detector circuit 107, second frequency error-detector circuit 108, first lock detecting circuit 109, second lock detecting circuit 110, the 3rd lock detecting circuit 111, change-over switch 112, LPF113, DAC114, VCO115, binarization circuit 116, demoder 117.
In addition, Fig. 2 is the block diagram of structure of the first frequency error-detector circuit 107 of expression first embodiment of the invention.This frequency error detection circuit comprises: the first limiting threshold initialization circuit 201, the second limiting threshold initialization circuit 202, first amplitude limiter circuit 203, second amplitude limiter circuit 204, deration of signal testing circuit 205, peak signal width holding circuit 206, object synchronization deration of signal initialization circuit 207 and error-detector circuit 208.
Fig. 3 is the figure of synchronization signal detection that schematically shows the optical disc reproducing apparatus of these Fig. 1 and Fig. 2.In addition, Fig. 4 is the figure of the figure that uses in the sychronizing signal detecting method of expression signal width detection circuit 205.
AFE104 carries out from the amplification of the simulating signal of light picker 102 output with among ADC105, using the parts to the such processing of wave shaping.The AFE104 simulating signal that above-mentioned correction has been carried out in output to ADC105.
ADC105 exports the simulating signal of AFE104 to convert digital signal to, and exports the parts of phase error detection circuit 106, first frequency error-detector circuit 107, second frequency error-detector circuit 108 and binarization circuit 116 to.ADC105 works according to the reference frequency of VCO115.
The data-bias detected phase error of phase error detection circuit 106 from the reproduction wave edges of ADC105 output, and output to first lock detecting circuit 109 and change-over switch 112 as error detection signal.
First frequency error-detector circuit 107 is from by reproducing the synchronizing signal width detection frequency error that wave test goes out, and outputs to second lock detecting circuit 110 and change-over switch 112 as error signal.
Second frequency error-detector circuit 108 detects frequency error the cycle between the synchronizing signal that is gone out by the reproduction wave test, and outputs to the 3rd lock detecting circuit 111 and change-over switch 112 as error signal.
When first lock detecting circuit 109 is converged in the predefined error range in the error signal that transmits from phase error detection circuit 106, locking signal is outputed to change-over switch 112.
Second lock detecting circuit 110 also when the error signal that transmits from first frequency error-detector circuit 107 is converged in the predefined error range, outputs to change-over switch 112 with locking signal.
The 3rd lock detecting circuit 111 also when the error signal that transmits from second frequency error-detector circuit 108 is converged in the predefined error range, outputs to change-over switch 112 with locking signal.
Change-over switch 112 be used for from the locking signal of first lock detecting circuit 109, second lock detecting circuit 110,111 inputs of the 3rd lock detecting circuit as control signal, any output in phase error detection circuit 106, first frequency error-detector circuit 107 or second error-detector circuit 108 is outputed to the on-off circuit of LPF113.As the example of the concrete control method of above-mentioned control signal, can consider following scheme.
The accuracy of detection of above-mentioned phase error detection circuit 106, first frequency error-detector circuit 107, second frequency error-detector circuit 108 these three circuit is successively; Phase error detection circuit 106 is best; Second frequency error-detector circuit 108 is taken second place, and is first frequency error-detector circuit 107 at last.But,, can consider that also frequency is 2 times as long as phase place is consistent.Therefore, different with accuracy of detection, in the switching of change-over switch 112, make second lock detecting circuit, 110 priority the highest, only when 110 lockings of second lock detecting circuit, carry out the judgement of the 3rd lock detecting circuit 111.And, effective at first for the output that makes the highest phase error detection output circuit 106 of precision after having confirmed these two lockings, carry out the judgement of first lock detecting circuit 109.
LPF113 is the low-pass filter that is used for converting to from the output of the change-over switch 112 of the usefulness that prevents to vibrate the less direct current signal of alternating component.Having removed the output of the LPF113 of this radio-frequency component exports DAC114.
DAC114 is used for converting the digital signal output of LPF113 to Analog signals'digital-analog conversion circuit.After converting simulating signal to by DAC114, VCO115 is exported.
VCO115 is the variable oscillator of working with reference to the output of DAC114.The output of this VCO115 is outputed to ADC105 as reference frequency.This reference frequency is used in ADC105 as sampling clock.
The demodulation process that demoder 117 carries out the output of binarization circuit 116, error correction calculation process, descrambling (Descramble) are handled, the data output of outside are controlled.
The first limiting threshold initialization circuit 201 is register circuits of one that are used for setting two different threshold values.In addition, the second limiting threshold initialization circuit 202 is the register circuits that are used to set another threshold value.These two threshold values are equivalent to Th_p and the Th_m of Fig. 3.
First amplitude limiter circuit 203 is output and the output of the first limiting threshold initialization circuit 201 of contrast ADC105, when two outputs are roughly the same to the circuit of the deration of signal testing circuit 205 outputs first amplitude limit detection signal.Equally, second amplitude limiter circuit 204 is output and the output of the second limiting threshold initialization circuit 202 of contrast ADC105, when two outputs are roughly the same to the circuit of the deration of signal testing circuit 205 outputs second amplitude limit detection signal.
In this embodiment, the output that needs to judge ADC105 tends to 0 level still away from 0 level.Therefore, the output of first amplitude limiter circuit 203 and second amplitude limiter circuit 204 is respectively 1 and gets final product.The output of this first amplitude limiter circuit 203 is Sli_p of Fig. 3, and the output of second amplitude limiter circuit 204 is Sli_m of this figure.And, the situation of the change point of 0 to 1 among Sli_p and the Sli_m or 1 to 0 is defined as " marginal information ".
Deration of signal testing circuit 205 is circuit of measuring the time range between amplitude limit according to the variation of the first amplitude limit detection signal and the second amplitude limit detection signal.At this, the time that records is outputed to peak signal width holding circuit 206.
Peak signal width holding circuit 206 is tracer signal width detection circuit 205 and the circuit that its recorded content is outputed to error-detector circuit 208.The present invention has characteristic about the work of these deration of signal testing circuits 205, peak signal width holding circuit 206, bright specifically with after state.
The deration of signal that object synchronization deration of signal initialization circuit 207 will become the synchronous judgment benchmark outputs to error-detector circuit 208.
Error-detector circuit 208 is circuit of output of output and the object synchronization deration of signal initialization circuit 207 of contrast peak signal width holding circuit 206.Calculate the difference of these two signals, this difference is outputed to second lock detecting circuit 110 and change-over switch 112 as error signal.
Below, the summary of the reproduction work in the optical disc reproducing apparatus of this embodiment is described.
As shown in Figure 1,102 pairs of CD 101 irradiating lasers of light picker receive the reflected light from dish, and the signal of reading thus carries out simulation process in AFE104, be input to ADC105.Carry out digitized signal at ADC105 and be transfused to phase error detection circuit 106.Phase error detection circuit 106 is according to the data-bias detected phase error of reproducing wave edges, and as error signal to first lock detecting circuit 109 and change-over switch 112 outputs.In addition; The output of ADC105 simultaneously is transfused to first frequency error-detector circuit 107; First frequency error-detector circuit 107 detects frequency error according to the synchronizing signal width that goes out from the reproduction wave test, and exports to second lock detecting circuit 110 and change-over switch 112 as error signal.And; The output of ADC105 simultaneously is transfused to second frequency error-detector circuit 108; Second frequency error-detector circuit 108 is according to from reproducing the cycle calculated rate error between the synchronizing signal that wave test goes out, and is input to change-over switch 112 as error signal.
According to the setting of change-over switch 112, any signal is outputed to LPF113 as error signal in phase error detection circuit 106, first frequency error-detector circuit 107 or the second frequency error-detector circuit 108.This error signal is removed radio-frequency component in LPF113, simulated in DAC114, and is input to VCO115.VCO115 is according to the error signal that obtains, and the cycle and the phase place of the sampling clock of adjustment ADC105 are with compensation of phase difference and difference on the frequency.
As stated; With output data synchronously and the output of the ADC105 that is sampled; In binarization circuit 116, use PRML etc. to be decoded into two-value data from many-valued reproduction Wave data; In demoder 117, carry out demodulation process, the error correction calculation process of binaryzation data, scramble process, to the data of outside output control.
The work of first frequency error-detector circuit 107 then, is described.The example of setting has been accomplished in explanation in the first limiting threshold initialization circuit 201 and the second limiting threshold initialization circuit 202.
Be imported into first amplitude limiter circuit, 203, the first amplitude limiter circuits 203 from the output Th_p of the reproducing signal waveform of ADC105 output and the first limiting threshold initialization circuit 201 and come output violent change result (Sli_p of Fig. 3) according to the difference of reproducing signal waveform and Th_p.Equally; From the reproducing signal waveform of ADC105 output be imported into second amplitude limiter circuit, 204, the second amplitude limiter circuits 204 as the Th_m of the output of the second limiting threshold initialization circuit 202 and come output violent change result (Sli_m of Fig. 3) according to the difference of reproducing signal waveform and Th_m.Synchronizing signal is reproduced running period (run length) maximum in the data owing to generally having, thereby amplitude is bigger, even the level of right and wrong 0 level also can amplitude limit.Here, be meant the read-around ratio of " 0 " or " 1 " in the ranking of the data of reading running period.The amplitude limit result that these obtain in amplitude limiter circuit is imported in the deration of signal testing circuit 205.
In the deration of signal testing circuit 205, come the detection signal width according to the deration of signal test pattern of Fig. 4 (a).From the counting of the edge commencing signal width shown in the start (beginning) of Fig. 4 (a), the data till the edge shown in the end (end) are counted and as the deration of signal.For example under situation like the case1 of Fig. 4 (a), till being timed to Sli_m and descending regularly from the rising of Sli_p as the deration of signal (L1 of Fig. 3) and to be detected.During the detection signal width (L_p of Fig. 3, L_m), shorter only using one amplitude limit result only having utilized Th_p or Th_m, but the deration of signal of the L1 through using Fig. 3 than the amplitude limit result 0 level under, can export the result of the approaching original deration of signal.
With the deration of signal that here obtains input peak signal width holding circuit 206, detect the maximum deration of signal in the deration of signal that peak signal width holding circuit 206 is measured in (for example 1 synchronization frame (sync frame) during) and export during certain as the synchronizing signal width.That in object synchronization deration of signal initialization circuit 207, sets is imported into error-detector circuit 208 as the deration of signal of benchmark and the deration of signal of peak signal width holding circuit 206 outputs; Error-detector circuit 208 is calculated the difference of two derations of signal, and exports as error signal.
When having used the above utilization of explaining based on the synchronization signal detection of the amplitude limit of two different threshold values; Then can prevent owing to the intersymbol interference makes short mark not carry out caused synchronizing signal erroneous detection such as zero crossing; And can detect synchronizing signal width to be detected situation, can improve the frequency of PLL and introduce precision near original mark lengths.
(second embodiment)
Then, second embodiment of the present invention is described.The purpose of this embodiment is in synchronization signal detection, to avoid faults.Be the deration of signal testing circuit 205 of Fig. 2 with the optical disc reproducing apparatus difference of first embodiment.
According to the deration of signal detection method of first embodiment, might be as the L1 ' of Fig. 3, make short marking signal amplitude hour when interfering owing to intersymbol, the signal of a plurality of marks is detected as the deration of signal.Therefore, only use the deration of signal L_p ' of a threshold value or L_m ' to set testing conditions.
For example under the situation of the case1 of Fig. 4 (b); As the L1_1 of Fig. 4 (b), will regularly begin from the rising edge of Sli_p to detect as the deration of signal (L1 ' of Fig. 3) till regularly to the Sli_m negative edge, detection regularly begins the deration of signal (L_p ' of Fig. 3) till the negative edge timing from the rising edge of Sli_p as the L_p of Fig. 4 (b) in addition.Judgement as (L1 '-L_p ') of the difference of these width whether below predefined allowable value α; If below α; Export L1 ' as in L1 ' 1, only comprising a mark,, then export L_p ' and perhaps do not export as comprising a plurality of marks among the L1 ' if surpass α.In addition, tolerance α can set arbitrarily, when still generally in the such detected deration of signal of L1 ', comprising a plurality of mark, and the shortest signal that also should in a signal, attach plural minimum running period (run length).This is can not become the Sli_m negative edge from the Sli_p rising edge when being one owing to subsidiary signal.Therefore, under the situation of Blu-ray Disc media such as (BlueRay Disc, registered trademarks), be 2 minimum running period, and therefore being preferably tolerance α is about 4T (T representes 1 data width), but is not limited to this value.
And Figure 11 is shown specifically deration of signal testing circuit 205.At first, the output of the output of first amplitude limiter circuit 203 and second amplitude limiter circuit 204 is imported into first deration of signal testing circuit 1101, detects L2_1, the L2_2 of Fig. 4 (c).In addition, the output of the output of first amplitude limiter circuit 203 and second amplitude limiter circuit 204 is imported into secondary signal width detection circuit 1102, detects L_p, L_m.Then, tolerance α is stored in the setting value of tolerance α initialization circuit 1103, and this setting value preestablishes register through the user and waits and carry out.The output of first deration of signal testing circuit 1101, secondary signal width detection circuit 1102, tolerance α initialization circuit 1103 is imported into deration of signal comparator circuit 1104; Judge whether to satisfy the case1 of Fig. 4 (c), the condition of case2, the deration of signal when satisfying is input to peak signal width holding circuit 206.
When using above-described deration of signal detection method, can prevent that intersymbol from interfering the erroneous detection that causes, and can detect synchronizing signal width to be detected situation near original mark lengths, can improve the frequency of PLL and introduce precision.
(the 3rd embodiment)
Then, the 3rd embodiment of the present invention is described.This embodiment is to be the embodiment of purpose to improve the synchronization signal detection precision.Be the deration of signal testing circuit 205 of Fig. 2 with the difference of the optical disc reproducing apparatus of first embodiment.In the sychronizing signal detecting method of first embodiment, synchronizing signal has to be reproduced running period maximum in the data, therefore is to detect a mark.But, be synchronizing signal according to reproducing medium and with (the for example 9T-9T) repeatedly in transport maximum cycle, can improve accuracy of detection so detect this plural graphic length.For example under the situation of the case1 of Fig. 4 (c), as the L2_1 of Fig. 4 (c), 205 pairs of risings from Sli_p of deration of signal testing circuit regularly begin to be used as synchronizing signal width (L2 of Fig. 3) to detecting till Sli_m rises regularly.
But, in this detection mode, make short marking signal amplitude hour interfering owing to intersymbol, might think the deration of signal that constitutes by a plurality of marks by mistake synchronizing signal (L2 ' of Fig. 3), therefore need protect.This method can be utilized second embodiment.For example, detect from the rising of Sli_p and regularly begin the deration of signal L_p ' till descend regularly, further detect from the decline of Sli_m and regularly begin the deration of signal L_m ' till rise regularly.Through with the difference of these derations of signal L_p ' and L_m ' sum and L2 ', i.e. (L2 '-(L_p '+L_m ')) below tolerance α as condition etc., can protect thus.As stated, being preferably tolerance α is about 4T, but is not limited thereto.
And Figure 11 is the figure of detailed expression signal width detection circuit 205.At first, the output of the output of first amplitude limiter circuit 203 and second amplitude limiter circuit 204 is imported into first deration of signal testing circuit 1101, detects L1_1, L1_2, L1_3, the L1_4 of Fig. 4 (b).In addition, the output of the output of first amplitude limiter circuit 203 and second amplitude limiter circuit 204 is imported into secondary signal width detection circuit 1102, detects L_p, L_m.Then, tolerance α is stored in the setting value of tolerance α initialization circuit 1103, and this setting value preestablishes register through the user and waits and carry out.The output of first deration of signal testing circuit 1101, secondary signal width detection circuit 1102, tolerance α initialization circuit 1103 is imported in the deration of signal comparator circuit 1104; Judge whether to satisfy the condition of case1～case4 of Fig. 4 (b), the deration of signal when satisfying is input to peak signal width holding circuit 206.
When using above-described sychronizing signal detecting method, and compare based on the detection of a mark, can make that synchronization signal detection is more difficult makes mistakes, can improve the frequency of PLL and introduce precision.
(the 4th embodiment)
Then, the 4th embodiment of the present invention is described.
The purpose of this embodiment is, when the synchronization signal detection of using based on the amplitude limit of two different threshold values, comes stably to detect synchronizing signal through the limiting threshold of when producing skew or asymmetric such asymmetry, proofreading and correct.
Fig. 5 representes the structural drawing of the first frequency error-detector circuit 107 ' in the optical disc reproducing apparatus of this embodiment.
The first limiting threshold initialization circuit 201 that this first frequency error-detector circuit 107 ' comprises, the second limiting threshold initialization circuit 202, first amplitude limiter circuit 203, second amplitude limiter circuit 204, deration of signal testing circuit 205, peak signal width holding circuit 206, object synchronization deration of signal initialization circuit 207, the error-detector circuit 208, also comprise asymmetric quantitative determination circuit 501, first adder operation circuit 502 and second adder operation circuit 503 in the first frequency error-detector circuit 107 that comprises Fig. 2.
In addition, Fig. 6 is the waveform synoptic diagram of work of asymmetric quantitative determination circuit 501 that is used for explaining the work of this first frequency error-detector circuit 107 ', and Fig. 7 is the block diagram of the structure of the asymmetric quantitative determination circuit 501 of expression.
Asymmetric quantitative determination circuit 501 is made up of MAX_AMP testing circuit 601, MIN_AMP testing circuit 602, adder operation circuit 603,1/2 computing circuit 604.
Be conceived to below describe with the difference of Fig. 2.
In Fig. 5, on the first limiting threshold initialization circuit 201 and the second limiting threshold initialization circuit, 202 structures with Fig. 2 in situation identical.But difference is proofreaied and correct through adder operation circuit before being to be input to corresponding amplitude limiter circuit.
Asymmetric quantitative determination circuit 501 is circuit that the waveform of the output data of detection ADC105 departs from.When being example with Fig. 6, this moment " departing from " is meant that waveform is displaced to the positive side of zero level or any side of minus side.
The MAX_AMP testing circuit 601 of asymmetric quantitative determination circuit 501 detects the maximal value (MAX_AMP) of the signal of being imported.In addition, MIN_AMP testing circuit 602 detects the minimum value (MIN_AMP) of same signal.
After the output addition of adder operation circuit 603 with the output of MAX_AMP testing circuit 601 and MIN_AMP testing circuit 602, by 1/2 computing circuit 604 it is removed with 2, obtain departing from of waveform thus.It is taken as correcting value β.
Processing with such detect " departing from " be because, the synchronizing signal that detect generally has to be reproduced running period maximum in the data, so its amplitude is maximum, it is suitable deciding correcting value based on envelope.
Additive operation is carried out in the output (correcting value β) of the output (Th_p) of 502 pairs first limiting threshold initialization circuits 201 of first adder operation circuit and asymmetric quantitative determination circuit 501, and first amplitude limiter circuit 203 is exported.The output of this first adder operation circuit 502 becomes the Th_p ' of Fig. 6.Equally, additive operation is carried out in the output (correcting value β) of the output (Th_m) of 503 pairs second limiting threshold initialization circuits 202 of second adding circuit and asymmetric quantitative determination circuit 501, and second amplitude limiter circuit 204 is exported.The output of this second adder operation circuit 503 becomes the Th_m ' of Fig. 6.
Then; From the reproducing signal waveform of ADC105 output be imported into first amplitude limiter circuit, 203, the first amplitude limiter circuits 203 as the Th_p ' of the output of first adder operation circuit 502 and come output violent change result (Sli_p ' of Fig. 6) according to the difference of reproducing signal waveform and Th_p '.Equally; From the reproducing signal waveform of ADC105 output be imported into second amplitude limiter circuit, 204, the second amplitude limiter circuits 204 as the Th_m ' of the output of second adding circuit 503 and come output violent change result (Sli_m ' of Fig. 6) according to the difference of reproducing signal waveform and Th_m '.Later reproduction work is identical with first embodiment.
When using above-described sychronizing signal detecting method; Even when producing skew or asymmetric such asymmetry; Also come the measured signal width, therefore can stably detect the synchronizing signal width, can improve the frequency of PLL and introduce precision with the threshold value after proofreading and correct.
In the present embodiment, the calculating of envelope has utilized peak value maintenance (peak hold).But be not limited to this, also can use other envelope computing method.In addition, the computing method of correcting value are not limited to this mode.Also have other methods that obtain the DC composition etc.
(the 5th embodiment)
Then, the 5th embodiment of the present invention is described.Fig. 8 is the block diagram of structure of the second frequency error-detector circuit 108 ' in the optical disc reproducing apparatus of expression fifth embodiment of the invention.This embodiment is with having used synchronization signal detection based on the amplitude limit of two different threshold values to be applied to the example of introducing based on the frequency of the PLL of synchronous signal cycle.
When the first frequency error-detector circuit 107 ' of the second frequency error-detector circuit 108 ' of this embodiment and the 4th embodiment was compared, common ground was to comprise the first limiting threshold initialization circuit 201, the second limiting threshold initialization circuit 202, first amplitude limiter circuit 203, second amplitude limiter circuit 204, deration of signal testing circuit 205, asymmetric quantitative determination circuit 501, first adder operation circuit 502, second adder operation circuit 503.And the processing of the output of deration of signal testing circuit 205 differs widely; In this embodiment, handle through synchronizing signal width setup circuit 801, synchronization signal detection circuit 802, synchronous signal cycle mensuration circuit 803, object synchronization signal period initialization circuit 804, error-detector circuit 805.
Synchronizing signal width setup circuit 801 is registers of setting the synchronizing signal width that becomes benchmark.The output of this synchronizing signal width setup circuit 801 is outputed to synchronization signal detection circuit 802.
Input has the output of deration of signal testing circuit 205 and above-mentioned synchronizing signal width setup circuit 801 on the synchronization signal detection circuit 802.Relatively these two derations of signal are estimated as synchronizing signal when unanimity is perhaps in predefined permissible range, and synchronization signal detection is regularly outputed to synchronous signal cycle mensuration circuit 803.
Synchronous signal cycle is measured circuit 803 and is measured from the cycle between the synchronization signal detection timing of synchronization signal detection circuit 802, outputs to error-detector circuit 805 as synchronous signal cycle.
Object synchronization signal period initialization circuit 804 is the registers that write down the synchronous signal cycle that becomes benchmark, and its cycle is outputed to error-detector circuit 805.
Error-detector circuit 805 is that the synchronous signal cycle of synchronous signal cycle mensuration circuit 803 outputs and the benchmark synchronous signal cycle of object synchronization signal period initialization circuit 804 outputs are compared, and obtains the circuit of its difference.Second frequency error-detector circuit 108 ' is exported this difference as the margin of error.
In this embodiment, also can use described in the 4th embodiment to the skew, asymmetrical limiting threshold correcting circuit.
When using above-described sychronizing signal detecting method, through the erroneous detection that prevents to interfere based on intersymbol, the period measurement between ability stabilizing synchronizing signal improves the frequency of PLL and introduces precision.
(the 6th embodiment)
Then, the 6th embodiment of the present invention is described.This embodiment be with switch the sychronizing signal detecting method use first embodiment for example and in the past the synchronization signal detection mode of mode be the embodiment of purpose.Be amplitude limiter circuit 901, deration of signal testing circuit 902, switch 903, the detection mode initialization circuit 904 of Fig. 9 with the difference of the optical disc reproducing apparatus of first embodiment.In amplitude limiter circuit 901, the reproducing signal waveform from ADC105 output is carried out amplitude limit with single level such as 0 level, and in deration of signal testing circuit 902 the detection signal width.Switch the output of said deration of signal testing circuit 205 in output and first embodiment of these deration of signal testing circuits 902 by switch 903.The switching of this output is implemented according to the setting value of detection mode initialization circuit 904, and this setting preestablishes register through the user and waits and carry out, perhaps also can be according to the kind of reproduction speed, representation media and carry out automatically.
Above-described and the switching of mode in the past is not limited to first embodiment, equally also can be applicable to other embodiments.
(the 7th embodiment)
Then, the 7th embodiment of the present invention is described.This embodiment is for example to use and not use the embodiment that switches to purpose between the asymmetric correction method based on the 4th embodiment.Be the output initialization circuit 1001 of Figure 10, asymmetric amount output circuit 1002 with the difference of the optical disc reproducing apparatus of the 4th embodiment.Preestablish register etc. and can control output initialization circuit 1001 through the user.Through the output of this output initialization circuit 1001, whether 1002 pairs of asymmetric amount output circuits switch to the correcting value β that first adding circuit 502 and second adding circuit 503 are exported as the output of asymmetric quantitative determination circuit 501.
More than, according to the clear specifically invention of accomplishing by the inventor of embodiment, need not superfluous words, the present invention is not limited to above-mentioned embodiment, in the scope that does not break away from its purport, various changes can be arranged.
[industrial utilizability]
In the above-mentioned explanation, specified optical disc reproducing apparatus, but purposes of the present invention is not limited to this.For example, also can be applicable to synchronization signal detection in the radio communication interval of portable phone etc.
Claims (14)
1. optical disc reproducing apparatus comprises:
AFE(analog front end) carries out simulation process to the output of pick-up;
Analog to digital converter uses the analog signal conversion of above-mentioned AFE(analog front end) being exported from the reference frequency of voltage-controlled oscillator output to become digital signal;
The frequency error detection circuit detects the frequency error that above-mentioned analog to digital converter is exported;
Low-pass filter circuit is removed the radio-frequency component of said frequencies error-detector circuit output;
D-A converting circuit converts the output of above-mentioned low-pass filter circuit to simulating signal; And
Voltage-controlled oscillator is exported the said reference frequency according to the output of above-mentioned D-A converting circuit,
This optical disc reproducing apparatus is characterised in that,
The said frequencies error-detector circuit comprises:
Set the register initialization circuit of first threshold;
First amplitude limiter circuit is carried out amplitude limit with above-mentioned first threshold to the output of above-mentioned analog to digital converter;
Set the register initialization circuit of second threshold value;
Second amplitude limiter circuit is carried out amplitude limit with above-mentioned second threshold value to the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit;
Peak signal width detection circuit, the wherein deration of signal of broad is write down and exported to contrast from the deration of signal and the deration of signal that itself keeps of above-mentioned deration of signal testing circuit output;
The register initialization circuit of target setting synchronizing signal width; And
Error-detector circuit contrasts the output and the above-mentioned object synchronization deration of signal of above-mentioned peak signal width detection circuit, and exports its difference.
2. optical disc reproducing apparatus according to claim 1 is characterized in that:
Above-mentioned deration of signal testing circuit makes up the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit detects a deration of signal.
3. optical disc reproducing apparatus according to claim 1 is characterized in that:
Above-mentioned deration of signal testing circuit detects first deration of signal that the combination according to the marginal information of the marginal information of above-mentioned first amplitude limiter circuit output and the output of above-mentioned second amplitude limiter circuit obtains; And the secondary signal width that the combination that detects the marginal information of the marginal information according to above-mentioned first amplitude limiter circuit output, perhaps above-mentioned second amplitude limiter circuit output obtains; When the difference of above-mentioned first deration of signal and above-mentioned secondary signal width is the tolerance of in the register initialization circuit, setting in advance when following; Above-mentioned first deration of signal is outputed to above-mentioned peak signal width detection circuit; When the difference of above-mentioned first deration of signal and above-mentioned secondary signal width surpasses tolerance, above-mentioned secondary signal width is outputed to above-mentioned peak signal width detection circuit.
4. optical disc reproducing apparatus according to claim 1 is characterized in that:
Above-mentioned deration of signal testing circuit,
Combination according to the marginal information of above-mentioned first amplitude limiter circuit output detects first deration of signal,
Combination according to the marginal information of above-mentioned second amplitude limiter circuit output detects the secondary signal width,
Detect the 3rd deration of signal of a plurality of marks according to the combination of the marginal information of the marginal information of above-mentioned first amplitude limiter circuit output and the output of above-mentioned second amplitude limiter circuit,
When the difference of above-mentioned first deration of signal and the above-mentioned secondary signal width sum and above-mentioned the 3rd deration of signal is the allowable value of in the register initialization circuit, setting in advance when following, export above-mentioned the 3rd deration of signal.
5. optical disc reproducing apparatus comprises:
AFE(analog front end) carries out simulation process to the output of pick-up;
Analog to digital converter uses the analog signal conversion of above-mentioned AFE(analog front end) being exported from the reference frequency of voltage-controlled oscillator output to become digital signal;
The frequency error detection circuit detects the frequency error that above-mentioned analog to digital converter is exported;
Low-pass filter is removed the radio-frequency component of said frequencies error-detector circuit output;
D-A converting circuit converts the output of above-mentioned low-pass filter to simulating signal; And
Voltage-controlled oscillator is exported the said reference frequency according to the output of above-mentioned D-A converting circuit,
This optical disc reproducing apparatus is characterised in that,
The said frequencies error-detector circuit comprises:
Asymmetric quantitative determination circuit calculates and output violent change threshold value correcting value according to the output of above-mentioned analog to digital converter;
First amplitude limiter circuit is used by the correction of first behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of above-mentioned analog to digital converter;
Second amplitude limiter circuit is used by the correction of second behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit;
Peak signal width detection circuit, the wherein deration of signal of broad is write down and exported to contrast from the deration of signal and the deration of signal that itself keeps of above-mentioned deration of signal testing circuit output;
The register initialization circuit of target setting synchronizing signal width; And
Error-detector circuit contrasts the output and the above-mentioned object synchronization deration of signal of above-mentioned peak signal width detection circuit, and exports its difference.
6. optical disc reproducing apparatus according to claim 5 is characterized in that,
Also comprise:
The register initialization circuit that the output of above-mentioned asymmetric quantitative determination circuit is set; With
According to the output of above-mentioned register initialization circuit the switch that switches that is switched on or switched off to the output of above-mentioned asymmetric quantitative determination circuit.
7. optical disc reproducing apparatus comprises:
AFE(analog front end) carries out simulation process to the output of pick-up;
Analog to digital converter uses the analog signal conversion of above-mentioned AFE(analog front end) being exported from the reference frequency of voltage-controlled oscillator output to become digital signal;
The first frequency error-detector circuit detects the frequency error that above-mentioned analog to digital converter is exported with first method;
The second frequency error-detector circuit detects the frequency error that above-mentioned analog to digital converter is exported with second method;
Switch is optionally exported the output of above-mentioned first frequency error-detector circuit and the output of above-mentioned second frequency error-detector circuit;
Switch the register initialization circuit of above-mentioned switch,
Low-pass filter circuit is removed the radio-frequency component of above-mentioned switch output;
D-A converting circuit converts the output of above-mentioned low-pass filter circuit to simulating signal; And
Voltage-controlled oscillator is exported the said reference frequency according to the output of above-mentioned D-A converting circuit,
This optical disc reproducing apparatus is characterised in that,
Above-mentioned first frequency error-detector circuit comprises:
Amplitude limiter circuit is carried out amplitude limit to the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned amplitude limiter circuit;
Peak signal width detection circuit, the wherein deration of signal of broad is write down and exported to contrast from the deration of signal and the deration of signal that itself keeps of above-mentioned deration of signal testing circuit output;
The object synchronization deration of signal initialization circuit of target setting synchronizing signal width; And
Error-detector circuit contrasts the output and the above-mentioned object synchronization deration of signal of above-mentioned peak signal width detection circuit, and exports its difference,
Above-mentioned second frequency error-detector circuit comprises:
Set the register initialization circuit of first threshold;
First amplitude limiter circuit is carried out amplitude limit with above-mentioned first threshold to the output of above-mentioned analog to digital converter;
Set the register initialization circuit of second threshold value;
Second amplitude limiter circuit is carried out amplitude limit with above-mentioned second threshold value to the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit;
Peak signal width detection circuit, the wherein deration of signal of broad is write down and exported to contrast from the deration of signal and the deration of signal that itself keeps of above-mentioned deration of signal testing circuit output;
The object synchronization deration of signal initialization circuit of target setting synchronizing signal width; And
Error-detector circuit contrasts the output and the above-mentioned object synchronization deration of signal of above-mentioned peak signal width detection circuit, and exports its difference.
8. optical disc reproducing apparatus comprises:
AFE(analog front end) carries out simulation process to the output of pick-up;
Analog to digital converter uses the analog signal conversion of above-mentioned AFE(analog front end) being exported by the reference frequency of voltage-controlled oscillator output to become digital signal;
The frequency error detection circuit detects the frequency error that above-mentioned analog to digital converter is exported;
Low-pass filter is removed the radio-frequency component of said frequencies error-detector circuit output;
D-A converting circuit converts the output of above-mentioned low-pass filter to simulating signal; And
Voltage-controlled oscillator is exported the said reference frequency according to the output of above-mentioned D-A converting circuit,
This optical disc reproducing apparatus is characterised in that,
The said frequencies error-detector circuit comprises:
Set the register initialization circuit of first threshold;
First amplitude limiter circuit is carried out amplitude limit with above-mentioned first threshold to the output of above-mentioned analog to digital converter;
Set the register initialization circuit of second threshold value;
Second amplitude limiter circuit is carried out amplitude limit with above-mentioned second threshold value to the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of second amplitude limiter circuit;
The register initialization circuit of target setting synchronizing signal width;
Synchronization signal detection circuit compares the output of above-mentioned synchronizing signal width and above-mentioned deration of signal testing circuit, and judges whether to be synchronizing signal;
Synchronous signal cycle is measured circuit, measures synchronous signal cycle according to the output of above-mentioned synchronization signal detection circuit;
Set the register initialization circuit of synchronous signal cycle;
Error-detector circuit, the output of above-mentioned synchronous signal cycle and above-mentioned synchronous signal cycle being measured circuit compares, and output error.
9. phase-locked loop circuit comprises:
Analog to digital converter uses the reference frequency by voltage-controlled oscillator output that analog signal conversion is become digital signal; With
The frequency error detection circuit detects the frequency error that above-mentioned analog to digital converter is exported,
This phase-locked loop circuit is characterised in that,
The said frequencies error-detector circuit comprises:
Set the register initialization circuit of first threshold;
First amplitude limiter circuit is carried out amplitude limit with above-mentioned first threshold to the output of above-mentioned analog to digital converter;
Set the register initialization circuit of second threshold value;
Second amplitude limiter circuit is carried out amplitude limit with above-mentioned second threshold value to the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit;
Peak signal width detection circuit compares with the deration of signal that itself keeps the deration of signal from above-mentioned deration of signal testing circuit output, writes down and export the wherein deration of signal of broad;
The register initialization circuit of target setting synchronizing signal width; And
Error-detector circuit compares the output and the above-mentioned object synchronization deration of signal of above-mentioned peak signal width detection circuit, and exports its difference.
10. phase-locked loop circuit according to claim 9 is characterized in that:
Above-mentioned deration of signal testing circuit makes up the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit detects a deration of signal.
11. phase-locked loop circuit according to claim 9 is characterized in that:
Above-mentioned deration of signal testing circuit detects first deration of signal that the combination according to the marginal information of the marginal information of above-mentioned first amplitude limiter circuit output and the output of above-mentioned second amplitude limiter circuit obtains; And the secondary signal width that the combination that detects the marginal information of the marginal information according to above-mentioned first amplitude limiter circuit output, perhaps above-mentioned second amplitude limiter circuit output obtains; When the difference of above-mentioned first deration of signal and above-mentioned secondary signal width is the allowable value of in the register initialization circuit, setting in advance when following; Export above-mentioned first deration of signal to above-mentioned peak signal width detection circuit; When the difference of above-mentioned first deration of signal and above-mentioned secondary signal width surpasses allowable value, export above-mentioned secondary signal width to above-mentioned peak signal width detection circuit.
12. phase-locked loop circuit according to claim 9 is characterized in that:
Above-mentioned deration of signal testing circuit,
Combination according to the marginal information of above-mentioned first amplitude limiter circuit output detects first deration of signal,
Combination according to the marginal information of above-mentioned second amplitude limiter circuit output detects the secondary signal width,
Detect the 3rd deration of signal of a plurality of marks according to the combination of the marginal information of the margin signal of above-mentioned first amplitude limiter circuit output and the output of above-mentioned second amplitude limiter circuit,
When the difference of above-mentioned first deration of signal and the above-mentioned secondary signal width sum and above-mentioned the 3rd deration of signal is the allowable value of in the register initialization circuit, setting in advance when following, export above-mentioned the 3rd deration of signal.
13. a phase-locked loop circuit comprises:
Analog to digital converter uses the reference frequency by voltage-controlled oscillator output that analog signal conversion is become digital signal; With
The frequency error detection circuit detects the frequency error that above-mentioned analog to digital converter is exported,
This phase-locked loop circuit is characterised in that,
The said frequencies error-detector circuit comprises:
Asymmetric quantitative determination circuit calculates and output violent change threshold value correcting value according to the output of above-mentioned analog to digital converter;
First amplitude limiter circuit is used by the correction of first behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of above-mentioned analog to digital converter;
Second amplitude limiter circuit is used by the correction of second behind the output calibration of above-mentioned asymmetric quantitative determination circuit back threshold value amplitude limit is carried out in the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit;
Peak signal width detection circuit compares with the deration of signal that itself keeps the deration of signal from above-mentioned deration of signal testing circuit output, writes down and export the wherein deration of signal of broad;
The object synchronization deration of signal initialization circuit of target setting synchronizing signal width; And
Error-detector circuit compares the output and the above-mentioned object synchronization deration of signal of above-mentioned peak signal width detection circuit, and exports its difference.
14. a phase-locked loop circuit comprises:
Analog to digital converter uses the reference frequency by voltage-controlled oscillator output that analog signal conversion is become digital signal; With
The frequency error detection circuit detects the frequency error that above-mentioned analog to digital converter is exported,
This phase-locked loop circuit is characterised in that,
The said frequencies error-detector circuit comprises:
Set the register initialization circuit of first threshold;
First amplitude limiter circuit is carried out amplitude limit with above-mentioned first threshold to the output of above-mentioned analog to digital converter;
Set the register initialization circuit of second threshold value;
Second amplitude limiter circuit is carried out amplitude limit with above-mentioned second threshold value to the output of above-mentioned analog to digital converter;
Deration of signal testing circuit comes the detection signal width according to the output of above-mentioned first amplitude limiter circuit and the output of above-mentioned second amplitude limiter circuit;
Set the register initialization circuit of synchronizing signal width;
Synchronization signal detection circuit compares the output of above-mentioned synchronizing signal width and above-mentioned deration of signal testing circuit, and judges whether to be synchronizing signal;
Synchronous signal cycle is measured circuit, measures synchronous signal cycle according to the output of above-mentioned synchronization signal detection circuit;
Set the register initialization circuit of synchronous signal cycle; And
Error-detector circuit, the output of above-mentioned synchronous signal cycle and above-mentioned synchronous signal cycle being measured circuit compares, and output error.
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| JP2007317206 | 2007-12-07 | ||
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| JP2008265950 | 2008-10-15 | ||
| JP2008-265950 | 2008-10-15 | ||
| JP2008265950A JP2009158080A (en) | 2007-12-07 | 2008-10-15 | Optical disk reproducing device and phase-locked loop circuit |
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| TW200935412A (en) | 2009-08-16 |
| JP2009158080A (en) | 2009-07-16 |
| CN101452712A (en) | 2009-06-10 |
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