CN1977330A - Clock signal generation device, semiconductor integrated circuit, and data reproduction method - Google Patents

Clock signal generation device, semiconductor integrated circuit, and data reproduction method Download PDF

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CN1977330A
CN1977330A CN 200580016617 CN200580016617A CN1977330A CN 1977330 A CN1977330 A CN 1977330A CN 200580016617 CN200580016617 CN 200580016617 CN 200580016617 A CN200580016617 A CN 200580016617A CN 1977330 A CN1977330 A CN 1977330A
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mentioned
phase error
clock signal
signal
value
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中田浩平
宫下晴旬
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

The invention offers a clock signal generating apparatus, a semiconductor integrate circuit and a method of data reproduction. It is possible to improve the PLL draw time by providing a phase difference detector having a wide phase difference detection range and by performing gain control based on the PLL synchronization state. By correcting a phase difference detection point when the phase difference increases, the phase difference detection range is made wider. Moreover, the PLL lock state is judged according to the standard deviation of the value obtained by smoothing the phase difference value so that the gain is switched between the draw transient state and the stationary state, thereby reducing and stabilizing the PLL draw time.

Description

Clock signal generating device, SIC (semiconductor integrated circuit) and data recording method
Technical field
The present invention relates to a kind of generation is used for from the PLL device (clock signal generating device) of the timing signal (clock signal) of the regenerated signal binaryzation of the cleaning of medium of the information of recording and be used for the SIC (semiconductor integrated circuit) and the data recording method of this device.
Background technology
Now, with information when the CD of the information of recording is regenerated, normally will be from signal input PLL (the Phase Locked Loop) circuit of dish regeneration, generate and the regenerated signal clock signal synchronous by the PLL circuit, and it is synchronous with this clock signal, regenerated signal is carried out digital processing, and regeneration numerical data (for example, with reference to Patent Document 1).
Figure 19 is the block diagram that expression generates the existing P LL circuit structure of clock signal.
Shaven head 4102 on CD 4101, detects the light volume reflection from CD with light beam irradiates, exports electric signal again.Analog signal processing circuit 4200 extracts regenerated signal from the electric signal by shaven head output.The balanced device 4203 that the amplitude that analog signal processing circuit 4200 comprises prime amplifier 4201 that electric signal is amplified, will carry out amplifying signal is controlled to be constant gain control circuit (AGC) 4202 and improves frequency characteristic.
PLL circuit 4300 generates and the regenerated signal clock signal synchronous.PLL circuit 4300 comprises: the A/D converter 301 that regenerated signal is carried out digitized processing with clock signal; Be made as the compensation canceller 4302 that zero mode is removed low-frequency component with central value with the digital value after the digitizing; From compensating the phase error computation device 4303 of the digital value calculating phase error after eliminating; Remove the loop filter 4304 of useless low-frequency component from phase error; The clock oscillator 4400 of the clock signal of the output valve matched frequency of generation and loop filter 4304.
Clock oscillator 4400 comprises the voltage-controlled oscillator (VCO) 4402 that the loop filter output valve is converted to D/A converter 4401, generation and the corresponding clock signal of voltage signal of voltage signal.
Figure 20 is the time chart of the action of expression phase error computation device 4303.The output valve of (A) representative ring path filter 4302 of Figure 20 (digital value after promptly compensation is eliminated).Phase error computation device 4303 detects zero crossing from this digital value, the side's that absolute value is little in two digital values of clamping zero crossing position is determined (Figure 20 (B)) as the zero crossing detection position, tendency in the digital value of zero crossing detection position is under the situation of rising edge, this digital value remained untouched export as phase error, on the contrary, tendency in the digital value of zero passage detection position is the situation of drop edge, this digital value meter be multiply by-1 value as phase error output (Figure 20 (C)).PLL circuit 4300 makes that according to the circuit operation of the phase error of exporting from phase error computation device 4303 as the frequency of control clock signal phase error is zero.
Compensation canceller 4302 operates according to the two-value signal 1 of phase error, output valve and 0 dutycycle, these values are carried out additional calculation, and then the value that will carry out accumulating operation is made as zero, and control compensates the level of elimination, promptly carries out the level (for example with reference to Patent Document 2) of binaryzation thus.
Patent Document 1: TOHKEMY 2000-100083 communique
Patent Document 2: TOHKEMY 2000-243032 communique
Patent Document 3: Japanese kokai publication hei 10-107623 communique
Patent Document 4: TOHKEMY 2000-285605 communique
Patent Document 5: TOHKEMY 2002-334520 communique
Patent Document 6: TOHKEMY 2000-343025 communique
Patent Document 7: No. 3301691 communique of Japan's special permission
But, in the prior art, there is following problem, because the scope that can calculate phase error has only clock signal ± 1/2 cycle, so the capture range of PLL circuit is narrow, become big at frequency error suddenly with regenerated signal, or when causing the quality of regenerated signal to worsen because of the dust on the CD, cut and fingerprint etc., regenerated signal and the not harmony of synchronization of clock signals contingency are then to just needing spended time more synchronously, the poorest situation is not reach synchronously at all, so that can not playback of data.
In addition, another problem that prior art exists is, is contained in the data reproduction synchronous code that regenerated signal contains in order to judge regenerated signal and synchronization of clock signals state, must to detect.Therefore, when the quality that causes regenerated signal because of the dust on the CD, cut and fingerprint etc. worsens,, cause regenerability to worsen even off resonance synchronously also wants spended time that synchronous off resonance situation is detected.
Summary of the invention
The present invention solves above-mentioned existing problem and constitutes, and its purpose is, a kind of clock signal generating device is provided, even regenerated signal and synchronization of clock signals off resonance also can improve regenerability by stably catching immediately again.
In addition, in the prior art, because the scope that can calculate phase error has only clock signal ± 1/2 cycle, so the capture range of PLL circuit is narrow, under the situation of the frequency detuning of regenerated signal and clock signal, the capturing motion of PLL needs the long time.Relative therewith, motion following such clock signal generating device, calculate frequency error from degree of tilt at the time shaft of phase error, by the frequency of clock signal being controlled, with the capture range expansion (for example with reference to Patent Document 3, Patent Document 4) of PLL according to the frequency error and the phase error that obtain.
But, in the technology of the capture range of above-mentioned existing amplification PLL, its problem is, because from the big position of the inclination of phase error, be that 180 ° of variations have taken place phase error momentary status is judged and to be captured error state, therefore, when the quality that causes regenerated signal because of the face contact of the dust on the CD, cut and fingerprint or CD etc. worsens etc., produce that flase drop is surveyed or omission is surveyed, can make the pull-in time instability of PLL, elongated to time that can data reproduction.
Another problem is, in order to improve the precision of the detection of capturing error state, and keep a plurality of phase errors, from the phase error detected phase graph of errors that keeps displacement, but, in order to obtain accurate accuracy in detection in the data interval of not modulated at known particular characteristics pattern, and must keep a plurality of phase errors, it is very huge that circuit scale will become.
In addition, another problem is, in existing compensation canceller, owing to be subjected to the influence of mark/spacing ratio that the amplitude of regenerated signal diminishes easily, thereby the binaryzation level fluctuates easily, under the bad state of the quality of regenerated signal, the binaryzation level will be controlled to wrong level, calculating can not be normally carried out, thereby the seizure of PLL can not be carried out according to the phase error of zero crossing.
The present invention is for solving above-mentioned known problem, its purpose is, realize clock signal device with simple circuit configuration, even under the inferior situation of the frequency detuning of regenerated signal and clock signal and regenerated signal, also can improve regenerability by the seizure of stably carrying out PLL immediately.
The invention provides clock signal generating device, generate and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, wherein, possess: respond above-mentioned clock signal above-mentioned regenerated signal is carried out pulsed modulation, be converted to digital value by having carried out above-mentioned pulse modulated regenerated signal, on time series, generate the A/D conversion equipment of a plurality of digital values; According to above-mentioned a plurality of each digital value, calculate the phase error computation device of the phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal; According to above-mentioned phase error, the loop filter of the control signal of the frequency of the above-mentioned clock signal of output control; To have the clock oscillation device of the signal of the frequency of mating as above-mentioned clock signal generation with above-mentioned control signal; According to above-mentioned phase error, judge whether above-mentioned phase error is in the falling phase error judgment means in the predetermined scope, in the above-mentioned phase error computation device, zero crossing to above-mentioned many digital values detects, judging phase error with above-mentioned falling phase error judgment means in above-mentioned predetermined scope the time, just calculate above-mentioned phase error near the digital value of zero level side according to two digital values that are arranged in above-mentioned zero crossing front and back, judging above-mentioned phase error with above-mentioned falling phase error judgment means not in above-mentioned predetermined scope the time, just, realize above-mentioned purpose thus according to calculating above-mentioned phase error away from the digital value of zero level side in above-mentioned two digital values.
Above-mentioned falling phase error judgment means comprises the low-pass filter with above-mentioned phase error smoothing, above-mentioned falling phase error judgment means also can be according to the comparative result of the output valve and the predetermined threshold value of above-mentioned low-pass filter, judges that above-mentioned phase error is whether in above-mentioned predetermined scope.
Above-mentioned falling phase error judgment means also can be controlled above-mentioned loop filter judging above-mentioned phase error not in above-mentioned predetermined scope the time, so that the gain of above-mentioned loop filter improves.
Also possesses amplitude according to above-mentioned control signal, judge whether above-mentioned regenerated signal and above-mentioned clock signal are in the synchronous judging unit of synchronous regime, when above-mentioned synchronous judging unit is judged to be above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, effective by the judgement that above-mentioned phase error judgment means is made, when judging that above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime, the judgement of being made by above-mentioned phase error judgment means is invalid.
Also possessing the level that will above-mentioned digital value be carried out binaryzation detects, eliminate the compensation cancellation element of the compensating component of above-mentioned digital value according to above-mentioned level, above-mentioned falling phase error judgment means also can be calculated above-mentioned phase error by the digital value that compensates elimination by above-mentioned compensation cancellation element.
Also possess amplitude, judge whether above-mentioned regenerated signal and above-mentioned clock signal are in the synchronous judging unit of synchronous regime according to above-mentioned control signal,
Above-mentioned synchronous judging unit also can be when judging above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, control above-mentioned compensation cancellation element to improve the gain of above-mentioned compensation cancellation element, when judging that above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime, control above-mentioned compensation cancellation element to reduce the gain of above-mentioned compensation cancellation element.
Also possess: the adding up device that above-mentioned digital value is added up in each predetermined interval; The equalization device of the averaging of accumulated value that will calculate through above-mentioned adding up device; The error detecting apparatus that difference between accumulated value that calculates through above-mentioned adding up device and the mean value that obtains through above-mentioned average treatment device is carried out error-detecting during greater than predetermined threshold value, when carrying out error-detecting, can judge that also above-mentioned synchronous judging unit is not in synchronous regime by above-mentioned error detecting apparatus.
The invention provides SIC (semiconductor integrated circuit), be used to generate and record the clock signal generating device of regenerated signal clock signal synchronous of the optical disc reproducing of information, wherein, above-mentioned clock signal generating device comprises: respond above-mentioned clock signal above-mentioned regenerated signal is carried out pulsed modulation, be converted to digital value by having carried out above-mentioned pulse modulated regenerated signal, on time series, generate the A/D conversion equipment of a plurality of digital values, with the clock oscillation device that generates above-mentioned clock signal, above-mentioned SIC (semiconductor integrated circuit) possesses: according to above-mentioned a plurality of each digital value, calculate the phase error computation device of the phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal; According to above-mentioned phase error, the loop filter of the control signal of the frequency of the above-mentioned clock signal of output control; According to above-mentioned phase error, judge whether above-mentioned phase error is in the falling phase error judgment means in the predetermined scope, in the above-mentioned phase error computation device, zero crossing to above-mentioned many digital values detects, judging phase error with above-mentioned falling phase error judgment means in above-mentioned predetermined scope the time, just calculate above-mentioned phase error near the digital value of zero level side according to two digital values that are arranged in above-mentioned zero crossing front and back, judging above-mentioned phase error with above-mentioned falling phase error judgment means not in above-mentioned predetermined scope the time, just according to calculating above-mentioned phase error away from the digital value of zero level side in above-mentioned two digital values, the signal that above-mentioned clock oscillation device generation has the frequency of mating with above-mentioned control signal is realized above-mentioned purpose thus as above-mentioned clock signal.
The invention provides data recording method, generate and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, output and above-mentioned clock signal are carried out above-mentioned regenerated signal the playback of data of digitized processing synchronously, wherein, comprise: (a) respond above-mentioned clock signal, above-mentioned regenerated signal is carried out pulsed modulation, be converted to digital value, on time series, generate the step of a plurality of digital values by having carried out above-mentioned pulse modulated regenerated signal; (b), calculate the step of the phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal according to above-mentioned a plurality of each digital value; (c) according to above-mentioned phase error, the step of the control signal of the frequency of the above-mentioned clock signal of output control; (d) generate the step of the signal of frequency as above-mentioned clock signal with corresponding above-mentioned control signal; (e), judge whether above-mentioned phase error is in the step in the predetermined scope, and above-mentioned steps (b) comprises: the step that detects the zero crossing of above-mentioned a plurality of digital values according to above-mentioned phase error; In above-mentioned falling phase error determining step, judge when above-mentioned phase error is in the above-mentioned predetermined scope,, calculate the step of above-mentioned phase error according to the digital value of two digital values that are arranged in above-mentioned zero crossing front and back near the zero level side; When judging that in above-mentioned falling phase error determining step above-mentioned phase error is not in above-mentioned predetermined scope, according in above-mentioned two digital values away from the digital value of zero level side, calculate the step of above-mentioned phase error, realize above-mentioned purpose thus.
The present invention provides clock signal generating device on the other hand, generate and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, wherein, possess: respond above-mentioned clock signal, above-mentioned regenerated signal is carried out pulsed modulation, be converted to digital value by having carried out above-mentioned pulse modulated regenerated signal, on time series, generate the A/D conversion equipment of a plurality of digital values; According to above-mentioned a plurality of each digital value, calculate the first phase error computation device of first phase error of phase error of the phase error of expression above-mentioned regenerated signal and above-mentioned clock signal; The first phase error computation device that the distribution of the displacement of above-mentioned first phase error is detected; According to the distribution testing result of the displacement of above-mentioned first phase error and above-mentioned first phase error, generate the loop filter of control signal of the frequency of the above-mentioned clock signal of control; Generation has the clock oscillation device of the signal of the frequency of mating with above-mentioned control signal as above-mentioned clock signal, realizes above-mentioned purpose thus.
Also possesses amplitude according to above-mentioned control signal, judge whether above-mentioned regenerated signal and above-mentioned clock signal are in the synchronous judging unit of synchronous regime, above-mentioned synchronous judging unit also can be when judging above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, if it is effective by the detection that the above-mentioned first displacement distribution pick-up unit carries out, when judging that above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime, it is effective to establish the detection of being undertaken by the above-mentioned first displacement distribution pick-up unit.
Also possesses the adding up device of above-mentioned digital value being made accumulation calculating in each predetermined interval; Equalization device to the averaging of accumulated value calculated through above-mentioned adding up device; The error detecting apparatus that the difference of the mean value that obtains at the accumulated value that calculates through above-mentioned adding up device with through above-mentioned average treatment device is carried out error-detecting during greater than predetermined threshold value, when carrying out error-detecting, can judge that also above-mentioned synchronous judging unit is not in synchronous regime by above-mentioned error detecting apparatus.
Above-mentioned loop filter also can generate above-mentioned control signal, and the deviation that makes the displacement of above-mentioned first phase error distribute diminishes.
When the deviation of above-mentioned distribution was big, above-mentioned loop filter also can only use the value of the polarity that deviation diminishes in above-mentioned phase error.
Above-mentioned displacement distribution pick-up unit also can carry out accumulation calculating and detect distribution by the symbol to above-mentioned displacement.
Above-mentioned displacement distribution pick-up unit also can be only the absolute value of above-mentioned displacement during greater than predetermined value the symbol to above-mentioned displacement carry out accumulation calculating.
Above-mentioned displacement distribution pick-up unit also can be at the absolute value of above-mentioned displacement during less than predetermined value, and the direction that diminishes at the absolute value of the accumulated value that above-mentioned displacement symbol is added up increases or reduce above-mentioned accumulated value.
Also possess: the high boost filter that promotes the radio-frequency component of above-mentioned digital value; Calculate the second phase error computation device of second phase error of the phase error between above-mentioned regenerated signal of expression and above-mentioned clock signal according to the output signal of above-mentioned high boost filter; To the second displacement distribution pick-up unit that the distribution of the displacement of above-mentioned second phase error detects, above-mentioned loop filter also can generate above-mentioned control signal so that the deviation that the displacement of first phase error distributes diminishes.
Also possessing the level that above-mentioned digital value is made binary conversion treatment detects, the compensation cancellation element of the compensating component of above-mentioned digital value being eliminated according to above-mentioned level, the above-mentioned first phase error computation device calculates above-mentioned first phase error according to the digital value of eliminating by above-mentioned compensation cancellation element compensation, and above-mentioned high boost filter also can be contained in the above-mentioned compensation cancellation element.
Also possesses amplitude according to above-mentioned control signal, whether above-mentioned regenerated signal and clock signal are in the synchronous judging unit that synchronous regime is judged, when determining above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, above-mentioned synchronous judging unit is controlled above-mentioned compensation cancellation element to improve the gain of above-mentioned compensation cancellation element, determining above-mentioned regenerated signal and above-mentioned clock signal when being in synchronous regime, above-mentioned synchronous judging unit also can be controlled above-mentioned compensation cancellation element to reduce the gain of above-mentioned compensation cancellation element.
Other inventions of the present invention provide SIC (semiconductor integrated circuit), it generates and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, wherein, above-mentioned clock signal generating device comprises the above-mentioned clock signal of response above-mentioned regenerated signal is carried out pulsed modulation, and be converted to digital value by having carried out above-mentioned pulse modulated regenerated signal, on time series, generate the A/D conversion equipment of a plurality of digital values, with the clock oscillation device that generates above-mentioned clock signal, above-mentioned SIC (semiconductor integrated circuit) comprises: the first phase error computation device of calculating first phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal according to above-mentioned a plurality of each digital value; The first displacement distribution pick-up unit that the displacement of above-mentioned first phase error is distributed and detects; The testing result that distributes according to the displacement of above-mentioned first phase error and above-mentioned first phase error, generate the loop filter of the control signal of the frequency of controlling above-mentioned clock signal, above-mentioned loop filter generates control signal, the deviation that makes the displacement of above-mentioned first phase error distribute diminishes, the signal that above-mentioned clock oscillation device generation has the frequency of mating with above-mentioned control signal is realized above-mentioned purpose thus as above-mentioned clock signal.
Other inventions of the present invention provide data recording method, generate and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, output and above-mentioned clock signal are carried out above-mentioned regenerated signal the playback of data of digitized processing synchronously, wherein, comprise: (a) respond above-mentioned clock signal, above-mentioned regenerated signal is carried out pulsed modulation, be converted to digital value, on time series, generate the step of a plurality of digital values by having carried out above-mentioned pulse modulated regenerated signal; (b), calculate the step of first phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal according to above-mentioned a plurality of each digital value; (c) step of the displacement distribution of above-mentioned first phase error of detection; (d) generate the step of control signal of the frequency of the above-mentioned clock signal of control according to the displacement distribution testing result of above-mentioned first phase error and above-mentioned first phase error; (e) generation has the signal of the frequency of mating with above-mentioned control signal as above-mentioned clock signal, above-mentioned steps (d) comprises: generate above-mentioned control signal, the step that the deviation that makes the displacement of above-mentioned first phase error distribute diminishes realizes above-mentioned purpose thus.
In above the present invention, by calculating phase error according to the result who the scope of phase error has been carried out judge, thereby can with the range expansion of the phase error that can calculate to the clock signal ± 1 cycle.
In addition, according to judging immediately, can generate the stable clock signal by control clock signal generating apparatus aptly from the control signal of loop filter output phase synchronization state to regenerated signal and clock signal.
According to clock signal generating device of the present invention, the correction of the scope by the phase error that carries out calculating can enlarge and capture error range, even take place to change suddenly to cause under the situation of synchronous off resonance in the frequency of regenerated signal, and also can be synchronous again.
In addition, according to the judged result of phase error and the judged result of synchronous regime, gain and falling phase error judgment means by control loop filter and compensation cancellation element, improve gain during not in synchronous regime in regenerated signal and clock signal, enlarge and calculate the scope of phase error and be drawn to synchronous regime as quick as thought, when being in synchronous regime, regenerated signal and clock signal reduce gain, the scope of calculating phase error is revised, can be generated the stable clock signal.
Also have,, obtain the distribution of the displacement of phase error, its deviation is detected according to other clock signal generating devices of the present invention.When the deviation that detects is big, as the phase error that does not have deviation to be the control signal of benchmark generation control clock signal frequency.Thus, even the state that the quality of regenerated signal is bad, also can be correct detect the state that PLL can not capture the frequency error of regeneration letter and clock signal, by frequency according to the testing result control clock signal, make frequency error be positioned at capture range, thereby can generate the stable clock signal.
In addition, according to one embodiment of present invention, distribute because the accumulated value that carries out accumulating operation by the symbol with the displacement of phase error is obtained the displacement of phase error, thereby needn't keep a plurality of phase errors, can in small-sized circuit, realize high-precision test.
Have again, according to one embodiment of present invention, will lack the amplitude amplification of mark/space portion, the accuracy of detection of binaryzation level is improved, and the action of catching of PLL is stablized by promote filter by high pass.
Description of drawings
Fig. 1 is the mode chart of structure of the PLL circuit of the expression embodiment of the invention 1;
Fig. 2 is the timing diagram of action of the phase error computation of the expression embodiment of the invention 1;
Fig. 3 is the mode chart of structure of the falling phase error decision circuitry of the expression embodiment of the invention 1;
Fig. 4 is the timing diagram of the action judged of the falling phase error of the expression embodiment of the invention 1;
Fig. 5 is the mode chart of structure of the synchronization judging circuit of the expression embodiment of the invention 1;
Fig. 6 is the state transition diagram of the state machine of the expression embodiment of the invention 1;
Fig. 7 is the timing diagram of the action that detects of the amplitude error of the expression embodiment of the invention 1;
Fig. 8 is the timing diagram of the action judged of the synchronous regime of the expression embodiment of the invention 1;
Fig. 9 is the mode chart of structure of the clock generating circuit of the expression embodiment of the invention 2;
Figure 10 is the mode chart of structure of the displacement distribution detector of the expression embodiment of the invention 2;
Figure 11 is the timing diagram of action of the displacement distribution detector of the expression embodiment of the invention 2;
Figure 12 is the timing diagram of action of the displacement distribution detector of the expression embodiment of the invention 2;
Figure 13 is the timing diagram of action of the displacement distribution detector of the expression embodiment of the invention 2;
Figure 14 is the mode chart of structure of the loop filter of the expression embodiment of the invention 2;
Figure 15 is the timing diagram of the action of expression displacement distribution detector of the embodiment of the invention 2 and loop filter;
Figure 16 is the mode chart of structure of the clock generating circuit of the expression embodiment of the invention 3;
Figure 17 is the mode chart of structure of the high boost filtering of the expression embodiment of the invention 3;
Figure 18 is the mode chart of structure of the dish device of the expression embodiment of the invention 4;
Figure 19 is the mode chart of the structure of expression existing P LL circuit;
Figure 20 is the timing diagram of action of the phase error computation of expression existing P LL circuit.
Symbol description
101 CDs
102 shaven heads
103 motors
200 analog signal processing circuits
201 prime amplifiers
202 AGC (gain control circuit)
203 compensators
300 PLL circuit
301 A/D converters
302 compensation cancellers
303 phase error computation devices
304 loop filters
400 clock oscillators
401 D/A converters
402 VCO (voltage-controlled oscillator)
500 falling phase error determining devices
501 chronotrons
502 comparers
600 synchronous determining devices
601 DC level detecting devices
602 LPF
603 subtracters
604 comparers
605 exchange level detector
606 LPF
607 subtracters
608 comparers
609 standard deviation calculation devices
610 comparers
611 continuous determining devices
612 state machines
613 gate generators
1101 CDs
1102 shaven heads
The 1102a light beam
The 1102b electric signal
1103 motors
1200 analog signal processing circuits
The 1200a regenerated signal
The servo regenerated signal of using of 1200b
1201 prime amplifiers
1202 AGC
1203 compensators
1300 clock signal generating devices
1301 A/D converters
The 1301a digital value
1302 compensation cancellers
Digital value after the 1302a compensation is eliminated
1303 phase error computation devices
The 1303a phase error
1303b phase error computation synchronizing signal
1304 loop filters
The 1304a control signal
1305 distributions detect uses the phase error computation device
1305a distributes to detect and uses the phase error computation value
1305b distributes to detect and uses the phase error computation timing signal
1400 clock oscillators
1401 D/A converters
1402 VCO
The 1400a clock signal
1500 displacement distribution detectors
1501 differential filters
1502,1504,1505,1506 chronotrons
1503,1510 totalizers
1507,1508,1509 subtracters
1501a differential filter output valve
The symbol of 1501b differential filter output valve
1511 comparers
1512 totalizers
The accumulated value of 1512a symbol
1513 comparers
1500a distribution testing result
1601 guiding channel circuit
The 1601a playback of data
1602 data demodulation circuits
1602a data demodulates result
1603 address decoders
The 1603a address value
1604 memory buffer
1605 CPU
1606 servo circuits
The 1606a motor drive signal
1606b shaven head drive signal
1607 interfaces
1701,1702,1703,1704,1705 chronotrons
1706,1707,1708,1709,1710 totalizers
1711 totalizers
3021 zero level detecting devices
3021a zero level detected value
3022 binaryzation DUTY detected values
3022a binaryzation detected value
3023 totalizers
3023a value level value
3024 high boost wave filters
3024a high boost filtering output value
3025 subtracters
3041 phase errors shielding device
3042,3045 amplifiers
3043,3046 totalizers
3044 chronotrons
Embodiment
Below, the embodiment with PLL device of the present invention (clock signal generating device) describes with reference to accompanying drawing pair.
(example 1 in real time)
Fig. 1 is the block diagram of structure of the PLL device of the expression embodiment of the invention 1.
Shaven head 102 on CD 101, detects the reflection light quantity from CD 101, the output electric signal with light beam irradiates.Analog signal processing circuit 200 extracts regenerated signal from the electric signal by shaven head 102 outputs.Analog signal processing circuit 200 comprises: the amplitude of prime amplifier 201 that electric signal is amplified, the signal that will amplify is controlled to be constant amplification control circuit (AGC) 202, improves the compensator 203 of frequency characteristic.
Secondly, the structure to PLL circuit 300 describes.
PLL circuit 300 generates and the regenerated signal clock signal synchronous.Clock signal generating circuit 300 comprises: the A/D converter 301 that regenerated signal is carried out digitized processing with clock signal, with with digitizing the central value of digital value zero the mode of being made as remove the compensation canceller 302 of low-frequency component, calculate from the phase error computation device 303 of the phase error of the digital value of compensation canceller 302 output and clock signal, the falling phase error determining device 500 of the correction of the computer capacity of the phase error that control phase Error Calculator 303 is carried out, remove the loop filter 304 of useless band component in the middle of the phase error, generation has the clock oscillator 400 with the clock signal of the output valve matched frequency of loop filter 304, the synchronous determining device of the phase synchronization state of regenerated signal and clock signal being judged by the loop filter output valve 600.
Carried out containing in the digitized digital value with A/D converter 301 and in analogue signal processor 200, be not removed and the composition of remaining useless low frequency.Compensation canceller 302 extracts this low-frequency band territory composition, by deducting the offset that extracts from digital value, removes low-frequency component.Thus, even, also can carry out the stable clock pulse and generate action such as adhering on the information recording surface of CD under the situation that dust and fingerprint, regenerated signal fluctuate because of low frequency.
Digital value after phase error computation device 303 is eliminated according to compensation is calculated phase error.Fig. 2 is the timing diagram of the action of expression phase error computation device 303.(A) of Fig. 2 represents to compensate digital value after the elimination with time series.From two digital values of these digital values before and after detection is positioned at zero crossing, usually the zero passage detection position is used as in the side's that absolute value is little in these two digital values position and determines (Fig. 2 (B)), and correction zero passage detection determining positions (Fig. 2 (C)) is used as in the position of the opposing party in two digital values.The judgement signal that sends by falling phase error determining device 500 is expression do not have to revise " L " time, select the zero passage detection position, on the contrary, when expression has " H " of correction, select zero passage detection position (Fig. 2 (D) (E)).When phase error is the edge that rises in the inclination of selecteed position digital value, remain untouched with this digital value and to export as phase error, in the inclination of selecteed position digital value during ,-1 value that multiply by after this digital value is exported as phase error for the edge that descends.
By loop filter 304, from phase error, remove useless frequency content.The output valve of loop filter 304 is input to clock oscillator 400.Clock oscillator 400 comprises D/A converter 401 and the voltage-controlled oscillator (VCO) 402 that the output valve of loop filter 304 is converted to voltage signal.When the output valve of loop filter 304 big, when the output voltage of D/A converter 401 is high, the frequency gets higher of the clock signal that generates by VCO402.In addition, when the output of loop filter 304 little, the output voltage of D/A converter 401 hour, the frequencies go lower of the clock signal that generates by VCO402.Therefore, when PLL circuit 300 is positive value at the phase error of being calculated by phase error computation device 303, the frequency of clock signal raises with regard to action, and when the phase error of being calculated by phase error computation device 303 was the value of bearing, the frequency of clock signal just reduced.
Fig. 3 is the block diagram of the structure of expression phase error determining device 500.To be made as P with the phase error that phase error computation device 303 calculates doubly, on its value of being delayed time, add (1-P) value doubly, again with this addition value input time delay device 501 by chronotron.The P value for example also can be 1/2.The cycling circuit that comprises chronotron 501 moves when calculating phase error by phase error computation device 303 at every turn, and thus, the output valve of chronotron 501 is under the situation that phase error continues to increase or reduces, and it is big that its absolute value all becomes.When comparer 502 becomes greater than predetermined positive threshold value in the output valve of chronotron 501, when perhaps becoming less than predetermined negative threshold value, need carry out the correction of phase error computation scope, the output phase error scope is judged signal.
Fig. 4 is the timing diagram of the action of expression falling phase error determining device 500.The digital value that (A) the expression regenerated signal of Fig. 4 and clock signal are in synchronous regime, the value in the zero passage detection position is zero.On the other hand, the frequency of Fig. 4 (B) expression clock signal is with respect to the digital value under the low situation of regenerated signal.Because the frequency of clock signal is low, so in each some cycle, the phase place of clock signal is more than 1/2 cycle with respect to the regenerated signal delay clock signals.(C) expression phase error at this moment of Fig. 4.Because in the time need not revising the phase error computation scope, the phase error computation scope has only ± 1/2 cycle, when so the phase delay of clock signal is stabilized in 1/2 cycle, phase error has just become the value of the frequency UP of expression clock signal, but, then rotate one-period more than 1/2 cycle if postpone, become the value that expression phase frequency DOWN represents, can not generate clock signal synchronous.The value that Fig. 4 (D) expression is corresponding at the chronotron 501 of phase error determining device 500.Under the low situation of the frequency of clock signal, the output valve of chronotron 501 absolute value when positive side increases, clock signal is with respect to the phase delay of regenerated signal during 1/2 cycle, will exceed predetermined positive threshold, consequently, must carry out the correction of falling phase error, falling phase error judges that signal becomes " H " (Fig. 4 (E)).Phase error computation device 303 is judged signal selection correction zero passage detection position according to falling phase error, thus, the scope that can calculate phase error is+1/2 the cycle～scope in+1 cycle, be no more than in phase place+during the scope in 1 cycle, can continue to export the phase error of expression frequency UP.Consequently, can generate stable clock signal synchronous.In addition, under the high situation of the frequency of clock signal, the output valve of chronotron 501 absolute value when minus side increases, in clock signal with respect to the phase place of regenerated signal in advance during 1/2 cycle, will exceed predetermined negative sense threshold value, consequently, falling phase error judges that signal becomes " H ".Phase error computation device 303 is judged signal selection correction zero passage detection position according to falling phase error, thus, the scope that can calculate phase error for-1/2 the cycle～scope in-1 cycle, be no more than the scope in-1 cycle in phase place, can continue to export the phase error of expression frequency DOWN.At this, control+side threshold value and-value of side threshold value, it is constant to make that the gain control circuit (AGC) 202 of amplitude by analog signal processing circuit 200 of the regenerated signal that is input to A/D converter 301 becomes, and thus, can determine to be the value corresponding to this amplitude.
Below, the action of synchronous determining device 600 is described.
Fig. 5 is the block diagram of the structure of the synchronous determining device 600 of expression.Determining device 600 comprises synchronously: detection is from the DC level detector 601 of the DC level of the digital value of A/D dress parallel operation 301 outputs; The variation of DC level detected value is carried out the low-pass filter (LPF) 602 of smoothing processing; Calculate the subtracter 603 of DC level detection value and LPF output valve difference; The comparer 604 that above-mentioned difference and predetermined DC error-detecting threshold value are compared; Detection is from the AC level detector 605 of the AC level of the digital value of A/D converter 301 outputs; The variation of AC level detection value is carried out the low-pass filter (LPF) 606 of smoothing processing; Calculate the subtracter 607 of the difference of AC level detection value and LPF output valve; The comparer 608 that above-mentioned difference and predetermined AC error-detecting threshold value are compared; The standard deviation calculation device 609 of the standard deviation of the output valve of ring path filter 304; The comparer 610 that above-mentioned standard deviation and predetermined standard deviation threshold are compared; Judge the successional continuous determining device 611 of comparative result; The state machine 612 that moves according to above-mentioned testing result; Control the gate pulse maker 613 of the action of PLL circuit 300 according to state machine 612.
(A) of Fig. 7 is expression changes the action that detects to the DC of digital value timing diagram.DC level detector 601 is to obtain in each predetermined interval take advantage of the value of calculation from the digital value of A/D converter 301 outputs, this interval is for the cycle that should detect the moving composition of DC fluctuation, very short, and as long as the information bit of representing greater than digital value " 1 " and the ratio (dutycycle) of " 0 " become 1: 1 interval substantially.By make the smoothing of DC level detection value with LPF602, try to achieve the mean value of DC level detection value.As long as LPF602 removes the frequency characteristic of the DC fluctuation composition that detect.In subtracter 603, the difference of DC level detection value and its mean value is calculated, under the situation that the DC fluctuation has taken place, it is big that the absolute value of difference becomes, and when exceeding DC error-detecting threshold value, detects by 604 pairs of DC errors of comparer.
(B) of Fig. 7 is the timing diagram of the action of the expression DC change that detects digital value.AC level detector 605 is obtained will be from the digital value of the A/D converter 301 output value at each predetermined interval integrating, and as long as this interval is short as much as possible for the cycle of the AC fluctuation composition that should detect.By the AC level detection value is level and smooth, try to achieve the mean value of AC level detection value with LPF606.The frequency characteristic that LPF606 needs only to removing the AC fluctuation composition that detect is just passable.In subtracter 607, the difference of AC level detection value and its mean value is calculated, and the absolute value of difference becomes big under the situation that the AC fluctuation has taken place, and when exceeding AC error-detecting threshold value, detects as the AC error by comparer 604.
Fig. 8 is the timing diagram of expression corresponding to the variation of the output valve of the loop filter 304 of regenerated signal and clock signal.The standard deviation that standard deviation calculation device 609 is calculated the output valve of loop filter 304 in each predetermined interval.Under regenerated signal and the nonsynchronous situation of clock signal, it is big that standard deviation value becomes, and if synchronously standard deviation value diminish.In comparer 610,, judge the synchronous regime that each is interval by comparing with this standard deviation value and the standard deviation critical value of being scheduled to.Moreover, in continuous determining device 611, if the judged result of each interval synchronous regime is judged as synchronous OK continuously in pre-determined number, then regenerated signal and synchronization of clock signals are by locking, output lock detection signal, on the contrary, if judged result is judged to be synchronous NG continuously in pre-determined number, then non-locking is synchronous, exports non-lock detection signal.Synchronous regime so just can judge rightly.
State machine 612 is according to above-mentioned DC error detection signal, AC error detection signal and close detection signal, non-lock detection signal carries out state exchange, gate generator 613 is according to the state of state machine 612, and the falling phase error of output control phase error range determining device 500 is judged the compensation canceller gain switching signal of the gain of the loop filter gain switching signal of enabling signal, 304 gains of control loop wave filter, control compensation canceller 302.
Fig. 6 is the state exchange of state machine 612 and gate generator 613 synoptic diagram in the action of each state.In case the action of PLL circuit 300 brings into operation, the state of state machine just begins from position reset entry into service.Reset on the throne, because the error of the frequency of regenerated signal and clock signal is big, so in order to make capturing motion steadily start falling phase error determining device 500, improve the gain of loop filter 304 in order to shorten pull-in time, for making it, the center by the control figure value becomes " zero " immediately, and the gain that improves compensation canceller 302.In case export non-lock detection signal, state just is transformed into a set.Set on the throne, because the error of the frequency of regenerated signal and clock signal becomes very little, so it is unnecessary that falling phase error is judged, moreover, in order to prevent that judging the execution error action because of the poor quality falling phase error of regenerated signal makes PLL circuit instability, and stop the running of falling phase error determining device 500.On the other hand, because eliminating control, the compensation of phase place and digital value also fully do not catch, so all gains are all high.If at this moment detection signal is closed in output, state is just moved to position " 3 ", if export non-lock detection signal, state is just got back to a reset once more.Position " 3 " is that regenerated signal and clock signal are judged as synchronous state fully, stablize for making the 300 all actions of PLL circuit, and the operation of falling phase error determining device 500 is stopped, the gain of loop filter 304 is reduced, the gain of compensation canceller 302 is reduced.At this, just move to a reset if carry out non-lock detection, if carry out the DC error-detecting or position " 2 " is just moved in the AC error-detecting.Position " 2 " is because of the DC change of digital value or the influence of AC change, thereby the control of compensation canceller 302 might be unstable, and thus, expression may not correctly be calculated phase error by phase error computation device 303.Therefore, catch so that the center vanishing of digital value is just passable as long as raising compensates the gain of canceller 302 for horse back.And, if carry out lock detection, then move to position " 3 " once more, can not stably catch but not moving to a set during lock detection.
As mentioned above, according to present embodiment, by carrying out that falling phase error is judged and the calculating of the phase error corresponding with it, the scope of the phase error that can calculate can from clock signal ± 1/2 cycle expanded to ± 1 cycle, even under the big situation of the frequency error of regenerated signal and clock signal, also can correctly calculate phase error, can stably generate and the regenerated signal clock signal synchronous.
In addition, standard deviation according to the output valve of loop loop filter 304 is judged regenerated signal and synchronization of clock signals state, according to this action of control phase error range determining device 500 and loop loop filter 304 as a result, can make thus from the action of PLL circuit 300 to begin to carry out, and can shorten pull-in time to the capturing motion of closed condition is stable.
In addition, from the DC change of carrying out regenerated signal by the digital value of A/D converter 301 or the error-detecting that AC changes, control the action of control compensation canceller 302 according to its result, even thus because the influence of cut dust on the optical disc information record surface and fingerprint etc. causes the regeneration action unstable, also capable of regeneration state can be returned to immediately, and regenerability can be improved.
Moreover, in the present embodiment, for after D/A conversion, compensating the formation of elimination at regenerated signal, but change because of also carrying out D/A to the compensation rate that has detected, in analog signal processing circuit 200, will compensate elimination.
Moreover, also can omit compensation canceller 302 in the formation of PLL circuit.In this case, as long as phase error computation device 303 is according to calculating phase error from the digital value of A/D converter output.
Moreover, also can on single semiconductor chip, form a part or the integral body of PLL circuit 300.For example in the structure of PLL circuit 300 shown in Figure 1, also compensation canceller 302, phase error computation device 303, loop filter 304, falling phase error determining device 500 and synchronous determining device 600 can be used as SIC (semiconductor integrated circuit) and realize.
Moreover in the present embodiment, Fig. 6 represents the action of state machine 612 and gate generator 613, but is not to be confined to this.
(embodiment 2)
Fig. 9 is the block diagram of structure of the clock signal generating device of the expression embodiment of the invention 2.
Clock signal generating device service recorder shown in Figure 9 has the CD of information to generate clock signal.Clock signal generating device comprises shaven head 1102, analog signal processing circuit 1200 and clock signal generating circuit 1300.
Shaven head 1102 is radiated at light beam 1102a on the CD 1101, detects the reflected light from CD 1101, generates electric signal 1102b according to reflected light again.
Analog signal processing circuit 1200 extracts regenerated signal 1200a from electric signal 1102b, the compensator 1203 that its amplitude that comprises the electric signal that prime amplifier 1201, control that electric signal 1102b is amplified amplified makes its constant gain control circuit (AGC) 1202 and improves frequency characteristic.
Clock signal generating device 1300 works as the PLL of the phase differential that makes regenerated signal 1200a and clock signal 1400a action near zero, generates and regenerated signal 1200a clock signal synchronous 1400a.Clock signal generating device 1300 comprises: the A/D converter 1301 that makes regenerated signal 1200a and clock signal carry out digital processing synchronously; To be controlled to be zero compensation canceller 1302 from the centered level of the digital value 1301a of A/D converter 1301 output; The phase error computation device 1303 that digital value 1302a and the phase error 1303a between the clock signal 1400a from the output of compensation canceller 1302 are calculated; The displacement distribution detector 1500 of the deviation that the displacement of detected phase error amount 1303a distributes; Remove the loop filter 1304 of useless frequency field composition from phase error 1303a; Generation is according to the clock oscillator 1400 of the clock signal 1400a of the frequency of loop filter 1304 output valves.
Not in analog signal processing circuit 1200, remove and the composition of residual useless low frequency having been undertaken by A/D converter 1301 containing among the digitized digital value 1301a.Compensation canceller 1302 deducts the offset that extracts by extracting this low-frequency component from digital value 1301a, remove low-frequency component.Thus,, cause because of low frequency under the situation of regenerated signal 1200a fluctuation, also can carry out the stable clock signal and generate action even on information recording surface, adhered to dust and fingerprint etc. such as CD 1101.
Phase error computation device 1303, the digital value 1302a after the compensation elimination calculates phase error.The action of phase calculator 1303 constantly with the timing identical (with reference to (A) of Figure 20) of the action of phase calculator 303 shown in Figure 19.Promptly, 1303 pairs of zero crossings of phase error computation device detect, the position that will be arranged in the less side of two digital value absolute values before and after the zero crossing usually is made as zero crossing determining positions (Figure 20 (B)), when the inclination in the digital value of zero crossing detection position is during to coboundary, just this digital value is remained untouched and export as phase error, in the inclination of the digital value of zero crossing detection position is during to lower limb, then will this on duty with the value after-1 as phase error output (Figure 20 (C)).
Utilize loop filter 1304 from phase error 1303a, to remove useless frequency field composition.Output valve input clock oscillator 1400 with loop filter 1304.Clock oscillator 1400 comprises D/A converter 1401 and the voltage-controlled oscillator (VCO) 1402 that the output valve 1304a of loop filter 1304 is converted to voltage signal.If it is big that the output valve 1304a of loop filter 1304 becomes, the output voltage of D/A converter 1401 diminishes, then the frequencies go lower of the clock signal 1400a that is generated by VCO1402.Therefore, when the phase error 1303a that is calculated by phase error computation device 1303 is positive value, the action that the PLL operation improves the frequency of clock signal 1400a, so that the frequency of locking signal 1400a improves, its action reduces the frequency of clock signal 1400a when being the value of bearing.
Below, displacement distribution detector 1500 is elaborated.
Figure 10 is the block diagram of expression displacement distribution detector 1500 structures.Displacement distribution detector 1500 comprises by phase error 1303a being carried out differential tries to achieve the differential filter 1501 of displacement (differential filter output valve 1501a) and the circuit that the deviation of the distribution of differential filter output valve 1501a is detected.
In differential filter 1501, the 1502nd, to each each phase error computation of being undertaken by phase error computation device 1303 locking and keep the chronotron of phase error constantly, through in totalizer 1503, two crowdes of phase error 1303a being carried out additional calculation, in the noise contribution of removing phase error 1303a, its resolution is improved.1504, the 1505, the 1506th, the chronotron that constantly output valve of totalizer 1503 is carried out locking and kept in each same phase Error Calculation, by subtracter 1507,1508,1509 respectively and the output valve of totalizer 1503 between carry out differential.And then in totalizer 1510, by with three differential value additions, in the noise of removing the differential result, its resolution is improved.
By comparer 1511, differential filter output valve 1501a and predetermined threshold value are carried out absolute value relatively, and when differential filter output valve 1501a was big, the symbol 1501b corresponding to differential filter output valve 1501a in totalizer 1512 carried out accumulation calculating.At symbol 1501b is timing, and product 1512a is carried out+1 additional calculation, when negative, carries out-1 subtraction at symbol 1501b.In addition, in the comparison of carrying out through comparer 1511, at differential filter output valve 1501a hour, carry out addition or subtraction so that the absolute value of the accumulated value 1512a of totalizer 1512 diminishes.Carry out+1 addition during for negative value at accumulated value 1512a, on the occasion of the time carry out-1 subtraction.Thus, if differential filter output valve 1501a deflection forward, then accumulated value 512a increases slowly along forward, on the contrary, if deflection negative sense then increase slowly along negative sense.In addition, at the absolute value of differential filter output valve 1501a hour, accumulated value 1512a just remains on the value about zero.
Accumulated value 1512a carries out absolute value relatively by comparer 1513 and predetermined threshold value, and comparative result is exported as distribution testing result 1500a.At accumulated value 1512a hour, as distribution testing result 1500a, the distribution of output differential filter output valve 1501a does not have the value of deviation, for example " 0 ".When accumulated value 1512a is big, as distribution testing result 1500a, when accumulated value 1512a is negative value, the value of the distribution deflection minus side of output expression differential filter output valve 1501a, for example " 1 ", accumulated value 1512a be on the occasion of the time, the distribution of output differential ripple output valve 1500a represent to be partial to positive side value, for example "+1 ".
Figure 11, Figure 12, Figure 13 are the timing block diagrams of the action of expression distribution detector 1500.
The frequency that Figure 11 represents regenerated signal 1200a and clock signal 1400a is the action when almost consistent in the scope that PLL can catch.In Figure 11, (A) variation of expression phase error 1303a on time series, (B) expression differential filter output valve 1501a, (C) variation of expression accumulated value 1512a on time series.When the frequency basically identical, shown in (A), phase error 1303a is near the value that produces error because of the influence of the unstable mobile composition of the noise contribution of regenerated signal 1200a and clock signal 1400a zero.Therefore, shown in (B), differential filter output valve 1501a just be not partial to yet with negative which side, all be taken near the value of error zero, the accumulated value 1512a shown in the figure (C) keeps near the value zero.
Figure 12 represents for regenerated signal 1200a, the action the when frequency of clock signal 1400a staggers the downside that PLL can not catch.In Figure 13, (A) variation of expression phase error 1303a on time series, (B) variation of expression differential filter output valve 1501a on time series, (C) variation of expression accumulated value 1512a on time series.When the frequency of clock signal 1400a is hanged down, shown in (A), because the influence of the noise contribution of regenerated signal 1200a and the unstable mobile composition of clock signal 1400a, phase error 1303a becomes the value that comprises the jagged low-frequency component with upper right inclination on the basis of high-frequency domain error.Therefore, shown in figure (B), be in interval on the dextrad in the variation of phase error 1303a, differential filter output valve 1501a always on the occasion of, in the interval that phase error 1303a diminishes suddenly, differential filter output valve 1501a is negative value always.Because the interval on the dextrad has occupied more than half part, so shown in (C), accumulated value 1512a increases to positive side slowly, thus, the frequency that can not catch that can detect clock signal 1400a staggers to a low side.
Figure 13 represents for regenerated signal 1200a, the action the when frequency of clock signal 1400a staggers the side of doing that PLL can not catch.In Figure 13, (A) variation of expression phase error 1303a on time series, (B) variation of expression differential filter output valve 1501a on time series, (C) variation of expression accumulated value 1512a on time series.When the frequency of clock signal 1400a is high, shown in (A), because the influence of the noise contribution of regenerated signal 1200a and the unstable mobile composition of clock signal 1400a, phase error 1303a becomes and comprises the value with the jagged low-frequency component that reduces trend to the right on the basis of high-frequency domain error.Therefore, shown in figure (B), the variation of phase error 1303a be in to the bottom right to the interval, differential filter output valve 1501a is negative value always, becomes big interval suddenly at phase error 1303a, differential filter output valve 1501a always on the occasion of.Since to the bottom right to the interval occupied more than half part, so as (C) shown in, accumulated value 1512a is slowly to the minus side increase, thus, the high side that the frequency that can detect clock signal 1400a staggers and can not catch.
In addition, shown in Figure 11～Figure 13 (A), phase error 1303a is according to the noise contribution of the quality of regenerated signal 1200a and clock signal 1400a and deviation, owing to carry out accumulation calculating with totalizer 1512, therefore, shown in (C), can detect the direction that staggers of the frequency in the time of can not catching exactly.
Below, explain the action of loop filter 1304.
Figure 14 is the block diagram of the structure of representative ring path filter 1304.Loop filter 1304 comprises the phase error shielding device 3041 of the value of phase error 1303a being done shielding processing according to the distribution testing result; Phase error after the shielding processing is amplified a amplifier 3042 doubly; Each group phase error computation pulse waveform is accumulated the totalizer 3043 and the chronotron 3044 of the phase error after the same shielding processing; The accumulated value of phase error is amplified b amplifier 3045 doubly; Totalizer 3046 with the output valve addition of two amplifiers 3042,3045.Be transfused to clock signal generator 1400 from the control signal 1304a of totalizer 3046 outputs.
When distribution testing result 1500a shows that the distribution of differential filter output valve is not offset, the output of just phase error 1303a being remained untouched of phase error shielding device 3041.In expression when positive lateral deviation is moved, if phase error 303a on the occasion of the output of remaining untouched, if for negative value then shield not output phase error value.On the contrary, in expression when minus side be offset, if phase error 1303a be negative value then export same as before, if on the occasion of shield not output phase error value.
To the phase error after the shielding processing, carry out the phase modulation (PM) of clock signal 1400a by amplifier 3042, the frequency modulation (PFM) of clock signal 1400a is that the totalizer 3043 that includes by totalizer and chronotron 3044 and amplifier 3045 carry out.By phase error shielding device 3041, when not carrying out shielding processing,, then only export positive phase error if the frequency of clock signal 1400a is low, therefore, the frequency of clock signal 1400a is along with the frequency of regenerated signal 1200a increases monotonously.In addition, if because the frequency height of clock signal 1400a then the negative phase error of output only, therefore, the frequency of clock signal 1400a is along with the frequency of regenerated signal 1200a reduces monotonously.Consequently,, do not carry out phase modulation (PM), obtain phase locked clock signal with regenerated signal 1200a with regard to not carrying out shielding processing in case catch the scope of frequency basically identical.In addition, in amplifier 3045, when distribution testing result 1500a shows forward or negative offset, just can further shorten the time of frequency acquisition by raising multiplying power b.
Figure 15 is a timing diagram, and it represents with respect to regenerated signal 1200a, the frequency of clock signal 1400a stagger the PHASE DISTRIBUTION monitor 1500 under the situation of the high side that PLL can not catch and the action of loop filter 1304.In Figure 15, (A) variation of expression phase error 1303a on time series, (B) variation of expression differential filter output valve 1501a on time series, (C) variation of expression accumulated value 1512a on time series, (D) variation of expression distribution testing result 1500a on time series, (E) variation of output valve on time series of expression phase error shielding device, (F) variation of expression control signal 304a on time series.At first half, because the frequency of clock signal 1400a is in the higher state that PLL can not catch, therefore, phase error (A) becomes the zigzag waveform with bottom right inclination, therefore, differential filter output valve (B) is negative value always, and the accumulated value of symbol (C) increases on negative sense.The accumulated value of symbol (C) if absolute value surpass predetermined threshold value B, the testing result that then distributes (D) becomes expression to the value of negative offset for example-1 to be had.(D) becomes-1 interval in the distribution testing result, owing to shielding of phase error (A) on the occasion of shielding device 3041 in phase error, so shown in the phase error after the shielding processing (E), the just negative value of output.Consequently, the control signal of clock frequency (F) begins to catch and is value near 0, but the direction that the frequency control of clock signal 1400a is being reduced.If the frequency of clock signal 1400a is near the frequency of regenerated signal 1200a, then the zigzag of phase error (A) tilts to diminish, the frequency that the absolute value of differential filter output valve (B) also surpasses predetermined threshold value reduces, and therefore, the demonstration of the absolute value of the accumulated value of symbol (C) reduces trend.Along with reducing of the absolute value of the accumulated value (C) of symbol, if be lower than predetermined threshold value, then owing to the skew that is judged as distribution diminishes, thereby distribution testing result (D) becomes expression and not have the value that is offset for example 0, do not move the shielding processing of being undertaken by phase error shielding device 3041, and direct output phase error value (A).In this state, the frequency error of regenerated signal 1200a and clock signal 1400a is in the scope that PLL can catch, therefore, the control signal of clock frequency (F) just can increase in regenerated signal 1200a, is controlled at the phase locked stable status of clock signal 1400a.
As mentioned above, according to embodiment 2 as can be known, the state that timely PLL can not catch at the frequency error of giving birth to signal and clock signal is the state of the quality deterioration of regenerated signal, also can correctly detect, frequency according to the testing result control clock signal makes frequency error be in the catching range, stable clock signal after can generating thus.
In addition, the accumulated value that carries out accumulation calculating by the displacement symbol with phase error is obtained the distribution of the displacement of phase error, thus, needn't keep a plurality of phase errors, just can be implemented in high-precision test on the miniature circuit.
Moreover, also can omit compensation canceller 1302 in the structure of clock generating circuit 1300.At this moment, phase error computation device 1303 is as long as calculate phase error according to the digital value from A/D converter 1301 outputs.
Moreover, also can on single semiconductor wafer, form the local or whole of clock generating circuit 1300.For example, in the structure of clock generating circuit shown in Figure 9 1300, compensation canceller 1302, phase error computation device 1303, comparer 1304 and displacement distribution detector 1600 can be used as SIC (semiconductor integrated circuit) and realize.
Moreover, in clock signal generation signal circuit 1300, be provided with synchronous determining device 600a, its structure is identical with the structure of the synchronous determining device 600 that carried out explanation in embodiment 1, uses synchronous determining device 600a also can control effective, invalid that displacement distributes and detects.For example, when synchronous determining device 600a judges regenerated signal and clock signal not in synchronous regime, as long as will take it is effective as by the detection of displacement distribution detector, when synchronous determining device 600a judges regenerated signal and clock signal and is in synchronous regime, as long as will take it is invalid as by the detection of displacement distribution detector.
In addition, the same with synchronous determining device 600, when determining device 600a detects error synchronously, also can judge regenerated signal and clock signal not in synchronous regime.
Moreover, the same with synchronous determining device 600, when synchronous determining device 600a judges regenerated signal and clock signal not in synchronous regime, control compensation canceller 1302 is so that the gain increase of compensation canceller 1302, when judging regenerated signal and clock signal and be in synchronous regime, also can control compensation canceller 1302 so that the gain of compensation canceller 1302 reduce.
(embodiment 3)
Figure 16 is the block diagram of structure of the clock signal generating device of expression embodiments of the invention 3.In Figure 16, still annotate identical reference marks and omit explanation for the structural detail identical with structural detail shown in Figure 9.
To be controlled to be zero compensation canceller 1302 from the centered level of the digital value 1301a of A/D converter 1301 output comprises: zero level detecting device 3021, binaryzation DUTY detecting device 3022, totalizer 3023, subtracter 3025, high boost wave filter 3024.
The high boost filtering output value that the radio-frequency component of digital value 1302a amplified after 3024 outputs of high boost wave filter will compensate and eliminate.For example weak points such as 2T that amplitude is easy to diminish and 3T indicate or short compartment amplifies.Represent high boost Filter Structures example at Figure 17.High boost wave filter shown in Figure 17 is a kind of 5 FIR wave filters, make the digital value 1302a and the clock signal 1400a synchronization delay that utilize chronotron 1701,1702,1703,1704,1705 inputs, the value of chronotron is imported totalizer 1706,1707,1707,1709,1710 respectively, and the value 3024a of additional calculation has been carried out 5 accumulated values in output with totalizer 1711.The FACTOR P of 5 totalizers, Q, R, S, T for example also can be made as P=2, Q=-18, R=63, S=-18, T=2.
Zero level detecting device 3021 is the same with phase error computation device 1303, after eliminating, compensation extracts zero crossing the digital value 1302a, the little side of absolute value is judged to be the zero crossing position in two digital values of zero crossing with clipping, and should worthwhilely do the output of zero level detected value.
Binaryzation DUTY detecting device 3022 is exported high boost filtering output value 3024a binaryzation to obtain the identical binaryzation detected value 3022a to extreme value of absolute value.For example, high boost filtering output value 3024a be on the occasion of with regard to the time, be made as+1, be made as-1 during for negative value.
Totalizer 3023 carries out accumulation calculating again with the value that zero level detected value 3021a and binaryzation detected value 3022a have carried out additional calculation, and accumulated value is exported as binaryzation level value 3023a.
In subtracter 3025, deduct binaryzation level value 3023a from digital value 1301a.
By above-mentioned loop structure, binaryzation level value 3023a Be Controlled gets slowly convergence zero, can remove the low-frequency fluctuation composition that is included in digital value 1301a.
Distribute to detect with phase error computation device 1305 with the high boost filtering output value as input, carry out and the same action of phase error computation device 1303 operations, and use phase error computation timing signal 1305b with phase error computation value 1305a with distributing to detect for the 1500 output distribution detections of displacement distribution monitor.
As mentioned above, according to the embodiment of the invention 3, amplitude at the radio-frequency component of regenerated signal 1200a is little, under the low situation of S/N, also can improve the precision of binaryzation and the accuracy of detection of zero crossing, and can stably compensate elimination control and phase error distribution detection by high boost wave filter 3024.
Moreover, in real-time example 3, the high boost wave filter is made as the FIR wave filter five times, but also can is the waveform equalizer put down in writing of Patent Document 5, Patent Document 6 for example, or several maximum-likelihood code translators shown in the Patent Document 9.
(embodiment 4)
Figure 18 is the block diagram of formation of the disk set of expression embodiments of the invention 4.At Figure 18, still annotate identical reference marks and omit explanation for the structural detail identical with structural detail shown in Figure 9.
Disk set comprises: laser 1102a is radiated at shaven head 1102 on the CD 1101; Drive the motor 1103 of CD 1101 runnings; The servo circuit 1606 of control motor 1103 and shaven head 1102; By extracting data reproduction signal 1200a and servo-drive system analog signal processing circuit 1300 among the shaven head 1102 electric signal 1102b that obtain with regenerated signal 1200b; The clock signal generating circuit 1300 of explanation among the foregoing description 2～embodiment 3; From digital value 1302a, extract the guiding channel circuit 1601 of playback of data 1601a; Carry out the demodulated data demodulator circuit 1602 of playback of data 1601a; Extract the address decoder 1603 of address information 1603a as a result the 1602a from data demodulates; The storage data demodulates is the memory buffer 1604 of 1602a as a result; Carry out the CPU1605 of whole control; The interface 1607 that is connected with the principal computer of outside.
Carry out optically focused from shaven head 1102 laser of launching at the magnetic track of CD 1101, the scanning magnetic track simultaneously, detects the reflected light from CD 101, output electric signal 1102b.Analog signal processing circuit 1200 extracts regenerated signal 1200a and servo-drive system regenerated signal 1200b from electric signal 1102b, wherein regenerated signal 1200a correspondence the information of record on the CD 1101, and servo-drive system usefulness regenerated signal 1200b correspondence the scanning mode for the magnetic track that forms on the CD 1101.
Servo circuit 1606 uses servoly to be controlled with regenerated signal 1200b, makes spot condition on CD 1102 of the rotating speed of motor 1103 and laser, the scanning mode of magnetic track reach the state of the best.
Clock signal generating circuit 1300 extracts and regenerated signal 1200a clock signal synchronous 1400a, with clock signal 1400a output synchronously regenerated signal has been carried out pulse modulated digital value.
Guiding channel circuit 1601 extracts digital value 1302a has been carried out the playback of data 1601a of binary conversion treatment, and then by in data demodulation circuit 1602 playback of data 1601a being carried out demodulation, can access the numerical information that is recorded on the CD 1101.
Address decoder 1603 extracts the address value that is included in the demodulation result 1602a, is sent to CPU1605 again.
CPU1605 obtains address value, and the action of control regeneration is simultaneously carried out the input and output of information by interface 1607 and principal computer.
As mentioned above, according to present embodiment 4 as can be known, by the clock signal that generates in the clock signal generating circuit that uses record among embodiment 2～embodiment 3, even because the not good quality of regenerated signal that causes of the performance of the quality of CD 1101 and shaven head 1102 worsens, also reproducing digital information stably.
Moreover it is that LSI realizes that clock signal generating device of the present invention can be used as integrated circuit.The composed component that clock signal generating device possesses both can individually be made a chip, also can will partly or entirely all be made on the chip.
Though integrated circuit is called LSI here, because the difference of integrated level sometimes is also referred to as IC, system LSI, super LSI, super LSI.
In addition, integrated circuit of the present invention is not limited to LSI, also can realize by special circuit or general processor.Also can utilize after LSI makes FPGA (Fieid Programmabie Gate Array) that can working procedure and can and set the structure the measured processor of recombinant the connection of the circuit unit of LSI inside.
And then, by the other technologies that improve or derive of semiconductor technology,, also can use this technology to carry out the integrated of functional clock if substitute the technology of the integrated circuit of LSI.The application of biotechnology etc. also becomes possibility.
In sum, with most preferred embodiment illustration of the present invention the present invention, but the present invention is not limited to the explanation carried out among this embodiment.The present invention is interpreted as and should just explains its scope by the scope of claim.The people in the industry is interpreted as from the record of concrete most preferred embodiment of the present invention, can implement the scope of equivalence according to record of the present invention or technology general knowledge.The patent of quoting in this manual, patent require and document, its content itself be documented in the same on the instructions particularly, should be understood to, its content conduct is quoted the reference of this instructions.
Utilizability on the industry
The effect that the present invention has is, even the frequency of the regenerated signal of input takes place by violent the change Change or regenerated signal temporarily are in the abnormalities such as amplitude diminishes, and also can generate immediately synchronously Clock signal, the present invention in optical disc apparatus as the PLL circuit that is used for data reproduction etc. Useful.
In addition, effect of the present invention also is, even in the frequency of regenerated signal and clock signal In the second-rate situation of inconsistent and regenerated signal, also can generate immediately when synchronous The clock signal, the present invention's conduct in optical disc apparatus is used for the clock signal generative circuit of data reproduction Deng in be useful.

Claims (21)

1. clock signal generating device generates and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, it is characterized in that, comprises:
The A/D conversion equipment responds above-mentioned clock signal above-mentioned regenerated signal is carried out pulsed modulation, by above-mentioned pulse modulated regenerated signal is converted to digital value, generates a plurality of digital values on time series;
The phase error computation device according to above-mentioned a plurality of digital values each, is calculated the phase error of the phase error of above-mentioned regenerated signal of expression and above-mentioned clock signal;
Loop filter, according to above-mentioned phase error, the control signal of the frequency of the above-mentioned clock signal of output control;
The clock oscillation device, the signal that will have the frequency of mating with above-mentioned control signal generates as above-mentioned clock signal;
The falling phase error judgment means according to above-mentioned phase error, judges whether above-mentioned phase error is in the predetermined scope,
Above-mentioned phase error computation device, zero crossing to above-mentioned a plurality of digital values detects, judging phase error with above-mentioned falling phase error judgment means in above-mentioned predetermined scope the time, according to the digital value of two digital values that are arranged in above-mentioned zero crossing front and back near the zero level side, calculate above-mentioned phase error, judging above-mentioned phase error with above-mentioned falling phase error judgment means not in above-mentioned predetermined scope the time, according in above-mentioned two digital values away from the digital value of zero level side, calculate above-mentioned phase error.
2. clock signal generating device as claimed in claim 1 is characterized in that,
Above-mentioned falling phase error judgment means comprises: above-mentioned phase error is carried out the low-pass filter of smoothing processing,
Above-mentioned falling phase error judgment means judges according to the comparative result of the output valve and the predetermined threshold value of above-mentioned low-pass filter whether phase error is in the above-mentioned predetermined scope.
3. clock signal generating device as claimed in claim 1 is characterized in that,
When above-mentioned falling phase error judgment means judges that above-mentioned phase error is not in above-mentioned predetermined scope, control above-mentioned loop filter so that the gain of above-mentioned loop filter uprises.
4. clock signal generating device as claimed in claim 1 is characterized in that,
Also comprise: according to the amplitude of above-mentioned control signal, judge whether above-mentioned regenerated signal and above-mentioned clock signal are in the synchronous judging unit of synchronous regime,
When above-mentioned synchronous judging unit is judged above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, effective by the judgement that above-mentioned phase error judgment means is made, when judging that above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime, the judgement of being made by above-mentioned phase error judgment means is invalid.
5. clock signal generating device as claimed in claim 1 is characterized in that,
Also comprise: the compensation cancellation element, detect the level that above-mentioned digital value is carried out binaryzation, eliminate the compensating component of above-mentioned digital value according to above-mentioned level,
Above-mentioned phase error computation device calculates above-mentioned phase error according to the digital value of being eliminated by above-mentioned compensation cancellation element compensation.
6. clock signal generating device as claimed in claim 5 is characterized in that,
Also comprise: synchronous judging unit, according to the amplitude of above-mentioned control signal, judge whether above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime,
Above-mentioned synchronous judging unit is when judging above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, control above-mentioned compensation cancellation element so that the gain of above-mentioned compensation cancellation element uprises, when judging that above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime, control above-mentioned compensation cancellation element, so that the gain step-down of above-mentioned compensation cancellation element.
7. clock signal generating device as claimed in claim 4 is characterized in that, comprises:
The adding up device that above-mentioned digital value is added up in each predetermined interval;
The equalization device of the averaging of accumulated value that will calculate through above-mentioned adding up device;
The error detecting apparatus that difference between the mean value that accumulated value that above-mentioned adding up device calculates and above-mentioned average treatment device obtain is carried out error-detecting during greater than predetermined threshold value,
When above-mentioned synchronous judging unit detects error at above-mentioned error detecting apparatus, be judged to be not in synchronous regime.
8. SIC (semiconductor integrated circuit), it is used in the clock signal generating device that generates with the regenerated signal clock signal synchronous of the optical disc reproducing that records information, it is characterized in that,
Above-mentioned clock signal generating device comprises: respond above-mentioned clock signal above-mentioned regenerated signal is carried out pulsed modulation, by above-mentioned pulse modulated regenerated signal is converted to digital value, on time series, generate the A/D conversion equipment of a plurality of digital values and generate the clock oscillation device of above-mentioned clock signal
Above-mentioned SIC (semiconductor integrated circuit) possesses:
According to above-mentioned a plurality of digital values each, calculate the phase error computation device of phase error of the phase error of above-mentioned regenerated signal of expression and above-mentioned clock signal;
According to above-mentioned phase error, the loop filter of the control signal of the frequency of the above-mentioned clock signal of output control;
According to above-mentioned phase error, judge whether above-mentioned phase error is in the falling phase error judgment means in the predetermined scope,
Above-mentioned phase error calculation element; Zero crossing to above-mentioned a plurality of digital values detects; Judge above-mentioned phase error in above-mentioned predetermined scope the time judging device with above-mentioned falling phase error; According to the digital value of two digital values that are arranged in above-mentioned zero crossing front and back near the zero level side; Calculate above-mentioned phase error; Judge above-mentioned phase error not in above-mentioned predetermined scope the time judging device with above-mentioned falling phase error; According in above-mentioned two digital values away from the digital value of zero level side; Calculate above-mentioned phase error
Above-mentioned clock oscillation device generation has the signal of the frequency of mating with above-mentioned control signal as above-mentioned clock signal.
9. data recording method generates and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, and output and above-mentioned clock signal is characterized in that synchronously and with the playback of data of above-mentioned reproduction signal binarization, comprising:
(a) respond above-mentioned clock signal, above-mentioned regenerated signal is carried out pulsed modulation,, on time series, generate the step of a plurality of digital values by above-mentioned pulse modulated regenerated signal is converted to digital value;
(b) according to above-mentioned a plurality of digital values each, calculate the step of the phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal;
(c) according to above-mentioned phase error, the step of the control signal of the frequency of the above-mentioned clock signal of output control;
(d) generation has the step of the signal of the frequency of mating with above-mentioned control signal as above-mentioned clock signal;
(e) according to above-mentioned phase error, judge whether above-mentioned phase error is in the step in the predetermined scope,
Above-mentioned steps (b) comprises:
Detect the step of the zero crossing of above-mentioned a plurality of digital values;
In above-mentioned falling phase error determining step, judge when above-mentioned phase error is in the above-mentioned predetermined scope, according to the digital value of two digital values that are arranged in above-mentioned zero crossing front and back, calculate the step of above-mentioned phase error near the zero level side;
In above-mentioned falling phase error determining step, when judging that above-mentioned phase error is not in above-mentioned predetermined scope, according in above-mentioned two digital values away from the digital value of zero level side, calculate the step of above-mentioned phase error.
10. clock signal generating device generates and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, it is characterized in that, comprises:
The A/D conversion equipment responds above-mentioned clock signal, and above-mentioned regenerated signal is carried out pulsed modulation, by above-mentioned pulse modulated regenerated signal is converted to digital value, generates a plurality of digital values on time series;
The first phase error computation device according to above-mentioned a plurality of digital values each, is calculated first phase error of phase error of the phase error of above-mentioned regenerated signal of expression and above-mentioned clock signal;
The first displacement distribution pick-up unit detects the distribution of the displacement of above-mentioned first phase error;
Loop filter according to the distribution testing result of the displacement of above-mentioned first phase error and above-mentioned first phase error, generates the control signal of the frequency of the above-mentioned clock signal of control;
Clock oscillation device, generation have the signal of the frequency of mating with above-mentioned control signal as above-mentioned clock signal;
Above-mentioned loop filter generates above-mentioned control signal, so that the displacement distribution bias of above-mentioned first phase error reduces.
11. clock signal generating device as claimed in claim 10 is characterized in that,
Also comprise: according to the amplitude of above-mentioned control signal, judge whether above-mentioned regenerated signal and above-mentioned clock signal are in the synchronous judging unit of synchronous regime,
Above-mentioned synchronous judging unit is when judging above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, effective by the detection that the above-mentioned first displacement distribution pick-up unit carries out, when judging that above-mentioned regenerated signal and above-mentioned clock signal are in synchronous regime, effective by the detection that the above-mentioned first displacement distribution pick-up unit carries out.
12. clock signal generating device as claimed in claim 11 is characterized in that,
Comprise:
Above-mentioned digital value is made the adding up device of accumulation calculating in each predetermined interval;
Equalization device to the averaging of accumulated value calculated through above-mentioned adding up device;
The error detecting apparatus that the difference of the mean value that accumulated value that calculates at above-mentioned adding up device and above-mentioned average treatment device obtain is carried out error-detecting during greater than predetermined threshold value,
Above-mentioned synchronous judging unit is judged as not in synchronous regime when detecting error by above-mentioned error detecting apparatus.
13. clock signal generating device as claimed in claim 10 is characterized in that,
When the deviation of above-mentioned distribution was big, above-mentioned loop filter only used the value of the polarity that deviation diminishes in above-mentioned phase error.
14. clock signal generating device as claimed in claim 10 is characterized in that,
Above-mentioned displacement distribution pick-up unit adds up by the symbol to above-mentioned displacement and detects distribution.
15. clock signal generating device as claimed in claim 14 is characterized in that,
Above-mentioned displacement distribution pick-up unit is only at the absolute value of above-mentioned displacement during greater than predetermined value, and the symbol of above-mentioned displacement is added up.
16. clock signal generating device as claimed in claim 15 is characterized in that,
During less than predetermined value, the direction that the absolute value of the accumulated value after above-mentioned displacement symbol is added up diminishes increases or reduces above-mentioned accumulated value to above-mentioned displacement distribution pick-up unit at the absolute value of above-mentioned displacement.
17. clock signal generating device as claimed in claim 10 is characterized in that, comprises:
Promote the high boost filter of the radio-frequency component of above-mentioned digital value;
According to the output signal of above-mentioned high boost filter, calculate the second phase error computation device of second phase error of the phase error between above-mentioned regenerated signal of expression and above-mentioned clock signal;
The second displacement distribution pick-up unit that the distribution of the displacement of above-mentioned second phase error is detected,
Above-mentioned loop filter generates above-mentioned control signal, so that the deviation that the displacement of second phase error distributes diminishes.
18. clock signal generating device as claimed in claim 17 is characterized in that,
Also comprise: the level to above-mentioned digital value binaryzation detects, the compensation cancellation element of the compensating component of above-mentioned digital value being eliminated according to above-mentioned level,
The above-mentioned first phase error computation device calculates above-mentioned first phase error according to the digital value after eliminating by above-mentioned compensation cancellation element compensation,
Above-mentioned high boost filter is contained in the above-mentioned compensation cancellation element.
19. clock signal generating device as claimed in claim 18 is characterized in that,
Also comprise: according to the amplitude of above-mentioned control signal, whether above-mentioned regenerated signal and clock signal are in the synchronous judging unit that synchronous regime is judged,
When determining above-mentioned regenerated signal and above-mentioned clock signal not in synchronous regime, above-mentioned synchronous judging unit is controlled above-mentioned compensation cancellation element so that the gain of above-mentioned compensation cancellation element uprises, determining above-mentioned regenerated signal and above-mentioned clock signal when being in synchronous regime, above-mentioned synchronous judging unit controls above-mentioned compensation cancellation element so that the gain step-down of above-mentioned compensation cancellation element.
20. a SIC (semiconductor integrated circuit), it is used in and generates with from the clock signal generating device of the regenerated signal clock signal synchronous of the optical disc reproducing of the information of recording, it is characterized in that,
Above-mentioned clock signal generating device comprises: respond above-mentioned clock signal above-mentioned regenerated signal is carried out pulsed modulation, and by above-mentioned pulse modulated regenerated signal is converted to digital value, on time series, generate the A/D conversion equipment of a plurality of digital values and generate the clock oscillation device of above-mentioned clock signal
Above-mentioned SIC (semiconductor integrated circuit) comprises:
According to above-mentioned a plurality of digital values each, calculate the first phase error computation device of first phase error of the phase error of above-mentioned regenerated signal of expression and above-mentioned clock signal;
The first displacement distribution pick-up unit that the displacement of above-mentioned first phase error is distributed and detects;
According to the testing result that the displacement of above-mentioned first phase error and above-mentioned first phase error distributes, generate the loop filter of control signal of the frequency of the above-mentioned clock signal of control,
Above-mentioned loop filter generates control signal, so that the deviation that the displacement of above-mentioned first phase error distributes diminishes,
Above-mentioned clock oscillation device generation has the signal of the frequency of mating with above-mentioned control signal as above-mentioned clock signal.
21. a data recording method generates and regenerated signal clock signal synchronous from the optical disc reproducing of the information of recording, output and above-mentioned clock signal is characterized in that synchronously and the playback of data of the above-mentioned regenerated signal of digitizing, comprising:
(a) respond above-mentioned clock signal, above-mentioned regenerated signal is carried out pulsed modulation,, on time series, generate the step of a plurality of digital values by above-mentioned pulse modulated regenerated signal is converted to digital value;
(b) according to above-mentioned a plurality of digital values each, calculate the step of first phase error of the phase error of representing above-mentioned regenerated signal and above-mentioned clock signal;
(c) step of the displacement distribution of above-mentioned first phase error of detection;
(d), generate the step of the control signal of the frequency of controlling above-mentioned clock signal according to the displacement distribution testing result of above-mentioned first phase error and above-mentioned first phase error;
(e) generate the signal have with the frequency of above-mentioned control signal coupling as above-mentioned clock signal,
Above-mentioned steps (d) comprises: generate above-mentioned control signal, so that the step that the deviation that the displacement of above-mentioned first phase error distributes diminishes.
CN 200580016617 2004-03-23 2005-03-23 Clock signal generation device, semiconductor integrated circuit, and data reproduction method Pending CN1977330A (en)

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JP084352/2004 2004-03-23
JP292214/2004 2004-10-05

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101452712B (en) * 2007-12-07 2012-03-07 瑞萨电子株式会社 Optical disk reproducing device and phase-locked loop circuit
CN102290063B (en) * 2007-11-20 2015-06-03 松下电器产业株式会社 Optical disc, optical disc recording/reproducing method
CN106405205A (en) * 2015-07-30 2017-02-15 钜泉光电科技(上海)股份有限公司 Zero-crossing detection circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290063B (en) * 2007-11-20 2015-06-03 松下电器产业株式会社 Optical disc, optical disc recording/reproducing method
CN101452712B (en) * 2007-12-07 2012-03-07 瑞萨电子株式会社 Optical disk reproducing device and phase-locked loop circuit
CN106405205A (en) * 2015-07-30 2017-02-15 钜泉光电科技(上海)股份有限公司 Zero-crossing detection circuit

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